1f5fbb83fSMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */ 20057131fSMauro Carvalho Chehab /* 30057131fSMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 40057131fSMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 50057131fSMauro Carvalho Chehab * 60057131fSMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 70057131fSMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 80057131fSMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 90057131fSMauro Carvalho Chehab * 100057131fSMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 110057131fSMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 120057131fSMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 130057131fSMauro Carvalho Chehab * more details. 140057131fSMauro Carvalho Chehab */ 150057131fSMauro Carvalho Chehab 160057131fSMauro Carvalho Chehab #ifndef _mipi_backend_defs_h 170057131fSMauro Carvalho Chehab #define _mipi_backend_defs_h 180057131fSMauro Carvalho Chehab 190057131fSMauro Carvalho Chehab #include "mipi_backend_common_defs.h" 200057131fSMauro Carvalho Chehab 210057131fSMauro Carvalho Chehab #define MIPI_BACKEND_REG_ALIGN 4 // assuming 32 bit control bus width 220057131fSMauro Carvalho Chehab 230057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_NOF_IRQS 3 // sid_lut 240057131fSMauro Carvalho Chehab 250057131fSMauro Carvalho Chehab // SH Backend Register IDs 260057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_ENABLE_REG_IDX 0 270057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_STATUS_REG_IDX 1 280057131fSMauro Carvalho Chehab //#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_IDX 2 290057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX 2 300057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG1_IDX 3 310057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG2_IDX 4 320057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG3_IDX 5 330057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX 6 340057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX 7 350057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX 8 360057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX 9 370057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_IDX 10 380057131fSMauro Carvalho Chehab //// 390057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_EN_REG_IDX 11 400057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX 12 410057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX 13 420057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P1_REG_IDX 14 430057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P2_REG_IDX 15 440057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P3_REG_IDX 16 450057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P0_REG_IDX 17 460057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P1_REG_IDX 18 470057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P2_REG_IDX 19 480057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P3_REG_IDX 20 490057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P0_REG_IDX 21 500057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P1_REG_IDX 22 510057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P2_REG_IDX 23 520057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P3_REG_IDX 24 530057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX 25 540057131fSMauro Carvalho Chehab //// 550057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX 26 560057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX 27 570057131fSMauro Carvalho Chehab //#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_IDX 28 580057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX 28 590057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_IDX 29 600057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_IDX 30 610057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_IDX 31 620057131fSMauro Carvalho Chehab 630057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_NOF_REGISTERS 32 // excluding the LP LUT entries 640057131fSMauro Carvalho Chehab 650057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX 32 660057131fSMauro Carvalho Chehab 670057131fSMauro Carvalho Chehab ///////////////////////////////////////////////////////////////////////////////////////////////////// 680057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_ENABLE_REG_WIDTH 1 690057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_STATUS_REG_WIDTH 1 700057131fSMauro Carvalho Chehab //#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_WIDTH 1 710057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG_WIDTH 32 720057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_WIDTH 7 730057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_WIDTH 9 740057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_WIDTH 8 750057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_WIDTH _HRT_MIPI_BACKEND_NOF_IRQS 760057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_WIDTH 0 770057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_WIDTH 1 780057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_WIDTH 1 + 2 + 6 790057131fSMauro Carvalho Chehab //#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_WIDTH 1 800057131fSMauro Carvalho Chehab //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_WIDTH 7 810057131fSMauro Carvalho Chehab //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_WIDTH 7 820057131fSMauro Carvalho Chehab //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_WIDTH 7 830057131fSMauro Carvalho Chehab //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_WIDTH 7 840057131fSMauro Carvalho Chehab 850057131fSMauro Carvalho Chehab ///////////////////////////////////////////////////////////////////////////////////////////////////// 860057131fSMauro Carvalho Chehab 870057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_NOF_SP_LUT_ENTRIES 4 880057131fSMauro Carvalho Chehab 890057131fSMauro Carvalho Chehab //#define _HRT_MIPI_BACKEND_MAX_NOF_LP_LUT_ENTRIES 16 // to satisfy hss model static array declaration 900057131fSMauro Carvalho Chehab 910057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH 2 920057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 6 930057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_PACKET_ID_WIDTH _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 940057131fSMauro Carvalho Chehab 950057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB 0 960057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB + (pix_width) - 1) 970057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) + 1) 980057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) + 1) 990057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) + (pix_width) - 1) 1000057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) + 1) 1010057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) + 1) 1020057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) + 1) 1030057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_STREAMING_WIDTH(pix_width) (_HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) + 1) 1040057131fSMauro Carvalho Chehab 1050057131fSMauro Carvalho Chehab /*************************************************************************************************/ 1060057131fSMauro Carvalho Chehab /* Custom Decoding */ 1070057131fSMauro Carvalho Chehab /* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */ 1080057131fSMauro Carvalho Chehab /*************************************************************************************************/ 1090057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_EN_IDX 0 /* 2bits */ 1100057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ 1110057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_EN_HIGH_PREC_IDX 8 // 1 bit 1120057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_EN_WIDTH 9 1130057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ 1140057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ 1150057131fSMauro Carvalho Chehab 1160057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_EN_OPTION_IDX 1 1170057131fSMauro Carvalho Chehab 1180057131fSMauro Carvalho Chehab /* Data State config = {get_bits(6bits), valid(1bit)} */ 1190057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ 1200057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S1_IDX 8 /* 7bits */ 1210057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S2_IDX 16 /* was 14 7bits */ 1220057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_WIDTH 24 /* was 21*/ 1230057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ 1240057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ 1250057131fSMauro Carvalho Chehab 1260057131fSMauro Carvalho Chehab /* Pixel Extractor config */ 1270057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 6bits */ 1280057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_ALIGN_IDX 6 /* 5bits */ 1290057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_MASK_IDX 11 /* was 10 18bits */ 1300057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_EN_IDX 29 /* was 28 1bits */ 1310057131fSMauro Carvalho Chehab 1320057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_WIDTH 30 /* was 29 */ 1330057131fSMauro Carvalho Chehab 1340057131fSMauro Carvalho Chehab /* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ 1350057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ 1360057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ 1370057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ 1380057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ 1390057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_WIDTH 16 1400057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ 1410057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ 1420057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ 1430057131fSMauro Carvalho Chehab #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ 1440057131fSMauro Carvalho Chehab 1450057131fSMauro Carvalho Chehab /*************************************************************************************************/ 1460057131fSMauro Carvalho Chehab /* MIPI backend output streaming interface definition */ 1470057131fSMauro Carvalho Chehab /* These parameters define the fields within the streaming bus. These should also be used by the */ 1480057131fSMauro Carvalho Chehab /* subsequent block, ie stream2mmio. */ 1490057131fSMauro Carvalho Chehab /*************************************************************************************************/ 1500057131fSMauro Carvalho Chehab /* The pipe backend - stream2mmio should be design time configurable in */ 1510057131fSMauro Carvalho Chehab /* PixWidth - Number of bits per pixel */ 1520057131fSMauro Carvalho Chehab /* PPC - Pixel per Clocks */ 1530057131fSMauro Carvalho Chehab /* NumSids - Max number of source Ids (ifc's) and derived from that: */ 1540057131fSMauro Carvalho Chehab /* SidWidth - Number of bits required for the sid parameter */ 1550057131fSMauro Carvalho Chehab /* In order to keep this configurability, below Macro's have these as a parameter */ 1560057131fSMauro Carvalho Chehab /*************************************************************************************************/ 1570057131fSMauro Carvalho Chehab 1580057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_EOP_BIT 0 1590057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_SOP_BIT 1 1600057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_EOF_BIT 2 1610057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_SOF_BIT 3 1620057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT 4 1630057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT + (sid_width) - 1) 1640057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, p) (HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) + 1 + p) 1650057131fSMauro Carvalho Chehab 1660057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, ppc) + ((pix_width) * p)) 1670057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) + (pix_width) - 1) 1680057131fSMauro Carvalho Chehab 1690057131fSMauro Carvalho Chehab #if 0 1700057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIX_BITS 14 1710057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_CHID_BITS 4 1720057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PPC 4 1730057131fSMauro Carvalho Chehab #endif 1740057131fSMauro Carvalho Chehab 1750057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_BITS(sid_width, ppc, pix_width) (HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, (ppc - 1)) + 1) 1760057131fSMauro Carvalho Chehab 1770057131fSMauro Carvalho Chehab /* SP and LP LUT BIT POSITIONS */ 1780057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT 0 // 0 1790057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_LUT_SID_LS_BIT HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT + 1 // 1 1800057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_LUT_SID_LS_BIT + (sid_width) - 1) // 1 + (4) - 1 = 4 1810057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 // 5 1820057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH - 1 // 6 1830057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 1840057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH - 1 // 12 1850057131fSMauro Carvalho Chehab 1860057131fSMauro Carvalho Chehab /* #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 */ 1870057131fSMauro Carvalho Chehab 1880057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 1890057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_LP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) + 1 // 13 1900057131fSMauro Carvalho Chehab 1910057131fSMauro Carvalho Chehab // temp solution 1920057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT + 1 // 8 1930057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT + 1 // 9 1940057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT + 1 // 10 1950057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT + 1 // 11 1960057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT + 1 // 12 1970057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 25 1980057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT + 1 // 26 1990057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 39 2000057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT + 1 // 40 2010057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 53 2020057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT + 1 // 54 2030057131fSMauro Carvalho Chehab //#define HRT_MIPI_BACKEND_STREAM_PIXD_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 67 2040057131fSMauro Carvalho Chehab 2050057131fSMauro Carvalho Chehab // vc hidden in pixb data (passed as raw12 the pipe) 2060057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, 1) + 10 //HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + 10 // 36 2070057131fSMauro Carvalho Chehab #define HRT_MIPI_BACKEND_STREAM_VC_MS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) + 1 // 37 2080057131fSMauro Carvalho Chehab 2090057131fSMauro Carvalho Chehab #endif /* _mipi_backend_defs_h */ 210