1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ 17 #define __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ 18 19 #include "isys_stream2mmio_public.h" 20 #include "device_access.h" /* ia_css_device_load_uint32 */ 21 #include "assert_support.h" /* assert */ 22 #include "print_support.h" /* print */ 23 24 #define STREAM2MMIO_COMMAND_REG_ID 0 25 #define STREAM2MMIO_ACKNOWLEDGE_REG_ID 1 26 #define STREAM2MMIO_PIX_WIDTH_ID_REG_ID 2 27 #define STREAM2MMIO_START_ADDR_REG_ID 3 /* master port address,NOT Byte */ 28 #define STREAM2MMIO_END_ADDR_REG_ID 4 /* master port address,NOT Byte */ 29 #define STREAM2MMIO_STRIDE_REG_ID 5 /* stride in master port words, increment is per packet for long sids, stride is not used for short sid's*/ 30 #define STREAM2MMIO_NUM_ITEMS_REG_ID 6 /* number of packets for store packets cmd, number of words for store_words cmd */ 31 #define STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID 7 /* if this register is 1, input will be stalled if there is no pending command for this sid */ 32 #define STREAM2MMIO_REGS_PER_SID 8 33 34 /***************************************************** 35 * 36 * Native command interface (NCI). 37 * 38 *****************************************************/ 39 /** 40 * @brief Get the stream2mmio-controller state. 41 * Refer to "stream2mmio_public.h" for details. 42 */ 43 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_state( 44 const stream2mmio_ID_t ID, 45 stream2mmio_state_t *state) 46 { 47 stream2mmio_sid_ID_t i; 48 49 /* 50 * Get the values of the register-set per 51 * stream2mmio-controller sids. 52 */ 53 for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) { 54 stream2mmio_get_sid_state(ID, i, &state->sid_state[i]); 55 } 56 } 57 58 /** 59 * @brief Get the state of the stream2mmio-controller sidess. 60 * Refer to "stream2mmio_public.h" for details. 61 */ 62 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_sid_state( 63 const stream2mmio_ID_t ID, 64 const stream2mmio_sid_ID_t sid_id, 65 stream2mmio_sid_state_t *state) 66 { 67 state->rcv_ack = 68 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_ACKNOWLEDGE_REG_ID); 69 70 state->pix_width_id = 71 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_PIX_WIDTH_ID_REG_ID); 72 73 state->start_addr = 74 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_START_ADDR_REG_ID); 75 76 state->end_addr = 77 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_END_ADDR_REG_ID); 78 79 state->strides = 80 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_STRIDE_REG_ID); 81 82 state->num_items = 83 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_NUM_ITEMS_REG_ID); 84 85 state->block_when_no_cmd = 86 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID); 87 } 88 89 /** 90 * @brief Dump the state of the stream2mmio-controller sidess. 91 * Refer to "stream2mmio_public.h" for details. 92 */ 93 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_print_sid_state( 94 stream2mmio_sid_state_t *state) 95 { 96 ia_css_print("\t \t Receive acks 0x%x\n", state->rcv_ack); 97 ia_css_print("\t \t Pixel width 0x%x\n", state->pix_width_id); 98 ia_css_print("\t \t Startaddr 0x%x\n", state->start_addr); 99 ia_css_print("\t \t Endaddr 0x%x\n", state->end_addr); 100 ia_css_print("\t \t Strides 0x%x\n", state->strides); 101 ia_css_print("\t \t Num Items 0x%x\n", state->num_items); 102 ia_css_print("\t \t block when no cmd 0x%x\n", state->block_when_no_cmd); 103 } 104 105 /** 106 * @brief Dump the ibuf-controller state. 107 * Refer to "stream2mmio_public.h" for details. 108 */ 109 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_dump_state( 110 const stream2mmio_ID_t ID, 111 stream2mmio_state_t *state) 112 { 113 stream2mmio_sid_ID_t i; 114 115 /* 116 * Get the values of the register-set per 117 * stream2mmio-controller sids. 118 */ 119 for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) { 120 ia_css_print("StREAM2MMIO ID %d SID %d\n", ID, i); 121 stream2mmio_print_sid_state(&state->sid_state[i]); 122 } 123 } 124 125 /* end of NCI */ 126 127 /***************************************************** 128 * 129 * Device level interface (DLI). 130 * 131 *****************************************************/ 132 /** 133 * @brief Load the register value. 134 * Refer to "stream2mmio_public.h" for details. 135 */ 136 STORAGE_CLASS_STREAM2MMIO_C hrt_data stream2mmio_reg_load( 137 const stream2mmio_ID_t ID, 138 const stream2mmio_sid_ID_t sid_id, 139 const uint32_t reg_idx) 140 { 141 u32 reg_bank_offset; 142 143 assert(ID < N_STREAM2MMIO_ID); 144 145 reg_bank_offset = STREAM2MMIO_REGS_PER_SID * sid_id; 146 return ia_css_device_load_uint32(STREAM2MMIO_CTRL_BASE[ID] + 147 (reg_bank_offset + reg_idx) * sizeof(hrt_data)); 148 } 149 150 /** 151 * @brief Store a value to the register. 152 * Refer to "stream2mmio_public.h" for details. 153 */ 154 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_reg_store( 155 const stream2mmio_ID_t ID, 156 const hrt_address reg, 157 const hrt_data value) 158 { 159 assert(ID < N_STREAM2MMIO_ID); 160 assert(STREAM2MMIO_CTRL_BASE[ID] != (hrt_address)-1); 161 162 ia_css_device_store_uint32(STREAM2MMIO_CTRL_BASE[ID] + 163 reg * sizeof(hrt_data), value); 164 } 165 166 /* end of DLI */ 167 168 #endif /* __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ */ 169