1 /* 2 * Support for Intel Camera Imaging ISP subsystem. 3 * Copyright (c) 2015, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef __CSI_RX_PRIVATE_H_INCLUDED__ 16 #define __CSI_RX_PRIVATE_H_INCLUDED__ 17 18 #include "rx_csi_defs.h" 19 #include "mipi_backend_defs.h" 20 #include "csi_rx.h" 21 22 #include "device_access.h" /* ia_css_device_load_uint32 */ 23 24 #include "assert_support.h" /* assert */ 25 #include "print_support.h" /* print */ 26 27 /***************************************************** 28 * 29 * Device level interface (DLI). 30 * 31 *****************************************************/ 32 /** 33 * @brief Load the register value. 34 * Refer to "csi_rx_public.h" for details. 35 */ 36 static inline hrt_data csi_rx_fe_ctrl_reg_load( 37 const csi_rx_frontend_ID_t ID, 38 const hrt_address reg) 39 { 40 assert(ID < N_CSI_RX_FRONTEND_ID); 41 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); 42 return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof( 43 hrt_data)); 44 } 45 46 /** 47 * @brief Store a value to the register. 48 * Refer to "ibuf_ctrl_public.h" for details. 49 */ 50 static inline void csi_rx_fe_ctrl_reg_store( 51 const csi_rx_frontend_ID_t ID, 52 const hrt_address reg, 53 const hrt_data value) 54 { 55 assert(ID < N_CSI_RX_FRONTEND_ID); 56 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); 57 58 ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data), 59 value); 60 } 61 62 /** 63 * @brief Load the register value. 64 * Refer to "csi_rx_public.h" for details. 65 */ 66 static inline hrt_data csi_rx_be_ctrl_reg_load( 67 const csi_rx_backend_ID_t ID, 68 const hrt_address reg) 69 { 70 assert(ID < N_CSI_RX_BACKEND_ID); 71 assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1); 72 return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof( 73 hrt_data)); 74 } 75 76 /** 77 * @brief Store a value to the register. 78 * Refer to "ibuf_ctrl_public.h" for details. 79 */ 80 static inline void csi_rx_be_ctrl_reg_store( 81 const csi_rx_backend_ID_t ID, 82 const hrt_address reg, 83 const hrt_data value) 84 { 85 assert(ID < N_CSI_RX_BACKEND_ID); 86 assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1); 87 88 ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg * sizeof(hrt_data), 89 value); 90 } 91 92 /* end of DLI */ 93 94 /***************************************************** 95 * 96 * Native command interface (NCI). 97 * 98 *****************************************************/ 99 /** 100 * @brief Get the state of the csi rx fe dlane process. 101 * Refer to "csi_rx_public.h" for details. 102 */ 103 static inline void csi_rx_fe_ctrl_get_dlane_state( 104 const csi_rx_frontend_ID_t ID, 105 const u32 lane, 106 csi_rx_fe_ctrl_lane_t *dlane_state) 107 { 108 dlane_state->termen = 109 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane)); 110 dlane_state->settle = 111 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane)); 112 } 113 114 /** 115 * @brief Get the csi rx fe state. 116 * Refer to "csi_rx_public.h" for details. 117 */ 118 static inline void csi_rx_fe_ctrl_get_state( 119 const csi_rx_frontend_ID_t ID, 120 csi_rx_fe_ctrl_state_t *state) 121 { 122 u32 i; 123 124 state->enable = 125 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ENABLE_REG_IDX); 126 state->nof_enable_lanes = 127 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX); 128 state->error_handling = 129 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ERROR_HANDLING_REG_IDX); 130 state->status = 131 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_REG_IDX); 132 state->status_dlane_hs = 133 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX); 134 state->status_dlane_lp = 135 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX); 136 state->clane.termen = 137 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX); 138 state->clane.settle = 139 csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX); 140 141 /* 142 * Get the values of the register-set per 143 * dlane. 144 */ 145 for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) { 146 csi_rx_fe_ctrl_get_dlane_state( 147 ID, 148 i, 149 &state->dlane[i]); 150 } 151 } 152 153 /** 154 * @brief dump the csi rx fe state. 155 * Refer to "csi_rx_public.h" for details. 156 */ 157 static inline void csi_rx_fe_ctrl_dump_state( 158 const csi_rx_frontend_ID_t ID, 159 csi_rx_fe_ctrl_state_t *state) 160 { 161 u32 i; 162 163 ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x\n", ID, 164 state->enable); 165 ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x\n", ID, 166 state->nof_enable_lanes); 167 ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x\n", ID, 168 state->error_handling); 169 ia_css_print("CSI RX FE STATE Controller %d Status 0x%x\n", ID, state->status); 170 ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x\n", ID, 171 state->status_dlane_hs); 172 ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x\n", ID, 173 state->status_dlane_lp); 174 ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x\n", ID, 175 state->clane.termen); 176 ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x\n", ID, 177 state->clane.settle); 178 179 /* 180 * Get the values of the register-set per 181 * dlane. 182 */ 183 for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) { 184 ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x\n", ID, i, 185 state->dlane[i].termen); 186 ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x\n", ID, i, 187 state->dlane[i].settle); 188 } 189 } 190 191 /** 192 * @brief Get the csi rx be state. 193 * Refer to "csi_rx_public.h" for details. 194 */ 195 static inline void csi_rx_be_ctrl_get_state( 196 const csi_rx_backend_ID_t ID, 197 csi_rx_be_ctrl_state_t *state) 198 { 199 u32 i; 200 201 state->enable = 202 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_ENABLE_REG_IDX); 203 204 state->status = 205 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_STATUS_REG_IDX); 206 207 for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) { 208 state->comp_format_reg[i] = 209 csi_rx_be_ctrl_reg_load(ID, 210 _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX + i); 211 } 212 213 state->raw16 = 214 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX); 215 216 state->raw18 = 217 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX); 218 state->force_raw8 = 219 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX); 220 state->irq_status = 221 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX); 222 #if 0 /* device access error for these registers */ 223 /* ToDo: rootcause this failure */ 224 state->custom_mode_enable = 225 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_EN_REG_IDX); 226 227 state->custom_mode_data_state = 228 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX); 229 for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) { 230 state->pec[i] = 231 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX + i); 232 } 233 state->custom_mode_valid_eop_config = 234 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX); 235 #endif 236 state->global_lut_disregard_reg = 237 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX); 238 state->packet_status_stall = 239 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX); 240 /* 241 * Get the values of the register-set per 242 * lut. 243 */ 244 for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) { 245 state->short_packet_lut_entry[i] = 246 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX + i); 247 } 248 for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) { 249 state->long_packet_lut_entry[i] = 250 csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX + i); 251 } 252 } 253 254 /** 255 * @brief Dump the csi rx be state. 256 * Refer to "csi_rx_public.h" for details. 257 */ 258 static inline void csi_rx_be_ctrl_dump_state( 259 const csi_rx_backend_ID_t ID, 260 csi_rx_be_ctrl_state_t *state) 261 { 262 u32 i; 263 264 ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x\n", ID, state->enable); 265 ia_css_print("CSI RX BE STATE Controller %d Status 0x%x\n", ID, state->status); 266 267 for (i = 0; i < N_CSI_RX_BE_MIPI_COMP_FMT_REG ; i++) { 268 ia_css_print("CSI RX BE STATE Controller %d comp format reg vc%d value 0x%x\n", 269 ID, i, state->status); 270 } 271 ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x\n", ID, state->raw16); 272 ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x\n", ID, state->raw18); 273 ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x\n", ID, 274 state->force_raw8); 275 ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x\n", ID, 276 state->irq_status); 277 #if 0 /* ToDo:Getting device access error for this register */ 278 for (i = 0; i < N_CSI_RX_BE_MIPI_CUSTOM_PEC ; i++) { 279 ia_css_print("CSI RX BE STATE Controller %d PEC ID %d custom pec 0x%x\n", ID, i, 280 state->pec[i]); 281 } 282 #endif 283 ia_css_print("CSI RX BE STATE Controller %d Global LUT disregard reg 0x%x\n", 284 ID, state->global_lut_disregard_reg); 285 ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x\n", ID, 286 state->packet_status_stall); 287 /* 288 * Get the values of the register-set per 289 * lut. 290 */ 291 for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) { 292 ia_css_print("CSI RX BE STATE Controller ID %d Short packet entry %d short packet lut id 0x%x\n", 293 ID, i, 294 state->short_packet_lut_entry[i]); 295 } 296 for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) { 297 ia_css_print("CSI RX BE STATE Controller ID %d Long packet entry %d long packet lut id 0x%x\n", 298 ID, i, 299 state->long_packet_lut_entry[i]); 300 } 301 } 302 303 /* end of NCI */ 304 305 #endif /* __CSI_RX_PRIVATE_H_INCLUDED__ */ 306