1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for Medifield PNW Camera Imaging ISP subsystem. 4 * 5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved. 6 * 7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License version 11 * 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * 19 */ 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/pm_qos.h> 24 #include <linux/timer.h> 25 #include <linux/delay.h> 26 #include <linux/dmi.h> 27 #include <linux/interrupt.h> 28 #include <linux/bits.h> 29 30 #include <asm/iosf_mbi.h> 31 32 #include "../../include/linux/atomisp_gmin_platform.h" 33 34 #include "atomisp_cmd.h" 35 #include "atomisp_common.h" 36 #include "atomisp_fops.h" 37 #include "atomisp_ioctl.h" 38 #include "atomisp_internal.h" 39 #include "atomisp-regs.h" 40 #include "atomisp_dfs_tables.h" 41 #include "atomisp_drvfs.h" 42 #include "hmm/hmm.h" 43 #include "atomisp_trace_event.h" 44 45 #include "sh_css_firmware.h" 46 47 #include "device_access.h" 48 49 /* Timeouts to wait for all subdevs to be registered */ 50 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */ 51 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */ 52 53 /* G-Min addition: pull this in from intel_mid_pm.h */ 54 #define CSTATE_EXIT_LATENCY_C1 1 55 56 static uint skip_fwload; 57 module_param(skip_fwload, uint, 0644); 58 MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load"); 59 60 /* memory optimization: deferred firmware loading */ 61 bool defer_fw_load; 62 module_param(defer_fw_load, bool, 0644); 63 MODULE_PARM_DESC(defer_fw_load, 64 "Defer FW loading until device is opened (default:disable)"); 65 66 /* cross componnet debug message flag */ 67 int dbg_level; 68 module_param(dbg_level, int, 0644); 69 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)"); 70 71 /* log function switch */ 72 int dbg_func = 2; 73 module_param(dbg_func, int, 0644); 74 MODULE_PARM_DESC(dbg_func, 75 "log function switch non/trace_printk/printk (default:printk)"); 76 77 int mipicsi_flag; 78 module_param(mipicsi_flag, int, 0644); 79 MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm"); 80 81 static char firmware_name[256]; 82 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0); 83 MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name."); 84 85 /*set to 16x16 since this is the amount of lines and pixels the sensor 86 exports extra. If these are kept at the 10x8 that they were on, in yuv 87 downscaling modes incorrect resolutions where requested to the sensor 88 driver with strange outcomes as a result. The proper way tot do this 89 would be to have a list of tables the specify the sensor res, mipi rec, 90 output res, and isp output res. however since we do not have this yet, 91 the chosen solution is the next best thing. */ 92 int pad_w = 16; 93 module_param(pad_w, int, 0644); 94 MODULE_PARM_DESC(pad_w, "extra data for ISP processing"); 95 96 int pad_h = 16; 97 module_param(pad_h, int, 0644); 98 MODULE_PARM_DESC(pad_h, "extra data for ISP processing"); 99 100 /* 101 * FIXME: this is a hack to make easier to support ISP2401 variant. 102 * As a given system will either be ISP2401 or not, we can just use 103 * a boolean, in order to replace existing #ifdef ISP2401 everywhere. 104 * 105 * Once this driver gets into a better shape, however, the best would 106 * be to replace this to something stored inside atomisp allocated 107 * structures. 108 */ 109 110 struct device *atomisp_dev; 111 112 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = { 113 { 114 .width = ISP_FREQ_RULE_ANY, 115 .height = ISP_FREQ_RULE_ANY, 116 .fps = ISP_FREQ_RULE_ANY, 117 .isp_freq = ISP_FREQ_400MHZ, 118 .run_mode = ATOMISP_RUN_MODE_VIDEO, 119 }, 120 { 121 .width = ISP_FREQ_RULE_ANY, 122 .height = ISP_FREQ_RULE_ANY, 123 .fps = ISP_FREQ_RULE_ANY, 124 .isp_freq = ISP_FREQ_400MHZ, 125 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 126 }, 127 { 128 .width = ISP_FREQ_RULE_ANY, 129 .height = ISP_FREQ_RULE_ANY, 130 .fps = ISP_FREQ_RULE_ANY, 131 .isp_freq = ISP_FREQ_400MHZ, 132 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 133 }, 134 { 135 .width = ISP_FREQ_RULE_ANY, 136 .height = ISP_FREQ_RULE_ANY, 137 .fps = ISP_FREQ_RULE_ANY, 138 .isp_freq = ISP_FREQ_400MHZ, 139 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 140 }, 141 { 142 .width = ISP_FREQ_RULE_ANY, 143 .height = ISP_FREQ_RULE_ANY, 144 .fps = ISP_FREQ_RULE_ANY, 145 .isp_freq = ISP_FREQ_457MHZ, 146 .run_mode = ATOMISP_RUN_MODE_SDV, 147 }, 148 }; 149 150 /* Merrifield and Moorefield DFS rules */ 151 static const struct atomisp_dfs_config dfs_config_merr = { 152 .lowest_freq = ISP_FREQ_200MHZ, 153 .max_freq_at_vmin = ISP_FREQ_400MHZ, 154 .highest_freq = ISP_FREQ_457MHZ, 155 .dfs_table = dfs_rules_merr, 156 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr), 157 }; 158 159 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = { 160 { 161 .width = ISP_FREQ_RULE_ANY, 162 .height = ISP_FREQ_RULE_ANY, 163 .fps = ISP_FREQ_RULE_ANY, 164 .isp_freq = ISP_FREQ_400MHZ, 165 .run_mode = ATOMISP_RUN_MODE_VIDEO, 166 }, 167 { 168 .width = ISP_FREQ_RULE_ANY, 169 .height = ISP_FREQ_RULE_ANY, 170 .fps = ISP_FREQ_RULE_ANY, 171 .isp_freq = ISP_FREQ_400MHZ, 172 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 173 }, 174 { 175 .width = ISP_FREQ_RULE_ANY, 176 .height = ISP_FREQ_RULE_ANY, 177 .fps = ISP_FREQ_RULE_ANY, 178 .isp_freq = ISP_FREQ_400MHZ, 179 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 180 }, 181 { 182 .width = ISP_FREQ_RULE_ANY, 183 .height = ISP_FREQ_RULE_ANY, 184 .fps = ISP_FREQ_RULE_ANY, 185 .isp_freq = ISP_FREQ_400MHZ, 186 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 187 }, 188 { 189 .width = ISP_FREQ_RULE_ANY, 190 .height = ISP_FREQ_RULE_ANY, 191 .fps = ISP_FREQ_RULE_ANY, 192 .isp_freq = ISP_FREQ_400MHZ, 193 .run_mode = ATOMISP_RUN_MODE_SDV, 194 }, 195 }; 196 197 static const struct atomisp_dfs_config dfs_config_merr_1179 = { 198 .lowest_freq = ISP_FREQ_200MHZ, 199 .max_freq_at_vmin = ISP_FREQ_400MHZ, 200 .highest_freq = ISP_FREQ_400MHZ, 201 .dfs_table = dfs_rules_merr_1179, 202 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179), 203 }; 204 205 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = { 206 { 207 .width = 1920, 208 .height = 1080, 209 .fps = 30, 210 .isp_freq = ISP_FREQ_266MHZ, 211 .run_mode = ATOMISP_RUN_MODE_VIDEO, 212 }, 213 { 214 .width = 1080, 215 .height = 1920, 216 .fps = 30, 217 .isp_freq = ISP_FREQ_266MHZ, 218 .run_mode = ATOMISP_RUN_MODE_VIDEO, 219 }, 220 { 221 .width = 1920, 222 .height = 1080, 223 .fps = 45, 224 .isp_freq = ISP_FREQ_320MHZ, 225 .run_mode = ATOMISP_RUN_MODE_VIDEO, 226 }, 227 { 228 .width = 1080, 229 .height = 1920, 230 .fps = 45, 231 .isp_freq = ISP_FREQ_320MHZ, 232 .run_mode = ATOMISP_RUN_MODE_VIDEO, 233 }, 234 { 235 .width = ISP_FREQ_RULE_ANY, 236 .height = ISP_FREQ_RULE_ANY, 237 .fps = 60, 238 .isp_freq = ISP_FREQ_356MHZ, 239 .run_mode = ATOMISP_RUN_MODE_VIDEO, 240 }, 241 { 242 .width = ISP_FREQ_RULE_ANY, 243 .height = ISP_FREQ_RULE_ANY, 244 .fps = ISP_FREQ_RULE_ANY, 245 .isp_freq = ISP_FREQ_200MHZ, 246 .run_mode = ATOMISP_RUN_MODE_VIDEO, 247 }, 248 { 249 .width = ISP_FREQ_RULE_ANY, 250 .height = ISP_FREQ_RULE_ANY, 251 .fps = ISP_FREQ_RULE_ANY, 252 .isp_freq = ISP_FREQ_400MHZ, 253 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 254 }, 255 { 256 .width = ISP_FREQ_RULE_ANY, 257 .height = ISP_FREQ_RULE_ANY, 258 .fps = ISP_FREQ_RULE_ANY, 259 .isp_freq = ISP_FREQ_400MHZ, 260 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 261 }, 262 { 263 .width = ISP_FREQ_RULE_ANY, 264 .height = ISP_FREQ_RULE_ANY, 265 .fps = ISP_FREQ_RULE_ANY, 266 .isp_freq = ISP_FREQ_200MHZ, 267 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 268 }, 269 { 270 .width = ISP_FREQ_RULE_ANY, 271 .height = ISP_FREQ_RULE_ANY, 272 .fps = ISP_FREQ_RULE_ANY, 273 .isp_freq = ISP_FREQ_400MHZ, 274 .run_mode = ATOMISP_RUN_MODE_SDV, 275 }, 276 }; 277 278 static struct atomisp_dfs_config dfs_config_merr_117a = { 279 .lowest_freq = ISP_FREQ_200MHZ, 280 .max_freq_at_vmin = ISP_FREQ_200MHZ, 281 .highest_freq = ISP_FREQ_400MHZ, 282 .dfs_table = dfs_rules_merr_117a, 283 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a), 284 }; 285 286 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = { 287 { 288 .width = ISP_FREQ_RULE_ANY, 289 .height = ISP_FREQ_RULE_ANY, 290 .fps = ISP_FREQ_RULE_ANY, 291 .isp_freq = ISP_FREQ_400MHZ, 292 .run_mode = ATOMISP_RUN_MODE_VIDEO, 293 }, 294 { 295 .width = ISP_FREQ_RULE_ANY, 296 .height = ISP_FREQ_RULE_ANY, 297 .fps = ISP_FREQ_RULE_ANY, 298 .isp_freq = ISP_FREQ_400MHZ, 299 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 300 }, 301 { 302 .width = ISP_FREQ_RULE_ANY, 303 .height = ISP_FREQ_RULE_ANY, 304 .fps = ISP_FREQ_RULE_ANY, 305 .isp_freq = ISP_FREQ_400MHZ, 306 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 307 }, 308 { 309 .width = ISP_FREQ_RULE_ANY, 310 .height = ISP_FREQ_RULE_ANY, 311 .fps = ISP_FREQ_RULE_ANY, 312 .isp_freq = ISP_FREQ_400MHZ, 313 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 314 }, 315 { 316 .width = ISP_FREQ_RULE_ANY, 317 .height = ISP_FREQ_RULE_ANY, 318 .fps = ISP_FREQ_RULE_ANY, 319 .isp_freq = ISP_FREQ_400MHZ, 320 .run_mode = ATOMISP_RUN_MODE_SDV, 321 }, 322 }; 323 324 static const struct atomisp_dfs_config dfs_config_byt = { 325 .lowest_freq = ISP_FREQ_200MHZ, 326 .max_freq_at_vmin = ISP_FREQ_400MHZ, 327 .highest_freq = ISP_FREQ_400MHZ, 328 .dfs_table = dfs_rules_byt, 329 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt), 330 }; 331 332 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = { 333 { 334 .width = ISP_FREQ_RULE_ANY, 335 .height = ISP_FREQ_RULE_ANY, 336 .fps = ISP_FREQ_RULE_ANY, 337 .isp_freq = ISP_FREQ_320MHZ, 338 .run_mode = ATOMISP_RUN_MODE_VIDEO, 339 }, 340 { 341 .width = ISP_FREQ_RULE_ANY, 342 .height = ISP_FREQ_RULE_ANY, 343 .fps = ISP_FREQ_RULE_ANY, 344 .isp_freq = ISP_FREQ_356MHZ, 345 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 346 }, 347 { 348 .width = ISP_FREQ_RULE_ANY, 349 .height = ISP_FREQ_RULE_ANY, 350 .fps = ISP_FREQ_RULE_ANY, 351 .isp_freq = ISP_FREQ_320MHZ, 352 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 353 }, 354 { 355 .width = ISP_FREQ_RULE_ANY, 356 .height = ISP_FREQ_RULE_ANY, 357 .fps = ISP_FREQ_RULE_ANY, 358 .isp_freq = ISP_FREQ_320MHZ, 359 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 360 }, 361 { 362 .width = 1280, 363 .height = 720, 364 .fps = ISP_FREQ_RULE_ANY, 365 .isp_freq = ISP_FREQ_320MHZ, 366 .run_mode = ATOMISP_RUN_MODE_SDV, 367 }, 368 { 369 .width = ISP_FREQ_RULE_ANY, 370 .height = ISP_FREQ_RULE_ANY, 371 .fps = ISP_FREQ_RULE_ANY, 372 .isp_freq = ISP_FREQ_356MHZ, 373 .run_mode = ATOMISP_RUN_MODE_SDV, 374 }, 375 }; 376 377 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = { 378 { 379 .width = ISP_FREQ_RULE_ANY, 380 .height = ISP_FREQ_RULE_ANY, 381 .fps = ISP_FREQ_RULE_ANY, 382 .isp_freq = ISP_FREQ_356MHZ, 383 .run_mode = ATOMISP_RUN_MODE_VIDEO, 384 }, 385 { 386 .width = ISP_FREQ_RULE_ANY, 387 .height = ISP_FREQ_RULE_ANY, 388 .fps = ISP_FREQ_RULE_ANY, 389 .isp_freq = ISP_FREQ_356MHZ, 390 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 391 }, 392 { 393 .width = ISP_FREQ_RULE_ANY, 394 .height = ISP_FREQ_RULE_ANY, 395 .fps = ISP_FREQ_RULE_ANY, 396 .isp_freq = ISP_FREQ_320MHZ, 397 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 398 }, 399 { 400 .width = ISP_FREQ_RULE_ANY, 401 .height = ISP_FREQ_RULE_ANY, 402 .fps = ISP_FREQ_RULE_ANY, 403 .isp_freq = ISP_FREQ_320MHZ, 404 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 405 }, 406 { 407 .width = ISP_FREQ_RULE_ANY, 408 .height = ISP_FREQ_RULE_ANY, 409 .fps = ISP_FREQ_RULE_ANY, 410 .isp_freq = ISP_FREQ_356MHZ, 411 .run_mode = ATOMISP_RUN_MODE_SDV, 412 }, 413 }; 414 415 static const struct atomisp_dfs_config dfs_config_cht = { 416 .lowest_freq = ISP_FREQ_100MHZ, 417 .max_freq_at_vmin = ISP_FREQ_356MHZ, 418 .highest_freq = ISP_FREQ_356MHZ, 419 .dfs_table = dfs_rules_cht, 420 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht), 421 }; 422 423 /* This one should be visible also by atomisp_cmd.c */ 424 const struct atomisp_dfs_config dfs_config_cht_soc = { 425 .lowest_freq = ISP_FREQ_100MHZ, 426 .max_freq_at_vmin = ISP_FREQ_356MHZ, 427 .highest_freq = ISP_FREQ_356MHZ, 428 .dfs_table = dfs_rules_cht_soc, 429 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc), 430 }; 431 432 int atomisp_video_init(struct atomisp_video_pipe *video, const char *name, 433 unsigned int run_mode) 434 { 435 int ret; 436 const char *direction; 437 438 switch (video->type) { 439 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 440 direction = "output"; 441 video->pad.flags = MEDIA_PAD_FL_SINK; 442 video->vdev.fops = &atomisp_fops; 443 video->vdev.ioctl_ops = &atomisp_ioctl_ops; 444 video->vdev.lock = &video->isp->mutex; 445 break; 446 default: 447 return -EINVAL; 448 } 449 450 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad); 451 if (ret < 0) 452 return ret; 453 454 /* Initialize the video device. */ 455 snprintf(video->vdev.name, sizeof(video->vdev.name), 456 "ATOMISP ISP %s %s", name, direction); 457 video->vdev.release = video_device_release_empty; 458 video_set_drvdata(&video->vdev, video->isp); 459 video->default_run_mode = run_mode; 460 461 return 0; 462 } 463 464 void atomisp_video_unregister(struct atomisp_video_pipe *video) 465 { 466 if (video_is_registered(&video->vdev)) { 467 media_entity_cleanup(&video->vdev.entity); 468 video_unregister_device(&video->vdev); 469 } 470 } 471 472 static int atomisp_save_iunit_reg(struct atomisp_device *isp) 473 { 474 struct pci_dev *pdev = to_pci_dev(isp->dev); 475 476 dev_dbg(isp->dev, "%s\n", __func__); 477 478 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts); 479 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */ 480 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap); 481 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr); 482 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data); 483 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr); 484 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control); 485 486 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs); 487 /* Ensure read/write combining is enabled. */ 488 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control); 489 isp->saved_regs.i_control |= 490 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING | 491 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING; 492 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, 493 &isp->saved_regs.csi_access_viol); 494 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL, 495 &isp->saved_regs.csi_rcomp_config); 496 /* 497 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE. 498 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path 499 * and sensor sending "continuous clock". 500 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence 501 * is missed, and IUNIT can hang. 502 * For both issues, setting this bit is a workaround. 503 */ 504 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE; 505 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 506 &isp->saved_regs.csi_afe_dly); 507 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, 508 &isp->saved_regs.csi_control); 509 if (isp->media_dev.hw_revision >= 510 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT)) 511 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN; 512 /* 513 * On CHT CSI_READY bit should be enabled before stream on 514 */ 515 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << 516 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0))) 517 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY; 518 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, 519 &isp->saved_regs.csi_afe_rcomp_config); 520 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL, 521 &isp->saved_regs.csi_afe_hs_control); 522 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL, 523 &isp->saved_regs.csi_deadline_control); 524 return 0; 525 } 526 527 static int __maybe_unused atomisp_restore_iunit_reg(struct atomisp_device *isp) 528 { 529 struct pci_dev *pdev = to_pci_dev(isp->dev); 530 531 dev_dbg(isp->dev, "%s\n", __func__); 532 533 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts); 534 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr); 535 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap); 536 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr); 537 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data); 538 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr); 539 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control); 540 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control); 541 542 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs); 543 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, 544 isp->saved_regs.csi_access_viol); 545 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL, 546 isp->saved_regs.csi_rcomp_config); 547 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 548 isp->saved_regs.csi_afe_dly); 549 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, 550 isp->saved_regs.csi_control); 551 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, 552 isp->saved_regs.csi_afe_rcomp_config); 553 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL, 554 isp->saved_regs.csi_afe_hs_control); 555 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL, 556 isp->saved_regs.csi_deadline_control); 557 558 /* 559 * for MRFLD, Software/firmware needs to write a 1 to bit0 560 * of the register at CSI_RECEIVER_SELECTION_REG to enable 561 * SH CSI backend write 0 will enable Arasan CSI backend, 562 * which has bugs(like sighting:4567697 and 4567699) and 563 * will be removed in B0 564 */ 565 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); 566 return 0; 567 } 568 569 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp) 570 { 571 struct pci_dev *pdev = to_pci_dev(isp->dev); 572 u32 irq; 573 unsigned long flags; 574 575 spin_lock_irqsave(&isp->lock, flags); 576 577 /* 578 * MRFLD HAS requirement: cannot power off i-unit if 579 * ISP has IRQ not serviced. 580 * So, here we need to check if there is any pending 581 * IRQ, if so, waiting for it to be served 582 */ 583 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 584 irq &= BIT(INTR_IIR); 585 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 586 587 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 588 if (!(irq & BIT(INTR_IIR))) 589 goto done; 590 591 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF); 592 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq); 593 if (irq != 0) { 594 dev_err(isp->dev, 595 "%s: fail to clear isp interrupt status reg=0x%x\n", 596 __func__, irq); 597 spin_unlock_irqrestore(&isp->lock, flags); 598 return -EAGAIN; 599 } else { 600 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 601 irq &= BIT(INTR_IIR); 602 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 603 604 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 605 if (!(irq & BIT(INTR_IIR))) { 606 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0); 607 goto done; 608 } 609 dev_err(isp->dev, 610 "%s: error in iunit interrupt. status reg=0x%x\n", 611 __func__, irq); 612 spin_unlock_irqrestore(&isp->lock, flags); 613 return -EAGAIN; 614 } 615 done: 616 /* 617 * MRFLD WORKAROUND: 618 * before powering off IUNIT, clear the pending interrupts 619 * and disable the interrupt. driver should avoid writing 0 620 * to IIR. It could block subsequent interrupt messages. 621 * HW sighting:4568410. 622 */ 623 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 624 irq &= ~BIT(INTR_IER); 625 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 626 627 atomisp_msi_irq_uninit(isp); 628 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 629 spin_unlock_irqrestore(&isp->lock, flags); 630 631 return 0; 632 } 633 634 /* 635 * WA for DDR DVFS enable/disable 636 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS 637 */ 638 static void punit_ddr_dvfs_enable(bool enable) 639 { 640 int door_bell = 1 << 8; 641 int max_wait = 30; 642 int reg; 643 644 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®); 645 if (enable) { 646 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1); 647 } else { 648 reg |= (MRFLD_BIT1 | door_bell); 649 reg &= ~(MRFLD_BIT0); 650 } 651 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg); 652 653 /* Check Req_ACK to see freq status, wait until door_bell is cleared */ 654 while ((reg & door_bell) && max_wait--) { 655 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®); 656 usleep_range(100, 500); 657 } 658 659 if (max_wait == -1) 660 pr_info("DDR DVFS, door bell is not cleared within 3ms\n"); 661 } 662 663 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable) 664 { 665 unsigned long timeout; 666 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON : 667 MRFLD_ISPSSPM0_IUNIT_POWER_OFF; 668 669 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off"); 670 671 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */ 672 if (IS_CHT && enable) 673 punit_ddr_dvfs_enable(false); 674 675 /* 676 * FIXME:WA for ECS28A, with this sleep, CTS 677 * android.hardware.camera2.cts.CameraDeviceTest#testCameraDeviceAbort 678 * PASS, no impact on other platforms 679 */ 680 if (IS_BYT && enable) 681 msleep(10); 682 683 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */ 684 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, 685 val, MRFLD_ISPSSPM0_ISPSSC_MASK); 686 687 /* WA:Enable DVFS */ 688 if (IS_CHT && !enable) 689 punit_ddr_dvfs_enable(true); 690 691 /* 692 * There should be no IUNIT access while power-down is 693 * in progress. HW sighting: 4567865. 694 * Wait up to 50 ms for the IUNIT to shut down. 695 * And we do the same for power on. 696 */ 697 timeout = jiffies + msecs_to_jiffies(50); 698 do { 699 u32 tmp; 700 701 /* Wait until ISPSSPM0 bit[25:24] shows the right value */ 702 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp); 703 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK; 704 if (tmp == val) { 705 trace_ipu_cstate(enable); 706 return 0; 707 } 708 709 if (time_after(jiffies, timeout)) 710 break; 711 712 /* FIXME: experienced value for delay */ 713 usleep_range(100, 150); 714 } while (1); 715 716 if (enable) 717 msleep(10); 718 719 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off"); 720 return -EBUSY; 721 } 722 723 int atomisp_power_off(struct device *dev) 724 { 725 struct atomisp_device *isp = dev_get_drvdata(dev); 726 struct pci_dev *pdev = to_pci_dev(dev); 727 int ret; 728 u32 reg; 729 730 atomisp_css_uninit(isp); 731 732 ret = atomisp_mrfld_pre_power_down(isp); 733 if (ret) 734 return ret; 735 736 /* 737 * MRFLD IUNIT DPHY is located in an always-power-on island 738 * MRFLD HW design need all CSI ports are disabled before 739 * powering down the IUNIT. 740 */ 741 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, ®); 742 reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK; 743 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg); 744 745 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 746 return atomisp_mrfld_power(isp, false); 747 } 748 749 int atomisp_power_on(struct device *dev) 750 { 751 struct atomisp_device *isp = (struct atomisp_device *) 752 dev_get_drvdata(dev); 753 int ret; 754 755 ret = atomisp_mrfld_power(isp, true); 756 if (ret) 757 return ret; 758 759 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency); 760 761 /*restore register values for iUnit and iUnitPHY registers*/ 762 if (isp->saved_regs.pcicmdsts) 763 atomisp_restore_iunit_reg(isp); 764 765 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 766 767 return atomisp_css_init(isp); 768 } 769 770 static int __maybe_unused atomisp_suspend(struct device *dev) 771 { 772 struct atomisp_device *isp = (struct atomisp_device *) 773 dev_get_drvdata(dev); 774 /* FIXME: only has one isp_subdev at present */ 775 struct atomisp_sub_device *asd = &isp->asd[0]; 776 unsigned long flags; 777 778 /* 779 * FIXME: Suspend is not supported by sensors. Abort if any video 780 * node was opened. 781 */ 782 if (atomisp_dev_users(isp)) 783 return -EBUSY; 784 785 spin_lock_irqsave(&isp->lock, flags); 786 if (asd->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) { 787 spin_unlock_irqrestore(&isp->lock, flags); 788 dev_err(isp->dev, "atomisp cannot suspend at this time.\n"); 789 return -EINVAL; 790 } 791 spin_unlock_irqrestore(&isp->lock, flags); 792 793 return atomisp_power_off(dev); 794 } 795 796 static int __maybe_unused atomisp_resume(struct device *dev) 797 { 798 return atomisp_power_on(dev); 799 } 800 801 int atomisp_csi_lane_config(struct atomisp_device *isp) 802 { 803 struct pci_dev *pdev = to_pci_dev(isp->dev); 804 static const struct { 805 u8 code; 806 u8 lanes[MRFLD_PORT_NUM]; 807 } portconfigs[] = { 808 /* Tangier/Merrifield available lane configurations */ 809 { 0x00, { 4, 1, 0 } }, /* 00000 */ 810 { 0x01, { 3, 1, 0 } }, /* 00001 */ 811 { 0x02, { 2, 1, 0 } }, /* 00010 */ 812 { 0x03, { 1, 1, 0 } }, /* 00011 */ 813 { 0x04, { 2, 1, 2 } }, /* 00100 */ 814 { 0x08, { 3, 1, 1 } }, /* 01000 */ 815 { 0x09, { 2, 1, 1 } }, /* 01001 */ 816 { 0x0a, { 1, 1, 1 } }, /* 01010 */ 817 818 /* Anniedale/Moorefield only configurations */ 819 { 0x10, { 4, 2, 0 } }, /* 10000 */ 820 { 0x11, { 3, 2, 0 } }, /* 10001 */ 821 { 0x12, { 2, 2, 0 } }, /* 10010 */ 822 { 0x13, { 1, 2, 0 } }, /* 10011 */ 823 { 0x14, { 2, 2, 2 } }, /* 10100 */ 824 { 0x18, { 3, 2, 1 } }, /* 11000 */ 825 { 0x19, { 2, 2, 1 } }, /* 11001 */ 826 { 0x1a, { 1, 2, 1 } }, /* 11010 */ 827 }; 828 829 unsigned int i, j; 830 u8 sensor_lanes[MRFLD_PORT_NUM] = { 0 }; 831 u32 csi_control; 832 int nportconfigs; 833 u32 port_config_mask; 834 int port3_lanes_shift; 835 836 if (isp->media_dev.hw_revision < 837 ATOMISP_HW_REVISION_ISP2401_LEGACY << 838 ATOMISP_HW_REVISION_SHIFT) { 839 /* Merrifield */ 840 port_config_mask = MRFLD_PORT_CONFIG_MASK; 841 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT; 842 } else { 843 /* Moorefield / Cherryview */ 844 port_config_mask = CHV_PORT_CONFIG_MASK; 845 port3_lanes_shift = CHV_PORT3_LANES_SHIFT; 846 } 847 848 if (isp->media_dev.hw_revision < 849 ATOMISP_HW_REVISION_ISP2401 << 850 ATOMISP_HW_REVISION_SHIFT) { 851 /* Merrifield / Moorefield legacy input system */ 852 nportconfigs = MRFLD_PORT_CONFIG_NUM; 853 } else { 854 /* Moorefield / Cherryview new input system */ 855 nportconfigs = ARRAY_SIZE(portconfigs); 856 } 857 858 for (i = 0; i < isp->input_cnt; i++) { 859 struct camera_mipi_info *mipi_info; 860 861 if (isp->inputs[i].type != RAW_CAMERA && 862 isp->inputs[i].type != SOC_CAMERA) 863 continue; 864 865 mipi_info = atomisp_to_sensor_mipi_info(isp->inputs[i].camera); 866 if (!mipi_info) 867 continue; 868 869 switch (mipi_info->port) { 870 case ATOMISP_CAMERA_PORT_PRIMARY: 871 sensor_lanes[0] = mipi_info->num_lanes; 872 break; 873 case ATOMISP_CAMERA_PORT_SECONDARY: 874 sensor_lanes[1] = mipi_info->num_lanes; 875 break; 876 case ATOMISP_CAMERA_PORT_TERTIARY: 877 sensor_lanes[2] = mipi_info->num_lanes; 878 break; 879 default: 880 dev_err(isp->dev, 881 "%s: invalid port: %d for the %dth sensor\n", 882 __func__, mipi_info->port, i); 883 return -EINVAL; 884 } 885 } 886 887 for (i = 0; i < nportconfigs; i++) { 888 for (j = 0; j < MRFLD_PORT_NUM; j++) 889 if (sensor_lanes[j] && 890 sensor_lanes[j] != portconfigs[i].lanes[j]) 891 break; 892 893 if (j == MRFLD_PORT_NUM) 894 break; /* Found matching setting */ 895 } 896 897 if (i >= nportconfigs) { 898 dev_err(isp->dev, 899 "%s: could not find the CSI port setting for %d-%d-%d\n", 900 __func__, 901 sensor_lanes[0], sensor_lanes[1], sensor_lanes[2]); 902 return -EINVAL; 903 } 904 905 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control); 906 csi_control &= ~port_config_mask; 907 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT) 908 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT)) 909 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT)) 910 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT)) 911 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT) 912 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT) 913 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift); 914 915 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control); 916 917 dev_dbg(isp->dev, 918 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n", 919 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1], 920 portconfigs[i].lanes[2], csi_control); 921 922 return 0; 923 } 924 925 static int atomisp_subdev_probe(struct atomisp_device *isp) 926 { 927 const struct atomisp_platform_data *pdata; 928 struct intel_v4l2_subdev_table *subdevs; 929 int ret, raw_index = -1, count; 930 931 pdata = atomisp_get_platform_data(); 932 if (!pdata) { 933 dev_err(isp->dev, "no platform data available\n"); 934 return 0; 935 } 936 937 /* FIXME: should return -EPROBE_DEFER if not all subdevs were probed */ 938 for (count = 0; count < SUBDEV_WAIT_TIMEOUT_MAX_COUNT; count++) { 939 int camera_count = 0; 940 941 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { 942 if (subdevs->type == RAW_CAMERA || 943 subdevs->type == SOC_CAMERA) 944 camera_count++; 945 } 946 if (camera_count) 947 break; 948 msleep(SUBDEV_WAIT_TIMEOUT); 949 } 950 /* Wait more time to give more time for subdev init code to finish */ 951 msleep(5 * SUBDEV_WAIT_TIMEOUT); 952 953 /* FIXME: should, instead, use I2C probe */ 954 955 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { 956 struct v4l2_subdev *subdev; 957 struct i2c_board_info *board_info = 958 &subdevs->v4l2_subdev.board_info; 959 struct i2c_adapter *adapter = 960 i2c_get_adapter(subdevs->v4l2_subdev.i2c_adapter_id); 961 962 dev_info(isp->dev, "Probing Subdev %s\n", board_info->type); 963 964 if (!adapter) { 965 dev_err(isp->dev, 966 "Failed to find i2c adapter for subdev %s\n", 967 board_info->type); 968 break; 969 } 970 971 /* In G-Min, the sensor devices will already be probed 972 * (via ACPI) and registered, do not create new 973 * ones */ 974 subdev = atomisp_gmin_find_subdev(adapter, board_info); 975 if (!subdev) { 976 dev_warn(isp->dev, "Subdev %s not found\n", 977 board_info->type); 978 continue; 979 } 980 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdev); 981 if (ret) { 982 dev_warn(isp->dev, "Subdev %s detection fail\n", 983 board_info->type); 984 continue; 985 } 986 987 if (!subdev) { 988 dev_warn(isp->dev, "Subdev %s detection fail\n", 989 board_info->type); 990 continue; 991 } 992 993 dev_info(isp->dev, "Subdev %s successfully register\n", 994 board_info->type); 995 996 switch (subdevs->type) { 997 case RAW_CAMERA: 998 dev_dbg(isp->dev, "raw_index: %d\n", raw_index); 999 raw_index = isp->input_cnt; 1000 fallthrough; 1001 case SOC_CAMERA: 1002 dev_dbg(isp->dev, "SOC_INDEX: %d\n", isp->input_cnt); 1003 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) { 1004 dev_warn(isp->dev, 1005 "too many atomisp inputs, ignored\n"); 1006 break; 1007 } 1008 1009 isp->inputs[isp->input_cnt].type = subdevs->type; 1010 isp->inputs[isp->input_cnt].port = subdevs->port; 1011 isp->inputs[isp->input_cnt].camera = subdev; 1012 isp->inputs[isp->input_cnt].sensor_index = 0; 1013 /* 1014 * initialize the subdev frame size, then next we can 1015 * judge whether frame_size store effective value via 1016 * pixel_format. 1017 */ 1018 isp->inputs[isp->input_cnt].frame_size.pixel_format = 0; 1019 isp->input_cnt++; 1020 break; 1021 case CAMERA_MOTOR: 1022 if (isp->motor) { 1023 dev_warn(isp->dev, 1024 "too many atomisp motors, ignored %s\n", 1025 board_info->type); 1026 continue; 1027 } 1028 isp->motor = subdev; 1029 break; 1030 case LED_FLASH: 1031 case XENON_FLASH: 1032 if (isp->flash) { 1033 dev_warn(isp->dev, 1034 "too many atomisp flash devices, ignored %s\n", 1035 board_info->type); 1036 continue; 1037 } 1038 isp->flash = subdev; 1039 break; 1040 default: 1041 dev_dbg(isp->dev, "unknown subdev probed\n"); 1042 break; 1043 } 1044 } 1045 1046 /* 1047 * HACK: Currently VCM belongs to primary sensor only, but correct 1048 * approach must be to acquire from platform code which sensor 1049 * owns it. 1050 */ 1051 if (isp->motor && raw_index >= 0) 1052 isp->inputs[raw_index].motor = isp->motor; 1053 1054 /* Proceed even if no modules detected. For COS mode and no modules. */ 1055 if (!isp->input_cnt) 1056 dev_warn(isp->dev, "no camera attached or fail to detect\n"); 1057 else 1058 dev_info(isp->dev, "detected %d camera sensors\n", 1059 isp->input_cnt); 1060 1061 return atomisp_csi_lane_config(isp); 1062 } 1063 1064 static void atomisp_unregister_entities(struct atomisp_device *isp) 1065 { 1066 unsigned int i; 1067 struct v4l2_subdev *sd, *next; 1068 1069 for (i = 0; i < isp->num_of_streams; i++) 1070 atomisp_subdev_unregister_entities(&isp->asd[i]); 1071 atomisp_tpg_unregister_entities(&isp->tpg); 1072 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) 1073 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); 1074 1075 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list) 1076 v4l2_device_unregister_subdev(sd); 1077 1078 v4l2_device_unregister(&isp->v4l2_dev); 1079 media_device_unregister(&isp->media_dev); 1080 media_device_cleanup(&isp->media_dev); 1081 } 1082 1083 static int atomisp_register_entities(struct atomisp_device *isp) 1084 { 1085 int ret = 0; 1086 unsigned int i; 1087 1088 isp->media_dev.dev = isp->dev; 1089 1090 strscpy(isp->media_dev.model, "Intel Atom ISP", 1091 sizeof(isp->media_dev.model)); 1092 1093 media_device_init(&isp->media_dev); 1094 isp->v4l2_dev.mdev = &isp->media_dev; 1095 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev); 1096 if (ret < 0) { 1097 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n", 1098 __func__, ret); 1099 goto v4l2_device_failed; 1100 } 1101 1102 ret = atomisp_subdev_probe(isp); 1103 if (ret < 0) 1104 goto csi_and_subdev_probe_failed; 1105 1106 /* Register internal entities */ 1107 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { 1108 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i], 1109 &isp->v4l2_dev); 1110 if (ret == 0) 1111 continue; 1112 1113 /* error case */ 1114 dev_err(isp->dev, "failed to register the CSI port: %d\n", i); 1115 /* deregister all registered CSI ports */ 1116 while (i--) 1117 atomisp_mipi_csi2_unregister_entities( 1118 &isp->csi2_port[i]); 1119 1120 goto csi_and_subdev_probe_failed; 1121 } 1122 1123 ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev); 1124 if (ret < 0) { 1125 dev_err(isp->dev, "atomisp_tpg_register_entities\n"); 1126 goto tpg_register_failed; 1127 } 1128 1129 for (i = 0; i < isp->num_of_streams; i++) { 1130 struct atomisp_sub_device *asd = &isp->asd[i]; 1131 1132 ret = atomisp_subdev_register_subdev(asd, &isp->v4l2_dev); 1133 if (ret < 0) { 1134 dev_err(isp->dev, "atomisp_subdev_register_subdev fail\n"); 1135 for (; i > 0; i--) 1136 atomisp_subdev_unregister_entities( 1137 &isp->asd[i - 1]); 1138 goto subdev_register_failed; 1139 } 1140 } 1141 1142 for (i = 0; i < isp->num_of_streams; i++) { 1143 struct atomisp_sub_device *asd = &isp->asd[i]; 1144 1145 init_completion(&asd->init_done); 1146 1147 asd->delayed_init_workq = 1148 alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE, 1149 1); 1150 if (!asd->delayed_init_workq) { 1151 dev_err(isp->dev, 1152 "Failed to initialize delayed init workq\n"); 1153 ret = -ENOMEM; 1154 1155 for (; i > 0; i--) 1156 destroy_workqueue(isp->asd[i - 1]. 1157 delayed_init_workq); 1158 goto wq_alloc_failed; 1159 } 1160 INIT_WORK(&asd->delayed_init_work, atomisp_delayed_init_work); 1161 } 1162 1163 for (i = 0; i < isp->input_cnt; i++) { 1164 if (isp->inputs[i].port >= ATOMISP_CAMERA_NR_PORTS) { 1165 dev_err(isp->dev, "isp->inputs port %d not supported\n", 1166 isp->inputs[i].port); 1167 ret = -EINVAL; 1168 goto link_failed; 1169 } 1170 } 1171 1172 if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) { 1173 dev_dbg(isp->dev, 1174 "TPG detected, camera_cnt: %d\n", isp->input_cnt); 1175 isp->inputs[isp->input_cnt].type = TEST_PATTERN; 1176 isp->inputs[isp->input_cnt].port = -1; 1177 isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd; 1178 } else { 1179 dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n"); 1180 } 1181 1182 return 0; 1183 1184 link_failed: 1185 for (i = 0; i < isp->num_of_streams; i++) 1186 destroy_workqueue(isp->asd[i]. 1187 delayed_init_workq); 1188 wq_alloc_failed: 1189 for (i = 0; i < isp->num_of_streams; i++) 1190 atomisp_subdev_unregister_entities( 1191 &isp->asd[i]); 1192 subdev_register_failed: 1193 atomisp_tpg_unregister_entities(&isp->tpg); 1194 tpg_register_failed: 1195 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) 1196 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); 1197 csi_and_subdev_probe_failed: 1198 v4l2_device_unregister(&isp->v4l2_dev); 1199 v4l2_device_failed: 1200 media_device_unregister(&isp->media_dev); 1201 media_device_cleanup(&isp->media_dev); 1202 return ret; 1203 } 1204 1205 static int atomisp_register_device_nodes(struct atomisp_device *isp) 1206 { 1207 int i, err; 1208 1209 for (i = 0; i < isp->num_of_streams; i++) { 1210 err = atomisp_subdev_register_video_nodes(&isp->asd[i], &isp->v4l2_dev); 1211 if (err) 1212 return err; 1213 } 1214 1215 err = atomisp_create_pads_links(isp); 1216 if (err) 1217 return err; 1218 1219 err = v4l2_device_register_subdev_nodes(&isp->v4l2_dev); 1220 if (err) 1221 return err; 1222 1223 return media_device_register(&isp->media_dev); 1224 } 1225 1226 static int atomisp_initialize_modules(struct atomisp_device *isp) 1227 { 1228 int ret; 1229 1230 ret = atomisp_mipi_csi2_init(isp); 1231 if (ret < 0) { 1232 dev_err(isp->dev, "mipi csi2 initialization failed\n"); 1233 goto error_mipi_csi2; 1234 } 1235 1236 ret = atomisp_tpg_init(isp); 1237 if (ret < 0) { 1238 dev_err(isp->dev, "tpg initialization failed\n"); 1239 goto error_tpg; 1240 } 1241 1242 ret = atomisp_subdev_init(isp); 1243 if (ret < 0) { 1244 dev_err(isp->dev, "ISP subdev initialization failed\n"); 1245 goto error_isp_subdev; 1246 } 1247 1248 return 0; 1249 1250 error_isp_subdev: 1251 error_tpg: 1252 atomisp_tpg_cleanup(isp); 1253 error_mipi_csi2: 1254 atomisp_mipi_csi2_cleanup(isp); 1255 return ret; 1256 } 1257 1258 static void atomisp_uninitialize_modules(struct atomisp_device *isp) 1259 { 1260 atomisp_tpg_cleanup(isp); 1261 atomisp_mipi_csi2_cleanup(isp); 1262 } 1263 1264 const struct firmware * 1265 atomisp_load_firmware(struct atomisp_device *isp) 1266 { 1267 const struct firmware *fw; 1268 int rc; 1269 char *fw_path = NULL; 1270 1271 if (skip_fwload) 1272 return NULL; 1273 1274 if (firmware_name[0] != '\0') { 1275 fw_path = firmware_name; 1276 } else { 1277 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT) 1278 == ATOMISP_HW_REVISION_ISP2401) 1279 fw_path = "shisp_2401a0_v21.bin"; 1280 1281 if (isp->media_dev.hw_revision == 1282 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT) 1283 | ATOMISP_HW_STEPPING_A0)) 1284 fw_path = "shisp_2401a0_legacy_v21.bin"; 1285 1286 if (isp->media_dev.hw_revision == 1287 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT) 1288 | ATOMISP_HW_STEPPING_B0)) 1289 fw_path = "shisp_2400b0_v21.bin"; 1290 } 1291 1292 if (!fw_path) { 1293 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n", 1294 isp->media_dev.hw_revision); 1295 return NULL; 1296 } 1297 1298 rc = request_firmware(&fw, fw_path, isp->dev); 1299 if (rc) { 1300 dev_err(isp->dev, 1301 "atomisp: Error %d while requesting firmware %s\n", 1302 rc, fw_path); 1303 return NULL; 1304 } 1305 1306 return fw; 1307 } 1308 1309 /* 1310 * Check for flags the driver was compiled with against the PCI 1311 * device. Always returns true on other than ISP 2400. 1312 */ 1313 static bool is_valid_device(struct pci_dev *pdev, const struct pci_device_id *id) 1314 { 1315 const char *name; 1316 const char *product; 1317 1318 product = dmi_get_system_info(DMI_PRODUCT_NAME); 1319 1320 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { 1321 case ATOMISP_PCI_DEVICE_SOC_MRFLD: 1322 name = "Merrifield"; 1323 break; 1324 case ATOMISP_PCI_DEVICE_SOC_BYT: 1325 name = "Baytrail"; 1326 break; 1327 case ATOMISP_PCI_DEVICE_SOC_ANN: 1328 name = "Anniedale"; 1329 break; 1330 case ATOMISP_PCI_DEVICE_SOC_CHT: 1331 name = "Cherrytrail"; 1332 break; 1333 default: 1334 dev_err(&pdev->dev, "%s: unknown device ID %x04:%x04\n", 1335 product, id->vendor, id->device); 1336 return false; 1337 } 1338 1339 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) { 1340 dev_err(&pdev->dev, "%s revision %d is not unsupported\n", 1341 name, pdev->revision); 1342 return false; 1343 } 1344 1345 /* 1346 * FIXME: 1347 * remove the if once the driver become generic 1348 */ 1349 1350 #ifndef ISP2401 1351 if (IS_ISP2401) { 1352 dev_err(&pdev->dev, "Support for %s (ISP2401) was disabled at compile time\n", 1353 name); 1354 return false; 1355 } 1356 #else 1357 if (!IS_ISP2401) { 1358 dev_err(&pdev->dev, "Support for %s (ISP2400) was disabled at compile time\n", 1359 name); 1360 return false; 1361 } 1362 #endif 1363 1364 dev_info(&pdev->dev, "Detected %s version %d (ISP240%c) on %s\n", 1365 name, pdev->revision, IS_ISP2401 ? '1' : '0', product); 1366 1367 return true; 1368 } 1369 1370 #define ATOM_ISP_PCI_BAR 0 1371 1372 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1373 { 1374 const struct atomisp_platform_data *pdata; 1375 struct atomisp_device *isp; 1376 unsigned int start; 1377 int err, val; 1378 u32 irq; 1379 1380 if (!is_valid_device(pdev, id)) 1381 return -ENODEV; 1382 1383 /* Pointer to struct device. */ 1384 atomisp_dev = &pdev->dev; 1385 1386 pdata = atomisp_get_platform_data(); 1387 if (!pdata) 1388 dev_warn(&pdev->dev, "no platform data available\n"); 1389 1390 err = pcim_enable_device(pdev); 1391 if (err) { 1392 dev_err(&pdev->dev, "Failed to enable CI ISP device (%d)\n", err); 1393 return err; 1394 } 1395 1396 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR); 1397 dev_dbg(&pdev->dev, "start: 0x%x\n", start); 1398 1399 err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev)); 1400 if (err) { 1401 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err); 1402 goto ioremap_fail; 1403 } 1404 1405 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL); 1406 if (!isp) { 1407 err = -ENOMEM; 1408 goto atomisp_dev_alloc_fail; 1409 } 1410 1411 isp->dev = &pdev->dev; 1412 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR]; 1413 isp->saved_regs.ispmmadr = start; 1414 1415 dev_dbg(&pdev->dev, "atomisp mmio base: %p\n", isp->base); 1416 1417 mutex_init(&isp->mutex); 1418 spin_lock_init(&isp->lock); 1419 1420 /* This is not a true PCI device on SoC, so the delay is not needed. */ 1421 pdev->d3hot_delay = 0; 1422 1423 pci_set_drvdata(pdev, isp); 1424 1425 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { 1426 case ATOMISP_PCI_DEVICE_SOC_MRFLD: 1427 isp->media_dev.hw_revision = 1428 (ATOMISP_HW_REVISION_ISP2400 1429 << ATOMISP_HW_REVISION_SHIFT) | 1430 ATOMISP_HW_STEPPING_B0; 1431 1432 switch (id->device) { 1433 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179: 1434 isp->dfs = &dfs_config_merr_1179; 1435 break; 1436 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A: 1437 isp->dfs = &dfs_config_merr_117a; 1438 1439 break; 1440 default: 1441 isp->dfs = &dfs_config_merr; 1442 break; 1443 } 1444 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1445 break; 1446 case ATOMISP_PCI_DEVICE_SOC_BYT: 1447 isp->media_dev.hw_revision = 1448 (ATOMISP_HW_REVISION_ISP2400 1449 << ATOMISP_HW_REVISION_SHIFT) | 1450 ATOMISP_HW_STEPPING_B0; 1451 1452 /* 1453 * Note: some Intel-based tablets with Android use a different 1454 * DFS table. Based on the comments at the Yocto Aero meta 1455 * version of this driver (at the ssid.h header), they're 1456 * identified via a "spid" var: 1457 * 1458 * androidboot.spid=vend:cust:manu:plat:prod:hard 1459 * 1460 * As we don't have this upstream, nor we know enough details 1461 * to use a DMI or PCI match table, the old code was just 1462 * removed, but let's keep a note here as a reminder that, 1463 * for certain devices, we may need to limit the max DFS 1464 * frequency to be below certain values, adjusting the 1465 * resolution accordingly. 1466 */ 1467 isp->dfs = &dfs_config_byt; 1468 1469 /* 1470 * HPLL frequency is known to be device-specific, but we don't 1471 * have specs yet for exactly how it varies. Default to 1472 * BYT-CR but let provisioning set it via EFI variable 1473 */ 1474 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ); 1475 1476 /* 1477 * for BYT/CHT we are put isp into D3cold to avoid pci registers access 1478 * in power off. Set d3cold_delay to 0 since default 100ms is not 1479 * necessary. 1480 */ 1481 pdev->d3cold_delay = 0; 1482 break; 1483 case ATOMISP_PCI_DEVICE_SOC_ANN: 1484 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401 1485 << ATOMISP_HW_REVISION_SHIFT); 1486 isp->media_dev.hw_revision |= pdev->revision < 2 ? 1487 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; 1488 isp->dfs = &dfs_config_merr; 1489 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1490 break; 1491 case ATOMISP_PCI_DEVICE_SOC_CHT: 1492 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401 1493 << ATOMISP_HW_REVISION_SHIFT); 1494 isp->media_dev.hw_revision |= pdev->revision < 2 ? 1495 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; 1496 1497 isp->dfs = &dfs_config_cht; 1498 pdev->d3cold_delay = 0; 1499 1500 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val); 1501 switch (val & CCK_FUSE_HPLL_FREQ_MASK) { 1502 case 0x00: 1503 isp->hpll_freq = HPLL_FREQ_800MHZ; 1504 break; 1505 case 0x01: 1506 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1507 break; 1508 case 0x02: 1509 isp->hpll_freq = HPLL_FREQ_2000MHZ; 1510 break; 1511 default: 1512 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1513 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n"); 1514 } 1515 break; 1516 default: 1517 dev_err(&pdev->dev, "un-supported IUNIT device\n"); 1518 err = -ENODEV; 1519 goto atomisp_dev_alloc_fail; 1520 } 1521 1522 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq); 1523 1524 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY; 1525 1526 /* Load isp firmware from user space */ 1527 if (!defer_fw_load) { 1528 isp->firmware = atomisp_load_firmware(isp); 1529 if (!isp->firmware) { 1530 err = -ENOENT; 1531 dev_dbg(&pdev->dev, "Firmware load failed\n"); 1532 goto load_fw_fail; 1533 } 1534 1535 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data); 1536 if (err) { 1537 dev_dbg(&pdev->dev, "Firmware version check failed\n"); 1538 goto fw_validation_fail; 1539 } 1540 } else { 1541 dev_info(&pdev->dev, "Firmware load will be deferred\n"); 1542 } 1543 1544 pci_set_master(pdev); 1545 1546 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1547 if (err < 0) { 1548 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err); 1549 goto enable_msi_fail; 1550 } 1551 1552 atomisp_msi_irq_init(isp); 1553 1554 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 1555 1556 /* 1557 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of 1558 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI 1559 * backend write 0 will enable Arasan CSI backend, which has 1560 * bugs(like sighting:4567697 and 4567699) and will be removed 1561 * in B0 1562 */ 1563 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); 1564 1565 if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) == 1566 ATOMISP_PCI_DEVICE_SOC_MRFLD) { 1567 u32 csi_afe_trim; 1568 1569 /* 1570 * Workaround for imbalance data eye issue which is observed 1571 * on TNG B0. 1572 */ 1573 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &csi_afe_trim); 1574 csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1575 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | 1576 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1577 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | 1578 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1579 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT)); 1580 csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM << 1581 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | 1582 (MRFLD_PCI_CSI2_HSRXCLKTRIM << 1583 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | 1584 (MRFLD_PCI_CSI3_HSRXCLKTRIM << 1585 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT); 1586 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, csi_afe_trim); 1587 } 1588 1589 err = atomisp_initialize_modules(isp); 1590 if (err < 0) { 1591 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err); 1592 goto initialize_modules_fail; 1593 } 1594 1595 err = atomisp_register_entities(isp); 1596 if (err < 0) { 1597 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err); 1598 goto register_entities_fail; 1599 } 1600 1601 INIT_WORK(&isp->assert_recovery_work, atomisp_assert_recovery_work); 1602 1603 /* save the iunit context only once after all the values are init'ed. */ 1604 atomisp_save_iunit_reg(isp); 1605 1606 pm_runtime_put_noidle(&pdev->dev); 1607 pm_runtime_allow(&pdev->dev); 1608 1609 /* Init ISP memory management */ 1610 hmm_init(); 1611 1612 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, 1613 atomisp_isr, atomisp_isr_thread, 1614 IRQF_SHARED, "isp_irq", isp); 1615 if (err) { 1616 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err); 1617 goto request_irq_fail; 1618 } 1619 1620 /* Load firmware into ISP memory */ 1621 if (!defer_fw_load) { 1622 err = atomisp_css_load_firmware(isp); 1623 if (err) { 1624 dev_err(&pdev->dev, "Failed to init css.\n"); 1625 goto css_init_fail; 1626 } 1627 } else { 1628 dev_dbg(&pdev->dev, "Skip css init.\n"); 1629 } 1630 /* Clear FW image from memory */ 1631 release_firmware(isp->firmware); 1632 isp->firmware = NULL; 1633 isp->css_env.isp_css_fw.data = NULL; 1634 1635 err = atomisp_register_device_nodes(isp); 1636 if (err) 1637 goto css_init_fail; 1638 1639 atomisp_drvfs_init(isp); 1640 1641 return 0; 1642 1643 css_init_fail: 1644 devm_free_irq(&pdev->dev, pdev->irq, isp); 1645 request_irq_fail: 1646 hmm_cleanup(); 1647 pm_runtime_get_noresume(&pdev->dev); 1648 atomisp_unregister_entities(isp); 1649 register_entities_fail: 1650 atomisp_uninitialize_modules(isp); 1651 initialize_modules_fail: 1652 cpu_latency_qos_remove_request(&isp->pm_qos); 1653 atomisp_msi_irq_uninit(isp); 1654 pci_free_irq_vectors(pdev); 1655 enable_msi_fail: 1656 fw_validation_fail: 1657 release_firmware(isp->firmware); 1658 load_fw_fail: 1659 /* 1660 * Switch off ISP, as keeping it powered on would prevent 1661 * reaching S0ix states. 1662 * 1663 * The following lines have been copied from atomisp suspend path 1664 */ 1665 1666 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 1667 irq &= BIT(INTR_IIR); 1668 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 1669 1670 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 1671 irq &= ~BIT(INTR_IER); 1672 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 1673 1674 atomisp_msi_irq_uninit(isp); 1675 1676 /* Address later when we worry about the ...field chips */ 1677 if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power(isp, false)) 1678 dev_err(&pdev->dev, "Failed to switch off ISP\n"); 1679 1680 atomisp_dev_alloc_fail: 1681 pcim_iounmap_regions(pdev, BIT(ATOM_ISP_PCI_BAR)); 1682 1683 ioremap_fail: 1684 return err; 1685 } 1686 1687 static void atomisp_pci_remove(struct pci_dev *pdev) 1688 { 1689 struct atomisp_device *isp = pci_get_drvdata(pdev); 1690 1691 dev_info(&pdev->dev, "Removing atomisp driver\n"); 1692 1693 atomisp_drvfs_exit(); 1694 1695 ia_css_unload_firmware(); 1696 hmm_cleanup(); 1697 1698 pm_runtime_forbid(&pdev->dev); 1699 pm_runtime_get_noresume(&pdev->dev); 1700 cpu_latency_qos_remove_request(&isp->pm_qos); 1701 1702 atomisp_msi_irq_uninit(isp); 1703 atomisp_unregister_entities(isp); 1704 1705 release_firmware(isp->firmware); 1706 } 1707 1708 static const struct pci_device_id atomisp_pci_tbl[] = { 1709 /* Merrifield */ 1710 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)}, 1711 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)}, 1712 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)}, 1713 /* Baytrail */ 1714 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)}, 1715 /* Anniedale (Merrifield+ / Moorefield) */ 1716 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)}, 1717 /* Cherrytrail */ 1718 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)}, 1719 {0,} 1720 }; 1721 1722 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl); 1723 1724 static const struct dev_pm_ops atomisp_pm_ops = { 1725 .runtime_suspend = atomisp_power_off, 1726 .runtime_resume = atomisp_power_on, 1727 .suspend = atomisp_suspend, 1728 .resume = atomisp_resume, 1729 }; 1730 1731 static struct pci_driver atomisp_pci_driver = { 1732 .driver = { 1733 .pm = &atomisp_pm_ops, 1734 }, 1735 .name = "atomisp-isp2", 1736 .id_table = atomisp_pci_tbl, 1737 .probe = atomisp_pci_probe, 1738 .remove = atomisp_pci_remove, 1739 }; 1740 1741 module_pci_driver(atomisp_pci_driver); 1742 1743 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>"); 1744 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>"); 1745 MODULE_LICENSE("GPL"); 1746 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver"); 1747