1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for Medifield PNW Camera Imaging ISP subsystem. 4 * 5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved. 6 * 7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License version 11 * 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * 19 */ 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/pm_qos.h> 24 #include <linux/timer.h> 25 #include <linux/delay.h> 26 #include <linux/dmi.h> 27 #include <linux/interrupt.h> 28 #include <linux/bits.h> 29 30 #include <asm/iosf_mbi.h> 31 32 #include "../../include/linux/atomisp_gmin_platform.h" 33 34 #include "atomisp_cmd.h" 35 #include "atomisp_common.h" 36 #include "atomisp_fops.h" 37 #include "atomisp_file.h" 38 #include "atomisp_ioctl.h" 39 #include "atomisp_internal.h" 40 #include "atomisp-regs.h" 41 #include "atomisp_dfs_tables.h" 42 #include "atomisp_drvfs.h" 43 #include "hmm/hmm.h" 44 #include "atomisp_trace_event.h" 45 46 #include "sh_css_firmware.h" 47 48 #include "device_access.h" 49 50 /* Timeouts to wait for all subdevs to be registered */ 51 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */ 52 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */ 53 54 /* G-Min addition: pull this in from intel_mid_pm.h */ 55 #define CSTATE_EXIT_LATENCY_C1 1 56 57 static uint skip_fwload; 58 module_param(skip_fwload, uint, 0644); 59 MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load"); 60 61 /* memory optimization: deferred firmware loading */ 62 bool defer_fw_load; 63 module_param(defer_fw_load, bool, 0644); 64 MODULE_PARM_DESC(defer_fw_load, 65 "Defer FW loading until device is opened (default:disable)"); 66 67 /* cross componnet debug message flag */ 68 int dbg_level; 69 module_param(dbg_level, int, 0644); 70 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)"); 71 72 /* log function switch */ 73 int dbg_func = 2; 74 module_param(dbg_func, int, 0644); 75 MODULE_PARM_DESC(dbg_func, 76 "log function switch non/trace_printk/printk (default:printk)"); 77 78 int mipicsi_flag; 79 module_param(mipicsi_flag, int, 0644); 80 MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm"); 81 82 static char firmware_name[256]; 83 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0); 84 MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name."); 85 86 /*set to 16x16 since this is the amount of lines and pixels the sensor 87 exports extra. If these are kept at the 10x8 that they were on, in yuv 88 downscaling modes incorrect resolutions where requested to the sensor 89 driver with strange outcomes as a result. The proper way tot do this 90 would be to have a list of tables the specify the sensor res, mipi rec, 91 output res, and isp output res. however since we do not have this yet, 92 the chosen solution is the next best thing. */ 93 int pad_w = 16; 94 module_param(pad_w, int, 0644); 95 MODULE_PARM_DESC(pad_w, "extra data for ISP processing"); 96 97 int pad_h = 16; 98 module_param(pad_h, int, 0644); 99 MODULE_PARM_DESC(pad_h, "extra data for ISP processing"); 100 101 /* 102 * FIXME: this is a hack to make easier to support ISP2401 variant. 103 * As a given system will either be ISP2401 or not, we can just use 104 * a boolean, in order to replace existing #ifdef ISP2401 everywhere. 105 * 106 * Once this driver gets into a better shape, however, the best would 107 * be to replace this to something stored inside atomisp allocated 108 * structures. 109 */ 110 111 struct device *atomisp_dev; 112 113 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = { 114 { 115 .width = ISP_FREQ_RULE_ANY, 116 .height = ISP_FREQ_RULE_ANY, 117 .fps = ISP_FREQ_RULE_ANY, 118 .isp_freq = ISP_FREQ_400MHZ, 119 .run_mode = ATOMISP_RUN_MODE_VIDEO, 120 }, 121 { 122 .width = ISP_FREQ_RULE_ANY, 123 .height = ISP_FREQ_RULE_ANY, 124 .fps = ISP_FREQ_RULE_ANY, 125 .isp_freq = ISP_FREQ_400MHZ, 126 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 127 }, 128 { 129 .width = ISP_FREQ_RULE_ANY, 130 .height = ISP_FREQ_RULE_ANY, 131 .fps = ISP_FREQ_RULE_ANY, 132 .isp_freq = ISP_FREQ_400MHZ, 133 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 134 }, 135 { 136 .width = ISP_FREQ_RULE_ANY, 137 .height = ISP_FREQ_RULE_ANY, 138 .fps = ISP_FREQ_RULE_ANY, 139 .isp_freq = ISP_FREQ_400MHZ, 140 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 141 }, 142 { 143 .width = ISP_FREQ_RULE_ANY, 144 .height = ISP_FREQ_RULE_ANY, 145 .fps = ISP_FREQ_RULE_ANY, 146 .isp_freq = ISP_FREQ_457MHZ, 147 .run_mode = ATOMISP_RUN_MODE_SDV, 148 }, 149 }; 150 151 /* Merrifield and Moorefield DFS rules */ 152 static const struct atomisp_dfs_config dfs_config_merr = { 153 .lowest_freq = ISP_FREQ_200MHZ, 154 .max_freq_at_vmin = ISP_FREQ_400MHZ, 155 .highest_freq = ISP_FREQ_457MHZ, 156 .dfs_table = dfs_rules_merr, 157 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr), 158 }; 159 160 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = { 161 { 162 .width = ISP_FREQ_RULE_ANY, 163 .height = ISP_FREQ_RULE_ANY, 164 .fps = ISP_FREQ_RULE_ANY, 165 .isp_freq = ISP_FREQ_400MHZ, 166 .run_mode = ATOMISP_RUN_MODE_VIDEO, 167 }, 168 { 169 .width = ISP_FREQ_RULE_ANY, 170 .height = ISP_FREQ_RULE_ANY, 171 .fps = ISP_FREQ_RULE_ANY, 172 .isp_freq = ISP_FREQ_400MHZ, 173 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 174 }, 175 { 176 .width = ISP_FREQ_RULE_ANY, 177 .height = ISP_FREQ_RULE_ANY, 178 .fps = ISP_FREQ_RULE_ANY, 179 .isp_freq = ISP_FREQ_400MHZ, 180 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 181 }, 182 { 183 .width = ISP_FREQ_RULE_ANY, 184 .height = ISP_FREQ_RULE_ANY, 185 .fps = ISP_FREQ_RULE_ANY, 186 .isp_freq = ISP_FREQ_400MHZ, 187 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 188 }, 189 { 190 .width = ISP_FREQ_RULE_ANY, 191 .height = ISP_FREQ_RULE_ANY, 192 .fps = ISP_FREQ_RULE_ANY, 193 .isp_freq = ISP_FREQ_400MHZ, 194 .run_mode = ATOMISP_RUN_MODE_SDV, 195 }, 196 }; 197 198 static const struct atomisp_dfs_config dfs_config_merr_1179 = { 199 .lowest_freq = ISP_FREQ_200MHZ, 200 .max_freq_at_vmin = ISP_FREQ_400MHZ, 201 .highest_freq = ISP_FREQ_400MHZ, 202 .dfs_table = dfs_rules_merr_1179, 203 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179), 204 }; 205 206 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = { 207 { 208 .width = 1920, 209 .height = 1080, 210 .fps = 30, 211 .isp_freq = ISP_FREQ_266MHZ, 212 .run_mode = ATOMISP_RUN_MODE_VIDEO, 213 }, 214 { 215 .width = 1080, 216 .height = 1920, 217 .fps = 30, 218 .isp_freq = ISP_FREQ_266MHZ, 219 .run_mode = ATOMISP_RUN_MODE_VIDEO, 220 }, 221 { 222 .width = 1920, 223 .height = 1080, 224 .fps = 45, 225 .isp_freq = ISP_FREQ_320MHZ, 226 .run_mode = ATOMISP_RUN_MODE_VIDEO, 227 }, 228 { 229 .width = 1080, 230 .height = 1920, 231 .fps = 45, 232 .isp_freq = ISP_FREQ_320MHZ, 233 .run_mode = ATOMISP_RUN_MODE_VIDEO, 234 }, 235 { 236 .width = ISP_FREQ_RULE_ANY, 237 .height = ISP_FREQ_RULE_ANY, 238 .fps = 60, 239 .isp_freq = ISP_FREQ_356MHZ, 240 .run_mode = ATOMISP_RUN_MODE_VIDEO, 241 }, 242 { 243 .width = ISP_FREQ_RULE_ANY, 244 .height = ISP_FREQ_RULE_ANY, 245 .fps = ISP_FREQ_RULE_ANY, 246 .isp_freq = ISP_FREQ_200MHZ, 247 .run_mode = ATOMISP_RUN_MODE_VIDEO, 248 }, 249 { 250 .width = ISP_FREQ_RULE_ANY, 251 .height = ISP_FREQ_RULE_ANY, 252 .fps = ISP_FREQ_RULE_ANY, 253 .isp_freq = ISP_FREQ_400MHZ, 254 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 255 }, 256 { 257 .width = ISP_FREQ_RULE_ANY, 258 .height = ISP_FREQ_RULE_ANY, 259 .fps = ISP_FREQ_RULE_ANY, 260 .isp_freq = ISP_FREQ_400MHZ, 261 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 262 }, 263 { 264 .width = ISP_FREQ_RULE_ANY, 265 .height = ISP_FREQ_RULE_ANY, 266 .fps = ISP_FREQ_RULE_ANY, 267 .isp_freq = ISP_FREQ_200MHZ, 268 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 269 }, 270 { 271 .width = ISP_FREQ_RULE_ANY, 272 .height = ISP_FREQ_RULE_ANY, 273 .fps = ISP_FREQ_RULE_ANY, 274 .isp_freq = ISP_FREQ_400MHZ, 275 .run_mode = ATOMISP_RUN_MODE_SDV, 276 }, 277 }; 278 279 static struct atomisp_dfs_config dfs_config_merr_117a = { 280 .lowest_freq = ISP_FREQ_200MHZ, 281 .max_freq_at_vmin = ISP_FREQ_200MHZ, 282 .highest_freq = ISP_FREQ_400MHZ, 283 .dfs_table = dfs_rules_merr_117a, 284 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a), 285 }; 286 287 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = { 288 { 289 .width = ISP_FREQ_RULE_ANY, 290 .height = ISP_FREQ_RULE_ANY, 291 .fps = ISP_FREQ_RULE_ANY, 292 .isp_freq = ISP_FREQ_400MHZ, 293 .run_mode = ATOMISP_RUN_MODE_VIDEO, 294 }, 295 { 296 .width = ISP_FREQ_RULE_ANY, 297 .height = ISP_FREQ_RULE_ANY, 298 .fps = ISP_FREQ_RULE_ANY, 299 .isp_freq = ISP_FREQ_400MHZ, 300 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 301 }, 302 { 303 .width = ISP_FREQ_RULE_ANY, 304 .height = ISP_FREQ_RULE_ANY, 305 .fps = ISP_FREQ_RULE_ANY, 306 .isp_freq = ISP_FREQ_400MHZ, 307 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 308 }, 309 { 310 .width = ISP_FREQ_RULE_ANY, 311 .height = ISP_FREQ_RULE_ANY, 312 .fps = ISP_FREQ_RULE_ANY, 313 .isp_freq = ISP_FREQ_400MHZ, 314 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 315 }, 316 { 317 .width = ISP_FREQ_RULE_ANY, 318 .height = ISP_FREQ_RULE_ANY, 319 .fps = ISP_FREQ_RULE_ANY, 320 .isp_freq = ISP_FREQ_400MHZ, 321 .run_mode = ATOMISP_RUN_MODE_SDV, 322 }, 323 }; 324 325 static const struct atomisp_dfs_config dfs_config_byt = { 326 .lowest_freq = ISP_FREQ_200MHZ, 327 .max_freq_at_vmin = ISP_FREQ_400MHZ, 328 .highest_freq = ISP_FREQ_400MHZ, 329 .dfs_table = dfs_rules_byt, 330 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt), 331 }; 332 333 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = { 334 { 335 .width = ISP_FREQ_RULE_ANY, 336 .height = ISP_FREQ_RULE_ANY, 337 .fps = ISP_FREQ_RULE_ANY, 338 .isp_freq = ISP_FREQ_320MHZ, 339 .run_mode = ATOMISP_RUN_MODE_VIDEO, 340 }, 341 { 342 .width = ISP_FREQ_RULE_ANY, 343 .height = ISP_FREQ_RULE_ANY, 344 .fps = ISP_FREQ_RULE_ANY, 345 .isp_freq = ISP_FREQ_356MHZ, 346 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 347 }, 348 { 349 .width = ISP_FREQ_RULE_ANY, 350 .height = ISP_FREQ_RULE_ANY, 351 .fps = ISP_FREQ_RULE_ANY, 352 .isp_freq = ISP_FREQ_320MHZ, 353 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 354 }, 355 { 356 .width = ISP_FREQ_RULE_ANY, 357 .height = ISP_FREQ_RULE_ANY, 358 .fps = ISP_FREQ_RULE_ANY, 359 .isp_freq = ISP_FREQ_320MHZ, 360 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 361 }, 362 { 363 .width = 1280, 364 .height = 720, 365 .fps = ISP_FREQ_RULE_ANY, 366 .isp_freq = ISP_FREQ_320MHZ, 367 .run_mode = ATOMISP_RUN_MODE_SDV, 368 }, 369 { 370 .width = ISP_FREQ_RULE_ANY, 371 .height = ISP_FREQ_RULE_ANY, 372 .fps = ISP_FREQ_RULE_ANY, 373 .isp_freq = ISP_FREQ_356MHZ, 374 .run_mode = ATOMISP_RUN_MODE_SDV, 375 }, 376 }; 377 378 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = { 379 { 380 .width = ISP_FREQ_RULE_ANY, 381 .height = ISP_FREQ_RULE_ANY, 382 .fps = ISP_FREQ_RULE_ANY, 383 .isp_freq = ISP_FREQ_356MHZ, 384 .run_mode = ATOMISP_RUN_MODE_VIDEO, 385 }, 386 { 387 .width = ISP_FREQ_RULE_ANY, 388 .height = ISP_FREQ_RULE_ANY, 389 .fps = ISP_FREQ_RULE_ANY, 390 .isp_freq = ISP_FREQ_356MHZ, 391 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 392 }, 393 { 394 .width = ISP_FREQ_RULE_ANY, 395 .height = ISP_FREQ_RULE_ANY, 396 .fps = ISP_FREQ_RULE_ANY, 397 .isp_freq = ISP_FREQ_320MHZ, 398 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 399 }, 400 { 401 .width = ISP_FREQ_RULE_ANY, 402 .height = ISP_FREQ_RULE_ANY, 403 .fps = ISP_FREQ_RULE_ANY, 404 .isp_freq = ISP_FREQ_320MHZ, 405 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 406 }, 407 { 408 .width = ISP_FREQ_RULE_ANY, 409 .height = ISP_FREQ_RULE_ANY, 410 .fps = ISP_FREQ_RULE_ANY, 411 .isp_freq = ISP_FREQ_356MHZ, 412 .run_mode = ATOMISP_RUN_MODE_SDV, 413 }, 414 }; 415 416 static const struct atomisp_dfs_config dfs_config_cht = { 417 .lowest_freq = ISP_FREQ_100MHZ, 418 .max_freq_at_vmin = ISP_FREQ_356MHZ, 419 .highest_freq = ISP_FREQ_356MHZ, 420 .dfs_table = dfs_rules_cht, 421 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht), 422 }; 423 424 /* This one should be visible also by atomisp_cmd.c */ 425 const struct atomisp_dfs_config dfs_config_cht_soc = { 426 .lowest_freq = ISP_FREQ_100MHZ, 427 .max_freq_at_vmin = ISP_FREQ_356MHZ, 428 .highest_freq = ISP_FREQ_356MHZ, 429 .dfs_table = dfs_rules_cht_soc, 430 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc), 431 }; 432 433 int atomisp_video_init(struct atomisp_video_pipe *video, const char *name, 434 unsigned int run_mode) 435 { 436 int ret; 437 const char *direction; 438 439 switch (video->type) { 440 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 441 direction = "output"; 442 video->pad.flags = MEDIA_PAD_FL_SINK; 443 video->vdev.fops = &atomisp_fops; 444 video->vdev.ioctl_ops = &atomisp_ioctl_ops; 445 break; 446 case V4L2_BUF_TYPE_VIDEO_OUTPUT: 447 direction = "input"; 448 video->pad.flags = MEDIA_PAD_FL_SOURCE; 449 video->vdev.fops = &atomisp_file_fops; 450 video->vdev.ioctl_ops = &atomisp_file_ioctl_ops; 451 break; 452 default: 453 return -EINVAL; 454 } 455 456 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad); 457 if (ret < 0) 458 return ret; 459 460 /* Initialize the video device. */ 461 snprintf(video->vdev.name, sizeof(video->vdev.name), 462 "ATOMISP ISP %s %s", name, direction); 463 video->vdev.release = video_device_release_empty; 464 video_set_drvdata(&video->vdev, video->isp); 465 video->default_run_mode = run_mode; 466 467 return 0; 468 } 469 470 void atomisp_acc_init(struct atomisp_acc_pipe *video, const char *name) 471 { 472 video->vdev.fops = &atomisp_fops; 473 video->vdev.ioctl_ops = &atomisp_ioctl_ops; 474 475 /* Initialize the video device. */ 476 snprintf(video->vdev.name, sizeof(video->vdev.name), 477 "ATOMISP ISP %s", name); 478 video->vdev.release = video_device_release_empty; 479 video_set_drvdata(&video->vdev, video->isp); 480 } 481 482 void atomisp_video_unregister(struct atomisp_video_pipe *video) 483 { 484 if (video_is_registered(&video->vdev)) { 485 media_entity_cleanup(&video->vdev.entity); 486 video_unregister_device(&video->vdev); 487 } 488 } 489 490 void atomisp_acc_unregister(struct atomisp_acc_pipe *video) 491 { 492 if (video_is_registered(&video->vdev)) 493 video_unregister_device(&video->vdev); 494 } 495 496 static int atomisp_save_iunit_reg(struct atomisp_device *isp) 497 { 498 struct pci_dev *pdev = to_pci_dev(isp->dev); 499 500 dev_dbg(isp->dev, "%s\n", __func__); 501 502 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts); 503 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */ 504 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap); 505 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr); 506 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data); 507 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr); 508 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control); 509 510 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs); 511 /* Ensure read/write combining is enabled. */ 512 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control); 513 isp->saved_regs.i_control |= 514 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING | 515 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING; 516 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, 517 &isp->saved_regs.csi_access_viol); 518 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL, 519 &isp->saved_regs.csi_rcomp_config); 520 /* 521 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE. 522 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path 523 * and sensor sending "continuous clock". 524 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence 525 * is missed, and IUNIT can hang. 526 * For both issues, setting this bit is a workaround. 527 */ 528 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE; 529 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 530 &isp->saved_regs.csi_afe_dly); 531 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, 532 &isp->saved_regs.csi_control); 533 if (isp->media_dev.hw_revision >= 534 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT)) 535 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN; 536 /* 537 * On CHT CSI_READY bit should be enabled before stream on 538 */ 539 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << 540 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0))) 541 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY; 542 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, 543 &isp->saved_regs.csi_afe_rcomp_config); 544 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL, 545 &isp->saved_regs.csi_afe_hs_control); 546 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL, 547 &isp->saved_regs.csi_deadline_control); 548 return 0; 549 } 550 551 static int __maybe_unused atomisp_restore_iunit_reg(struct atomisp_device *isp) 552 { 553 struct pci_dev *pdev = to_pci_dev(isp->dev); 554 555 dev_dbg(isp->dev, "%s\n", __func__); 556 557 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts); 558 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr); 559 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap); 560 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr); 561 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data); 562 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr); 563 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control); 564 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control); 565 566 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs); 567 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, 568 isp->saved_regs.csi_access_viol); 569 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL, 570 isp->saved_regs.csi_rcomp_config); 571 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 572 isp->saved_regs.csi_afe_dly); 573 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, 574 isp->saved_regs.csi_control); 575 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, 576 isp->saved_regs.csi_afe_rcomp_config); 577 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL, 578 isp->saved_regs.csi_afe_hs_control); 579 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL, 580 isp->saved_regs.csi_deadline_control); 581 582 /* 583 * for MRFLD, Software/firmware needs to write a 1 to bit0 584 * of the register at CSI_RECEIVER_SELECTION_REG to enable 585 * SH CSI backend write 0 will enable Arasan CSI backend, 586 * which has bugs(like sighting:4567697 and 4567699) and 587 * will be removed in B0 588 */ 589 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); 590 return 0; 591 } 592 593 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp) 594 { 595 struct pci_dev *pdev = to_pci_dev(isp->dev); 596 u32 irq; 597 unsigned long flags; 598 599 spin_lock_irqsave(&isp->lock, flags); 600 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) { 601 spin_unlock_irqrestore(&isp->lock, flags); 602 dev_dbg(isp->dev, "<%s %d.\n", __func__, __LINE__); 603 return 0; 604 } 605 /* 606 * MRFLD HAS requirement: cannot power off i-unit if 607 * ISP has IRQ not serviced. 608 * So, here we need to check if there is any pending 609 * IRQ, if so, waiting for it to be served 610 */ 611 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 612 irq &= BIT(INTR_IIR); 613 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 614 615 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 616 if (!(irq & BIT(INTR_IIR))) 617 goto done; 618 619 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF); 620 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq); 621 if (irq != 0) { 622 dev_err(isp->dev, 623 "%s: fail to clear isp interrupt status reg=0x%x\n", 624 __func__, irq); 625 spin_unlock_irqrestore(&isp->lock, flags); 626 return -EAGAIN; 627 } else { 628 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 629 irq &= BIT(INTR_IIR); 630 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 631 632 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 633 if (!(irq & BIT(INTR_IIR))) { 634 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0); 635 goto done; 636 } 637 dev_err(isp->dev, 638 "%s: error in iunit interrupt. status reg=0x%x\n", 639 __func__, irq); 640 spin_unlock_irqrestore(&isp->lock, flags); 641 return -EAGAIN; 642 } 643 done: 644 /* 645 * MRFLD WORKAROUND: 646 * before powering off IUNIT, clear the pending interrupts 647 * and disable the interrupt. driver should avoid writing 0 648 * to IIR. It could block subsequent interrupt messages. 649 * HW sighting:4568410. 650 */ 651 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 652 irq &= ~BIT(INTR_IER); 653 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 654 655 atomisp_msi_irq_uninit(isp); 656 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 657 spin_unlock_irqrestore(&isp->lock, flags); 658 659 return 0; 660 } 661 662 /* 663 * WA for DDR DVFS enable/disable 664 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS 665 */ 666 static void punit_ddr_dvfs_enable(bool enable) 667 { 668 int door_bell = 1 << 8; 669 int max_wait = 30; 670 int reg; 671 672 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®); 673 if (enable) { 674 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1); 675 } else { 676 reg |= (MRFLD_BIT1 | door_bell); 677 reg &= ~(MRFLD_BIT0); 678 } 679 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg); 680 681 /* Check Req_ACK to see freq status, wait until door_bell is cleared */ 682 while ((reg & door_bell) && max_wait--) { 683 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®); 684 usleep_range(100, 500); 685 } 686 687 if (max_wait == -1) 688 pr_info("DDR DVFS, door bell is not cleared within 3ms\n"); 689 } 690 691 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable) 692 { 693 unsigned long timeout; 694 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON : 695 MRFLD_ISPSSPM0_IUNIT_POWER_OFF; 696 697 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off"); 698 699 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */ 700 if (IS_CHT && enable) 701 punit_ddr_dvfs_enable(false); 702 703 /* 704 * FIXME:WA for ECS28A, with this sleep, CTS 705 * android.hardware.camera2.cts.CameraDeviceTest#testCameraDeviceAbort 706 * PASS, no impact on other platforms 707 */ 708 if (IS_BYT && enable) 709 msleep(10); 710 711 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */ 712 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, 713 val, MRFLD_ISPSSPM0_ISPSSC_MASK); 714 715 /* WA:Enable DVFS */ 716 if (IS_CHT && !enable) 717 punit_ddr_dvfs_enable(true); 718 719 /* 720 * There should be no IUNIT access while power-down is 721 * in progress. HW sighting: 4567865. 722 * Wait up to 50 ms for the IUNIT to shut down. 723 * And we do the same for power on. 724 */ 725 timeout = jiffies + msecs_to_jiffies(50); 726 do { 727 u32 tmp; 728 729 /* Wait until ISPSSPM0 bit[25:24] shows the right value */ 730 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp); 731 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK; 732 if (tmp == val) { 733 trace_ipu_cstate(enable); 734 return 0; 735 } 736 737 if (time_after(jiffies, timeout)) 738 break; 739 740 /* FIXME: experienced value for delay */ 741 usleep_range(100, 150); 742 } while (1); 743 744 if (enable) 745 msleep(10); 746 747 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off"); 748 return -EBUSY; 749 } 750 751 /* Workaround for pmu_nc_set_power_state not ready in MRFLD */ 752 int atomisp_mrfld_power_down(struct atomisp_device *isp) 753 { 754 return atomisp_mrfld_power(isp, false); 755 } 756 757 /* Workaround for pmu_nc_set_power_state not ready in MRFLD */ 758 int atomisp_mrfld_power_up(struct atomisp_device *isp) 759 { 760 return atomisp_mrfld_power(isp, true); 761 } 762 763 int atomisp_runtime_suspend(struct device *dev) 764 { 765 struct atomisp_device *isp = (struct atomisp_device *) 766 dev_get_drvdata(dev); 767 int ret; 768 769 ret = atomisp_mrfld_pre_power_down(isp); 770 if (ret) 771 return ret; 772 773 /*Turn off the ISP d-phy*/ 774 ret = atomisp_ospm_dphy_down(isp); 775 if (ret) 776 return ret; 777 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 778 return atomisp_mrfld_power_down(isp); 779 } 780 781 int atomisp_runtime_resume(struct device *dev) 782 { 783 struct atomisp_device *isp = (struct atomisp_device *) 784 dev_get_drvdata(dev); 785 int ret; 786 787 ret = atomisp_mrfld_power_up(isp); 788 if (ret) 789 return ret; 790 791 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency); 792 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) { 793 /*Turn on ISP d-phy */ 794 ret = atomisp_ospm_dphy_up(isp); 795 if (ret) { 796 dev_err(isp->dev, "Failed to power up ISP!.\n"); 797 return -EINVAL; 798 } 799 } 800 801 /*restore register values for iUnit and iUnitPHY registers*/ 802 if (isp->saved_regs.pcicmdsts) 803 atomisp_restore_iunit_reg(isp); 804 805 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 806 return 0; 807 } 808 809 static int __maybe_unused atomisp_suspend(struct device *dev) 810 { 811 struct atomisp_device *isp = (struct atomisp_device *) 812 dev_get_drvdata(dev); 813 /* FIXME: only has one isp_subdev at present */ 814 struct atomisp_sub_device *asd = &isp->asd[0]; 815 unsigned long flags; 816 int ret; 817 818 /* 819 * FIXME: Suspend is not supported by sensors. Abort if any video 820 * node was opened. 821 */ 822 if (atomisp_dev_users(isp)) 823 return -EBUSY; 824 825 spin_lock_irqsave(&isp->lock, flags); 826 if (asd->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) { 827 spin_unlock_irqrestore(&isp->lock, flags); 828 dev_err(isp->dev, "atomisp cannot suspend at this time.\n"); 829 return -EINVAL; 830 } 831 spin_unlock_irqrestore(&isp->lock, flags); 832 833 ret = atomisp_mrfld_pre_power_down(isp); 834 if (ret) 835 return ret; 836 837 /*Turn off the ISP d-phy */ 838 ret = atomisp_ospm_dphy_down(isp); 839 if (ret) { 840 dev_err(isp->dev, "fail to power off ISP\n"); 841 return ret; 842 } 843 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 844 return atomisp_mrfld_power_down(isp); 845 } 846 847 static int __maybe_unused atomisp_resume(struct device *dev) 848 { 849 struct atomisp_device *isp = (struct atomisp_device *) 850 dev_get_drvdata(dev); 851 int ret; 852 853 ret = atomisp_mrfld_power_up(isp); 854 if (ret) 855 return ret; 856 857 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency); 858 859 /*Turn on ISP d-phy */ 860 ret = atomisp_ospm_dphy_up(isp); 861 if (ret) { 862 dev_err(isp->dev, "Failed to power up ISP!.\n"); 863 return -EINVAL; 864 } 865 866 /*restore register values for iUnit and iUnitPHY registers*/ 867 if (isp->saved_regs.pcicmdsts) 868 atomisp_restore_iunit_reg(isp); 869 870 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 871 return 0; 872 } 873 874 int atomisp_csi_lane_config(struct atomisp_device *isp) 875 { 876 struct pci_dev *pdev = to_pci_dev(isp->dev); 877 static const struct { 878 u8 code; 879 u8 lanes[MRFLD_PORT_NUM]; 880 } portconfigs[] = { 881 /* Tangier/Merrifield available lane configurations */ 882 { 0x00, { 4, 1, 0 } }, /* 00000 */ 883 { 0x01, { 3, 1, 0 } }, /* 00001 */ 884 { 0x02, { 2, 1, 0 } }, /* 00010 */ 885 { 0x03, { 1, 1, 0 } }, /* 00011 */ 886 { 0x04, { 2, 1, 2 } }, /* 00100 */ 887 { 0x08, { 3, 1, 1 } }, /* 01000 */ 888 { 0x09, { 2, 1, 1 } }, /* 01001 */ 889 { 0x0a, { 1, 1, 1 } }, /* 01010 */ 890 891 /* Anniedale/Moorefield only configurations */ 892 { 0x10, { 4, 2, 0 } }, /* 10000 */ 893 { 0x11, { 3, 2, 0 } }, /* 10001 */ 894 { 0x12, { 2, 2, 0 } }, /* 10010 */ 895 { 0x13, { 1, 2, 0 } }, /* 10011 */ 896 { 0x14, { 2, 2, 2 } }, /* 10100 */ 897 { 0x18, { 3, 2, 1 } }, /* 11000 */ 898 { 0x19, { 2, 2, 1 } }, /* 11001 */ 899 { 0x1a, { 1, 2, 1 } }, /* 11010 */ 900 }; 901 902 unsigned int i, j; 903 u8 sensor_lanes[MRFLD_PORT_NUM] = { 0 }; 904 u32 csi_control; 905 int nportconfigs; 906 u32 port_config_mask; 907 int port3_lanes_shift; 908 909 if (isp->media_dev.hw_revision < 910 ATOMISP_HW_REVISION_ISP2401_LEGACY << 911 ATOMISP_HW_REVISION_SHIFT) { 912 /* Merrifield */ 913 port_config_mask = MRFLD_PORT_CONFIG_MASK; 914 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT; 915 } else { 916 /* Moorefield / Cherryview */ 917 port_config_mask = CHV_PORT_CONFIG_MASK; 918 port3_lanes_shift = CHV_PORT3_LANES_SHIFT; 919 } 920 921 if (isp->media_dev.hw_revision < 922 ATOMISP_HW_REVISION_ISP2401 << 923 ATOMISP_HW_REVISION_SHIFT) { 924 /* Merrifield / Moorefield legacy input system */ 925 nportconfigs = MRFLD_PORT_CONFIG_NUM; 926 } else { 927 /* Moorefield / Cherryview new input system */ 928 nportconfigs = ARRAY_SIZE(portconfigs); 929 } 930 931 for (i = 0; i < isp->input_cnt; i++) { 932 struct camera_mipi_info *mipi_info; 933 934 if (isp->inputs[i].type != RAW_CAMERA && 935 isp->inputs[i].type != SOC_CAMERA) 936 continue; 937 938 mipi_info = atomisp_to_sensor_mipi_info(isp->inputs[i].camera); 939 if (!mipi_info) 940 continue; 941 942 switch (mipi_info->port) { 943 case ATOMISP_CAMERA_PORT_PRIMARY: 944 sensor_lanes[0] = mipi_info->num_lanes; 945 break; 946 case ATOMISP_CAMERA_PORT_SECONDARY: 947 sensor_lanes[1] = mipi_info->num_lanes; 948 break; 949 case ATOMISP_CAMERA_PORT_TERTIARY: 950 sensor_lanes[2] = mipi_info->num_lanes; 951 break; 952 default: 953 dev_err(isp->dev, 954 "%s: invalid port: %d for the %dth sensor\n", 955 __func__, mipi_info->port, i); 956 return -EINVAL; 957 } 958 } 959 960 for (i = 0; i < nportconfigs; i++) { 961 for (j = 0; j < MRFLD_PORT_NUM; j++) 962 if (sensor_lanes[j] && 963 sensor_lanes[j] != portconfigs[i].lanes[j]) 964 break; 965 966 if (j == MRFLD_PORT_NUM) 967 break; /* Found matching setting */ 968 } 969 970 if (i >= nportconfigs) { 971 dev_err(isp->dev, 972 "%s: could not find the CSI port setting for %d-%d-%d\n", 973 __func__, 974 sensor_lanes[0], sensor_lanes[1], sensor_lanes[2]); 975 return -EINVAL; 976 } 977 978 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control); 979 csi_control &= ~port_config_mask; 980 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT) 981 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT)) 982 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT)) 983 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT)) 984 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT) 985 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT) 986 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift); 987 988 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control); 989 990 dev_dbg(isp->dev, 991 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n", 992 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1], 993 portconfigs[i].lanes[2], csi_control); 994 995 return 0; 996 } 997 998 static int atomisp_subdev_probe(struct atomisp_device *isp) 999 { 1000 const struct atomisp_platform_data *pdata; 1001 struct intel_v4l2_subdev_table *subdevs; 1002 int ret, raw_index = -1, count; 1003 1004 pdata = atomisp_get_platform_data(); 1005 if (!pdata) { 1006 dev_err(isp->dev, "no platform data available\n"); 1007 return 0; 1008 } 1009 1010 /* FIXME: should return -EPROBE_DEFER if not all subdevs were probed */ 1011 for (count = 0; count < SUBDEV_WAIT_TIMEOUT_MAX_COUNT; count++) { 1012 int camera_count = 0; 1013 1014 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { 1015 if (subdevs->type == RAW_CAMERA || 1016 subdevs->type == SOC_CAMERA) 1017 camera_count++; 1018 } 1019 if (camera_count) 1020 break; 1021 msleep(SUBDEV_WAIT_TIMEOUT); 1022 } 1023 /* Wait more time to give more time for subdev init code to finish */ 1024 msleep(5 * SUBDEV_WAIT_TIMEOUT); 1025 1026 /* FIXME: should, instead, use I2C probe */ 1027 1028 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { 1029 struct v4l2_subdev *subdev; 1030 struct i2c_board_info *board_info = 1031 &subdevs->v4l2_subdev.board_info; 1032 struct i2c_adapter *adapter = 1033 i2c_get_adapter(subdevs->v4l2_subdev.i2c_adapter_id); 1034 int sensor_num, i; 1035 1036 dev_info(isp->dev, "Probing Subdev %s\n", board_info->type); 1037 1038 if (!adapter) { 1039 dev_err(isp->dev, 1040 "Failed to find i2c adapter for subdev %s\n", 1041 board_info->type); 1042 break; 1043 } 1044 1045 /* In G-Min, the sensor devices will already be probed 1046 * (via ACPI) and registered, do not create new 1047 * ones */ 1048 subdev = atomisp_gmin_find_subdev(adapter, board_info); 1049 if (!subdev) { 1050 dev_warn(isp->dev, "Subdev %s not found\n", 1051 board_info->type); 1052 continue; 1053 } 1054 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdev); 1055 if (ret) { 1056 dev_warn(isp->dev, "Subdev %s detection fail\n", 1057 board_info->type); 1058 continue; 1059 } 1060 1061 if (!subdev) { 1062 dev_warn(isp->dev, "Subdev %s detection fail\n", 1063 board_info->type); 1064 continue; 1065 } 1066 1067 dev_info(isp->dev, "Subdev %s successfully register\n", 1068 board_info->type); 1069 1070 switch (subdevs->type) { 1071 case RAW_CAMERA: 1072 dev_dbg(isp->dev, "raw_index: %d\n", raw_index); 1073 raw_index = isp->input_cnt; 1074 fallthrough; 1075 case SOC_CAMERA: 1076 dev_dbg(isp->dev, "SOC_INDEX: %d\n", isp->input_cnt); 1077 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) { 1078 dev_warn(isp->dev, 1079 "too many atomisp inputs, ignored\n"); 1080 break; 1081 } 1082 1083 isp->inputs[isp->input_cnt].type = subdevs->type; 1084 isp->inputs[isp->input_cnt].port = subdevs->port; 1085 isp->inputs[isp->input_cnt].camera = subdev; 1086 isp->inputs[isp->input_cnt].sensor_index = 0; 1087 /* 1088 * initialize the subdev frame size, then next we can 1089 * judge whether frame_size store effective value via 1090 * pixel_format. 1091 */ 1092 isp->inputs[isp->input_cnt].frame_size.pixel_format = 0; 1093 isp->inputs[isp->input_cnt].camera_caps = 1094 atomisp_get_default_camera_caps(); 1095 sensor_num = isp->inputs[isp->input_cnt] 1096 .camera_caps->sensor_num; 1097 isp->input_cnt++; 1098 for (i = 1; i < sensor_num; i++) { 1099 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) { 1100 dev_warn(isp->dev, 1101 "atomisp inputs out of range\n"); 1102 break; 1103 } 1104 isp->inputs[isp->input_cnt] = 1105 isp->inputs[isp->input_cnt - 1]; 1106 isp->inputs[isp->input_cnt].sensor_index = i; 1107 isp->input_cnt++; 1108 } 1109 break; 1110 case CAMERA_MOTOR: 1111 if (isp->motor) { 1112 dev_warn(isp->dev, 1113 "too many atomisp motors, ignored %s\n", 1114 board_info->type); 1115 continue; 1116 } 1117 isp->motor = subdev; 1118 break; 1119 case LED_FLASH: 1120 case XENON_FLASH: 1121 if (isp->flash) { 1122 dev_warn(isp->dev, 1123 "too many atomisp flash devices, ignored %s\n", 1124 board_info->type); 1125 continue; 1126 } 1127 isp->flash = subdev; 1128 break; 1129 default: 1130 dev_dbg(isp->dev, "unknown subdev probed\n"); 1131 break; 1132 } 1133 } 1134 1135 /* 1136 * HACK: Currently VCM belongs to primary sensor only, but correct 1137 * approach must be to acquire from platform code which sensor 1138 * owns it. 1139 */ 1140 if (isp->motor && raw_index >= 0) 1141 isp->inputs[raw_index].motor = isp->motor; 1142 1143 /* Proceed even if no modules detected. For COS mode and no modules. */ 1144 if (!isp->input_cnt) 1145 dev_warn(isp->dev, "no camera attached or fail to detect\n"); 1146 else 1147 dev_info(isp->dev, "detected %d camera sensors\n", 1148 isp->input_cnt); 1149 1150 return atomisp_csi_lane_config(isp); 1151 } 1152 1153 static void atomisp_unregister_entities(struct atomisp_device *isp) 1154 { 1155 unsigned int i; 1156 struct v4l2_subdev *sd, *next; 1157 1158 for (i = 0; i < isp->num_of_streams; i++) 1159 atomisp_subdev_unregister_entities(&isp->asd[i]); 1160 atomisp_tpg_unregister_entities(&isp->tpg); 1161 atomisp_file_input_unregister_entities(&isp->file_dev); 1162 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) 1163 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); 1164 1165 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list) 1166 v4l2_device_unregister_subdev(sd); 1167 1168 v4l2_device_unregister(&isp->v4l2_dev); 1169 media_device_unregister(&isp->media_dev); 1170 media_device_cleanup(&isp->media_dev); 1171 } 1172 1173 static int atomisp_register_entities(struct atomisp_device *isp) 1174 { 1175 int ret = 0; 1176 unsigned int i; 1177 1178 isp->media_dev.dev = isp->dev; 1179 1180 strscpy(isp->media_dev.model, "Intel Atom ISP", 1181 sizeof(isp->media_dev.model)); 1182 1183 media_device_init(&isp->media_dev); 1184 isp->v4l2_dev.mdev = &isp->media_dev; 1185 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev); 1186 if (ret < 0) { 1187 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n", 1188 __func__, ret); 1189 goto v4l2_device_failed; 1190 } 1191 1192 ret = atomisp_subdev_probe(isp); 1193 if (ret < 0) 1194 goto csi_and_subdev_probe_failed; 1195 1196 /* Register internal entities */ 1197 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { 1198 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i], 1199 &isp->v4l2_dev); 1200 if (ret == 0) 1201 continue; 1202 1203 /* error case */ 1204 dev_err(isp->dev, "failed to register the CSI port: %d\n", i); 1205 /* deregister all registered CSI ports */ 1206 while (i--) 1207 atomisp_mipi_csi2_unregister_entities( 1208 &isp->csi2_port[i]); 1209 1210 goto csi_and_subdev_probe_failed; 1211 } 1212 1213 ret = 1214 atomisp_file_input_register_entities(&isp->file_dev, &isp->v4l2_dev); 1215 if (ret < 0) { 1216 dev_err(isp->dev, "atomisp_file_input_register_entities\n"); 1217 goto file_input_register_failed; 1218 } 1219 1220 ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev); 1221 if (ret < 0) { 1222 dev_err(isp->dev, "atomisp_tpg_register_entities\n"); 1223 goto tpg_register_failed; 1224 } 1225 1226 for (i = 0; i < isp->num_of_streams; i++) { 1227 struct atomisp_sub_device *asd = &isp->asd[i]; 1228 1229 ret = atomisp_subdev_register_entities(asd, &isp->v4l2_dev); 1230 if (ret < 0) { 1231 dev_err(isp->dev, 1232 "atomisp_subdev_register_entities fail\n"); 1233 for (; i > 0; i--) 1234 atomisp_subdev_unregister_entities( 1235 &isp->asd[i - 1]); 1236 goto subdev_register_failed; 1237 } 1238 } 1239 1240 for (i = 0; i < isp->num_of_streams; i++) { 1241 struct atomisp_sub_device *asd = &isp->asd[i]; 1242 1243 init_completion(&asd->init_done); 1244 1245 asd->delayed_init_workq = 1246 alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE, 1247 1); 1248 if (!asd->delayed_init_workq) { 1249 dev_err(isp->dev, 1250 "Failed to initialize delayed init workq\n"); 1251 ret = -ENOMEM; 1252 1253 for (; i > 0; i--) 1254 destroy_workqueue(isp->asd[i - 1]. 1255 delayed_init_workq); 1256 goto wq_alloc_failed; 1257 } 1258 INIT_WORK(&asd->delayed_init_work, atomisp_delayed_init_work); 1259 } 1260 1261 for (i = 0; i < isp->input_cnt; i++) { 1262 if (isp->inputs[i].port >= ATOMISP_CAMERA_NR_PORTS) { 1263 dev_err(isp->dev, "isp->inputs port %d not supported\n", 1264 isp->inputs[i].port); 1265 ret = -EINVAL; 1266 goto link_failed; 1267 } 1268 } 1269 1270 dev_dbg(isp->dev, 1271 "FILE_INPUT enable, camera_cnt: %d\n", isp->input_cnt); 1272 isp->inputs[isp->input_cnt].type = FILE_INPUT; 1273 isp->inputs[isp->input_cnt].port = -1; 1274 isp->inputs[isp->input_cnt].camera_caps = 1275 atomisp_get_default_camera_caps(); 1276 isp->inputs[isp->input_cnt++].camera = &isp->file_dev.sd; 1277 1278 if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) { 1279 dev_dbg(isp->dev, 1280 "TPG detected, camera_cnt: %d\n", isp->input_cnt); 1281 isp->inputs[isp->input_cnt].type = TEST_PATTERN; 1282 isp->inputs[isp->input_cnt].port = -1; 1283 isp->inputs[isp->input_cnt].camera_caps = 1284 atomisp_get_default_camera_caps(); 1285 isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd; 1286 } else { 1287 dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n"); 1288 } 1289 1290 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev); 1291 if (ret < 0) 1292 goto link_failed; 1293 1294 return media_device_register(&isp->media_dev); 1295 1296 link_failed: 1297 for (i = 0; i < isp->num_of_streams; i++) 1298 destroy_workqueue(isp->asd[i]. 1299 delayed_init_workq); 1300 wq_alloc_failed: 1301 for (i = 0; i < isp->num_of_streams; i++) 1302 atomisp_subdev_unregister_entities( 1303 &isp->asd[i]); 1304 subdev_register_failed: 1305 atomisp_tpg_unregister_entities(&isp->tpg); 1306 tpg_register_failed: 1307 atomisp_file_input_unregister_entities(&isp->file_dev); 1308 file_input_register_failed: 1309 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) 1310 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); 1311 csi_and_subdev_probe_failed: 1312 v4l2_device_unregister(&isp->v4l2_dev); 1313 v4l2_device_failed: 1314 media_device_unregister(&isp->media_dev); 1315 media_device_cleanup(&isp->media_dev); 1316 return ret; 1317 } 1318 1319 static int atomisp_initialize_modules(struct atomisp_device *isp) 1320 { 1321 int ret; 1322 1323 ret = atomisp_mipi_csi2_init(isp); 1324 if (ret < 0) { 1325 dev_err(isp->dev, "mipi csi2 initialization failed\n"); 1326 goto error_mipi_csi2; 1327 } 1328 1329 ret = atomisp_file_input_init(isp); 1330 if (ret < 0) { 1331 dev_err(isp->dev, 1332 "file input device initialization failed\n"); 1333 goto error_file_input; 1334 } 1335 1336 ret = atomisp_tpg_init(isp); 1337 if (ret < 0) { 1338 dev_err(isp->dev, "tpg initialization failed\n"); 1339 goto error_tpg; 1340 } 1341 1342 ret = atomisp_subdev_init(isp); 1343 if (ret < 0) { 1344 dev_err(isp->dev, "ISP subdev initialization failed\n"); 1345 goto error_isp_subdev; 1346 } 1347 1348 return 0; 1349 1350 error_isp_subdev: 1351 error_tpg: 1352 atomisp_tpg_cleanup(isp); 1353 error_file_input: 1354 atomisp_file_input_cleanup(isp); 1355 error_mipi_csi2: 1356 atomisp_mipi_csi2_cleanup(isp); 1357 return ret; 1358 } 1359 1360 static void atomisp_uninitialize_modules(struct atomisp_device *isp) 1361 { 1362 atomisp_tpg_cleanup(isp); 1363 atomisp_file_input_cleanup(isp); 1364 atomisp_mipi_csi2_cleanup(isp); 1365 } 1366 1367 const struct firmware * 1368 atomisp_load_firmware(struct atomisp_device *isp) 1369 { 1370 const struct firmware *fw; 1371 int rc; 1372 char *fw_path = NULL; 1373 1374 if (skip_fwload) 1375 return NULL; 1376 1377 if (firmware_name[0] != '\0') { 1378 fw_path = firmware_name; 1379 } else { 1380 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT) 1381 == ATOMISP_HW_REVISION_ISP2401) 1382 fw_path = "shisp_2401a0_v21.bin"; 1383 1384 if (isp->media_dev.hw_revision == 1385 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT) 1386 | ATOMISP_HW_STEPPING_A0)) 1387 fw_path = "shisp_2401a0_legacy_v21.bin"; 1388 1389 if (isp->media_dev.hw_revision == 1390 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT) 1391 | ATOMISP_HW_STEPPING_B0)) 1392 fw_path = "shisp_2400b0_v21.bin"; 1393 } 1394 1395 if (!fw_path) { 1396 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n", 1397 isp->media_dev.hw_revision); 1398 return NULL; 1399 } 1400 1401 rc = request_firmware(&fw, fw_path, isp->dev); 1402 if (rc) { 1403 dev_err(isp->dev, 1404 "atomisp: Error %d while requesting firmware %s\n", 1405 rc, fw_path); 1406 return NULL; 1407 } 1408 1409 return fw; 1410 } 1411 1412 /* 1413 * Check for flags the driver was compiled with against the PCI 1414 * device. Always returns true on other than ISP 2400. 1415 */ 1416 static bool is_valid_device(struct pci_dev *pdev, const struct pci_device_id *id) 1417 { 1418 const char *name; 1419 const char *product; 1420 1421 product = dmi_get_system_info(DMI_PRODUCT_NAME); 1422 1423 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { 1424 case ATOMISP_PCI_DEVICE_SOC_MRFLD: 1425 name = "Merrifield"; 1426 break; 1427 case ATOMISP_PCI_DEVICE_SOC_BYT: 1428 name = "Baytrail"; 1429 break; 1430 case ATOMISP_PCI_DEVICE_SOC_ANN: 1431 name = "Anniedale"; 1432 break; 1433 case ATOMISP_PCI_DEVICE_SOC_CHT: 1434 name = "Cherrytrail"; 1435 break; 1436 default: 1437 dev_err(&pdev->dev, "%s: unknown device ID %x04:%x04\n", 1438 product, id->vendor, id->device); 1439 return false; 1440 } 1441 1442 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) { 1443 dev_err(&pdev->dev, "%s revision %d is not unsupported\n", 1444 name, pdev->revision); 1445 return false; 1446 } 1447 1448 /* 1449 * FIXME: 1450 * remove the if once the driver become generic 1451 */ 1452 1453 #ifndef ISP2401 1454 if (IS_ISP2401) { 1455 dev_err(&pdev->dev, "Support for %s (ISP2401) was disabled at compile time\n", 1456 name); 1457 return false; 1458 } 1459 #else 1460 if (!IS_ISP2401) { 1461 dev_err(&pdev->dev, "Support for %s (ISP2400) was disabled at compile time\n", 1462 name); 1463 return false; 1464 } 1465 #endif 1466 1467 dev_info(&pdev->dev, "Detected %s version %d (ISP240%c) on %s\n", 1468 name, pdev->revision, IS_ISP2401 ? '1' : '0', product); 1469 1470 return true; 1471 } 1472 1473 static int init_atomisp_wdts(struct atomisp_device *isp) 1474 { 1475 int i, err; 1476 1477 atomic_set(&isp->wdt_work_queued, 0); 1478 isp->wdt_work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1); 1479 if (!isp->wdt_work_queue) { 1480 dev_err(isp->dev, "Failed to initialize wdt work queue\n"); 1481 err = -ENOMEM; 1482 goto alloc_fail; 1483 } 1484 INIT_WORK(&isp->wdt_work, atomisp_wdt_work); 1485 1486 for (i = 0; i < isp->num_of_streams; i++) { 1487 struct atomisp_sub_device *asd = &isp->asd[i]; 1488 1489 if (!IS_ISP2401) { 1490 timer_setup(&asd->wdt, atomisp_wdt, 0); 1491 } else { 1492 timer_setup(&asd->video_out_capture.wdt, 1493 atomisp_wdt, 0); 1494 timer_setup(&asd->video_out_preview.wdt, 1495 atomisp_wdt, 0); 1496 timer_setup(&asd->video_out_vf.wdt, atomisp_wdt, 0); 1497 timer_setup(&asd->video_out_video_capture.wdt, 1498 atomisp_wdt, 0); 1499 } 1500 } 1501 return 0; 1502 alloc_fail: 1503 return err; 1504 } 1505 1506 #define ATOM_ISP_PCI_BAR 0 1507 1508 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1509 { 1510 const struct atomisp_platform_data *pdata; 1511 struct atomisp_device *isp; 1512 unsigned int start; 1513 int err, val; 1514 u32 irq; 1515 1516 if (!is_valid_device(pdev, id)) 1517 return -ENODEV; 1518 1519 /* Pointer to struct device. */ 1520 atomisp_dev = &pdev->dev; 1521 1522 pdata = atomisp_get_platform_data(); 1523 if (!pdata) 1524 dev_warn(&pdev->dev, "no platform data available\n"); 1525 1526 err = pcim_enable_device(pdev); 1527 if (err) { 1528 dev_err(&pdev->dev, "Failed to enable CI ISP device (%d)\n", err); 1529 return err; 1530 } 1531 1532 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR); 1533 dev_dbg(&pdev->dev, "start: 0x%x\n", start); 1534 1535 err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev)); 1536 if (err) { 1537 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err); 1538 goto ioremap_fail; 1539 } 1540 1541 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL); 1542 if (!isp) { 1543 err = -ENOMEM; 1544 goto atomisp_dev_alloc_fail; 1545 } 1546 1547 isp->dev = &pdev->dev; 1548 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR]; 1549 isp->sw_contex.power_state = ATOM_ISP_POWER_UP; 1550 isp->saved_regs.ispmmadr = start; 1551 1552 dev_dbg(&pdev->dev, "atomisp mmio base: %p\n", isp->base); 1553 1554 rt_mutex_init(&isp->mutex); 1555 rt_mutex_init(&isp->loading); 1556 mutex_init(&isp->streamoff_mutex); 1557 spin_lock_init(&isp->lock); 1558 1559 /* This is not a true PCI device on SoC, so the delay is not needed. */ 1560 pdev->d3hot_delay = 0; 1561 1562 pci_set_drvdata(pdev, isp); 1563 1564 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { 1565 case ATOMISP_PCI_DEVICE_SOC_MRFLD: 1566 isp->media_dev.hw_revision = 1567 (ATOMISP_HW_REVISION_ISP2400 1568 << ATOMISP_HW_REVISION_SHIFT) | 1569 ATOMISP_HW_STEPPING_B0; 1570 1571 switch (id->device) { 1572 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179: 1573 isp->dfs = &dfs_config_merr_1179; 1574 break; 1575 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A: 1576 isp->dfs = &dfs_config_merr_117a; 1577 1578 break; 1579 default: 1580 isp->dfs = &dfs_config_merr; 1581 break; 1582 } 1583 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1584 break; 1585 case ATOMISP_PCI_DEVICE_SOC_BYT: 1586 isp->media_dev.hw_revision = 1587 (ATOMISP_HW_REVISION_ISP2400 1588 << ATOMISP_HW_REVISION_SHIFT) | 1589 ATOMISP_HW_STEPPING_B0; 1590 1591 /* 1592 * Note: some Intel-based tablets with Android use a different 1593 * DFS table. Based on the comments at the Yocto Aero meta 1594 * version of this driver (at the ssid.h header), they're 1595 * identified via a "spid" var: 1596 * 1597 * androidboot.spid=vend:cust:manu:plat:prod:hard 1598 * 1599 * As we don't have this upstream, nor we know enough details 1600 * to use a DMI or PCI match table, the old code was just 1601 * removed, but let's keep a note here as a reminder that, 1602 * for certain devices, we may need to limit the max DFS 1603 * frequency to be below certain values, adjusting the 1604 * resolution accordingly. 1605 */ 1606 isp->dfs = &dfs_config_byt; 1607 1608 /* 1609 * HPLL frequency is known to be device-specific, but we don't 1610 * have specs yet for exactly how it varies. Default to 1611 * BYT-CR but let provisioning set it via EFI variable 1612 */ 1613 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ); 1614 1615 /* 1616 * for BYT/CHT we are put isp into D3cold to avoid pci registers access 1617 * in power off. Set d3cold_delay to 0 since default 100ms is not 1618 * necessary. 1619 */ 1620 pdev->d3cold_delay = 0; 1621 break; 1622 case ATOMISP_PCI_DEVICE_SOC_ANN: 1623 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401 1624 << ATOMISP_HW_REVISION_SHIFT); 1625 isp->media_dev.hw_revision |= pdev->revision < 2 ? 1626 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; 1627 isp->dfs = &dfs_config_merr; 1628 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1629 break; 1630 case ATOMISP_PCI_DEVICE_SOC_CHT: 1631 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401 1632 << ATOMISP_HW_REVISION_SHIFT); 1633 isp->media_dev.hw_revision |= pdev->revision < 2 ? 1634 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; 1635 1636 isp->dfs = &dfs_config_cht; 1637 pdev->d3cold_delay = 0; 1638 1639 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val); 1640 switch (val & CCK_FUSE_HPLL_FREQ_MASK) { 1641 case 0x00: 1642 isp->hpll_freq = HPLL_FREQ_800MHZ; 1643 break; 1644 case 0x01: 1645 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1646 break; 1647 case 0x02: 1648 isp->hpll_freq = HPLL_FREQ_2000MHZ; 1649 break; 1650 default: 1651 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1652 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n"); 1653 } 1654 break; 1655 default: 1656 dev_err(&pdev->dev, "un-supported IUNIT device\n"); 1657 err = -ENODEV; 1658 goto atomisp_dev_alloc_fail; 1659 } 1660 1661 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq); 1662 1663 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY; 1664 1665 /* Load isp firmware from user space */ 1666 if (!defer_fw_load) { 1667 isp->firmware = atomisp_load_firmware(isp); 1668 if (!isp->firmware) { 1669 err = -ENOENT; 1670 dev_dbg(&pdev->dev, "Firmware load failed\n"); 1671 goto load_fw_fail; 1672 } 1673 1674 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data); 1675 if (err) { 1676 dev_dbg(&pdev->dev, "Firmware version check failed\n"); 1677 goto fw_validation_fail; 1678 } 1679 } else { 1680 dev_info(&pdev->dev, "Firmware load will be deferred\n"); 1681 } 1682 1683 pci_set_master(pdev); 1684 1685 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1686 if (err < 0) { 1687 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err); 1688 goto enable_msi_fail; 1689 } 1690 1691 atomisp_msi_irq_init(isp); 1692 1693 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 1694 1695 /* 1696 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of 1697 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI 1698 * backend write 0 will enable Arasan CSI backend, which has 1699 * bugs(like sighting:4567697 and 4567699) and will be removed 1700 * in B0 1701 */ 1702 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); 1703 1704 if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) == 1705 ATOMISP_PCI_DEVICE_SOC_MRFLD) { 1706 u32 csi_afe_trim; 1707 1708 /* 1709 * Workaround for imbalance data eye issue which is observed 1710 * on TNG B0. 1711 */ 1712 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &csi_afe_trim); 1713 csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1714 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | 1715 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1716 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | 1717 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1718 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT)); 1719 csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM << 1720 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | 1721 (MRFLD_PCI_CSI2_HSRXCLKTRIM << 1722 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | 1723 (MRFLD_PCI_CSI3_HSRXCLKTRIM << 1724 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT); 1725 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, csi_afe_trim); 1726 } 1727 1728 rt_mutex_lock(&isp->loading); 1729 1730 err = atomisp_initialize_modules(isp); 1731 if (err < 0) { 1732 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err); 1733 goto initialize_modules_fail; 1734 } 1735 1736 err = atomisp_register_entities(isp); 1737 if (err < 0) { 1738 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err); 1739 goto register_entities_fail; 1740 } 1741 err = atomisp_create_pads_links(isp); 1742 if (err < 0) 1743 goto register_entities_fail; 1744 /* init atomisp wdts */ 1745 err = init_atomisp_wdts(isp); 1746 if (err != 0) 1747 goto wdt_work_queue_fail; 1748 1749 /* save the iunit context only once after all the values are init'ed. */ 1750 atomisp_save_iunit_reg(isp); 1751 1752 pm_runtime_put_noidle(&pdev->dev); 1753 pm_runtime_allow(&pdev->dev); 1754 1755 /* Init ISP memory management */ 1756 hmm_init(); 1757 1758 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, 1759 atomisp_isr, atomisp_isr_thread, 1760 IRQF_SHARED, "isp_irq", isp); 1761 if (err) { 1762 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err); 1763 goto request_irq_fail; 1764 } 1765 1766 /* Load firmware into ISP memory */ 1767 if (!defer_fw_load) { 1768 err = atomisp_css_load_firmware(isp); 1769 if (err) { 1770 dev_err(&pdev->dev, "Failed to init css.\n"); 1771 goto css_init_fail; 1772 } 1773 } else { 1774 dev_dbg(&pdev->dev, "Skip css init.\n"); 1775 } 1776 /* Clear FW image from memory */ 1777 release_firmware(isp->firmware); 1778 isp->firmware = NULL; 1779 isp->css_env.isp_css_fw.data = NULL; 1780 isp->ready = true; 1781 rt_mutex_unlock(&isp->loading); 1782 1783 atomisp_drvfs_init(isp); 1784 1785 return 0; 1786 1787 css_init_fail: 1788 devm_free_irq(&pdev->dev, pdev->irq, isp); 1789 request_irq_fail: 1790 hmm_cleanup(); 1791 pm_runtime_get_noresume(&pdev->dev); 1792 destroy_workqueue(isp->wdt_work_queue); 1793 wdt_work_queue_fail: 1794 atomisp_unregister_entities(isp); 1795 register_entities_fail: 1796 atomisp_uninitialize_modules(isp); 1797 initialize_modules_fail: 1798 rt_mutex_unlock(&isp->loading); 1799 cpu_latency_qos_remove_request(&isp->pm_qos); 1800 atomisp_msi_irq_uninit(isp); 1801 pci_free_irq_vectors(pdev); 1802 enable_msi_fail: 1803 fw_validation_fail: 1804 release_firmware(isp->firmware); 1805 load_fw_fail: 1806 /* 1807 * Switch off ISP, as keeping it powered on would prevent 1808 * reaching S0ix states. 1809 * 1810 * The following lines have been copied from atomisp suspend path 1811 */ 1812 1813 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 1814 irq &= BIT(INTR_IIR); 1815 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 1816 1817 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 1818 irq &= ~BIT(INTR_IER); 1819 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 1820 1821 atomisp_msi_irq_uninit(isp); 1822 1823 atomisp_ospm_dphy_down(isp); 1824 1825 /* Address later when we worry about the ...field chips */ 1826 if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power_down(isp)) 1827 dev_err(&pdev->dev, "Failed to switch off ISP\n"); 1828 1829 atomisp_dev_alloc_fail: 1830 pcim_iounmap_regions(pdev, BIT(ATOM_ISP_PCI_BAR)); 1831 1832 ioremap_fail: 1833 return err; 1834 } 1835 1836 static void atomisp_pci_remove(struct pci_dev *pdev) 1837 { 1838 struct atomisp_device *isp = pci_get_drvdata(pdev); 1839 1840 dev_info(&pdev->dev, "Removing atomisp driver\n"); 1841 1842 atomisp_drvfs_exit(); 1843 1844 ia_css_unload_firmware(); 1845 hmm_cleanup(); 1846 1847 pm_runtime_forbid(&pdev->dev); 1848 pm_runtime_get_noresume(&pdev->dev); 1849 cpu_latency_qos_remove_request(&isp->pm_qos); 1850 1851 atomisp_msi_irq_uninit(isp); 1852 atomisp_unregister_entities(isp); 1853 1854 destroy_workqueue(isp->wdt_work_queue); 1855 atomisp_file_input_cleanup(isp); 1856 1857 release_firmware(isp->firmware); 1858 } 1859 1860 static const struct pci_device_id atomisp_pci_tbl[] = { 1861 /* Merrifield */ 1862 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)}, 1863 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)}, 1864 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)}, 1865 /* Baytrail */ 1866 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)}, 1867 /* Anniedale (Merrifield+ / Moorefield) */ 1868 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)}, 1869 /* Cherrytrail */ 1870 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)}, 1871 {0,} 1872 }; 1873 1874 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl); 1875 1876 static const struct dev_pm_ops atomisp_pm_ops = { 1877 .runtime_suspend = atomisp_runtime_suspend, 1878 .runtime_resume = atomisp_runtime_resume, 1879 .suspend = atomisp_suspend, 1880 .resume = atomisp_resume, 1881 }; 1882 1883 static struct pci_driver atomisp_pci_driver = { 1884 .driver = { 1885 .pm = &atomisp_pm_ops, 1886 }, 1887 .name = "atomisp-isp2", 1888 .id_table = atomisp_pci_tbl, 1889 .probe = atomisp_pci_probe, 1890 .remove = atomisp_pci_remove, 1891 }; 1892 1893 module_pci_driver(atomisp_pci_driver); 1894 1895 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>"); 1896 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>"); 1897 MODULE_LICENSE("GPL"); 1898 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver"); 1899