1 /* 2 * Support for Medifield PNW Camera Imaging ISP subsystem. 3 * 4 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved. 5 * 6 * Copyright (c) 2010 Silicon Hive www.siliconhive.com. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License version 10 * 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * 18 */ 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/pm_qos.h> 23 #include <linux/timer.h> 24 #include <linux/delay.h> 25 #include <linux/dmi.h> 26 #include <linux/interrupt.h> 27 28 #include <asm/iosf_mbi.h> 29 30 #include "../../include/linux/atomisp_gmin_platform.h" 31 32 #include "atomisp_cmd.h" 33 #include "atomisp_common.h" 34 #include "atomisp_fops.h" 35 #include "atomisp_file.h" 36 #include "atomisp_ioctl.h" 37 #include "atomisp_internal.h" 38 #include "atomisp_acc.h" 39 #include "atomisp-regs.h" 40 #include "atomisp_dfs_tables.h" 41 #include "atomisp_drvfs.h" 42 #include "hmm/hmm.h" 43 #include "atomisp_trace_event.h" 44 45 #include "device_access.h" 46 47 /* Timeouts to wait for all subdevs to be registered */ 48 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */ 49 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */ 50 51 /* G-Min addition: pull this in from intel_mid_pm.h */ 52 #define CSTATE_EXIT_LATENCY_C1 1 53 54 static uint skip_fwload; 55 module_param(skip_fwload, uint, 0644); 56 MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load"); 57 58 /* set reserved memory pool size in page */ 59 static unsigned int repool_pgnr; 60 module_param(repool_pgnr, uint, 0644); 61 MODULE_PARM_DESC(repool_pgnr, 62 "Set the reserved memory pool size in page (default:0)"); 63 64 /* set dynamic memory pool size in page */ 65 unsigned int dypool_pgnr = UINT_MAX; 66 module_param(dypool_pgnr, uint, 0644); 67 MODULE_PARM_DESC(dypool_pgnr, 68 "Set the dynamic memory pool size in page (default:0)"); 69 70 bool dypool_enable; 71 module_param(dypool_enable, bool, 0644); 72 MODULE_PARM_DESC(dypool_enable, 73 "dynamic memory pool enable/disable (default:disable)"); 74 75 /* memory optimization: deferred firmware loading */ 76 bool defer_fw_load; 77 module_param(defer_fw_load, bool, 0644); 78 MODULE_PARM_DESC(defer_fw_load, 79 "Defer FW loading until device is opened (default:disable)"); 80 81 /* cross componnet debug message flag */ 82 int dbg_level; 83 module_param(dbg_level, int, 0644); 84 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)"); 85 86 /* log function switch */ 87 int dbg_func = 2; 88 module_param(dbg_func, int, 0644); 89 MODULE_PARM_DESC(dbg_func, 90 "log function switch non/trace_printk/printk (default:printk)"); 91 92 int mipicsi_flag; 93 module_param(mipicsi_flag, int, 0644); 94 MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm"); 95 96 /*set to 16x16 since this is the amount of lines and pixels the sensor 97 exports extra. If these are kept at the 10x8 that they were on, in yuv 98 downscaling modes incorrect resolutions where requested to the sensor 99 driver with strange outcomes as a result. The proper way tot do this 100 would be to have a list of tables the specify the sensor res, mipi rec, 101 output res, and isp output res. however since we do not have this yet, 102 the chosen solution is the next best thing. */ 103 int pad_w = 16; 104 module_param(pad_w, int, 0644); 105 MODULE_PARM_DESC(pad_w, "extra data for ISP processing"); 106 107 int pad_h = 16; 108 module_param(pad_h, int, 0644); 109 MODULE_PARM_DESC(pad_h, "extra data for ISP processing"); 110 111 /* 112 * FIXME: this is a hack to make easier to support ISP2401 variant. 113 * As a given system will either be ISP2401 or not, we can just use 114 * a boolean, in order to replace existing #ifdef ISP2401 everywhere. 115 * 116 * Once this driver gets into a better shape, however, the best would 117 * be to replace this to something stored inside atomisp allocated 118 * structures. 119 */ 120 bool atomisp_hw_is_isp2401; 121 122 /* Types of atomisp hardware */ 123 #define HW_IS_ISP2400 0 124 #define HW_IS_ISP2401 1 125 126 struct device *atomisp_dev; 127 128 void __iomem *atomisp_io_base; 129 130 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = { 131 { 132 .width = ISP_FREQ_RULE_ANY, 133 .height = ISP_FREQ_RULE_ANY, 134 .fps = ISP_FREQ_RULE_ANY, 135 .isp_freq = ISP_FREQ_400MHZ, 136 .run_mode = ATOMISP_RUN_MODE_VIDEO, 137 }, 138 { 139 .width = ISP_FREQ_RULE_ANY, 140 .height = ISP_FREQ_RULE_ANY, 141 .fps = ISP_FREQ_RULE_ANY, 142 .isp_freq = ISP_FREQ_400MHZ, 143 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 144 }, 145 { 146 .width = ISP_FREQ_RULE_ANY, 147 .height = ISP_FREQ_RULE_ANY, 148 .fps = ISP_FREQ_RULE_ANY, 149 .isp_freq = ISP_FREQ_400MHZ, 150 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 151 }, 152 { 153 .width = ISP_FREQ_RULE_ANY, 154 .height = ISP_FREQ_RULE_ANY, 155 .fps = ISP_FREQ_RULE_ANY, 156 .isp_freq = ISP_FREQ_400MHZ, 157 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 158 }, 159 { 160 .width = ISP_FREQ_RULE_ANY, 161 .height = ISP_FREQ_RULE_ANY, 162 .fps = ISP_FREQ_RULE_ANY, 163 .isp_freq = ISP_FREQ_457MHZ, 164 .run_mode = ATOMISP_RUN_MODE_SDV, 165 }, 166 }; 167 168 /* Merrifield and Moorefield DFS rules */ 169 static const struct atomisp_dfs_config dfs_config_merr = { 170 .lowest_freq = ISP_FREQ_200MHZ, 171 .max_freq_at_vmin = ISP_FREQ_400MHZ, 172 .highest_freq = ISP_FREQ_457MHZ, 173 .dfs_table = dfs_rules_merr, 174 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr), 175 }; 176 177 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = { 178 { 179 .width = ISP_FREQ_RULE_ANY, 180 .height = ISP_FREQ_RULE_ANY, 181 .fps = ISP_FREQ_RULE_ANY, 182 .isp_freq = ISP_FREQ_400MHZ, 183 .run_mode = ATOMISP_RUN_MODE_VIDEO, 184 }, 185 { 186 .width = ISP_FREQ_RULE_ANY, 187 .height = ISP_FREQ_RULE_ANY, 188 .fps = ISP_FREQ_RULE_ANY, 189 .isp_freq = ISP_FREQ_400MHZ, 190 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 191 }, 192 { 193 .width = ISP_FREQ_RULE_ANY, 194 .height = ISP_FREQ_RULE_ANY, 195 .fps = ISP_FREQ_RULE_ANY, 196 .isp_freq = ISP_FREQ_400MHZ, 197 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 198 }, 199 { 200 .width = ISP_FREQ_RULE_ANY, 201 .height = ISP_FREQ_RULE_ANY, 202 .fps = ISP_FREQ_RULE_ANY, 203 .isp_freq = ISP_FREQ_400MHZ, 204 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 205 }, 206 { 207 .width = ISP_FREQ_RULE_ANY, 208 .height = ISP_FREQ_RULE_ANY, 209 .fps = ISP_FREQ_RULE_ANY, 210 .isp_freq = ISP_FREQ_400MHZ, 211 .run_mode = ATOMISP_RUN_MODE_SDV, 212 }, 213 }; 214 215 static const struct atomisp_dfs_config dfs_config_merr_1179 = { 216 .lowest_freq = ISP_FREQ_200MHZ, 217 .max_freq_at_vmin = ISP_FREQ_400MHZ, 218 .highest_freq = ISP_FREQ_400MHZ, 219 .dfs_table = dfs_rules_merr_1179, 220 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179), 221 }; 222 223 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = { 224 { 225 .width = 1920, 226 .height = 1080, 227 .fps = 30, 228 .isp_freq = ISP_FREQ_266MHZ, 229 .run_mode = ATOMISP_RUN_MODE_VIDEO, 230 }, 231 { 232 .width = 1080, 233 .height = 1920, 234 .fps = 30, 235 .isp_freq = ISP_FREQ_266MHZ, 236 .run_mode = ATOMISP_RUN_MODE_VIDEO, 237 }, 238 { 239 .width = 1920, 240 .height = 1080, 241 .fps = 45, 242 .isp_freq = ISP_FREQ_320MHZ, 243 .run_mode = ATOMISP_RUN_MODE_VIDEO, 244 }, 245 { 246 .width = 1080, 247 .height = 1920, 248 .fps = 45, 249 .isp_freq = ISP_FREQ_320MHZ, 250 .run_mode = ATOMISP_RUN_MODE_VIDEO, 251 }, 252 { 253 .width = ISP_FREQ_RULE_ANY, 254 .height = ISP_FREQ_RULE_ANY, 255 .fps = 60, 256 .isp_freq = ISP_FREQ_356MHZ, 257 .run_mode = ATOMISP_RUN_MODE_VIDEO, 258 }, 259 { 260 .width = ISP_FREQ_RULE_ANY, 261 .height = ISP_FREQ_RULE_ANY, 262 .fps = ISP_FREQ_RULE_ANY, 263 .isp_freq = ISP_FREQ_200MHZ, 264 .run_mode = ATOMISP_RUN_MODE_VIDEO, 265 }, 266 { 267 .width = ISP_FREQ_RULE_ANY, 268 .height = ISP_FREQ_RULE_ANY, 269 .fps = ISP_FREQ_RULE_ANY, 270 .isp_freq = ISP_FREQ_400MHZ, 271 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 272 }, 273 { 274 .width = ISP_FREQ_RULE_ANY, 275 .height = ISP_FREQ_RULE_ANY, 276 .fps = ISP_FREQ_RULE_ANY, 277 .isp_freq = ISP_FREQ_400MHZ, 278 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 279 }, 280 { 281 .width = ISP_FREQ_RULE_ANY, 282 .height = ISP_FREQ_RULE_ANY, 283 .fps = ISP_FREQ_RULE_ANY, 284 .isp_freq = ISP_FREQ_200MHZ, 285 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 286 }, 287 { 288 .width = ISP_FREQ_RULE_ANY, 289 .height = ISP_FREQ_RULE_ANY, 290 .fps = ISP_FREQ_RULE_ANY, 291 .isp_freq = ISP_FREQ_400MHZ, 292 .run_mode = ATOMISP_RUN_MODE_SDV, 293 }, 294 }; 295 296 static struct atomisp_dfs_config dfs_config_merr_117a = { 297 .lowest_freq = ISP_FREQ_200MHZ, 298 .max_freq_at_vmin = ISP_FREQ_200MHZ, 299 .highest_freq = ISP_FREQ_400MHZ, 300 .dfs_table = dfs_rules_merr_117a, 301 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a), 302 }; 303 304 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = { 305 { 306 .width = ISP_FREQ_RULE_ANY, 307 .height = ISP_FREQ_RULE_ANY, 308 .fps = ISP_FREQ_RULE_ANY, 309 .isp_freq = ISP_FREQ_400MHZ, 310 .run_mode = ATOMISP_RUN_MODE_VIDEO, 311 }, 312 { 313 .width = ISP_FREQ_RULE_ANY, 314 .height = ISP_FREQ_RULE_ANY, 315 .fps = ISP_FREQ_RULE_ANY, 316 .isp_freq = ISP_FREQ_400MHZ, 317 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 318 }, 319 { 320 .width = ISP_FREQ_RULE_ANY, 321 .height = ISP_FREQ_RULE_ANY, 322 .fps = ISP_FREQ_RULE_ANY, 323 .isp_freq = ISP_FREQ_400MHZ, 324 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 325 }, 326 { 327 .width = ISP_FREQ_RULE_ANY, 328 .height = ISP_FREQ_RULE_ANY, 329 .fps = ISP_FREQ_RULE_ANY, 330 .isp_freq = ISP_FREQ_400MHZ, 331 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 332 }, 333 { 334 .width = ISP_FREQ_RULE_ANY, 335 .height = ISP_FREQ_RULE_ANY, 336 .fps = ISP_FREQ_RULE_ANY, 337 .isp_freq = ISP_FREQ_400MHZ, 338 .run_mode = ATOMISP_RUN_MODE_SDV, 339 }, 340 }; 341 342 static const struct atomisp_dfs_config dfs_config_byt = { 343 .lowest_freq = ISP_FREQ_200MHZ, 344 .max_freq_at_vmin = ISP_FREQ_400MHZ, 345 .highest_freq = ISP_FREQ_400MHZ, 346 .dfs_table = dfs_rules_byt, 347 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt), 348 }; 349 350 static const struct atomisp_freq_scaling_rule dfs_rules_byt_cr[] = { 351 { 352 .width = ISP_FREQ_RULE_ANY, 353 .height = ISP_FREQ_RULE_ANY, 354 .fps = ISP_FREQ_RULE_ANY, 355 .isp_freq = ISP_FREQ_320MHZ, 356 .run_mode = ATOMISP_RUN_MODE_VIDEO, 357 }, 358 { 359 .width = ISP_FREQ_RULE_ANY, 360 .height = ISP_FREQ_RULE_ANY, 361 .fps = ISP_FREQ_RULE_ANY, 362 .isp_freq = ISP_FREQ_320MHZ, 363 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 364 }, 365 { 366 .width = ISP_FREQ_RULE_ANY, 367 .height = ISP_FREQ_RULE_ANY, 368 .fps = ISP_FREQ_RULE_ANY, 369 .isp_freq = ISP_FREQ_320MHZ, 370 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 371 }, 372 { 373 .width = ISP_FREQ_RULE_ANY, 374 .height = ISP_FREQ_RULE_ANY, 375 .fps = ISP_FREQ_RULE_ANY, 376 .isp_freq = ISP_FREQ_320MHZ, 377 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 378 }, 379 { 380 .width = ISP_FREQ_RULE_ANY, 381 .height = ISP_FREQ_RULE_ANY, 382 .fps = ISP_FREQ_RULE_ANY, 383 .isp_freq = ISP_FREQ_320MHZ, 384 .run_mode = ATOMISP_RUN_MODE_SDV, 385 }, 386 }; 387 388 static const struct atomisp_dfs_config dfs_config_byt_cr = { 389 .lowest_freq = ISP_FREQ_200MHZ, 390 .max_freq_at_vmin = ISP_FREQ_320MHZ, 391 .highest_freq = ISP_FREQ_320MHZ, 392 .dfs_table = dfs_rules_byt_cr, 393 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt_cr), 394 }; 395 396 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = { 397 { 398 .width = ISP_FREQ_RULE_ANY, 399 .height = ISP_FREQ_RULE_ANY, 400 .fps = ISP_FREQ_RULE_ANY, 401 .isp_freq = ISP_FREQ_320MHZ, 402 .run_mode = ATOMISP_RUN_MODE_VIDEO, 403 }, 404 { 405 .width = ISP_FREQ_RULE_ANY, 406 .height = ISP_FREQ_RULE_ANY, 407 .fps = ISP_FREQ_RULE_ANY, 408 .isp_freq = ISP_FREQ_356MHZ, 409 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 410 }, 411 { 412 .width = ISP_FREQ_RULE_ANY, 413 .height = ISP_FREQ_RULE_ANY, 414 .fps = ISP_FREQ_RULE_ANY, 415 .isp_freq = ISP_FREQ_320MHZ, 416 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 417 }, 418 { 419 .width = ISP_FREQ_RULE_ANY, 420 .height = ISP_FREQ_RULE_ANY, 421 .fps = ISP_FREQ_RULE_ANY, 422 .isp_freq = ISP_FREQ_320MHZ, 423 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 424 }, 425 { 426 .width = 1280, 427 .height = 720, 428 .fps = ISP_FREQ_RULE_ANY, 429 .isp_freq = ISP_FREQ_320MHZ, 430 .run_mode = ATOMISP_RUN_MODE_SDV, 431 }, 432 { 433 .width = ISP_FREQ_RULE_ANY, 434 .height = ISP_FREQ_RULE_ANY, 435 .fps = ISP_FREQ_RULE_ANY, 436 .isp_freq = ISP_FREQ_356MHZ, 437 .run_mode = ATOMISP_RUN_MODE_SDV, 438 }, 439 }; 440 441 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = { 442 { 443 .width = ISP_FREQ_RULE_ANY, 444 .height = ISP_FREQ_RULE_ANY, 445 .fps = ISP_FREQ_RULE_ANY, 446 .isp_freq = ISP_FREQ_356MHZ, 447 .run_mode = ATOMISP_RUN_MODE_VIDEO, 448 }, 449 { 450 .width = ISP_FREQ_RULE_ANY, 451 .height = ISP_FREQ_RULE_ANY, 452 .fps = ISP_FREQ_RULE_ANY, 453 .isp_freq = ISP_FREQ_356MHZ, 454 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 455 }, 456 { 457 .width = ISP_FREQ_RULE_ANY, 458 .height = ISP_FREQ_RULE_ANY, 459 .fps = ISP_FREQ_RULE_ANY, 460 .isp_freq = ISP_FREQ_320MHZ, 461 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 462 }, 463 { 464 .width = ISP_FREQ_RULE_ANY, 465 .height = ISP_FREQ_RULE_ANY, 466 .fps = ISP_FREQ_RULE_ANY, 467 .isp_freq = ISP_FREQ_320MHZ, 468 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 469 }, 470 { 471 .width = ISP_FREQ_RULE_ANY, 472 .height = ISP_FREQ_RULE_ANY, 473 .fps = ISP_FREQ_RULE_ANY, 474 .isp_freq = ISP_FREQ_356MHZ, 475 .run_mode = ATOMISP_RUN_MODE_SDV, 476 }, 477 }; 478 479 static const struct atomisp_dfs_config dfs_config_cht = { 480 .lowest_freq = ISP_FREQ_100MHZ, 481 .max_freq_at_vmin = ISP_FREQ_356MHZ, 482 .highest_freq = ISP_FREQ_356MHZ, 483 .dfs_table = dfs_rules_cht, 484 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht), 485 }; 486 487 /* This one should be visible also by atomisp_cmd.c */ 488 const struct atomisp_dfs_config dfs_config_cht_soc = { 489 .lowest_freq = ISP_FREQ_100MHZ, 490 .max_freq_at_vmin = ISP_FREQ_356MHZ, 491 .highest_freq = ISP_FREQ_356MHZ, 492 .dfs_table = dfs_rules_cht_soc, 493 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc), 494 }; 495 496 int atomisp_video_init(struct atomisp_video_pipe *video, const char *name) 497 { 498 int ret; 499 const char *direction; 500 501 switch (video->type) { 502 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 503 direction = "output"; 504 video->pad.flags = MEDIA_PAD_FL_SINK; 505 video->vdev.fops = &atomisp_fops; 506 video->vdev.ioctl_ops = &atomisp_ioctl_ops; 507 break; 508 case V4L2_BUF_TYPE_VIDEO_OUTPUT: 509 direction = "input"; 510 video->pad.flags = MEDIA_PAD_FL_SOURCE; 511 video->vdev.fops = &atomisp_file_fops; 512 video->vdev.ioctl_ops = &atomisp_file_ioctl_ops; 513 break; 514 default: 515 return -EINVAL; 516 } 517 518 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad); 519 if (ret < 0) 520 return ret; 521 522 /* Initialize the video device. */ 523 snprintf(video->vdev.name, sizeof(video->vdev.name), 524 "ATOMISP ISP %s %s", name, direction); 525 video->vdev.release = video_device_release_empty; 526 video_set_drvdata(&video->vdev, video->isp); 527 528 return 0; 529 } 530 531 void atomisp_acc_init(struct atomisp_acc_pipe *video, const char *name) 532 { 533 video->vdev.fops = &atomisp_fops; 534 video->vdev.ioctl_ops = &atomisp_ioctl_ops; 535 536 /* Initialize the video device. */ 537 snprintf(video->vdev.name, sizeof(video->vdev.name), 538 "ATOMISP ISP %s", name); 539 video->vdev.release = video_device_release_empty; 540 video_set_drvdata(&video->vdev, video->isp); 541 } 542 543 void atomisp_video_unregister(struct atomisp_video_pipe *video) 544 { 545 if (video_is_registered(&video->vdev)) { 546 media_entity_cleanup(&video->vdev.entity); 547 video_unregister_device(&video->vdev); 548 } 549 } 550 551 void atomisp_acc_unregister(struct atomisp_acc_pipe *video) 552 { 553 if (video_is_registered(&video->vdev)) 554 video_unregister_device(&video->vdev); 555 } 556 557 static int atomisp_save_iunit_reg(struct atomisp_device *isp) 558 { 559 struct pci_dev *dev = isp->pdev; 560 561 dev_dbg(isp->dev, "%s\n", __func__); 562 563 pci_read_config_word(dev, PCI_COMMAND, &isp->saved_regs.pcicmdsts); 564 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */ 565 pci_read_config_dword(dev, PCI_MSI_CAPID, &isp->saved_regs.msicap); 566 pci_read_config_dword(dev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr); 567 pci_read_config_word(dev, PCI_MSI_DATA, &isp->saved_regs.msi_data); 568 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr); 569 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, 570 &isp->saved_regs.interrupt_control); 571 572 pci_read_config_dword(dev, MRFLD_PCI_PMCS, 573 &isp->saved_regs.pmcs); 574 /* Ensure read/write combining is enabled. */ 575 pci_read_config_dword(dev, PCI_I_CONTROL, 576 &isp->saved_regs.i_control); 577 isp->saved_regs.i_control |= 578 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING | 579 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING; 580 pci_read_config_dword(dev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, 581 &isp->saved_regs.csi_access_viol); 582 pci_read_config_dword(dev, MRFLD_PCI_CSI_RCOMP_CONTROL, 583 &isp->saved_regs.csi_rcomp_config); 584 /* 585 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE. 586 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path 587 * and sensor sending "continuous clock". 588 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence 589 * is missed, and IUNIT can hang. 590 * For both issues, setting this bit is a workaround. 591 */ 592 isp->saved_regs.csi_rcomp_config |= 593 MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE; 594 pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 595 &isp->saved_regs.csi_afe_dly); 596 pci_read_config_dword(dev, MRFLD_PCI_CSI_CONTROL, 597 &isp->saved_regs.csi_control); 598 if (isp->media_dev.hw_revision >= 599 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT)) 600 isp->saved_regs.csi_control |= 601 MRFLD_PCI_CSI_CONTROL_PARPATHEN; 602 /* 603 * On CHT CSI_READY bit should be enabled before stream on 604 */ 605 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << 606 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0))) 607 isp->saved_regs.csi_control |= 608 MRFLD_PCI_CSI_CONTROL_CSI_READY; 609 pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, 610 &isp->saved_regs.csi_afe_rcomp_config); 611 pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_HS_CONTROL, 612 &isp->saved_regs.csi_afe_hs_control); 613 pci_read_config_dword(dev, MRFLD_PCI_CSI_DEADLINE_CONTROL, 614 &isp->saved_regs.csi_deadline_control); 615 return 0; 616 } 617 618 static int __maybe_unused atomisp_restore_iunit_reg(struct atomisp_device *isp) 619 { 620 struct pci_dev *dev = isp->pdev; 621 622 dev_dbg(isp->dev, "%s\n", __func__); 623 624 pci_write_config_word(dev, PCI_COMMAND, isp->saved_regs.pcicmdsts); 625 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 626 isp->saved_regs.ispmmadr); 627 pci_write_config_dword(dev, PCI_MSI_CAPID, isp->saved_regs.msicap); 628 pci_write_config_dword(dev, PCI_MSI_ADDR, isp->saved_regs.msi_addr); 629 pci_write_config_word(dev, PCI_MSI_DATA, isp->saved_regs.msi_data); 630 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, isp->saved_regs.intr); 631 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, 632 isp->saved_regs.interrupt_control); 633 pci_write_config_dword(dev, PCI_I_CONTROL, 634 isp->saved_regs.i_control); 635 636 pci_write_config_dword(dev, MRFLD_PCI_PMCS, 637 isp->saved_regs.pmcs); 638 pci_write_config_dword(dev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, 639 isp->saved_regs.csi_access_viol); 640 pci_write_config_dword(dev, MRFLD_PCI_CSI_RCOMP_CONTROL, 641 isp->saved_regs.csi_rcomp_config); 642 pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 643 isp->saved_regs.csi_afe_dly); 644 pci_write_config_dword(dev, MRFLD_PCI_CSI_CONTROL, 645 isp->saved_regs.csi_control); 646 pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, 647 isp->saved_regs.csi_afe_rcomp_config); 648 pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_HS_CONTROL, 649 isp->saved_regs.csi_afe_hs_control); 650 pci_write_config_dword(dev, MRFLD_PCI_CSI_DEADLINE_CONTROL, 651 isp->saved_regs.csi_deadline_control); 652 653 /* 654 * for MRFLD, Software/firmware needs to write a 1 to bit0 655 * of the register at CSI_RECEIVER_SELECTION_REG to enable 656 * SH CSI backend write 0 will enable Arasan CSI backend, 657 * which has bugs(like sighting:4567697 and 4567699) and 658 * will be removed in B0 659 */ 660 atomisp_store_uint32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); 661 return 0; 662 } 663 664 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp) 665 { 666 struct pci_dev *dev = isp->pdev; 667 u32 irq; 668 unsigned long flags; 669 670 spin_lock_irqsave(&isp->lock, flags); 671 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) { 672 spin_unlock_irqrestore(&isp->lock, flags); 673 dev_dbg(isp->dev, "<%s %d.\n", __func__, __LINE__); 674 return 0; 675 } 676 /* 677 * MRFLD HAS requirement: cannot power off i-unit if 678 * ISP has IRQ not serviced. 679 * So, here we need to check if there is any pending 680 * IRQ, if so, waiting for it to be served 681 */ 682 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); 683 irq = irq & 1 << INTR_IIR; 684 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq); 685 686 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); 687 if (!(irq & (1 << INTR_IIR))) 688 goto done; 689 690 atomisp_store_uint32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF); 691 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq); 692 if (irq != 0) { 693 dev_err(isp->dev, 694 "%s: fail to clear isp interrupt status reg=0x%x\n", 695 __func__, irq); 696 spin_unlock_irqrestore(&isp->lock, flags); 697 return -EAGAIN; 698 } else { 699 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); 700 irq = irq & 1 << INTR_IIR; 701 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq); 702 703 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); 704 if (!(irq & (1 << INTR_IIR))) { 705 atomisp_store_uint32(MRFLD_INTR_ENABLE_REG, 0x0); 706 goto done; 707 } 708 dev_err(isp->dev, 709 "%s: error in iunit interrupt. status reg=0x%x\n", 710 __func__, irq); 711 spin_unlock_irqrestore(&isp->lock, flags); 712 return -EAGAIN; 713 } 714 done: 715 /* 716 * MRFLD WORKAROUND: 717 * before powering off IUNIT, clear the pending interrupts 718 * and disable the interrupt. driver should avoid writing 0 719 * to IIR. It could block subsequent interrupt messages. 720 * HW sighting:4568410. 721 */ 722 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); 723 irq &= ~(1 << INTR_IER); 724 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq); 725 726 atomisp_msi_irq_uninit(isp, dev); 727 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 728 spin_unlock_irqrestore(&isp->lock, flags); 729 730 return 0; 731 } 732 733 /* 734 * WA for DDR DVFS enable/disable 735 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS 736 */ 737 static void punit_ddr_dvfs_enable(bool enable) 738 { 739 int door_bell = 1 << 8; 740 int max_wait = 30; 741 int reg; 742 743 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®); 744 if (enable) { 745 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1); 746 } else { 747 reg |= (MRFLD_BIT1 | door_bell); 748 reg &= ~(MRFLD_BIT0); 749 } 750 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg); 751 752 /* Check Req_ACK to see freq status, wait until door_bell is cleared */ 753 while ((reg & door_bell) && max_wait--) { 754 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®); 755 usleep_range(100, 500); 756 } 757 758 if (max_wait == -1) 759 pr_info("DDR DVFS, door bell is not cleared within 3ms\n"); 760 } 761 762 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable) 763 { 764 unsigned long timeout; 765 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON : 766 MRFLD_ISPSSPM0_IUNIT_POWER_OFF; 767 768 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off"); 769 770 /*WA:Enable DVFS*/ 771 if (IS_CHT && enable) 772 punit_ddr_dvfs_enable(true); 773 774 /* 775 * FIXME:WA for ECS28A, with this sleep, CTS 776 * android.hardware.camera2.cts.CameraDeviceTest#testCameraDeviceAbort 777 * PASS, no impact on other platforms 778 */ 779 if (IS_BYT && enable) 780 msleep(10); 781 782 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */ 783 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, 784 val, MRFLD_ISPSSPM0_ISPSSC_MASK); 785 786 /*WA:Enable DVFS*/ 787 if (IS_CHT && !enable) 788 punit_ddr_dvfs_enable(true); 789 790 /* 791 * There should be no IUNIT access while power-down is 792 * in progress. HW sighting: 4567865. 793 * Wait up to 50 ms for the IUNIT to shut down. 794 * And we do the same for power on. 795 */ 796 timeout = jiffies + msecs_to_jiffies(50); 797 do { 798 u32 tmp; 799 800 /* Wait until ISPSSPM0 bit[25:24] shows the right value */ 801 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp); 802 tmp = (tmp & MRFLD_ISPSSPM0_ISPSSC_MASK) >> MRFLD_ISPSSPM0_ISPSSS_OFFSET; 803 if (tmp == val) { 804 trace_ipu_cstate(enable); 805 return 0; 806 } 807 808 if (time_after(jiffies, timeout)) 809 break; 810 811 /* FIXME: experienced value for delay */ 812 usleep_range(100, 150); 813 } while (1); 814 815 if (enable) 816 msleep(10); 817 818 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off"); 819 return -EBUSY; 820 } 821 822 /* Workaround for pmu_nc_set_power_state not ready in MRFLD */ 823 int atomisp_mrfld_power_down(struct atomisp_device *isp) 824 { 825 return 0; 826 // FIXME: at least with ISP2401, the code below causes the driver to break 827 // return atomisp_mrfld_power(isp, false); 828 } 829 830 /* Workaround for pmu_nc_set_power_state not ready in MRFLD */ 831 int atomisp_mrfld_power_up(struct atomisp_device *isp) 832 { 833 return 0; 834 // FIXME: at least with ISP2401, the code below causes the driver to break 835 // return atomisp_mrfld_power(isp, true); 836 } 837 838 int atomisp_runtime_suspend(struct device *dev) 839 { 840 struct atomisp_device *isp = (struct atomisp_device *) 841 dev_get_drvdata(dev); 842 int ret; 843 844 ret = atomisp_mrfld_pre_power_down(isp); 845 if (ret) 846 return ret; 847 848 /*Turn off the ISP d-phy*/ 849 ret = atomisp_ospm_dphy_down(isp); 850 if (ret) 851 return ret; 852 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 853 return atomisp_mrfld_power_down(isp); 854 } 855 856 int atomisp_runtime_resume(struct device *dev) 857 { 858 struct atomisp_device *isp = (struct atomisp_device *) 859 dev_get_drvdata(dev); 860 int ret; 861 862 ret = atomisp_mrfld_power_up(isp); 863 if (ret) 864 return ret; 865 866 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency); 867 if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) { 868 /*Turn on ISP d-phy */ 869 ret = atomisp_ospm_dphy_up(isp); 870 if (ret) { 871 dev_err(isp->dev, "Failed to power up ISP!.\n"); 872 return -EINVAL; 873 } 874 } 875 876 /*restore register values for iUnit and iUnitPHY registers*/ 877 if (isp->saved_regs.pcicmdsts) 878 atomisp_restore_iunit_reg(isp); 879 880 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 881 return 0; 882 } 883 884 static int __maybe_unused atomisp_suspend(struct device *dev) 885 { 886 struct atomisp_device *isp = (struct atomisp_device *) 887 dev_get_drvdata(dev); 888 /* FIXME: only has one isp_subdev at present */ 889 struct atomisp_sub_device *asd = &isp->asd[0]; 890 unsigned long flags; 891 int ret; 892 893 /* 894 * FIXME: Suspend is not supported by sensors. Abort if any video 895 * node was opened. 896 */ 897 if (atomisp_dev_users(isp)) 898 return -EBUSY; 899 900 spin_lock_irqsave(&isp->lock, flags); 901 if (asd->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) { 902 spin_unlock_irqrestore(&isp->lock, flags); 903 dev_err(isp->dev, "atomisp cannot suspend at this time.\n"); 904 return -EINVAL; 905 } 906 spin_unlock_irqrestore(&isp->lock, flags); 907 908 ret = atomisp_mrfld_pre_power_down(isp); 909 if (ret) 910 return ret; 911 912 /*Turn off the ISP d-phy */ 913 ret = atomisp_ospm_dphy_down(isp); 914 if (ret) { 915 dev_err(isp->dev, "fail to power off ISP\n"); 916 return ret; 917 } 918 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 919 return atomisp_mrfld_power_down(isp); 920 } 921 922 static int __maybe_unused atomisp_resume(struct device *dev) 923 { 924 struct atomisp_device *isp = (struct atomisp_device *) 925 dev_get_drvdata(dev); 926 int ret; 927 928 ret = atomisp_mrfld_power_up(isp); 929 if (ret) 930 return ret; 931 932 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency); 933 934 /*Turn on ISP d-phy */ 935 ret = atomisp_ospm_dphy_up(isp); 936 if (ret) { 937 dev_err(isp->dev, "Failed to power up ISP!.\n"); 938 return -EINVAL; 939 } 940 941 /*restore register values for iUnit and iUnitPHY registers*/ 942 if (isp->saved_regs.pcicmdsts) 943 atomisp_restore_iunit_reg(isp); 944 945 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 946 return 0; 947 } 948 949 int atomisp_csi_lane_config(struct atomisp_device *isp) 950 { 951 static const struct { 952 u8 code; 953 u8 lanes[MRFLD_PORT_NUM]; 954 } portconfigs[] = { 955 /* Tangier/Merrifield available lane configurations */ 956 { 0x00, { 4, 1, 0 } }, /* 00000 */ 957 { 0x01, { 3, 1, 0 } }, /* 00001 */ 958 { 0x02, { 2, 1, 0 } }, /* 00010 */ 959 { 0x03, { 1, 1, 0 } }, /* 00011 */ 960 { 0x04, { 2, 1, 2 } }, /* 00100 */ 961 { 0x08, { 3, 1, 1 } }, /* 01000 */ 962 { 0x09, { 2, 1, 1 } }, /* 01001 */ 963 { 0x0a, { 1, 1, 1 } }, /* 01010 */ 964 965 /* Anniedale/Moorefield only configurations */ 966 { 0x10, { 4, 2, 0 } }, /* 10000 */ 967 { 0x11, { 3, 2, 0 } }, /* 10001 */ 968 { 0x12, { 2, 2, 0 } }, /* 10010 */ 969 { 0x13, { 1, 2, 0 } }, /* 10011 */ 970 { 0x14, { 2, 2, 2 } }, /* 10100 */ 971 { 0x18, { 3, 2, 1 } }, /* 11000 */ 972 { 0x19, { 2, 2, 1 } }, /* 11001 */ 973 { 0x1a, { 1, 2, 1 } }, /* 11010 */ 974 }; 975 976 unsigned int i, j; 977 u8 sensor_lanes[MRFLD_PORT_NUM] = { 0 }; 978 u32 csi_control; 979 int nportconfigs; 980 u32 port_config_mask; 981 int port3_lanes_shift; 982 983 if (isp->media_dev.hw_revision < 984 ATOMISP_HW_REVISION_ISP2401_LEGACY << 985 ATOMISP_HW_REVISION_SHIFT) { 986 /* Merrifield */ 987 port_config_mask = MRFLD_PORT_CONFIG_MASK; 988 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT; 989 } else { 990 /* Moorefield / Cherryview */ 991 port_config_mask = CHV_PORT_CONFIG_MASK; 992 port3_lanes_shift = CHV_PORT3_LANES_SHIFT; 993 } 994 995 if (isp->media_dev.hw_revision < 996 ATOMISP_HW_REVISION_ISP2401 << 997 ATOMISP_HW_REVISION_SHIFT) { 998 /* Merrifield / Moorefield legacy input system */ 999 nportconfigs = MRFLD_PORT_CONFIG_NUM; 1000 } else { 1001 /* Moorefield / Cherryview new input system */ 1002 nportconfigs = ARRAY_SIZE(portconfigs); 1003 } 1004 1005 for (i = 0; i < isp->input_cnt; i++) { 1006 struct camera_mipi_info *mipi_info; 1007 1008 if (isp->inputs[i].type != RAW_CAMERA && 1009 isp->inputs[i].type != SOC_CAMERA) 1010 continue; 1011 1012 mipi_info = atomisp_to_sensor_mipi_info(isp->inputs[i].camera); 1013 if (!mipi_info) 1014 continue; 1015 1016 switch (mipi_info->port) { 1017 case ATOMISP_CAMERA_PORT_PRIMARY: 1018 sensor_lanes[0] = mipi_info->num_lanes; 1019 break; 1020 case ATOMISP_CAMERA_PORT_SECONDARY: 1021 sensor_lanes[1] = mipi_info->num_lanes; 1022 break; 1023 case ATOMISP_CAMERA_PORT_TERTIARY: 1024 sensor_lanes[2] = mipi_info->num_lanes; 1025 break; 1026 default: 1027 dev_err(isp->dev, 1028 "%s: invalid port: %d for the %dth sensor\n", 1029 __func__, mipi_info->port, i); 1030 return -EINVAL; 1031 } 1032 } 1033 1034 for (i = 0; i < nportconfigs; i++) { 1035 for (j = 0; j < MRFLD_PORT_NUM; j++) 1036 if (sensor_lanes[j] && 1037 sensor_lanes[j] != portconfigs[i].lanes[j]) 1038 break; 1039 1040 if (j == MRFLD_PORT_NUM) 1041 break; /* Found matching setting */ 1042 } 1043 1044 if (i >= nportconfigs) { 1045 dev_err(isp->dev, 1046 "%s: could not find the CSI port setting for %d-%d-%d\n", 1047 __func__, 1048 sensor_lanes[0], sensor_lanes[1], sensor_lanes[2]); 1049 return -EINVAL; 1050 } 1051 1052 pci_read_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, &csi_control); 1053 csi_control &= ~port_config_mask; 1054 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT) 1055 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT)) 1056 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT)) 1057 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT)) 1058 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT) 1059 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT) 1060 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift); 1061 1062 pci_write_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, csi_control); 1063 1064 dev_dbg(isp->dev, 1065 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n", 1066 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1], 1067 portconfigs[i].lanes[2], csi_control); 1068 1069 return 0; 1070 } 1071 1072 static int atomisp_subdev_probe(struct atomisp_device *isp) 1073 { 1074 const struct atomisp_platform_data *pdata; 1075 struct intel_v4l2_subdev_table *subdevs; 1076 int ret, raw_index = -1, count; 1077 1078 pdata = atomisp_get_platform_data(); 1079 if (!pdata) { 1080 dev_err(isp->dev, "no platform data available\n"); 1081 return 0; 1082 } 1083 1084 /* FIXME: should return -EPROBE_DEFER if not all subdevs were probed */ 1085 for (count = 0; count < SUBDEV_WAIT_TIMEOUT_MAX_COUNT; count++) { 1086 int camera_count = 0; 1087 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { 1088 if (subdevs->type == RAW_CAMERA || 1089 subdevs->type == SOC_CAMERA) 1090 camera_count ++; 1091 } 1092 if (camera_count) 1093 break; 1094 msleep(SUBDEV_WAIT_TIMEOUT); 1095 count++; 1096 } 1097 /* Wait more time to give more time for subdev init code to finish */ 1098 msleep(5 * SUBDEV_WAIT_TIMEOUT); 1099 1100 /* FIXME: should, instead, use I2C probe */ 1101 1102 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { 1103 struct v4l2_subdev *subdev; 1104 struct i2c_board_info *board_info = 1105 &subdevs->v4l2_subdev.board_info; 1106 struct i2c_adapter *adapter = 1107 i2c_get_adapter(subdevs->v4l2_subdev.i2c_adapter_id); 1108 int sensor_num, i; 1109 1110 dev_info(isp->dev, "Probing Subdev %s\n", board_info->type); 1111 1112 if (!adapter) { 1113 dev_err(isp->dev, 1114 "Failed to find i2c adapter for subdev %s\n", 1115 board_info->type); 1116 break; 1117 } 1118 1119 /* In G-Min, the sensor devices will already be probed 1120 * (via ACPI) and registered, do not create new 1121 * ones */ 1122 subdev = atomisp_gmin_find_subdev(adapter, board_info); 1123 if (!subdev) { 1124 dev_warn(isp->dev, "Subdev %s not found\n", 1125 board_info->type); 1126 continue; 1127 } 1128 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdev); 1129 if (ret) { 1130 dev_warn(isp->dev, "Subdev %s detection fail\n", 1131 board_info->type); 1132 continue; 1133 } 1134 1135 if (!subdev) { 1136 dev_warn(isp->dev, "Subdev %s detection fail\n", 1137 board_info->type); 1138 continue; 1139 } 1140 1141 dev_info(isp->dev, "Subdev %s successfully register\n", 1142 board_info->type); 1143 1144 switch (subdevs->type) { 1145 case RAW_CAMERA: 1146 raw_index = isp->input_cnt; 1147 dev_dbg(isp->dev, "raw_index: %d\n", raw_index); 1148 /* pass-though */ 1149 case SOC_CAMERA: 1150 dev_dbg(isp->dev, "SOC_INDEX: %d\n", isp->input_cnt); 1151 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) { 1152 dev_warn(isp->dev, 1153 "too many atomisp inputs, ignored\n"); 1154 break; 1155 } 1156 1157 isp->inputs[isp->input_cnt].type = subdevs->type; 1158 isp->inputs[isp->input_cnt].port = subdevs->port; 1159 isp->inputs[isp->input_cnt].camera = subdev; 1160 isp->inputs[isp->input_cnt].sensor_index = 0; 1161 /* 1162 * initialize the subdev frame size, then next we can 1163 * judge whether frame_size store effective value via 1164 * pixel_format. 1165 */ 1166 isp->inputs[isp->input_cnt].frame_size.pixel_format = 0; 1167 isp->inputs[isp->input_cnt].camera_caps = 1168 atomisp_get_default_camera_caps(); 1169 sensor_num = isp->inputs[isp->input_cnt] 1170 .camera_caps->sensor_num; 1171 isp->input_cnt++; 1172 for (i = 1; i < sensor_num; i++) { 1173 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) { 1174 dev_warn(isp->dev, 1175 "atomisp inputs out of range\n"); 1176 break; 1177 } 1178 isp->inputs[isp->input_cnt] = 1179 isp->inputs[isp->input_cnt - 1]; 1180 isp->inputs[isp->input_cnt].sensor_index = i; 1181 isp->input_cnt++; 1182 } 1183 break; 1184 case CAMERA_MOTOR: 1185 if (isp->motor) { 1186 dev_warn(isp->dev, 1187 "too many atomisp motors, ignored %s\n", 1188 board_info->type); 1189 continue; 1190 } 1191 isp->motor = subdev; 1192 break; 1193 case LED_FLASH: 1194 case XENON_FLASH: 1195 if (isp->flash) { 1196 dev_warn(isp->dev, 1197 "too many atomisp flash devices, ignored %s\n", 1198 board_info->type); 1199 continue; 1200 } 1201 isp->flash = subdev; 1202 break; 1203 default: 1204 dev_dbg(isp->dev, "unknown subdev probed\n"); 1205 break; 1206 } 1207 } 1208 1209 /* 1210 * HACK: Currently VCM belongs to primary sensor only, but correct 1211 * approach must be to acquire from platform code which sensor 1212 * owns it. 1213 */ 1214 if (isp->motor && raw_index >= 0) 1215 isp->inputs[raw_index].motor = isp->motor; 1216 1217 /* Proceed even if no modules detected. For COS mode and no modules. */ 1218 if (!isp->input_cnt) 1219 dev_warn(isp->dev, "no camera attached or fail to detect\n"); 1220 else 1221 dev_info(isp->dev, "detected %d camera sensors\n", 1222 isp->input_cnt); 1223 1224 return atomisp_csi_lane_config(isp); 1225 } 1226 1227 static void atomisp_unregister_entities(struct atomisp_device *isp) 1228 { 1229 unsigned int i; 1230 struct v4l2_subdev *sd, *next; 1231 1232 for (i = 0; i < isp->num_of_streams; i++) 1233 atomisp_subdev_unregister_entities(&isp->asd[i]); 1234 atomisp_tpg_unregister_entities(&isp->tpg); 1235 atomisp_file_input_unregister_entities(&isp->file_dev); 1236 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) 1237 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); 1238 1239 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list) 1240 v4l2_device_unregister_subdev(sd); 1241 1242 v4l2_device_unregister(&isp->v4l2_dev); 1243 media_device_unregister(&isp->media_dev); 1244 } 1245 1246 static int atomisp_register_entities(struct atomisp_device *isp) 1247 { 1248 int ret = 0; 1249 unsigned int i; 1250 1251 isp->media_dev.dev = isp->dev; 1252 1253 strlcpy(isp->media_dev.model, "Intel Atom ISP", 1254 sizeof(isp->media_dev.model)); 1255 1256 media_device_init(&isp->media_dev); 1257 isp->v4l2_dev.mdev = &isp->media_dev; 1258 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev); 1259 if (ret < 0) { 1260 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n", 1261 __func__, ret); 1262 goto v4l2_device_failed; 1263 } 1264 1265 ret = atomisp_subdev_probe(isp); 1266 if (ret < 0) 1267 goto csi_and_subdev_probe_failed; 1268 1269 /* Register internal entities */ 1270 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { 1271 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i], 1272 &isp->v4l2_dev); 1273 if (ret == 0) 1274 continue; 1275 1276 /* error case */ 1277 dev_err(isp->dev, "failed to register the CSI port: %d\n", i); 1278 /* deregister all registered CSI ports */ 1279 while (i--) 1280 atomisp_mipi_csi2_unregister_entities( 1281 &isp->csi2_port[i]); 1282 1283 goto csi_and_subdev_probe_failed; 1284 } 1285 1286 ret = 1287 atomisp_file_input_register_entities(&isp->file_dev, &isp->v4l2_dev); 1288 if (ret < 0) { 1289 dev_err(isp->dev, "atomisp_file_input_register_entities\n"); 1290 goto file_input_register_failed; 1291 } 1292 1293 ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev); 1294 if (ret < 0) { 1295 dev_err(isp->dev, "atomisp_tpg_register_entities\n"); 1296 goto tpg_register_failed; 1297 } 1298 1299 for (i = 0; i < isp->num_of_streams; i++) { 1300 struct atomisp_sub_device *asd = &isp->asd[i]; 1301 1302 ret = atomisp_subdev_register_entities(asd, &isp->v4l2_dev); 1303 if (ret < 0) { 1304 dev_err(isp->dev, 1305 "atomisp_subdev_register_entities fail\n"); 1306 for (; i > 0; i--) 1307 atomisp_subdev_unregister_entities( 1308 &isp->asd[i - 1]); 1309 goto subdev_register_failed; 1310 } 1311 } 1312 1313 for (i = 0; i < isp->num_of_streams; i++) { 1314 struct atomisp_sub_device *asd = &isp->asd[i]; 1315 1316 init_completion(&asd->init_done); 1317 1318 asd->delayed_init_workq = 1319 alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE, 1320 1); 1321 if (!asd->delayed_init_workq) { 1322 dev_err(isp->dev, 1323 "Failed to initialize delayed init workq\n"); 1324 ret = -ENOMEM; 1325 1326 for (; i > 0; i--) 1327 destroy_workqueue(isp->asd[i - 1]. 1328 delayed_init_workq); 1329 goto wq_alloc_failed; 1330 } 1331 INIT_WORK(&asd->delayed_init_work, atomisp_delayed_init_work); 1332 } 1333 1334 for (i = 0; i < isp->input_cnt; i++) { 1335 if (isp->inputs[i].port >= ATOMISP_CAMERA_NR_PORTS) { 1336 dev_err(isp->dev, "isp->inputs port %d not supported\n", 1337 isp->inputs[i].port); 1338 ret = -EINVAL; 1339 goto link_failed; 1340 } 1341 } 1342 1343 dev_dbg(isp->dev, 1344 "FILE_INPUT enable, camera_cnt: %d\n", isp->input_cnt); 1345 isp->inputs[isp->input_cnt].type = FILE_INPUT; 1346 isp->inputs[isp->input_cnt].port = -1; 1347 isp->inputs[isp->input_cnt].camera_caps = 1348 atomisp_get_default_camera_caps(); 1349 isp->inputs[isp->input_cnt++].camera = &isp->file_dev.sd; 1350 1351 if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) { 1352 dev_dbg(isp->dev, 1353 "TPG detected, camera_cnt: %d\n", isp->input_cnt); 1354 isp->inputs[isp->input_cnt].type = TEST_PATTERN; 1355 isp->inputs[isp->input_cnt].port = -1; 1356 isp->inputs[isp->input_cnt].camera_caps = 1357 atomisp_get_default_camera_caps(); 1358 isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd; 1359 } else { 1360 dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n"); 1361 } 1362 1363 ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev); 1364 if (ret < 0) 1365 goto link_failed; 1366 1367 return media_device_register(&isp->media_dev); 1368 1369 link_failed: 1370 for (i = 0; i < isp->num_of_streams; i++) 1371 destroy_workqueue(isp->asd[i]. 1372 delayed_init_workq); 1373 wq_alloc_failed: 1374 for (i = 0; i < isp->num_of_streams; i++) 1375 atomisp_subdev_unregister_entities( 1376 &isp->asd[i]); 1377 subdev_register_failed: 1378 atomisp_tpg_unregister_entities(&isp->tpg); 1379 tpg_register_failed: 1380 atomisp_file_input_unregister_entities(&isp->file_dev); 1381 file_input_register_failed: 1382 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) 1383 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); 1384 csi_and_subdev_probe_failed: 1385 v4l2_device_unregister(&isp->v4l2_dev); 1386 v4l2_device_failed: 1387 media_device_unregister(&isp->media_dev); 1388 media_device_cleanup(&isp->media_dev); 1389 return ret; 1390 } 1391 1392 static int atomisp_initialize_modules(struct atomisp_device *isp) 1393 { 1394 int ret; 1395 1396 ret = atomisp_mipi_csi2_init(isp); 1397 if (ret < 0) { 1398 dev_err(isp->dev, "mipi csi2 initialization failed\n"); 1399 goto error_mipi_csi2; 1400 } 1401 1402 ret = atomisp_file_input_init(isp); 1403 if (ret < 0) { 1404 dev_err(isp->dev, 1405 "file input device initialization failed\n"); 1406 goto error_file_input; 1407 } 1408 1409 ret = atomisp_tpg_init(isp); 1410 if (ret < 0) { 1411 dev_err(isp->dev, "tpg initialization failed\n"); 1412 goto error_tpg; 1413 } 1414 1415 ret = atomisp_subdev_init(isp); 1416 if (ret < 0) { 1417 dev_err(isp->dev, "ISP subdev initialization failed\n"); 1418 goto error_isp_subdev; 1419 } 1420 1421 return 0; 1422 1423 error_isp_subdev: 1424 error_tpg: 1425 atomisp_tpg_cleanup(isp); 1426 error_file_input: 1427 atomisp_file_input_cleanup(isp); 1428 error_mipi_csi2: 1429 atomisp_mipi_csi2_cleanup(isp); 1430 return ret; 1431 } 1432 1433 static void atomisp_uninitialize_modules(struct atomisp_device *isp) 1434 { 1435 atomisp_tpg_cleanup(isp); 1436 atomisp_file_input_cleanup(isp); 1437 atomisp_mipi_csi2_cleanup(isp); 1438 } 1439 1440 const struct firmware * 1441 atomisp_load_firmware(struct atomisp_device *isp) 1442 { 1443 const struct firmware *fw; 1444 int rc; 1445 char *fw_path = NULL; 1446 1447 if (skip_fwload) 1448 return NULL; 1449 1450 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT) 1451 == ATOMISP_HW_REVISION_ISP2401) 1452 fw_path = "shisp_2401a0_v21.bin"; 1453 1454 if (isp->media_dev.hw_revision == 1455 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT) 1456 | ATOMISP_HW_STEPPING_A0)) 1457 fw_path = "shisp_2401a0_legacy_v21.bin"; 1458 1459 if (isp->media_dev.hw_revision == 1460 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT) 1461 | ATOMISP_HW_STEPPING_B0)) 1462 fw_path = "shisp_2400b0_v21.bin"; 1463 1464 if (!fw_path) { 1465 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n", 1466 isp->media_dev.hw_revision); 1467 return NULL; 1468 } 1469 1470 rc = request_firmware(&fw, fw_path, isp->dev); 1471 if (rc) { 1472 dev_err(isp->dev, 1473 "atomisp: Error %d while requesting firmware %s\n", 1474 rc, fw_path); 1475 return NULL; 1476 } 1477 1478 return fw; 1479 } 1480 1481 /* 1482 * Check for flags the driver was compiled with against the PCI 1483 * device. Always returns true on other than ISP 2400. 1484 */ 1485 static bool is_valid_device(struct pci_dev *dev, 1486 const struct pci_device_id *id) 1487 { 1488 unsigned int a0_max_id = 0; 1489 const char *name; 1490 const char *product; 1491 1492 product = dmi_get_system_info(DMI_PRODUCT_NAME); 1493 1494 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { 1495 case ATOMISP_PCI_DEVICE_SOC_MRFLD: 1496 a0_max_id = ATOMISP_PCI_REV_MRFLD_A0_MAX; 1497 atomisp_hw_is_isp2401 = false; 1498 name = "Merrifield"; 1499 break; 1500 case ATOMISP_PCI_DEVICE_SOC_BYT: 1501 a0_max_id = ATOMISP_PCI_REV_BYT_A0_MAX; 1502 atomisp_hw_is_isp2401 = false; 1503 name = "Baytrail"; 1504 break; 1505 case ATOMISP_PCI_DEVICE_SOC_ANN: 1506 name = "Anniedale"; 1507 atomisp_hw_is_isp2401 = true; 1508 break; 1509 case ATOMISP_PCI_DEVICE_SOC_CHT: 1510 name = "Cherrytrail"; 1511 atomisp_hw_is_isp2401 = true; 1512 break; 1513 default: 1514 dev_err(&dev->dev, "%s: unknown device ID %x04:%x04\n", 1515 product, id->vendor, id->device); 1516 return false; 1517 } 1518 1519 if (dev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) { 1520 dev_err(&dev->dev, "%s revision %d is not unsupported\n", 1521 name, dev->revision); 1522 return false; 1523 } 1524 1525 /* 1526 * FIXME: 1527 * remove the if once the driver become generic 1528 */ 1529 1530 #if defined(ISP2400) 1531 if (atomisp_hw_is_isp2401) { 1532 dev_err(&dev->dev, "Support for %s (ISP2401) was disabled at compile time\n", 1533 name); 1534 return false; 1535 } 1536 #else 1537 if (!atomisp_hw_is_isp2401) { 1538 dev_err(&dev->dev, "Support for %s (ISP2400) was disabled at compile time\n", 1539 name); 1540 return false; 1541 } 1542 #endif 1543 1544 dev_info(&dev->dev, "Detected %s version %d (ISP240%c) on %s\n", 1545 name, dev->revision, 1546 atomisp_hw_is_isp2401 ? '1' : '0', 1547 product); 1548 1549 return true; 1550 } 1551 1552 static int init_atomisp_wdts(struct atomisp_device *isp) 1553 { 1554 int i, err; 1555 1556 atomic_set(&isp->wdt_work_queued, 0); 1557 isp->wdt_work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1); 1558 if (!isp->wdt_work_queue) { 1559 dev_err(isp->dev, "Failed to initialize wdt work queue\n"); 1560 err = -ENOMEM; 1561 goto alloc_fail; 1562 } 1563 INIT_WORK(&isp->wdt_work, atomisp_wdt_work); 1564 1565 for (i = 0; i < isp->num_of_streams; i++) { 1566 struct atomisp_sub_device *asd = &isp->asd[i]; 1567 if (!atomisp_hw_is_isp2401) 1568 timer_setup(&asd->wdt, atomisp_wdt, 0); 1569 else { 1570 timer_setup(&asd->video_out_capture.wdt, 1571 atomisp_wdt, 0); 1572 timer_setup(&asd->video_out_preview.wdt, 1573 atomisp_wdt, 0); 1574 timer_setup(&asd->video_out_vf.wdt, atomisp_wdt, 0); 1575 timer_setup(&asd->video_out_video_capture.wdt, 1576 atomisp_wdt, 0); 1577 } 1578 } 1579 return 0; 1580 alloc_fail: 1581 return err; 1582 } 1583 1584 #define ATOM_ISP_PCI_BAR 0 1585 1586 static int atomisp_pci_probe(struct pci_dev *dev, 1587 const struct pci_device_id *id) 1588 { 1589 const struct atomisp_platform_data *pdata; 1590 struct atomisp_device *isp; 1591 unsigned int start; 1592 void __iomem *base; 1593 int err, val; 1594 u32 irq; 1595 1596 if (!is_valid_device(dev, id)) 1597 return -ENODEV; 1598 1599 /* Pointer to struct device. */ 1600 atomisp_dev = &dev->dev; 1601 1602 pdata = atomisp_get_platform_data(); 1603 if (!pdata) 1604 dev_warn(&dev->dev, "no platform data available\n"); 1605 1606 err = pcim_enable_device(dev); 1607 if (err) { 1608 dev_err(&dev->dev, "Failed to enable CI ISP device (%d)\n", 1609 err); 1610 return err; 1611 } 1612 1613 start = pci_resource_start(dev, ATOM_ISP_PCI_BAR); 1614 dev_dbg(&dev->dev, "start: 0x%x\n", start); 1615 1616 err = pcim_iomap_regions(dev, 1 << ATOM_ISP_PCI_BAR, pci_name(dev)); 1617 if (err) { 1618 dev_err(&dev->dev, "Failed to I/O memory remapping (%d)\n", 1619 err); 1620 goto ioremap_fail; 1621 } 1622 1623 base = pcim_iomap_table(dev)[ATOM_ISP_PCI_BAR]; 1624 dev_dbg(&dev->dev, "base: %p\n", base); 1625 1626 atomisp_io_base = base; 1627 1628 dev_dbg(&dev->dev, "atomisp_io_base: %p\n", atomisp_io_base); 1629 1630 isp = devm_kzalloc(&dev->dev, sizeof(struct atomisp_device), GFP_KERNEL); 1631 if (!isp) { 1632 err = -ENOMEM; 1633 goto atomisp_dev_alloc_fail; 1634 } 1635 isp->pdev = dev; 1636 isp->dev = &dev->dev; 1637 isp->sw_contex.power_state = ATOM_ISP_POWER_UP; 1638 isp->saved_regs.ispmmadr = start; 1639 1640 rt_mutex_init(&isp->mutex); 1641 mutex_init(&isp->streamoff_mutex); 1642 spin_lock_init(&isp->lock); 1643 1644 /* This is not a true PCI device on SoC, so the delay is not needed. */ 1645 isp->pdev->d3_delay = 0; 1646 1647 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { 1648 case ATOMISP_PCI_DEVICE_SOC_MRFLD: 1649 isp->media_dev.hw_revision = 1650 (ATOMISP_HW_REVISION_ISP2400 1651 << ATOMISP_HW_REVISION_SHIFT) | 1652 ATOMISP_HW_STEPPING_B0; 1653 1654 switch (id->device) { 1655 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179: 1656 isp->dfs = &dfs_config_merr_1179; 1657 break; 1658 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A: 1659 isp->dfs = &dfs_config_merr_117a; 1660 1661 break; 1662 default: 1663 isp->dfs = &dfs_config_merr; 1664 break; 1665 } 1666 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1667 break; 1668 case ATOMISP_PCI_DEVICE_SOC_BYT: 1669 isp->media_dev.hw_revision = 1670 (ATOMISP_HW_REVISION_ISP2400 1671 << ATOMISP_HW_REVISION_SHIFT) | 1672 ATOMISP_HW_STEPPING_B0; 1673 #ifdef FIXME 1674 if (INTEL_MID_BOARD(3, TABLET, BYT, BLK, PRO, CRV2) || 1675 INTEL_MID_BOARD(3, TABLET, BYT, BLK, ENG, CRV2)) { 1676 isp->dfs = &dfs_config_byt_cr; 1677 isp->hpll_freq = HPLL_FREQ_2000MHZ; 1678 } else 1679 #endif 1680 { 1681 isp->dfs = &dfs_config_byt; 1682 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1683 } 1684 /* HPLL frequency is known to be device-specific, but we don't 1685 * have specs yet for exactly how it varies. Default to 1686 * BYT-CR but let provisioning set it via EFI variable */ 1687 isp->hpll_freq = gmin_get_var_int(&dev->dev, false, "HpllFreq", 1688 HPLL_FREQ_2000MHZ); 1689 1690 /* 1691 * for BYT/CHT we are put isp into D3cold to avoid pci registers access 1692 * in power off. Set d3cold_delay to 0 since default 100ms is not 1693 * necessary. 1694 */ 1695 isp->pdev->d3cold_delay = 0; 1696 break; 1697 case ATOMISP_PCI_DEVICE_SOC_ANN: 1698 isp->media_dev.hw_revision = ( 1699 #ifdef ISP2401_NEW_INPUT_SYSTEM 1700 ATOMISP_HW_REVISION_ISP2401 1701 #else 1702 ATOMISP_HW_REVISION_ISP2401_LEGACY 1703 #endif 1704 << ATOMISP_HW_REVISION_SHIFT); 1705 isp->media_dev.hw_revision |= isp->pdev->revision < 2 ? 1706 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; 1707 isp->dfs = &dfs_config_merr; 1708 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1709 break; 1710 case ATOMISP_PCI_DEVICE_SOC_CHT: 1711 isp->media_dev.hw_revision = ( 1712 #ifdef ISP2401_NEW_INPUT_SYSTEM 1713 ATOMISP_HW_REVISION_ISP2401 1714 #else 1715 ATOMISP_HW_REVISION_ISP2401_LEGACY 1716 #endif 1717 << ATOMISP_HW_REVISION_SHIFT); 1718 isp->media_dev.hw_revision |= isp->pdev->revision < 2 ? 1719 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; 1720 1721 isp->dfs = &dfs_config_cht; 1722 isp->pdev->d3cold_delay = 0; 1723 1724 iosf_mbi_read(CCK_PORT, MBI_REG_READ, CCK_FUSE_REG_0, &val); 1725 switch (val & CCK_FUSE_HPLL_FREQ_MASK) { 1726 case 0x00: 1727 isp->hpll_freq = HPLL_FREQ_800MHZ; 1728 break; 1729 case 0x01: 1730 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1731 break; 1732 case 0x02: 1733 isp->hpll_freq = HPLL_FREQ_2000MHZ; 1734 break; 1735 default: 1736 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1737 dev_warn(isp->dev, 1738 "read HPLL from cck failed.default 1600MHz.\n"); 1739 } 1740 break; 1741 default: 1742 dev_err(&dev->dev, "un-supported IUNIT device\n"); 1743 err = -ENODEV; 1744 goto atomisp_dev_alloc_fail; 1745 } 1746 1747 dev_info(&dev->dev, "ISP HPLL frequency base = %d MHz\n", 1748 isp->hpll_freq); 1749 1750 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY; 1751 1752 /* Load isp firmware from user space */ 1753 if (!defer_fw_load) { 1754 isp->firmware = atomisp_load_firmware(isp); 1755 if (!isp->firmware) { 1756 err = -ENOENT; 1757 dev_dbg(&dev->dev, "Firmware load failed\n"); 1758 goto load_fw_fail; 1759 } 1760 1761 err = atomisp_css_check_firmware_version(isp); 1762 if (err) { 1763 dev_dbg(&dev->dev, "Firmware version check failed\n"); 1764 goto fw_validation_fail; 1765 } 1766 } else { 1767 dev_info(&dev->dev, "Firmware load will be deferred\n"); 1768 } 1769 1770 pci_set_master(dev); 1771 pci_set_drvdata(dev, isp); 1772 1773 err = pci_enable_msi(dev); 1774 if (err) { 1775 dev_err(&dev->dev, "Failed to enable msi (%d)\n", err); 1776 goto enable_msi_fail; 1777 } 1778 1779 atomisp_msi_irq_init(isp, dev); 1780 1781 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 1782 1783 /* 1784 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of 1785 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI 1786 * backend write 0 will enable Arasan CSI backend, which has 1787 * bugs(like sighting:4567697 and 4567699) and will be removed 1788 * in B0 1789 */ 1790 atomisp_store_uint32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); 1791 1792 if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) == 1793 ATOMISP_PCI_DEVICE_SOC_MRFLD) { 1794 u32 csi_afe_trim; 1795 1796 /* 1797 * Workaround for imbalance data eye issue which is observed 1798 * on TNG B0. 1799 */ 1800 pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 1801 &csi_afe_trim); 1802 csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1803 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | 1804 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1805 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | 1806 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1807 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT)); 1808 csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM << 1809 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | 1810 (MRFLD_PCI_CSI2_HSRXCLKTRIM << 1811 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | 1812 (MRFLD_PCI_CSI3_HSRXCLKTRIM << 1813 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT); 1814 pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 1815 csi_afe_trim); 1816 } 1817 1818 err = atomisp_initialize_modules(isp); 1819 if (err < 0) { 1820 dev_err(&dev->dev, "atomisp_initialize_modules (%d)\n", err); 1821 goto initialize_modules_fail; 1822 } 1823 1824 err = atomisp_register_entities(isp); 1825 if (err < 0) { 1826 dev_err(&dev->dev, "atomisp_register_entities failed (%d)\n", 1827 err); 1828 goto register_entities_fail; 1829 } 1830 err = atomisp_create_pads_links(isp); 1831 if (err < 0) 1832 goto register_entities_fail; 1833 /* init atomisp wdts */ 1834 if (init_atomisp_wdts(isp) != 0) 1835 goto wdt_work_queue_fail; 1836 1837 /* save the iunit context only once after all the values are init'ed. */ 1838 atomisp_save_iunit_reg(isp); 1839 1840 pm_runtime_put_noidle(&dev->dev); 1841 pm_runtime_allow(&dev->dev); 1842 1843 hmm_init_mem_stat(repool_pgnr, dypool_enable, dypool_pgnr); 1844 err = hmm_pool_register(repool_pgnr, HMM_POOL_TYPE_RESERVED); 1845 if (err) { 1846 dev_err(&dev->dev, "Failed to register reserved memory pool.\n"); 1847 goto hmm_pool_fail; 1848 } 1849 1850 /* Init ISP memory management */ 1851 hmm_init(); 1852 1853 err = devm_request_threaded_irq(&dev->dev, dev->irq, 1854 atomisp_isr, atomisp_isr_thread, 1855 IRQF_SHARED, "isp_irq", isp); 1856 if (err) { 1857 dev_err(&dev->dev, "Failed to request irq (%d)\n", err); 1858 goto request_irq_fail; 1859 } 1860 1861 /* Load firmware into ISP memory */ 1862 if (!defer_fw_load) { 1863 err = atomisp_css_load_firmware(isp); 1864 if (err) { 1865 dev_err(&dev->dev, "Failed to init css.\n"); 1866 goto css_init_fail; 1867 } 1868 } else { 1869 dev_dbg(&dev->dev, "Skip css init.\n"); 1870 } 1871 /* Clear FW image from memory */ 1872 release_firmware(isp->firmware); 1873 isp->firmware = NULL; 1874 isp->css_env.isp_css_fw.data = NULL; 1875 1876 atomisp_drvfs_init(&dev->driver->driver, isp); 1877 1878 return 0; 1879 1880 css_init_fail: 1881 devm_free_irq(&dev->dev, dev->irq, isp); 1882 request_irq_fail: 1883 hmm_cleanup(); 1884 hmm_pool_unregister(HMM_POOL_TYPE_RESERVED); 1885 hmm_pool_fail: 1886 destroy_workqueue(isp->wdt_work_queue); 1887 wdt_work_queue_fail: 1888 atomisp_acc_cleanup(isp); 1889 atomisp_unregister_entities(isp); 1890 register_entities_fail: 1891 atomisp_uninitialize_modules(isp); 1892 initialize_modules_fail: 1893 cpu_latency_qos_remove_request(&isp->pm_qos); 1894 atomisp_msi_irq_uninit(isp, dev); 1895 pci_disable_msi(dev); 1896 enable_msi_fail: 1897 fw_validation_fail: 1898 release_firmware(isp->firmware); 1899 load_fw_fail: 1900 /* 1901 * Switch off ISP, as keeping it powered on would prevent 1902 * reaching S0ix states. 1903 * 1904 * The following lines have been copied from atomisp suspend path 1905 */ 1906 1907 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); 1908 irq = irq & 1 << INTR_IIR; 1909 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq); 1910 1911 pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); 1912 irq &= ~(1 << INTR_IER); 1913 pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq); 1914 1915 atomisp_msi_irq_uninit(isp, dev); 1916 1917 atomisp_ospm_dphy_down(isp); 1918 1919 /* Address later when we worry about the ...field chips */ 1920 if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power_down(isp)) 1921 dev_err(&dev->dev, "Failed to switch off ISP\n"); 1922 1923 atomisp_dev_alloc_fail: 1924 pcim_iounmap_regions(dev, 1 << ATOM_ISP_PCI_BAR); 1925 1926 ioremap_fail: 1927 return err; 1928 } 1929 1930 static void atomisp_pci_remove(struct pci_dev *dev) 1931 { 1932 struct atomisp_device *isp = (struct atomisp_device *) 1933 pci_get_drvdata(dev); 1934 1935 dev_info(&dev->dev, "Removing atomisp driver\n"); 1936 1937 atomisp_drvfs_exit(); 1938 1939 atomisp_acc_cleanup(isp); 1940 1941 atomisp_css_unload_firmware(isp); 1942 hmm_cleanup(); 1943 1944 pm_runtime_forbid(&dev->dev); 1945 pm_runtime_get_noresume(&dev->dev); 1946 cpu_latency_qos_remove_request(&isp->pm_qos); 1947 1948 atomisp_msi_irq_uninit(isp, dev); 1949 atomisp_unregister_entities(isp); 1950 1951 destroy_workqueue(isp->wdt_work_queue); 1952 atomisp_file_input_cleanup(isp); 1953 1954 release_firmware(isp->firmware); 1955 1956 hmm_pool_unregister(HMM_POOL_TYPE_RESERVED); 1957 } 1958 1959 static const struct pci_device_id atomisp_pci_tbl[] = { 1960 /* Merrifield */ 1961 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)}, 1962 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)}, 1963 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)}, 1964 /* Baytrail */ 1965 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)}, 1966 /* Anniedale (Merrifield+ / Moorefield) */ 1967 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)}, 1968 /* Cherrytrail */ 1969 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)}, 1970 {0,} 1971 }; 1972 1973 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl); 1974 1975 static const struct dev_pm_ops atomisp_pm_ops = { 1976 .runtime_suspend = atomisp_runtime_suspend, 1977 .runtime_resume = atomisp_runtime_resume, 1978 .suspend = atomisp_suspend, 1979 .resume = atomisp_resume, 1980 }; 1981 1982 static struct pci_driver atomisp_pci_driver = { 1983 .driver = { 1984 .pm = &atomisp_pm_ops, 1985 }, 1986 .name = "atomisp-isp2", 1987 .id_table = atomisp_pci_tbl, 1988 .probe = atomisp_pci_probe, 1989 .remove = atomisp_pci_remove, 1990 }; 1991 1992 module_pci_driver(atomisp_pci_driver); 1993 1994 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>"); 1995 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>"); 1996 MODULE_LICENSE("GPL"); 1997 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver"); 1998