1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for Medifield PNW Camera Imaging ISP subsystem. 4 * 5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved. 6 * 7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License version 11 * 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * 19 */ 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/pm_domain.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/pm_qos.h> 25 #include <linux/timer.h> 26 #include <linux/delay.h> 27 #include <linux/dmi.h> 28 #include <linux/interrupt.h> 29 #include <linux/bits.h> 30 31 #include <asm/iosf_mbi.h> 32 33 #include "../../include/linux/atomisp_gmin_platform.h" 34 35 #include "atomisp_cmd.h" 36 #include "atomisp_common.h" 37 #include "atomisp_fops.h" 38 #include "atomisp_ioctl.h" 39 #include "atomisp_internal.h" 40 #include "atomisp-regs.h" 41 #include "atomisp_dfs_tables.h" 42 #include "atomisp_drvfs.h" 43 #include "hmm/hmm.h" 44 #include "atomisp_trace_event.h" 45 46 #include "sh_css_firmware.h" 47 48 #include "device_access.h" 49 50 /* Timeouts to wait for all subdevs to be registered */ 51 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */ 52 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */ 53 54 /* G-Min addition: pull this in from intel_mid_pm.h */ 55 #define CSTATE_EXIT_LATENCY_C1 1 56 57 static uint skip_fwload; 58 module_param(skip_fwload, uint, 0644); 59 MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load"); 60 61 /* cross componnet debug message flag */ 62 int dbg_level; 63 module_param(dbg_level, int, 0644); 64 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)"); 65 66 /* log function switch */ 67 int dbg_func = 1; 68 module_param(dbg_func, int, 0644); 69 MODULE_PARM_DESC(dbg_func, 70 "log function switch non/printk (default:printk)"); 71 72 int mipicsi_flag; 73 module_param(mipicsi_flag, int, 0644); 74 MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm"); 75 76 static char firmware_name[256]; 77 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0); 78 MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name."); 79 80 /*set to 16x16 since this is the amount of lines and pixels the sensor 81 exports extra. If these are kept at the 10x8 that they were on, in yuv 82 downscaling modes incorrect resolutions where requested to the sensor 83 driver with strange outcomes as a result. The proper way tot do this 84 would be to have a list of tables the specify the sensor res, mipi rec, 85 output res, and isp output res. however since we do not have this yet, 86 the chosen solution is the next best thing. */ 87 int pad_w = 16; 88 module_param(pad_w, int, 0644); 89 MODULE_PARM_DESC(pad_w, "extra data for ISP processing"); 90 91 int pad_h = 16; 92 module_param(pad_h, int, 0644); 93 MODULE_PARM_DESC(pad_h, "extra data for ISP processing"); 94 95 /* 96 * FIXME: this is a hack to make easier to support ISP2401 variant. 97 * As a given system will either be ISP2401 or not, we can just use 98 * a boolean, in order to replace existing #ifdef ISP2401 everywhere. 99 * 100 * Once this driver gets into a better shape, however, the best would 101 * be to replace this to something stored inside atomisp allocated 102 * structures. 103 */ 104 105 struct device *atomisp_dev; 106 107 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = { 108 { 109 .width = ISP_FREQ_RULE_ANY, 110 .height = ISP_FREQ_RULE_ANY, 111 .fps = ISP_FREQ_RULE_ANY, 112 .isp_freq = ISP_FREQ_400MHZ, 113 .run_mode = ATOMISP_RUN_MODE_VIDEO, 114 }, 115 { 116 .width = ISP_FREQ_RULE_ANY, 117 .height = ISP_FREQ_RULE_ANY, 118 .fps = ISP_FREQ_RULE_ANY, 119 .isp_freq = ISP_FREQ_400MHZ, 120 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 121 }, 122 { 123 .width = ISP_FREQ_RULE_ANY, 124 .height = ISP_FREQ_RULE_ANY, 125 .fps = ISP_FREQ_RULE_ANY, 126 .isp_freq = ISP_FREQ_400MHZ, 127 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 128 }, 129 { 130 .width = ISP_FREQ_RULE_ANY, 131 .height = ISP_FREQ_RULE_ANY, 132 .fps = ISP_FREQ_RULE_ANY, 133 .isp_freq = ISP_FREQ_400MHZ, 134 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 135 }, 136 { 137 .width = ISP_FREQ_RULE_ANY, 138 .height = ISP_FREQ_RULE_ANY, 139 .fps = ISP_FREQ_RULE_ANY, 140 .isp_freq = ISP_FREQ_457MHZ, 141 .run_mode = ATOMISP_RUN_MODE_SDV, 142 }, 143 }; 144 145 /* Merrifield and Moorefield DFS rules */ 146 static const struct atomisp_dfs_config dfs_config_merr = { 147 .lowest_freq = ISP_FREQ_200MHZ, 148 .max_freq_at_vmin = ISP_FREQ_400MHZ, 149 .highest_freq = ISP_FREQ_457MHZ, 150 .dfs_table = dfs_rules_merr, 151 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr), 152 }; 153 154 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = { 155 { 156 .width = ISP_FREQ_RULE_ANY, 157 .height = ISP_FREQ_RULE_ANY, 158 .fps = ISP_FREQ_RULE_ANY, 159 .isp_freq = ISP_FREQ_400MHZ, 160 .run_mode = ATOMISP_RUN_MODE_VIDEO, 161 }, 162 { 163 .width = ISP_FREQ_RULE_ANY, 164 .height = ISP_FREQ_RULE_ANY, 165 .fps = ISP_FREQ_RULE_ANY, 166 .isp_freq = ISP_FREQ_400MHZ, 167 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 168 }, 169 { 170 .width = ISP_FREQ_RULE_ANY, 171 .height = ISP_FREQ_RULE_ANY, 172 .fps = ISP_FREQ_RULE_ANY, 173 .isp_freq = ISP_FREQ_400MHZ, 174 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 175 }, 176 { 177 .width = ISP_FREQ_RULE_ANY, 178 .height = ISP_FREQ_RULE_ANY, 179 .fps = ISP_FREQ_RULE_ANY, 180 .isp_freq = ISP_FREQ_400MHZ, 181 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 182 }, 183 { 184 .width = ISP_FREQ_RULE_ANY, 185 .height = ISP_FREQ_RULE_ANY, 186 .fps = ISP_FREQ_RULE_ANY, 187 .isp_freq = ISP_FREQ_400MHZ, 188 .run_mode = ATOMISP_RUN_MODE_SDV, 189 }, 190 }; 191 192 static const struct atomisp_dfs_config dfs_config_merr_1179 = { 193 .lowest_freq = ISP_FREQ_200MHZ, 194 .max_freq_at_vmin = ISP_FREQ_400MHZ, 195 .highest_freq = ISP_FREQ_400MHZ, 196 .dfs_table = dfs_rules_merr_1179, 197 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179), 198 }; 199 200 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = { 201 { 202 .width = 1920, 203 .height = 1080, 204 .fps = 30, 205 .isp_freq = ISP_FREQ_266MHZ, 206 .run_mode = ATOMISP_RUN_MODE_VIDEO, 207 }, 208 { 209 .width = 1080, 210 .height = 1920, 211 .fps = 30, 212 .isp_freq = ISP_FREQ_266MHZ, 213 .run_mode = ATOMISP_RUN_MODE_VIDEO, 214 }, 215 { 216 .width = 1920, 217 .height = 1080, 218 .fps = 45, 219 .isp_freq = ISP_FREQ_320MHZ, 220 .run_mode = ATOMISP_RUN_MODE_VIDEO, 221 }, 222 { 223 .width = 1080, 224 .height = 1920, 225 .fps = 45, 226 .isp_freq = ISP_FREQ_320MHZ, 227 .run_mode = ATOMISP_RUN_MODE_VIDEO, 228 }, 229 { 230 .width = ISP_FREQ_RULE_ANY, 231 .height = ISP_FREQ_RULE_ANY, 232 .fps = 60, 233 .isp_freq = ISP_FREQ_356MHZ, 234 .run_mode = ATOMISP_RUN_MODE_VIDEO, 235 }, 236 { 237 .width = ISP_FREQ_RULE_ANY, 238 .height = ISP_FREQ_RULE_ANY, 239 .fps = ISP_FREQ_RULE_ANY, 240 .isp_freq = ISP_FREQ_200MHZ, 241 .run_mode = ATOMISP_RUN_MODE_VIDEO, 242 }, 243 { 244 .width = ISP_FREQ_RULE_ANY, 245 .height = ISP_FREQ_RULE_ANY, 246 .fps = ISP_FREQ_RULE_ANY, 247 .isp_freq = ISP_FREQ_400MHZ, 248 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 249 }, 250 { 251 .width = ISP_FREQ_RULE_ANY, 252 .height = ISP_FREQ_RULE_ANY, 253 .fps = ISP_FREQ_RULE_ANY, 254 .isp_freq = ISP_FREQ_400MHZ, 255 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 256 }, 257 { 258 .width = ISP_FREQ_RULE_ANY, 259 .height = ISP_FREQ_RULE_ANY, 260 .fps = ISP_FREQ_RULE_ANY, 261 .isp_freq = ISP_FREQ_200MHZ, 262 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 263 }, 264 { 265 .width = ISP_FREQ_RULE_ANY, 266 .height = ISP_FREQ_RULE_ANY, 267 .fps = ISP_FREQ_RULE_ANY, 268 .isp_freq = ISP_FREQ_400MHZ, 269 .run_mode = ATOMISP_RUN_MODE_SDV, 270 }, 271 }; 272 273 static struct atomisp_dfs_config dfs_config_merr_117a = { 274 .lowest_freq = ISP_FREQ_200MHZ, 275 .max_freq_at_vmin = ISP_FREQ_200MHZ, 276 .highest_freq = ISP_FREQ_400MHZ, 277 .dfs_table = dfs_rules_merr_117a, 278 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a), 279 }; 280 281 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = { 282 { 283 .width = ISP_FREQ_RULE_ANY, 284 .height = ISP_FREQ_RULE_ANY, 285 .fps = ISP_FREQ_RULE_ANY, 286 .isp_freq = ISP_FREQ_400MHZ, 287 .run_mode = ATOMISP_RUN_MODE_VIDEO, 288 }, 289 { 290 .width = ISP_FREQ_RULE_ANY, 291 .height = ISP_FREQ_RULE_ANY, 292 .fps = ISP_FREQ_RULE_ANY, 293 .isp_freq = ISP_FREQ_400MHZ, 294 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 295 }, 296 { 297 .width = ISP_FREQ_RULE_ANY, 298 .height = ISP_FREQ_RULE_ANY, 299 .fps = ISP_FREQ_RULE_ANY, 300 .isp_freq = ISP_FREQ_400MHZ, 301 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 302 }, 303 { 304 .width = ISP_FREQ_RULE_ANY, 305 .height = ISP_FREQ_RULE_ANY, 306 .fps = ISP_FREQ_RULE_ANY, 307 .isp_freq = ISP_FREQ_400MHZ, 308 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 309 }, 310 { 311 .width = ISP_FREQ_RULE_ANY, 312 .height = ISP_FREQ_RULE_ANY, 313 .fps = ISP_FREQ_RULE_ANY, 314 .isp_freq = ISP_FREQ_400MHZ, 315 .run_mode = ATOMISP_RUN_MODE_SDV, 316 }, 317 }; 318 319 static const struct atomisp_dfs_config dfs_config_byt = { 320 .lowest_freq = ISP_FREQ_200MHZ, 321 .max_freq_at_vmin = ISP_FREQ_400MHZ, 322 .highest_freq = ISP_FREQ_400MHZ, 323 .dfs_table = dfs_rules_byt, 324 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt), 325 }; 326 327 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = { 328 { 329 .width = ISP_FREQ_RULE_ANY, 330 .height = ISP_FREQ_RULE_ANY, 331 .fps = ISP_FREQ_RULE_ANY, 332 .isp_freq = ISP_FREQ_320MHZ, 333 .run_mode = ATOMISP_RUN_MODE_VIDEO, 334 }, 335 { 336 .width = ISP_FREQ_RULE_ANY, 337 .height = ISP_FREQ_RULE_ANY, 338 .fps = ISP_FREQ_RULE_ANY, 339 .isp_freq = ISP_FREQ_356MHZ, 340 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 341 }, 342 { 343 .width = ISP_FREQ_RULE_ANY, 344 .height = ISP_FREQ_RULE_ANY, 345 .fps = ISP_FREQ_RULE_ANY, 346 .isp_freq = ISP_FREQ_320MHZ, 347 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 348 }, 349 { 350 .width = ISP_FREQ_RULE_ANY, 351 .height = ISP_FREQ_RULE_ANY, 352 .fps = ISP_FREQ_RULE_ANY, 353 .isp_freq = ISP_FREQ_320MHZ, 354 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 355 }, 356 { 357 .width = 1280, 358 .height = 720, 359 .fps = ISP_FREQ_RULE_ANY, 360 .isp_freq = ISP_FREQ_320MHZ, 361 .run_mode = ATOMISP_RUN_MODE_SDV, 362 }, 363 { 364 .width = ISP_FREQ_RULE_ANY, 365 .height = ISP_FREQ_RULE_ANY, 366 .fps = ISP_FREQ_RULE_ANY, 367 .isp_freq = ISP_FREQ_356MHZ, 368 .run_mode = ATOMISP_RUN_MODE_SDV, 369 }, 370 }; 371 372 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = { 373 { 374 .width = ISP_FREQ_RULE_ANY, 375 .height = ISP_FREQ_RULE_ANY, 376 .fps = ISP_FREQ_RULE_ANY, 377 .isp_freq = ISP_FREQ_356MHZ, 378 .run_mode = ATOMISP_RUN_MODE_VIDEO, 379 }, 380 { 381 .width = ISP_FREQ_RULE_ANY, 382 .height = ISP_FREQ_RULE_ANY, 383 .fps = ISP_FREQ_RULE_ANY, 384 .isp_freq = ISP_FREQ_356MHZ, 385 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, 386 }, 387 { 388 .width = ISP_FREQ_RULE_ANY, 389 .height = ISP_FREQ_RULE_ANY, 390 .fps = ISP_FREQ_RULE_ANY, 391 .isp_freq = ISP_FREQ_320MHZ, 392 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, 393 }, 394 { 395 .width = ISP_FREQ_RULE_ANY, 396 .height = ISP_FREQ_RULE_ANY, 397 .fps = ISP_FREQ_RULE_ANY, 398 .isp_freq = ISP_FREQ_320MHZ, 399 .run_mode = ATOMISP_RUN_MODE_PREVIEW, 400 }, 401 { 402 .width = ISP_FREQ_RULE_ANY, 403 .height = ISP_FREQ_RULE_ANY, 404 .fps = ISP_FREQ_RULE_ANY, 405 .isp_freq = ISP_FREQ_356MHZ, 406 .run_mode = ATOMISP_RUN_MODE_SDV, 407 }, 408 }; 409 410 static const struct atomisp_dfs_config dfs_config_cht = { 411 .lowest_freq = ISP_FREQ_100MHZ, 412 .max_freq_at_vmin = ISP_FREQ_356MHZ, 413 .highest_freq = ISP_FREQ_356MHZ, 414 .dfs_table = dfs_rules_cht, 415 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht), 416 }; 417 418 /* This one should be visible also by atomisp_cmd.c */ 419 const struct atomisp_dfs_config dfs_config_cht_soc = { 420 .lowest_freq = ISP_FREQ_100MHZ, 421 .max_freq_at_vmin = ISP_FREQ_356MHZ, 422 .highest_freq = ISP_FREQ_356MHZ, 423 .dfs_table = dfs_rules_cht_soc, 424 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc), 425 }; 426 427 int atomisp_video_init(struct atomisp_video_pipe *video, const char *name, 428 unsigned int run_mode) 429 { 430 int ret; 431 const char *direction; 432 433 switch (video->type) { 434 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 435 direction = "output"; 436 video->pad.flags = MEDIA_PAD_FL_SINK; 437 video->vdev.fops = &atomisp_fops; 438 video->vdev.ioctl_ops = &atomisp_ioctl_ops; 439 video->vdev.lock = &video->isp->mutex; 440 break; 441 default: 442 return -EINVAL; 443 } 444 445 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad); 446 if (ret < 0) 447 return ret; 448 449 /* Initialize the video device. */ 450 snprintf(video->vdev.name, sizeof(video->vdev.name), 451 "ATOMISP ISP %s %s", name, direction); 452 video->vdev.release = video_device_release_empty; 453 video_set_drvdata(&video->vdev, video->isp); 454 video->default_run_mode = run_mode; 455 456 return 0; 457 } 458 459 void atomisp_video_unregister(struct atomisp_video_pipe *video) 460 { 461 if (video_is_registered(&video->vdev)) { 462 media_entity_cleanup(&video->vdev.entity); 463 video_unregister_device(&video->vdev); 464 } 465 } 466 467 static int atomisp_save_iunit_reg(struct atomisp_device *isp) 468 { 469 struct pci_dev *pdev = to_pci_dev(isp->dev); 470 471 dev_dbg(isp->dev, "%s\n", __func__); 472 473 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts); 474 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */ 475 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap); 476 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr); 477 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data); 478 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr); 479 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control); 480 481 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs); 482 /* Ensure read/write combining is enabled. */ 483 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control); 484 isp->saved_regs.i_control |= 485 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING | 486 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING; 487 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, 488 &isp->saved_regs.csi_access_viol); 489 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL, 490 &isp->saved_regs.csi_rcomp_config); 491 /* 492 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE. 493 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path 494 * and sensor sending "continuous clock". 495 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence 496 * is missed, and IUNIT can hang. 497 * For both issues, setting this bit is a workaround. 498 */ 499 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE; 500 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 501 &isp->saved_regs.csi_afe_dly); 502 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, 503 &isp->saved_regs.csi_control); 504 if (isp->media_dev.hw_revision >= 505 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT)) 506 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN; 507 /* 508 * On CHT CSI_READY bit should be enabled before stream on 509 */ 510 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << 511 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0))) 512 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY; 513 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, 514 &isp->saved_regs.csi_afe_rcomp_config); 515 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL, 516 &isp->saved_regs.csi_afe_hs_control); 517 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL, 518 &isp->saved_regs.csi_deadline_control); 519 return 0; 520 } 521 522 static int atomisp_restore_iunit_reg(struct atomisp_device *isp) 523 { 524 struct pci_dev *pdev = to_pci_dev(isp->dev); 525 526 dev_dbg(isp->dev, "%s\n", __func__); 527 528 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts); 529 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr); 530 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap); 531 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr); 532 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data); 533 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr); 534 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control); 535 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control); 536 537 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs); 538 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, 539 isp->saved_regs.csi_access_viol); 540 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL, 541 isp->saved_regs.csi_rcomp_config); 542 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, 543 isp->saved_regs.csi_afe_dly); 544 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, 545 isp->saved_regs.csi_control); 546 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, 547 isp->saved_regs.csi_afe_rcomp_config); 548 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL, 549 isp->saved_regs.csi_afe_hs_control); 550 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL, 551 isp->saved_regs.csi_deadline_control); 552 553 /* 554 * for MRFLD, Software/firmware needs to write a 1 to bit0 555 * of the register at CSI_RECEIVER_SELECTION_REG to enable 556 * SH CSI backend write 0 will enable Arasan CSI backend, 557 * which has bugs(like sighting:4567697 and 4567699) and 558 * will be removed in B0 559 */ 560 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); 561 return 0; 562 } 563 564 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp) 565 { 566 struct pci_dev *pdev = to_pci_dev(isp->dev); 567 u32 irq; 568 unsigned long flags; 569 570 spin_lock_irqsave(&isp->lock, flags); 571 572 /* 573 * MRFLD HAS requirement: cannot power off i-unit if 574 * ISP has IRQ not serviced. 575 * So, here we need to check if there is any pending 576 * IRQ, if so, waiting for it to be served 577 */ 578 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 579 irq &= BIT(INTR_IIR); 580 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 581 582 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 583 if (!(irq & BIT(INTR_IIR))) 584 goto done; 585 586 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF); 587 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq); 588 if (irq != 0) { 589 dev_err(isp->dev, 590 "%s: fail to clear isp interrupt status reg=0x%x\n", 591 __func__, irq); 592 spin_unlock_irqrestore(&isp->lock, flags); 593 return -EAGAIN; 594 } else { 595 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 596 irq &= BIT(INTR_IIR); 597 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 598 599 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 600 if (!(irq & BIT(INTR_IIR))) { 601 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0); 602 goto done; 603 } 604 dev_err(isp->dev, 605 "%s: error in iunit interrupt. status reg=0x%x\n", 606 __func__, irq); 607 spin_unlock_irqrestore(&isp->lock, flags); 608 return -EAGAIN; 609 } 610 done: 611 /* 612 * MRFLD WORKAROUND: 613 * before powering off IUNIT, clear the pending interrupts 614 * and disable the interrupt. driver should avoid writing 0 615 * to IIR. It could block subsequent interrupt messages. 616 * HW sighting:4568410. 617 */ 618 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 619 irq &= ~BIT(INTR_IER); 620 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 621 622 atomisp_msi_irq_uninit(isp); 623 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 624 spin_unlock_irqrestore(&isp->lock, flags); 625 626 return 0; 627 } 628 629 /* 630 * WA for DDR DVFS enable/disable 631 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS 632 */ 633 static void punit_ddr_dvfs_enable(bool enable) 634 { 635 int reg; 636 637 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®); 638 if (enable) { 639 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1); 640 } else { 641 reg |= MRFLD_BIT1; 642 reg &= ~(MRFLD_BIT0); 643 } 644 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg); 645 } 646 647 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable) 648 { 649 struct pci_dev *pdev = to_pci_dev(isp->dev); 650 unsigned long timeout; 651 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON : 652 MRFLD_ISPSSPM0_IUNIT_POWER_OFF; 653 654 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off"); 655 656 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */ 657 if (IS_CHT && enable) { 658 punit_ddr_dvfs_enable(false); 659 msleep(20); 660 } 661 662 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */ 663 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, 664 val, MRFLD_ISPSSPM0_ISPSSC_MASK); 665 666 /* WA:Enable DVFS */ 667 if (IS_CHT && !enable) 668 punit_ddr_dvfs_enable(true); 669 670 /* 671 * There should be no IUNIT access while power-down is 672 * in progress. HW sighting: 4567865. 673 * Wait up to 50 ms for the IUNIT to shut down. 674 * And we do the same for power on. 675 */ 676 timeout = jiffies + msecs_to_jiffies(50); 677 do { 678 u32 tmp; 679 680 /* Wait until ISPSSPM0 bit[25:24] shows the right value */ 681 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp); 682 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK; 683 if (tmp == val) { 684 trace_ipu_cstate(enable); 685 pdev->current_state = enable ? PCI_D0 : PCI_D3cold; 686 return 0; 687 } 688 689 if (time_after(jiffies, timeout)) 690 break; 691 692 /* FIXME: experienced value for delay */ 693 usleep_range(100, 150); 694 } while (1); 695 696 if (enable) 697 msleep(10); 698 699 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off"); 700 return -EBUSY; 701 } 702 703 int atomisp_power_off(struct device *dev) 704 { 705 struct atomisp_device *isp = dev_get_drvdata(dev); 706 struct pci_dev *pdev = to_pci_dev(dev); 707 int ret; 708 u32 reg; 709 710 atomisp_css_uninit(isp); 711 712 ret = atomisp_mrfld_pre_power_down(isp); 713 if (ret) 714 return ret; 715 716 /* 717 * MRFLD IUNIT DPHY is located in an always-power-on island 718 * MRFLD HW design need all CSI ports are disabled before 719 * powering down the IUNIT. 720 */ 721 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, ®); 722 reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK; 723 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg); 724 725 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 726 pci_save_state(pdev); 727 return atomisp_mrfld_power(isp, false); 728 } 729 730 int atomisp_power_on(struct device *dev) 731 { 732 struct atomisp_device *isp = (struct atomisp_device *) 733 dev_get_drvdata(dev); 734 int ret; 735 736 ret = atomisp_mrfld_power(isp, true); 737 if (ret) 738 return ret; 739 740 pci_restore_state(to_pci_dev(dev)); 741 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency); 742 743 /*restore register values for iUnit and iUnitPHY registers*/ 744 if (isp->saved_regs.pcicmdsts) 745 atomisp_restore_iunit_reg(isp); 746 747 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); 748 749 return atomisp_css_init(isp); 750 } 751 752 static int atomisp_suspend(struct device *dev) 753 { 754 struct atomisp_device *isp = (struct atomisp_device *) 755 dev_get_drvdata(dev); 756 unsigned long flags; 757 758 /* 759 * FIXME: Suspend is not supported by sensors. Abort if any video 760 * node was opened. 761 */ 762 if (atomisp_dev_users(isp)) 763 return -EBUSY; 764 765 spin_lock_irqsave(&isp->lock, flags); 766 if (isp->asd.streaming != ATOMISP_DEVICE_STREAMING_DISABLED) { 767 spin_unlock_irqrestore(&isp->lock, flags); 768 dev_err(isp->dev, "atomisp cannot suspend at this time.\n"); 769 return -EINVAL; 770 } 771 spin_unlock_irqrestore(&isp->lock, flags); 772 773 pm_runtime_resume(dev); 774 775 return atomisp_power_off(dev); 776 } 777 778 static int atomisp_resume(struct device *dev) 779 { 780 return atomisp_power_on(dev); 781 } 782 783 int atomisp_csi_lane_config(struct atomisp_device *isp) 784 { 785 struct pci_dev *pdev = to_pci_dev(isp->dev); 786 static const struct { 787 u8 code; 788 u8 lanes[MRFLD_PORT_NUM]; 789 } portconfigs[] = { 790 /* Tangier/Merrifield available lane configurations */ 791 { 0x00, { 4, 1, 0 } }, /* 00000 */ 792 { 0x01, { 3, 1, 0 } }, /* 00001 */ 793 { 0x02, { 2, 1, 0 } }, /* 00010 */ 794 { 0x03, { 1, 1, 0 } }, /* 00011 */ 795 { 0x04, { 2, 1, 2 } }, /* 00100 */ 796 { 0x08, { 3, 1, 1 } }, /* 01000 */ 797 { 0x09, { 2, 1, 1 } }, /* 01001 */ 798 { 0x0a, { 1, 1, 1 } }, /* 01010 */ 799 800 /* Anniedale/Moorefield only configurations */ 801 { 0x10, { 4, 2, 0 } }, /* 10000 */ 802 { 0x11, { 3, 2, 0 } }, /* 10001 */ 803 { 0x12, { 2, 2, 0 } }, /* 10010 */ 804 { 0x13, { 1, 2, 0 } }, /* 10011 */ 805 { 0x14, { 2, 2, 2 } }, /* 10100 */ 806 { 0x18, { 3, 2, 1 } }, /* 11000 */ 807 { 0x19, { 2, 2, 1 } }, /* 11001 */ 808 { 0x1a, { 1, 2, 1 } }, /* 11010 */ 809 }; 810 811 unsigned int i, j; 812 u8 sensor_lanes[MRFLD_PORT_NUM] = { 0 }; 813 u32 csi_control; 814 int nportconfigs; 815 u32 port_config_mask; 816 int port3_lanes_shift; 817 818 if (isp->media_dev.hw_revision < 819 ATOMISP_HW_REVISION_ISP2401_LEGACY << 820 ATOMISP_HW_REVISION_SHIFT) { 821 /* Merrifield */ 822 port_config_mask = MRFLD_PORT_CONFIG_MASK; 823 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT; 824 } else { 825 /* Moorefield / Cherryview */ 826 port_config_mask = CHV_PORT_CONFIG_MASK; 827 port3_lanes_shift = CHV_PORT3_LANES_SHIFT; 828 } 829 830 if (isp->media_dev.hw_revision < 831 ATOMISP_HW_REVISION_ISP2401 << 832 ATOMISP_HW_REVISION_SHIFT) { 833 /* Merrifield / Moorefield legacy input system */ 834 nportconfigs = MRFLD_PORT_CONFIG_NUM; 835 } else { 836 /* Moorefield / Cherryview new input system */ 837 nportconfigs = ARRAY_SIZE(portconfigs); 838 } 839 840 for (i = 0; i < isp->input_cnt; i++) { 841 struct camera_mipi_info *mipi_info; 842 843 if (isp->inputs[i].type != RAW_CAMERA) 844 continue; 845 846 mipi_info = atomisp_to_sensor_mipi_info(isp->inputs[i].camera); 847 if (!mipi_info) 848 continue; 849 850 switch (mipi_info->port) { 851 case ATOMISP_CAMERA_PORT_PRIMARY: 852 sensor_lanes[0] = mipi_info->num_lanes; 853 break; 854 case ATOMISP_CAMERA_PORT_SECONDARY: 855 sensor_lanes[1] = mipi_info->num_lanes; 856 break; 857 case ATOMISP_CAMERA_PORT_TERTIARY: 858 sensor_lanes[2] = mipi_info->num_lanes; 859 break; 860 default: 861 dev_err(isp->dev, 862 "%s: invalid port: %d for the %dth sensor\n", 863 __func__, mipi_info->port, i); 864 return -EINVAL; 865 } 866 } 867 868 for (i = 0; i < nportconfigs; i++) { 869 for (j = 0; j < MRFLD_PORT_NUM; j++) 870 if (sensor_lanes[j] && 871 sensor_lanes[j] != portconfigs[i].lanes[j]) 872 break; 873 874 if (j == MRFLD_PORT_NUM) 875 break; /* Found matching setting */ 876 } 877 878 if (i >= nportconfigs) { 879 dev_err(isp->dev, 880 "%s: could not find the CSI port setting for %d-%d-%d\n", 881 __func__, 882 sensor_lanes[0], sensor_lanes[1], sensor_lanes[2]); 883 return -EINVAL; 884 } 885 886 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control); 887 csi_control &= ~port_config_mask; 888 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT) 889 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT)) 890 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT)) 891 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT)) 892 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT) 893 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT) 894 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift); 895 896 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control); 897 898 dev_dbg(isp->dev, 899 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n", 900 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1], 901 portconfigs[i].lanes[2], csi_control); 902 903 return 0; 904 } 905 906 static int atomisp_subdev_probe(struct atomisp_device *isp) 907 { 908 const struct atomisp_platform_data *pdata; 909 struct intel_v4l2_subdev_table *subdevs; 910 int ret, raw_index = -1, count; 911 912 pdata = atomisp_get_platform_data(); 913 if (!pdata) { 914 dev_err(isp->dev, "no platform data available\n"); 915 return 0; 916 } 917 918 /* FIXME: should return -EPROBE_DEFER if not all subdevs were probed */ 919 for (count = 0; count < SUBDEV_WAIT_TIMEOUT_MAX_COUNT; count++) { 920 int camera_count = 0; 921 922 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { 923 if (subdevs->type == RAW_CAMERA) 924 camera_count++; 925 } 926 if (camera_count) 927 break; 928 msleep(SUBDEV_WAIT_TIMEOUT); 929 } 930 /* Wait more time to give more time for subdev init code to finish */ 931 msleep(5 * SUBDEV_WAIT_TIMEOUT); 932 933 /* FIXME: should, instead, use I2C probe */ 934 935 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { 936 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdevs->subdev); 937 if (ret) 938 continue; 939 940 switch (subdevs->type) { 941 case RAW_CAMERA: 942 dev_dbg(isp->dev, "raw_index: %d\n", raw_index); 943 raw_index = isp->input_cnt; 944 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) { 945 dev_warn(isp->dev, 946 "too many atomisp inputs, ignored\n"); 947 break; 948 } 949 950 isp->inputs[isp->input_cnt].type = subdevs->type; 951 isp->inputs[isp->input_cnt].port = subdevs->port; 952 isp->inputs[isp->input_cnt].camera = subdevs->subdev; 953 isp->inputs[isp->input_cnt].sensor_index = 0; 954 /* 955 * initialize the subdev frame size, then next we can 956 * judge whether frame_size store effective value via 957 * pixel_format. 958 */ 959 isp->inputs[isp->input_cnt].frame_size.pixel_format = 0; 960 isp->input_cnt++; 961 break; 962 case CAMERA_MOTOR: 963 if (isp->motor) { 964 dev_warn(isp->dev, "too many atomisp motors\n"); 965 continue; 966 } 967 isp->motor = subdevs->subdev; 968 break; 969 case LED_FLASH: 970 if (isp->flash) { 971 dev_warn(isp->dev, "too many atomisp flash devices\n"); 972 continue; 973 } 974 isp->flash = subdevs->subdev; 975 break; 976 default: 977 dev_dbg(isp->dev, "unknown subdev probed\n"); 978 break; 979 } 980 } 981 982 /* 983 * HACK: Currently VCM belongs to primary sensor only, but correct 984 * approach must be to acquire from platform code which sensor 985 * owns it. 986 */ 987 if (isp->motor && raw_index >= 0) 988 isp->inputs[raw_index].motor = isp->motor; 989 990 /* Proceed even if no modules detected. For COS mode and no modules. */ 991 if (!isp->input_cnt) 992 dev_warn(isp->dev, "no camera attached or fail to detect\n"); 993 else 994 dev_info(isp->dev, "detected %d camera sensors\n", 995 isp->input_cnt); 996 997 return atomisp_csi_lane_config(isp); 998 } 999 1000 static void atomisp_unregister_entities(struct atomisp_device *isp) 1001 { 1002 unsigned int i; 1003 struct v4l2_subdev *sd, *next; 1004 1005 atomisp_subdev_unregister_entities(&isp->asd); 1006 atomisp_tpg_unregister_entities(&isp->tpg); 1007 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) 1008 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); 1009 1010 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list) 1011 v4l2_device_unregister_subdev(sd); 1012 1013 v4l2_device_unregister(&isp->v4l2_dev); 1014 media_device_unregister(&isp->media_dev); 1015 media_device_cleanup(&isp->media_dev); 1016 } 1017 1018 static int atomisp_register_entities(struct atomisp_device *isp) 1019 { 1020 int ret = 0; 1021 unsigned int i; 1022 1023 isp->media_dev.dev = isp->dev; 1024 1025 strscpy(isp->media_dev.model, "Intel Atom ISP", 1026 sizeof(isp->media_dev.model)); 1027 1028 media_device_init(&isp->media_dev); 1029 isp->v4l2_dev.mdev = &isp->media_dev; 1030 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev); 1031 if (ret < 0) { 1032 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n", 1033 __func__, ret); 1034 goto v4l2_device_failed; 1035 } 1036 1037 ret = atomisp_subdev_probe(isp); 1038 if (ret < 0) 1039 goto csi_and_subdev_probe_failed; 1040 1041 /* Register internal entities */ 1042 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { 1043 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i], 1044 &isp->v4l2_dev); 1045 if (ret == 0) 1046 continue; 1047 1048 /* error case */ 1049 dev_err(isp->dev, "failed to register the CSI port: %d\n", i); 1050 /* deregister all registered CSI ports */ 1051 while (i--) 1052 atomisp_mipi_csi2_unregister_entities( 1053 &isp->csi2_port[i]); 1054 1055 goto csi_and_subdev_probe_failed; 1056 } 1057 1058 ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev); 1059 if (ret < 0) { 1060 dev_err(isp->dev, "atomisp_tpg_register_entities\n"); 1061 goto tpg_register_failed; 1062 } 1063 1064 ret = atomisp_subdev_register_subdev(&isp->asd, &isp->v4l2_dev); 1065 if (ret < 0) { 1066 dev_err(isp->dev, "atomisp_subdev_register_subdev fail\n"); 1067 goto subdev_register_failed; 1068 } 1069 1070 for (i = 0; i < isp->input_cnt; i++) { 1071 if (isp->inputs[i].port >= ATOMISP_CAMERA_NR_PORTS) { 1072 dev_err(isp->dev, "isp->inputs port %d not supported\n", 1073 isp->inputs[i].port); 1074 ret = -EINVAL; 1075 goto link_failed; 1076 } 1077 } 1078 1079 if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) { 1080 dev_dbg(isp->dev, 1081 "TPG detected, camera_cnt: %d\n", isp->input_cnt); 1082 isp->inputs[isp->input_cnt].type = TEST_PATTERN; 1083 isp->inputs[isp->input_cnt].port = -1; 1084 isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd; 1085 } else { 1086 dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n"); 1087 } 1088 1089 return 0; 1090 1091 link_failed: 1092 atomisp_subdev_unregister_entities(&isp->asd); 1093 subdev_register_failed: 1094 atomisp_tpg_unregister_entities(&isp->tpg); 1095 tpg_register_failed: 1096 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) 1097 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); 1098 csi_and_subdev_probe_failed: 1099 v4l2_device_unregister(&isp->v4l2_dev); 1100 v4l2_device_failed: 1101 media_device_unregister(&isp->media_dev); 1102 media_device_cleanup(&isp->media_dev); 1103 return ret; 1104 } 1105 1106 static int atomisp_register_device_nodes(struct atomisp_device *isp) 1107 { 1108 int err; 1109 1110 err = atomisp_subdev_register_video_nodes(&isp->asd, &isp->v4l2_dev); 1111 if (err) 1112 return err; 1113 1114 err = atomisp_create_pads_links(isp); 1115 if (err) 1116 return err; 1117 1118 err = v4l2_device_register_subdev_nodes(&isp->v4l2_dev); 1119 if (err) 1120 return err; 1121 1122 return media_device_register(&isp->media_dev); 1123 } 1124 1125 static int atomisp_initialize_modules(struct atomisp_device *isp) 1126 { 1127 int ret; 1128 1129 ret = atomisp_mipi_csi2_init(isp); 1130 if (ret < 0) { 1131 dev_err(isp->dev, "mipi csi2 initialization failed\n"); 1132 goto error_mipi_csi2; 1133 } 1134 1135 ret = atomisp_tpg_init(isp); 1136 if (ret < 0) { 1137 dev_err(isp->dev, "tpg initialization failed\n"); 1138 goto error_tpg; 1139 } 1140 1141 ret = atomisp_subdev_init(isp); 1142 if (ret < 0) { 1143 dev_err(isp->dev, "ISP subdev initialization failed\n"); 1144 goto error_isp_subdev; 1145 } 1146 1147 return 0; 1148 1149 error_isp_subdev: 1150 error_tpg: 1151 atomisp_tpg_cleanup(isp); 1152 error_mipi_csi2: 1153 atomisp_mipi_csi2_cleanup(isp); 1154 return ret; 1155 } 1156 1157 static void atomisp_uninitialize_modules(struct atomisp_device *isp) 1158 { 1159 atomisp_tpg_cleanup(isp); 1160 atomisp_mipi_csi2_cleanup(isp); 1161 } 1162 1163 const struct firmware * 1164 atomisp_load_firmware(struct atomisp_device *isp) 1165 { 1166 const struct firmware *fw; 1167 int rc; 1168 char *fw_path = NULL; 1169 1170 if (skip_fwload) 1171 return NULL; 1172 1173 if (firmware_name[0] != '\0') { 1174 fw_path = firmware_name; 1175 } else { 1176 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT) 1177 == ATOMISP_HW_REVISION_ISP2401) 1178 fw_path = "shisp_2401a0_v21.bin"; 1179 1180 if (isp->media_dev.hw_revision == 1181 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT) 1182 | ATOMISP_HW_STEPPING_A0)) 1183 fw_path = "shisp_2401a0_legacy_v21.bin"; 1184 1185 if (isp->media_dev.hw_revision == 1186 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT) 1187 | ATOMISP_HW_STEPPING_B0)) 1188 fw_path = "shisp_2400b0_v21.bin"; 1189 } 1190 1191 if (!fw_path) { 1192 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n", 1193 isp->media_dev.hw_revision); 1194 return NULL; 1195 } 1196 1197 rc = request_firmware(&fw, fw_path, isp->dev); 1198 if (rc) { 1199 dev_err(isp->dev, 1200 "atomisp: Error %d while requesting firmware %s\n", 1201 rc, fw_path); 1202 return NULL; 1203 } 1204 1205 return fw; 1206 } 1207 1208 /* 1209 * Check for flags the driver was compiled with against the PCI 1210 * device. Always returns true on other than ISP 2400. 1211 */ 1212 static bool is_valid_device(struct pci_dev *pdev, const struct pci_device_id *id) 1213 { 1214 const char *name; 1215 const char *product; 1216 1217 product = dmi_get_system_info(DMI_PRODUCT_NAME); 1218 1219 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { 1220 case ATOMISP_PCI_DEVICE_SOC_MRFLD: 1221 name = "Merrifield"; 1222 break; 1223 case ATOMISP_PCI_DEVICE_SOC_BYT: 1224 name = "Baytrail"; 1225 break; 1226 case ATOMISP_PCI_DEVICE_SOC_ANN: 1227 name = "Anniedale"; 1228 break; 1229 case ATOMISP_PCI_DEVICE_SOC_CHT: 1230 name = "Cherrytrail"; 1231 break; 1232 default: 1233 dev_err(&pdev->dev, "%s: unknown device ID %x04:%x04\n", 1234 product, id->vendor, id->device); 1235 return false; 1236 } 1237 1238 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) { 1239 dev_err(&pdev->dev, "%s revision %d is not unsupported\n", 1240 name, pdev->revision); 1241 return false; 1242 } 1243 1244 /* 1245 * FIXME: 1246 * remove the if once the driver become generic 1247 */ 1248 1249 #ifndef ISP2401 1250 if (IS_ISP2401) { 1251 dev_err(&pdev->dev, "Support for %s (ISP2401) was disabled at compile time\n", 1252 name); 1253 return false; 1254 } 1255 #else 1256 if (!IS_ISP2401) { 1257 dev_err(&pdev->dev, "Support for %s (ISP2400) was disabled at compile time\n", 1258 name); 1259 return false; 1260 } 1261 #endif 1262 1263 dev_info(&pdev->dev, "Detected %s version %d (ISP240%c) on %s\n", 1264 name, pdev->revision, IS_ISP2401 ? '1' : '0', product); 1265 1266 return true; 1267 } 1268 1269 #define ATOM_ISP_PCI_BAR 0 1270 1271 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1272 { 1273 const struct atomisp_platform_data *pdata; 1274 struct atomisp_device *isp; 1275 unsigned int start; 1276 int err, val; 1277 u32 irq; 1278 1279 if (!is_valid_device(pdev, id)) 1280 return -ENODEV; 1281 1282 /* Pointer to struct device. */ 1283 atomisp_dev = &pdev->dev; 1284 1285 pdata = atomisp_get_platform_data(); 1286 if (!pdata) 1287 dev_warn(&pdev->dev, "no platform data available\n"); 1288 1289 err = pcim_enable_device(pdev); 1290 if (err) { 1291 dev_err(&pdev->dev, "Failed to enable CI ISP device (%d)\n", err); 1292 return err; 1293 } 1294 1295 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR); 1296 dev_dbg(&pdev->dev, "start: 0x%x\n", start); 1297 1298 err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev)); 1299 if (err) { 1300 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err); 1301 goto ioremap_fail; 1302 } 1303 1304 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL); 1305 if (!isp) { 1306 err = -ENOMEM; 1307 goto atomisp_dev_alloc_fail; 1308 } 1309 1310 isp->dev = &pdev->dev; 1311 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR]; 1312 isp->saved_regs.ispmmadr = start; 1313 1314 dev_dbg(&pdev->dev, "atomisp mmio base: %p\n", isp->base); 1315 1316 mutex_init(&isp->mutex); 1317 spin_lock_init(&isp->lock); 1318 1319 /* This is not a true PCI device on SoC, so the delay is not needed. */ 1320 pdev->d3hot_delay = 0; 1321 1322 pci_set_drvdata(pdev, isp); 1323 1324 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { 1325 case ATOMISP_PCI_DEVICE_SOC_MRFLD: 1326 isp->media_dev.hw_revision = 1327 (ATOMISP_HW_REVISION_ISP2400 1328 << ATOMISP_HW_REVISION_SHIFT) | 1329 ATOMISP_HW_STEPPING_B0; 1330 1331 switch (id->device) { 1332 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179: 1333 isp->dfs = &dfs_config_merr_1179; 1334 break; 1335 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A: 1336 isp->dfs = &dfs_config_merr_117a; 1337 1338 break; 1339 default: 1340 isp->dfs = &dfs_config_merr; 1341 break; 1342 } 1343 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1344 break; 1345 case ATOMISP_PCI_DEVICE_SOC_BYT: 1346 isp->media_dev.hw_revision = 1347 (ATOMISP_HW_REVISION_ISP2400 1348 << ATOMISP_HW_REVISION_SHIFT) | 1349 ATOMISP_HW_STEPPING_B0; 1350 1351 /* 1352 * Note: some Intel-based tablets with Android use a different 1353 * DFS table. Based on the comments at the Yocto Aero meta 1354 * version of this driver (at the ssid.h header), they're 1355 * identified via a "spid" var: 1356 * 1357 * androidboot.spid=vend:cust:manu:plat:prod:hard 1358 * 1359 * As we don't have this upstream, nor we know enough details 1360 * to use a DMI or PCI match table, the old code was just 1361 * removed, but let's keep a note here as a reminder that, 1362 * for certain devices, we may need to limit the max DFS 1363 * frequency to be below certain values, adjusting the 1364 * resolution accordingly. 1365 */ 1366 isp->dfs = &dfs_config_byt; 1367 1368 /* 1369 * HPLL frequency is known to be device-specific, but we don't 1370 * have specs yet for exactly how it varies. Default to 1371 * BYT-CR but let provisioning set it via EFI variable 1372 */ 1373 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ); 1374 1375 /* 1376 * for BYT/CHT we are put isp into D3cold to avoid pci registers access 1377 * in power off. Set d3cold_delay to 0 since default 100ms is not 1378 * necessary. 1379 */ 1380 pdev->d3cold_delay = 0; 1381 break; 1382 case ATOMISP_PCI_DEVICE_SOC_ANN: 1383 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401 1384 << ATOMISP_HW_REVISION_SHIFT); 1385 isp->media_dev.hw_revision |= pdev->revision < 2 ? 1386 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; 1387 isp->dfs = &dfs_config_merr; 1388 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1389 break; 1390 case ATOMISP_PCI_DEVICE_SOC_CHT: 1391 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401 1392 << ATOMISP_HW_REVISION_SHIFT); 1393 isp->media_dev.hw_revision |= pdev->revision < 2 ? 1394 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; 1395 1396 isp->dfs = &dfs_config_cht; 1397 pdev->d3cold_delay = 0; 1398 1399 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val); 1400 switch (val & CCK_FUSE_HPLL_FREQ_MASK) { 1401 case 0x00: 1402 isp->hpll_freq = HPLL_FREQ_800MHZ; 1403 break; 1404 case 0x01: 1405 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1406 break; 1407 case 0x02: 1408 isp->hpll_freq = HPLL_FREQ_2000MHZ; 1409 break; 1410 default: 1411 isp->hpll_freq = HPLL_FREQ_1600MHZ; 1412 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n"); 1413 } 1414 break; 1415 default: 1416 dev_err(&pdev->dev, "un-supported IUNIT device\n"); 1417 err = -ENODEV; 1418 goto atomisp_dev_alloc_fail; 1419 } 1420 1421 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq); 1422 1423 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY; 1424 1425 /* Load isp firmware from user space */ 1426 isp->firmware = atomisp_load_firmware(isp); 1427 if (!isp->firmware) { 1428 err = -ENOENT; 1429 dev_dbg(&pdev->dev, "Firmware load failed\n"); 1430 goto load_fw_fail; 1431 } 1432 1433 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data); 1434 if (err) { 1435 dev_dbg(&pdev->dev, "Firmware version check failed\n"); 1436 goto fw_validation_fail; 1437 } 1438 1439 pci_set_master(pdev); 1440 1441 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1442 if (err < 0) { 1443 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err); 1444 goto enable_msi_fail; 1445 } 1446 1447 atomisp_msi_irq_init(isp); 1448 1449 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); 1450 1451 /* 1452 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of 1453 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI 1454 * backend write 0 will enable Arasan CSI backend, which has 1455 * bugs(like sighting:4567697 and 4567699) and will be removed 1456 * in B0 1457 */ 1458 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); 1459 1460 if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) == 1461 ATOMISP_PCI_DEVICE_SOC_MRFLD) { 1462 u32 csi_afe_trim; 1463 1464 /* 1465 * Workaround for imbalance data eye issue which is observed 1466 * on TNG B0. 1467 */ 1468 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &csi_afe_trim); 1469 csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1470 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | 1471 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1472 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | 1473 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << 1474 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT)); 1475 csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM << 1476 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | 1477 (MRFLD_PCI_CSI2_HSRXCLKTRIM << 1478 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | 1479 (MRFLD_PCI_CSI3_HSRXCLKTRIM << 1480 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT); 1481 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, csi_afe_trim); 1482 } 1483 1484 err = atomisp_initialize_modules(isp); 1485 if (err < 0) { 1486 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err); 1487 goto initialize_modules_fail; 1488 } 1489 1490 err = atomisp_register_entities(isp); 1491 if (err < 0) { 1492 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err); 1493 goto register_entities_fail; 1494 } 1495 1496 INIT_WORK(&isp->assert_recovery_work, atomisp_assert_recovery_work); 1497 1498 /* save the iunit context only once after all the values are init'ed. */ 1499 atomisp_save_iunit_reg(isp); 1500 1501 /* 1502 * The atomisp does not use standard PCI power-management through the 1503 * PCI config space. Instead this driver directly tells the P-Unit to 1504 * disable the ISP over the IOSF. The standard PCI subsystem pm_ops will 1505 * try to access the config space before (resume) / after (suspend) this 1506 * driver has turned the ISP on / off, resulting in the following errors: 1507 * 1508 * "Unable to change power state from D0 to D3hot, device inaccessible" 1509 * "Unable to change power state from D3cold to D0, device inaccessible" 1510 * 1511 * To avoid these errors override the pm_domain so that all the PCI 1512 * subsys suspend / resume handling is skipped. 1513 */ 1514 isp->pm_domain.ops.runtime_suspend = atomisp_power_off; 1515 isp->pm_domain.ops.runtime_resume = atomisp_power_on; 1516 isp->pm_domain.ops.suspend = atomisp_suspend; 1517 isp->pm_domain.ops.resume = atomisp_resume; 1518 1519 dev_pm_domain_set(&pdev->dev, &isp->pm_domain); 1520 1521 pm_runtime_put_noidle(&pdev->dev); 1522 pm_runtime_allow(&pdev->dev); 1523 1524 /* Init ISP memory management */ 1525 hmm_init(); 1526 1527 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, 1528 atomisp_isr, atomisp_isr_thread, 1529 IRQF_SHARED, "isp_irq", isp); 1530 if (err) { 1531 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err); 1532 goto request_irq_fail; 1533 } 1534 1535 /* Load firmware into ISP memory */ 1536 err = atomisp_css_load_firmware(isp); 1537 if (err) { 1538 dev_err(&pdev->dev, "Failed to init css.\n"); 1539 goto css_init_fail; 1540 } 1541 /* Clear FW image from memory */ 1542 release_firmware(isp->firmware); 1543 isp->firmware = NULL; 1544 isp->css_env.isp_css_fw.data = NULL; 1545 1546 err = atomisp_register_device_nodes(isp); 1547 if (err) 1548 goto css_init_fail; 1549 1550 atomisp_drvfs_init(isp); 1551 1552 return 0; 1553 1554 css_init_fail: 1555 devm_free_irq(&pdev->dev, pdev->irq, isp); 1556 request_irq_fail: 1557 hmm_cleanup(); 1558 pm_runtime_get_noresume(&pdev->dev); 1559 dev_pm_domain_set(&pdev->dev, NULL); 1560 atomisp_unregister_entities(isp); 1561 register_entities_fail: 1562 atomisp_uninitialize_modules(isp); 1563 initialize_modules_fail: 1564 cpu_latency_qos_remove_request(&isp->pm_qos); 1565 atomisp_msi_irq_uninit(isp); 1566 pci_free_irq_vectors(pdev); 1567 enable_msi_fail: 1568 fw_validation_fail: 1569 release_firmware(isp->firmware); 1570 load_fw_fail: 1571 /* 1572 * Switch off ISP, as keeping it powered on would prevent 1573 * reaching S0ix states. 1574 * 1575 * The following lines have been copied from atomisp suspend path 1576 */ 1577 1578 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 1579 irq &= BIT(INTR_IIR); 1580 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 1581 1582 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq); 1583 irq &= ~BIT(INTR_IER); 1584 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq); 1585 1586 atomisp_msi_irq_uninit(isp); 1587 1588 /* Address later when we worry about the ...field chips */ 1589 if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power(isp, false)) 1590 dev_err(&pdev->dev, "Failed to switch off ISP\n"); 1591 1592 atomisp_dev_alloc_fail: 1593 pcim_iounmap_regions(pdev, BIT(ATOM_ISP_PCI_BAR)); 1594 1595 ioremap_fail: 1596 return err; 1597 } 1598 1599 static void atomisp_pci_remove(struct pci_dev *pdev) 1600 { 1601 struct atomisp_device *isp = pci_get_drvdata(pdev); 1602 1603 dev_info(&pdev->dev, "Removing atomisp driver\n"); 1604 1605 atomisp_drvfs_exit(); 1606 1607 ia_css_unload_firmware(); 1608 hmm_cleanup(); 1609 1610 pm_runtime_forbid(&pdev->dev); 1611 pm_runtime_get_noresume(&pdev->dev); 1612 dev_pm_domain_set(&pdev->dev, NULL); 1613 cpu_latency_qos_remove_request(&isp->pm_qos); 1614 1615 atomisp_msi_irq_uninit(isp); 1616 atomisp_unregister_entities(isp); 1617 1618 release_firmware(isp->firmware); 1619 } 1620 1621 static const struct pci_device_id atomisp_pci_tbl[] = { 1622 /* Merrifield */ 1623 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)}, 1624 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)}, 1625 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)}, 1626 /* Baytrail */ 1627 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)}, 1628 /* Anniedale (Merrifield+ / Moorefield) */ 1629 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)}, 1630 /* Cherrytrail */ 1631 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)}, 1632 {0,} 1633 }; 1634 1635 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl); 1636 1637 1638 static struct pci_driver atomisp_pci_driver = { 1639 .name = "atomisp-isp2", 1640 .id_table = atomisp_pci_tbl, 1641 .probe = atomisp_pci_probe, 1642 .remove = atomisp_pci_remove, 1643 }; 1644 1645 module_pci_driver(atomisp_pci_driver); 1646 1647 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>"); 1648 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>"); 1649 MODULE_LICENSE("GPL"); 1650 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver"); 1651