1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Support for OmniVision OV2722 1080p HD camera sensor.
4  *
5  * Copyright (c) 2013 Intel Corporation. All Rights Reserved.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License version
9  * 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  *
17  */
18 
19 #ifndef __OV2722_H__
20 #define __OV2722_H__
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/i2c.h>
24 #include <linux/delay.h>
25 #include <linux/videodev2.h>
26 #include <linux/spinlock.h>
27 #include <media/v4l2-subdev.h>
28 #include <media/v4l2-device.h>
29 #include <linux/v4l2-mediabus.h>
30 #include <media/media-entity.h>
31 #include <media/v4l2-ctrls.h>
32 
33 #include "../include/linux/atomisp_platform.h"
34 
35 #define OV2722_POWER_UP_RETRY_NUM 5
36 
37 /* Defines for register writes and register array processing */
38 #define I2C_MSG_LENGTH		0x2
39 #define I2C_RETRY_COUNT		5
40 
41 #define OV2722_FOCAL_LENGTH_NUM	278	/*2.78mm*/
42 
43 #define MAX_FMTS		1
44 
45 /*
46  * focal length bits definition:
47  * bits 31-16: numerator, bits 15-0: denominator
48  */
49 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064
50 
51 /*
52  * current f-number bits definition:
53  * bits 31-16: numerator, bits 15-0: denominator
54  */
55 #define OV2722_F_NUMBER_DEFAULT 0x1a000a
56 
57 /*
58  * f-number range bits definition:
59  * bits 31-24: max f-number numerator
60  * bits 23-16: max f-number denominator
61  * bits 15-8: min f-number numerator
62  * bits 7-0: min f-number denominator
63  */
64 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a
65 #define OV2720_ID	0x2720
66 #define OV2722_ID	0x2722
67 
68 #define OV2722_FINE_INTG_TIME_MIN 0
69 #define OV2722_FINE_INTG_TIME_MAX_MARGIN 0
70 #define OV2722_COARSE_INTG_TIME_MIN 1
71 #define OV2722_COARSE_INTG_TIME_MAX_MARGIN 4
72 
73 /*
74  * OV2722 System control registers
75  */
76 #define OV2722_SW_SLEEP				0x0100
77 #define OV2722_SW_RESET				0x0103
78 #define OV2722_SW_STREAM			0x0100
79 
80 #define OV2722_SC_CMMN_CHIP_ID_H		0x300A
81 #define OV2722_SC_CMMN_CHIP_ID_L		0x300B
82 #define OV2722_SC_CMMN_SCCB_ID			0x300C
83 #define OV2722_SC_CMMN_SUB_ID			0x302A /* process, version*/
84 
85 #define OV2722_SC_CMMN_PAD_OEN0			0x3000
86 #define OV2722_SC_CMMN_PAD_OEN1			0x3001
87 #define OV2722_SC_CMMN_PAD_OEN2			0x3002
88 #define OV2722_SC_CMMN_PAD_OUT0			0x3008
89 #define OV2722_SC_CMMN_PAD_OUT1			0x3009
90 #define OV2722_SC_CMMN_PAD_OUT2			0x300D
91 #define OV2722_SC_CMMN_PAD_SEL0			0x300E
92 #define OV2722_SC_CMMN_PAD_SEL1			0x300F
93 #define OV2722_SC_CMMN_PAD_SEL2			0x3010
94 
95 #define OV2722_SC_CMMN_PAD_PK			0x3011
96 #define OV2722_SC_CMMN_A_PWC_PK_O_13		0x3013
97 #define OV2722_SC_CMMN_A_PWC_PK_O_14		0x3014
98 
99 #define OV2722_SC_CMMN_CLKRST0			0x301A
100 #define OV2722_SC_CMMN_CLKRST1			0x301B
101 #define OV2722_SC_CMMN_CLKRST2			0x301C
102 #define OV2722_SC_CMMN_CLKRST3			0x301D
103 #define OV2722_SC_CMMN_CLKRST4			0x301E
104 #define OV2722_SC_CMMN_CLKRST5			0x3005
105 #define OV2722_SC_CMMN_PCLK_DIV_CTRL		0x3007
106 #define OV2722_SC_CMMN_CLOCK_SEL		0x3020
107 #define OV2722_SC_SOC_CLKRST5			0x3040
108 
109 #define OV2722_SC_CMMN_PLL_CTRL0		0x3034
110 #define OV2722_SC_CMMN_PLL_CTRL1		0x3035
111 #define OV2722_SC_CMMN_PLL_CTRL2		0x3039
112 #define OV2722_SC_CMMN_PLL_CTRL3		0x3037
113 #define OV2722_SC_CMMN_PLL_MULTIPLIER		0x3036
114 #define OV2722_SC_CMMN_PLL_DEBUG_OPT		0x3038
115 #define OV2722_SC_CMMN_PLLS_CTRL0		0x303A
116 #define OV2722_SC_CMMN_PLLS_CTRL1		0x303B
117 #define OV2722_SC_CMMN_PLLS_CTRL2		0x303C
118 #define OV2722_SC_CMMN_PLLS_CTRL3		0x303D
119 
120 #define OV2722_SC_CMMN_MIPI_PHY_16		0x3016
121 #define OV2722_SC_CMMN_MIPI_PHY_17		0x3017
122 #define OV2722_SC_CMMN_MIPI_SC_CTRL_18		0x3018
123 #define OV2722_SC_CMMN_MIPI_SC_CTRL_19		0x3019
124 #define OV2722_SC_CMMN_MIPI_SC_CTRL_21		0x3021
125 #define OV2722_SC_CMMN_MIPI_SC_CTRL_22		0x3022
126 
127 #define OV2722_AEC_PK_EXPO_H			0x3500
128 #define OV2722_AEC_PK_EXPO_M			0x3501
129 #define OV2722_AEC_PK_EXPO_L			0x3502
130 #define OV2722_AEC_MANUAL_CTRL			0x3503
131 #define OV2722_AGC_ADJ_H			0x3508
132 #define OV2722_AGC_ADJ_L			0x3509
133 #define OV2722_VTS_DIFF_H			0x350c
134 #define OV2722_VTS_DIFF_L			0x350d
135 #define OV2722_GROUP_ACCESS			0x3208
136 #define OV2722_HTS_H				0x380c
137 #define OV2722_HTS_L				0x380d
138 #define OV2722_VTS_H				0x380e
139 #define OV2722_VTS_L				0x380f
140 
141 #define OV2722_MWB_GAIN_R_H			0x5186
142 #define OV2722_MWB_GAIN_R_L			0x5187
143 #define OV2722_MWB_GAIN_G_H			0x5188
144 #define OV2722_MWB_GAIN_G_L			0x5189
145 #define OV2722_MWB_GAIN_B_H			0x518a
146 #define OV2722_MWB_GAIN_B_L			0x518b
147 
148 #define OV2722_H_CROP_START_H			0x3800
149 #define OV2722_H_CROP_START_L			0x3801
150 #define OV2722_V_CROP_START_H			0x3802
151 #define OV2722_V_CROP_START_L			0x3803
152 #define OV2722_H_CROP_END_H			0x3804
153 #define OV2722_H_CROP_END_L			0x3805
154 #define OV2722_V_CROP_END_H			0x3806
155 #define OV2722_V_CROP_END_L			0x3807
156 #define OV2722_H_OUTSIZE_H			0x3808
157 #define OV2722_H_OUTSIZE_L			0x3809
158 #define OV2722_V_OUTSIZE_H			0x380a
159 #define OV2722_V_OUTSIZE_L			0x380b
160 
161 #define OV2722_START_STREAMING			0x01
162 #define OV2722_STOP_STREAMING			0x00
163 
164 struct regval_list {
165 	u16 reg_num;
166 	u8 value;
167 };
168 
169 struct ov2722_resolution {
170 	u8 *desc;
171 	const struct ov2722_reg *regs;
172 	int res;
173 	int width;
174 	int height;
175 	int fps;
176 	int pix_clk_freq;
177 	u32 skip_frames;
178 	u16 pixels_per_line;
179 	u16 lines_per_frame;
180 	bool used;
181 	int mipi_freq;
182 };
183 
184 struct ov2722_format {
185 	u8 *desc;
186 	u32 pixelformat;
187 	struct ov2722_reg *regs;
188 };
189 
190 /*
191  * ov2722 device structure.
192  */
193 struct ov2722_device {
194 	struct v4l2_subdev sd;
195 	struct media_pad pad;
196 	struct v4l2_mbus_framefmt format;
197 	struct mutex input_lock;
198 	struct ov2722_resolution *res;
199 
200 	struct camera_sensor_platform_data *platform_data;
201 	int power_on;
202 	u16 pixels_per_line;
203 	u16 lines_per_frame;
204 	u8 type;
205 
206 	struct v4l2_ctrl_handler ctrl_handler;
207 	struct v4l2_ctrl *link_freq;
208 };
209 
210 enum ov2722_tok_type {
211 	OV2722_8BIT  = 0x0001,
212 	OV2722_16BIT = 0x0002,
213 	OV2722_32BIT = 0x0004,
214 	OV2722_TOK_TERM   = 0xf000,	/* terminating token for reg list */
215 	OV2722_TOK_DELAY  = 0xfe00,	/* delay token for reg list */
216 	OV2722_TOK_MASK = 0xfff0
217 };
218 
219 /**
220  * struct ov2722_reg - MI sensor  register format
221  * @type: type of the register
222  * @reg: 16-bit offset to register
223  * @val: 8/16/32-bit register value
224  *
225  * Define a structure for sensor register initialization values
226  */
227 struct ov2722_reg {
228 	enum ov2722_tok_type type;
229 	u16 reg;
230 	u32 val;	/* @set value for read/mod/write, @mask */
231 };
232 
233 #define to_ov2722_sensor(x) container_of(x, struct ov2722_device, sd)
234 
235 #define OV2722_MAX_WRITE_BUF_SIZE	30
236 
237 struct ov2722_write_buffer {
238 	u16 addr;
239 	u8 data[OV2722_MAX_WRITE_BUF_SIZE];
240 };
241 
242 struct ov2722_write_ctrl {
243 	int index;
244 	struct ov2722_write_buffer buffer;
245 };
246 
247 /*
248  * Register settings for various resolution
249  */
250 #if 0
251 static struct ov2722_reg const ov2722_QVGA_30fps[] = {
252 	{OV2722_8BIT, 0x3718, 0x10},
253 	{OV2722_8BIT, 0x3702, 0x0c},
254 	{OV2722_8BIT, 0x373a, 0x1c},
255 	{OV2722_8BIT, 0x3715, 0x01},
256 	{OV2722_8BIT, 0x3703, 0x0c},
257 	{OV2722_8BIT, 0x3705, 0x06},
258 	{OV2722_8BIT, 0x3730, 0x0e},
259 	{OV2722_8BIT, 0x3704, 0x1c},
260 	{OV2722_8BIT, 0x3f06, 0x00},
261 	{OV2722_8BIT, 0x371c, 0x00},
262 	{OV2722_8BIT, 0x371d, 0x46},
263 	{OV2722_8BIT, 0x371e, 0x00},
264 	{OV2722_8BIT, 0x371f, 0x63},
265 	{OV2722_8BIT, 0x3708, 0x61},
266 	{OV2722_8BIT, 0x3709, 0x12},
267 	{OV2722_8BIT, 0x3800, 0x01},
268 	{OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */
269 	{OV2722_8BIT, 0x3802, 0x00},
270 	{OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32 */
271 	{OV2722_8BIT, 0x3804, 0x06},
272 	{OV2722_8BIT, 0x3805, 0x95}, /* H crop end:  1685 */
273 	{OV2722_8BIT, 0x3806, 0x04},
274 	{OV2722_8BIT, 0x3807, 0x27}, /* V crop end:  1063 */
275 	{OV2722_8BIT, 0x3808, 0x01},
276 	{OV2722_8BIT, 0x3809, 0x50}, /* H output size: 336 */
277 	{OV2722_8BIT, 0x380a, 0x01},
278 	{OV2722_8BIT, 0x380b, 0x00}, /* V output size: 256 */
279 
280 	/* H blank timing */
281 	{OV2722_8BIT, 0x380c, 0x08},
282 	{OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */
283 	{OV2722_8BIT, 0x380e, 0x04},
284 	{OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */
285 	{OV2722_8BIT, 0x3810, 0x00},
286 	{OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */
287 	{OV2722_8BIT, 0x3812, 0x00},
288 	{OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */
289 	{OV2722_8BIT, 0x3820, 0xc0},
290 	{OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/
291 	{OV2722_8BIT, 0x3814, 0x71},
292 	{OV2722_8BIT, 0x3815, 0x71},
293 	{OV2722_8BIT, 0x3612, 0x49},
294 	{OV2722_8BIT, 0x3618, 0x00},
295 	{OV2722_8BIT, 0x3a08, 0x01},
296 	{OV2722_8BIT, 0x3a09, 0xc3},
297 	{OV2722_8BIT, 0x3a0a, 0x01},
298 	{OV2722_8BIT, 0x3a0b, 0x77},
299 	{OV2722_8BIT, 0x3a0d, 0x00},
300 	{OV2722_8BIT, 0x3a0e, 0x00},
301 	{OV2722_8BIT, 0x4520, 0x09},
302 	{OV2722_8BIT, 0x4837, 0x1b},
303 	{OV2722_8BIT, 0x3000, 0xff},
304 	{OV2722_8BIT, 0x3001, 0xff},
305 	{OV2722_8BIT, 0x3002, 0xf0},
306 	{OV2722_8BIT, 0x3600, 0x08},
307 	{OV2722_8BIT, 0x3621, 0xc0},
308 	{OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */
309 	{OV2722_8BIT, 0x3633, 0x63},
310 	{OV2722_8BIT, 0x3634, 0x24},
311 	{OV2722_8BIT, 0x3f01, 0x0c},
312 	{OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */
313 	{OV2722_8BIT, 0x3614, 0xf0},
314 	{OV2722_8BIT, 0x3630, 0x2d},
315 	{OV2722_8BIT, 0x370b, 0x62},
316 	{OV2722_8BIT, 0x3706, 0x61},
317 	{OV2722_8BIT, 0x4000, 0x02},
318 	{OV2722_8BIT, 0x4002, 0xc5},
319 	{OV2722_8BIT, 0x4005, 0x08},
320 	{OV2722_8BIT, 0x404f, 0x84},
321 	{OV2722_8BIT, 0x4051, 0x00},
322 	{OV2722_8BIT, 0x5000, 0xff},
323 	{OV2722_8BIT, 0x3a18, 0x00},
324 	{OV2722_8BIT, 0x3a19, 0x80},
325 	{OV2722_8BIT, 0x4521, 0x00},
326 	{OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */
327 	{OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */
328 	{OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */
329 	{OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */
330 	{OV2722_8BIT, 0x370c, 0x0c},
331 	{OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */
332 	{OV2722_8BIT, 0x3035, 0x00},
333 	{OV2722_8BIT, 0x3036, 0x26},
334 	{OV2722_8BIT, 0x3037, 0xa1},
335 	{OV2722_8BIT, 0x303e, 0x19},
336 	{OV2722_8BIT, 0x3038, 0x06},
337 	{OV2722_8BIT, 0x3018, 0x04},
338 
339 	/* Added for power optimization */
340 	{OV2722_8BIT, 0x3000, 0x00},
341 	{OV2722_8BIT, 0x3001, 0x00},
342 	{OV2722_8BIT, 0x3002, 0x00},
343 	{OV2722_8BIT, 0x3a0f, 0x40},
344 	{OV2722_8BIT, 0x3a10, 0x38},
345 	{OV2722_8BIT, 0x3a1b, 0x48},
346 	{OV2722_8BIT, 0x3a1e, 0x30},
347 	{OV2722_8BIT, 0x3a11, 0x90},
348 	{OV2722_8BIT, 0x3a1f, 0x10},
349 	{OV2722_8BIT, 0x3011, 0x22},
350 	{OV2722_8BIT, 0x3a00, 0x58},
351 	{OV2722_8BIT, 0x3503, 0x17},
352 	{OV2722_8BIT, 0x3500, 0x00},
353 	{OV2722_8BIT, 0x3501, 0x46},
354 	{OV2722_8BIT, 0x3502, 0x00},
355 	{OV2722_8BIT, 0x3508, 0x00},
356 	{OV2722_8BIT, 0x3509, 0x10},
357 	{OV2722_TOK_TERM, 0, 0},
358 
359 };
360 
361 static struct ov2722_reg const ov2722_480P_30fps[] = {
362 	{OV2722_8BIT, 0x3718, 0x10},
363 	{OV2722_8BIT, 0x3702, 0x18},
364 	{OV2722_8BIT, 0x373a, 0x3c},
365 	{OV2722_8BIT, 0x3715, 0x01},
366 	{OV2722_8BIT, 0x3703, 0x1d},
367 	{OV2722_8BIT, 0x3705, 0x12},
368 	{OV2722_8BIT, 0x3730, 0x1f},
369 	{OV2722_8BIT, 0x3704, 0x3f},
370 	{OV2722_8BIT, 0x3f06, 0x1d},
371 	{OV2722_8BIT, 0x371c, 0x00},
372 	{OV2722_8BIT, 0x371d, 0x83},
373 	{OV2722_8BIT, 0x371e, 0x00},
374 	{OV2722_8BIT, 0x371f, 0xbd},
375 	{OV2722_8BIT, 0x3708, 0x63},
376 	{OV2722_8BIT, 0x3709, 0x52},
377 	{OV2722_8BIT, 0x3800, 0x00},
378 	{OV2722_8BIT, 0x3801, 0xf2}, /* H crop start: 322 - 80 = 242*/
379 	{OV2722_8BIT, 0x3802, 0x00},
380 	{OV2722_8BIT, 0x3803, 0x20}, /* V crop start:  32*/
381 	{OV2722_8BIT, 0x3804, 0x06},
382 	{OV2722_8BIT, 0x3805, 0xBB}, /* H crop end:   1643 + 80 = 1723*/
383 	{OV2722_8BIT, 0x3806, 0x04},
384 	{OV2722_8BIT, 0x3807, 0x03}, /* V crop end:   1027*/
385 	{OV2722_8BIT, 0x3808, 0x02},
386 	{OV2722_8BIT, 0x3809, 0xE0}, /* H output size: 656 +80 = 736*/
387 	{OV2722_8BIT, 0x380a, 0x01},
388 	{OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */
389 
390 	/* H blank timing */
391 	{OV2722_8BIT, 0x380c, 0x08},
392 	{OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */
393 	{OV2722_8BIT, 0x380e, 0x04},
394 	{OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */
395 	{OV2722_8BIT, 0x3810, 0x00},
396 	{OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */
397 	{OV2722_8BIT, 0x3812, 0x00},
398 	{OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */
399 	{OV2722_8BIT, 0x3820, 0x80},
400 	{OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/
401 	{OV2722_8BIT, 0x3814, 0x31},
402 	{OV2722_8BIT, 0x3815, 0x31},
403 	{OV2722_8BIT, 0x3612, 0x4b},
404 	{OV2722_8BIT, 0x3618, 0x04},
405 	{OV2722_8BIT, 0x3a08, 0x02},
406 	{OV2722_8BIT, 0x3a09, 0x67},
407 	{OV2722_8BIT, 0x3a0a, 0x02},
408 	{OV2722_8BIT, 0x3a0b, 0x00},
409 	{OV2722_8BIT, 0x3a0d, 0x00},
410 	{OV2722_8BIT, 0x3a0e, 0x00},
411 	{OV2722_8BIT, 0x4520, 0x0a},
412 	{OV2722_8BIT, 0x4837, 0x1b},
413 	{OV2722_8BIT, 0x3000, 0xff},
414 	{OV2722_8BIT, 0x3001, 0xff},
415 	{OV2722_8BIT, 0x3002, 0xf0},
416 	{OV2722_8BIT, 0x3600, 0x08},
417 	{OV2722_8BIT, 0x3621, 0xc0},
418 	{OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */
419 	{OV2722_8BIT, 0x3633, 0x63},
420 	{OV2722_8BIT, 0x3634, 0x24},
421 	{OV2722_8BIT, 0x3f01, 0x0c},
422 	{OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */
423 	{OV2722_8BIT, 0x3614, 0xf0},
424 	{OV2722_8BIT, 0x3630, 0x2d},
425 	{OV2722_8BIT, 0x370b, 0x62},
426 	{OV2722_8BIT, 0x3706, 0x61},
427 	{OV2722_8BIT, 0x4000, 0x02},
428 	{OV2722_8BIT, 0x4002, 0xc5},
429 	{OV2722_8BIT, 0x4005, 0x08},
430 	{OV2722_8BIT, 0x404f, 0x84},
431 	{OV2722_8BIT, 0x4051, 0x00},
432 	{OV2722_8BIT, 0x5000, 0xff},
433 	{OV2722_8BIT, 0x3a18, 0x00},
434 	{OV2722_8BIT, 0x3a19, 0x80},
435 	{OV2722_8BIT, 0x4521, 0x00},
436 	{OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */
437 	{OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */
438 	{OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */
439 	{OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */
440 	{OV2722_8BIT, 0x370c, 0x0c},
441 	{OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */
442 	{OV2722_8BIT, 0x3035, 0x00},
443 	{OV2722_8BIT, 0x3036, 0x26},
444 	{OV2722_8BIT, 0x3037, 0xa1},
445 	{OV2722_8BIT, 0x303e, 0x19},
446 	{OV2722_8BIT, 0x3038, 0x06},
447 	{OV2722_8BIT, 0x3018, 0x04},
448 
449 	/* Added for power optimization */
450 	{OV2722_8BIT, 0x3000, 0x00},
451 	{OV2722_8BIT, 0x3001, 0x00},
452 	{OV2722_8BIT, 0x3002, 0x00},
453 	{OV2722_8BIT, 0x3a0f, 0x40},
454 	{OV2722_8BIT, 0x3a10, 0x38},
455 	{OV2722_8BIT, 0x3a1b, 0x48},
456 	{OV2722_8BIT, 0x3a1e, 0x30},
457 	{OV2722_8BIT, 0x3a11, 0x90},
458 	{OV2722_8BIT, 0x3a1f, 0x10},
459 	{OV2722_8BIT, 0x3011, 0x22},
460 	{OV2722_8BIT, 0x3a00, 0x58},
461 	{OV2722_8BIT, 0x3503, 0x17},
462 	{OV2722_8BIT, 0x3500, 0x00},
463 	{OV2722_8BIT, 0x3501, 0x46},
464 	{OV2722_8BIT, 0x3502, 0x00},
465 	{OV2722_8BIT, 0x3508, 0x00},
466 	{OV2722_8BIT, 0x3509, 0x10},
467 	{OV2722_TOK_TERM, 0, 0},
468 };
469 
470 static struct ov2722_reg const ov2722_VGA_30fps[] = {
471 	{OV2722_8BIT, 0x3718, 0x10},
472 	{OV2722_8BIT, 0x3702, 0x18},
473 	{OV2722_8BIT, 0x373a, 0x3c},
474 	{OV2722_8BIT, 0x3715, 0x01},
475 	{OV2722_8BIT, 0x3703, 0x1d},
476 	{OV2722_8BIT, 0x3705, 0x12},
477 	{OV2722_8BIT, 0x3730, 0x1f},
478 	{OV2722_8BIT, 0x3704, 0x3f},
479 	{OV2722_8BIT, 0x3f06, 0x1d},
480 	{OV2722_8BIT, 0x371c, 0x00},
481 	{OV2722_8BIT, 0x371d, 0x83},
482 	{OV2722_8BIT, 0x371e, 0x00},
483 	{OV2722_8BIT, 0x371f, 0xbd},
484 	{OV2722_8BIT, 0x3708, 0x63},
485 	{OV2722_8BIT, 0x3709, 0x52},
486 	{OV2722_8BIT, 0x3800, 0x01},
487 	{OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */
488 	{OV2722_8BIT, 0x3802, 0x00},
489 	{OV2722_8BIT, 0x3803, 0x20}, /* V crop start:  32*/
490 	{OV2722_8BIT, 0x3804, 0x06},
491 	{OV2722_8BIT, 0x3805, 0x6B}, /* H crop end:   1643*/
492 	{OV2722_8BIT, 0x3806, 0x04},
493 	{OV2722_8BIT, 0x3807, 0x03}, /* V crop end:   1027*/
494 	{OV2722_8BIT, 0x3808, 0x02},
495 	{OV2722_8BIT, 0x3809, 0x90}, /* H output size: 656 */
496 	{OV2722_8BIT, 0x380a, 0x01},
497 	{OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */
498 
499 	/* H blank timing */
500 	{OV2722_8BIT, 0x380c, 0x08},
501 	{OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */
502 	{OV2722_8BIT, 0x380e, 0x04},
503 	{OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */
504 	{OV2722_8BIT, 0x3810, 0x00},
505 	{OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */
506 	{OV2722_8BIT, 0x3812, 0x00},
507 	{OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */
508 	{OV2722_8BIT, 0x3820, 0x80},
509 	{OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/
510 	{OV2722_8BIT, 0x3814, 0x31},
511 	{OV2722_8BIT, 0x3815, 0x31},
512 	{OV2722_8BIT, 0x3612, 0x4b},
513 	{OV2722_8BIT, 0x3618, 0x04},
514 	{OV2722_8BIT, 0x3a08, 0x02},
515 	{OV2722_8BIT, 0x3a09, 0x67},
516 	{OV2722_8BIT, 0x3a0a, 0x02},
517 	{OV2722_8BIT, 0x3a0b, 0x00},
518 	{OV2722_8BIT, 0x3a0d, 0x00},
519 	{OV2722_8BIT, 0x3a0e, 0x00},
520 	{OV2722_8BIT, 0x4520, 0x0a},
521 	{OV2722_8BIT, 0x4837, 0x29},
522 	{OV2722_8BIT, 0x3000, 0xff},
523 	{OV2722_8BIT, 0x3001, 0xff},
524 	{OV2722_8BIT, 0x3002, 0xf0},
525 	{OV2722_8BIT, 0x3600, 0x08},
526 	{OV2722_8BIT, 0x3621, 0xc0},
527 	{OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */
528 	{OV2722_8BIT, 0x3633, 0x63},
529 	{OV2722_8BIT, 0x3634, 0x24},
530 	{OV2722_8BIT, 0x3f01, 0x0c},
531 	{OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */
532 	{OV2722_8BIT, 0x3614, 0xf0},
533 	{OV2722_8BIT, 0x3630, 0x2d},
534 	{OV2722_8BIT, 0x370b, 0x62},
535 	{OV2722_8BIT, 0x3706, 0x61},
536 	{OV2722_8BIT, 0x4000, 0x02},
537 	{OV2722_8BIT, 0x4002, 0xc5},
538 	{OV2722_8BIT, 0x4005, 0x08},
539 	{OV2722_8BIT, 0x404f, 0x84},
540 	{OV2722_8BIT, 0x4051, 0x00},
541 	{OV2722_8BIT, 0x5000, 0xff},
542 	{OV2722_8BIT, 0x3a18, 0x00},
543 	{OV2722_8BIT, 0x3a19, 0x80},
544 	{OV2722_8BIT, 0x4521, 0x00},
545 	{OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */
546 	{OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */
547 	{OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */
548 	{OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */
549 	{OV2722_8BIT, 0x370c, 0x0c},
550 	{OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */
551 	{OV2722_8BIT, 0x3035, 0x00},
552 	{OV2722_8BIT, 0x3036, 0x26},
553 	{OV2722_8BIT, 0x3037, 0xa1},
554 	{OV2722_8BIT, 0x303e, 0x19},
555 	{OV2722_8BIT, 0x3038, 0x06},
556 	{OV2722_8BIT, 0x3018, 0x04},
557 
558 	/* Added for power optimization */
559 	{OV2722_8BIT, 0x3000, 0x00},
560 	{OV2722_8BIT, 0x3001, 0x00},
561 	{OV2722_8BIT, 0x3002, 0x00},
562 	{OV2722_8BIT, 0x3a0f, 0x40},
563 	{OV2722_8BIT, 0x3a10, 0x38},
564 	{OV2722_8BIT, 0x3a1b, 0x48},
565 	{OV2722_8BIT, 0x3a1e, 0x30},
566 	{OV2722_8BIT, 0x3a11, 0x90},
567 	{OV2722_8BIT, 0x3a1f, 0x10},
568 	{OV2722_8BIT, 0x3011, 0x22},
569 	{OV2722_8BIT, 0x3a00, 0x58},
570 	{OV2722_8BIT, 0x3503, 0x17},
571 	{OV2722_8BIT, 0x3500, 0x00},
572 	{OV2722_8BIT, 0x3501, 0x46},
573 	{OV2722_8BIT, 0x3502, 0x00},
574 	{OV2722_8BIT, 0x3508, 0x00},
575 	{OV2722_8BIT, 0x3509, 0x10},
576 	{OV2722_TOK_TERM, 0, 0},
577 };
578 #endif
579 
580 static struct ov2722_reg const ov2722_1632_1092_30fps[] = {
581 	{OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for
582 				a whole frame complete.(vblank) */
583 	{OV2722_8BIT, 0x3718, 0x10},
584 	{OV2722_8BIT, 0x3702, 0x24},
585 	{OV2722_8BIT, 0x373a, 0x60},
586 	{OV2722_8BIT, 0x3715, 0x01},
587 	{OV2722_8BIT, 0x3703, 0x2e},
588 	{OV2722_8BIT, 0x3705, 0x10},
589 	{OV2722_8BIT, 0x3730, 0x30},
590 	{OV2722_8BIT, 0x3704, 0x62},
591 	{OV2722_8BIT, 0x3f06, 0x3a},
592 	{OV2722_8BIT, 0x371c, 0x00},
593 	{OV2722_8BIT, 0x371d, 0xc4},
594 	{OV2722_8BIT, 0x371e, 0x01},
595 	{OV2722_8BIT, 0x371f, 0x0d},
596 	{OV2722_8BIT, 0x3708, 0x61},
597 	{OV2722_8BIT, 0x3709, 0x12},
598 	{OV2722_8BIT, 0x3800, 0x00},
599 	{OV2722_8BIT, 0x3801, 0x9E}, /* H crop start: 158 */
600 	{OV2722_8BIT, 0x3802, 0x00},
601 	{OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */
602 	{OV2722_8BIT, 0x3804, 0x07},
603 	{OV2722_8BIT, 0x3805, 0x05}, /* H crop end: 1797 */
604 	{OV2722_8BIT, 0x3806, 0x04},
605 	{OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */
606 
607 	{OV2722_8BIT, 0x3808, 0x06},
608 	{OV2722_8BIT, 0x3809, 0x60}, /* H output size: 1632 */
609 	{OV2722_8BIT, 0x380a, 0x04},
610 	{OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */
611 	{OV2722_8BIT, 0x380c, 0x08},
612 	{OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */
613 	{OV2722_8BIT, 0x380e, 0x04},
614 	{OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */
615 	{OV2722_8BIT, 0x3810, 0x00},
616 	{OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */
617 	{OV2722_8BIT, 0x3812, 0x00},
618 	{OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */
619 	{OV2722_8BIT, 0x3820, 0x80},
620 	{OV2722_8BIT, 0x3821, 0x06}, /*  mirror */
621 	{OV2722_8BIT, 0x3814, 0x11},
622 	{OV2722_8BIT, 0x3815, 0x11},
623 	{OV2722_8BIT, 0x3612, 0x0b},
624 	{OV2722_8BIT, 0x3618, 0x04},
625 	{OV2722_8BIT, 0x3a08, 0x01},
626 	{OV2722_8BIT, 0x3a09, 0x50},
627 	{OV2722_8BIT, 0x3a0a, 0x01},
628 	{OV2722_8BIT, 0x3a0b, 0x18},
629 	{OV2722_8BIT, 0x3a0d, 0x03},
630 	{OV2722_8BIT, 0x3a0e, 0x03},
631 	{OV2722_8BIT, 0x4520, 0x00},
632 	{OV2722_8BIT, 0x4837, 0x1b},
633 	{OV2722_8BIT, 0x3600, 0x08},
634 	{OV2722_8BIT, 0x3621, 0xc0},
635 	{OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */
636 	{OV2722_8BIT, 0x3633, 0x23},
637 	{OV2722_8BIT, 0x3634, 0x54},
638 	{OV2722_8BIT, 0x3f01, 0x0c},
639 	{OV2722_8BIT, 0x5001, 0xc1},
640 	{OV2722_8BIT, 0x3614, 0xf0},
641 	{OV2722_8BIT, 0x3630, 0x2d},
642 	{OV2722_8BIT, 0x370b, 0x62},
643 	{OV2722_8BIT, 0x3706, 0x61},
644 	{OV2722_8BIT, 0x4000, 0x02},
645 	{OV2722_8BIT, 0x4002, 0xc5},
646 	{OV2722_8BIT, 0x4005, 0x08},
647 	{OV2722_8BIT, 0x404f, 0x84},
648 	{OV2722_8BIT, 0x4051, 0x00},
649 	{OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */
650 	{OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */
651 	{OV2722_8BIT, 0x3a18, 0x00},
652 	{OV2722_8BIT, 0x3a19, 0x80},
653 	{OV2722_8BIT, 0x4521, 0x00},
654 	{OV2722_8BIT, 0x5183, 0xb0},
655 	{OV2722_8BIT, 0x5184, 0xb0},
656 	{OV2722_8BIT, 0x5185, 0xb0},
657 	{OV2722_8BIT, 0x370c, 0x0c},
658 	{OV2722_8BIT, 0x3035, 0x00},
659 	{OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */
660 	{OV2722_8BIT, 0x3037, 0xa1},
661 	{OV2722_8BIT, 0x303e, 0x19},
662 	{OV2722_8BIT, 0x3038, 0x06},
663 	{OV2722_8BIT, 0x3018, 0x04},
664 	{OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */
665 	{OV2722_8BIT, 0x3001, 0x00},
666 	{OV2722_8BIT, 0x3002, 0x00},
667 	{OV2722_8BIT, 0x3a0f, 0x40},
668 	{OV2722_8BIT, 0x3a10, 0x38},
669 	{OV2722_8BIT, 0x3a1b, 0x48},
670 	{OV2722_8BIT, 0x3a1e, 0x30},
671 	{OV2722_8BIT, 0x3a11, 0x90},
672 	{OV2722_8BIT, 0x3a1f, 0x10},
673 	{OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */
674 	{OV2722_8BIT, 0x3500, 0x00},
675 	{OV2722_8BIT, 0x3501, 0x3F},
676 	{OV2722_8BIT, 0x3502, 0x00},
677 	{OV2722_8BIT, 0x3508, 0x00},
678 	{OV2722_8BIT, 0x3509, 0x00},
679 	{OV2722_TOK_TERM, 0, 0}
680 };
681 
682 static struct ov2722_reg const ov2722_1452_1092_30fps[] = {
683 	{OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for
684 				a whole frame complete.(vblank) */
685 	{OV2722_8BIT, 0x3718, 0x10},
686 	{OV2722_8BIT, 0x3702, 0x24},
687 	{OV2722_8BIT, 0x373a, 0x60},
688 	{OV2722_8BIT, 0x3715, 0x01},
689 	{OV2722_8BIT, 0x3703, 0x2e},
690 	{OV2722_8BIT, 0x3705, 0x10},
691 	{OV2722_8BIT, 0x3730, 0x30},
692 	{OV2722_8BIT, 0x3704, 0x62},
693 	{OV2722_8BIT, 0x3f06, 0x3a},
694 	{OV2722_8BIT, 0x371c, 0x00},
695 	{OV2722_8BIT, 0x371d, 0xc4},
696 	{OV2722_8BIT, 0x371e, 0x01},
697 	{OV2722_8BIT, 0x371f, 0x0d},
698 	{OV2722_8BIT, 0x3708, 0x61},
699 	{OV2722_8BIT, 0x3709, 0x12},
700 	{OV2722_8BIT, 0x3800, 0x00},
701 	{OV2722_8BIT, 0x3801, 0xF8}, /* H crop start: 248 */
702 	{OV2722_8BIT, 0x3802, 0x00},
703 	{OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */
704 	{OV2722_8BIT, 0x3804, 0x06},
705 	{OV2722_8BIT, 0x3805, 0xab}, /* H crop end: 1707 */
706 	{OV2722_8BIT, 0x3806, 0x04},
707 	{OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */
708 	{OV2722_8BIT, 0x3808, 0x05},
709 	{OV2722_8BIT, 0x3809, 0xac}, /* H output size: 1452 */
710 	{OV2722_8BIT, 0x380a, 0x04},
711 	{OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */
712 	{OV2722_8BIT, 0x380c, 0x08},
713 	{OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */
714 	{OV2722_8BIT, 0x380e, 0x04},
715 	{OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */
716 	{OV2722_8BIT, 0x3810, 0x00},
717 	{OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */
718 	{OV2722_8BIT, 0x3812, 0x00},
719 	{OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */
720 	{OV2722_8BIT, 0x3820, 0x80},
721 	{OV2722_8BIT, 0x3821, 0x06}, /*  mirror */
722 	{OV2722_8BIT, 0x3814, 0x11},
723 	{OV2722_8BIT, 0x3815, 0x11},
724 	{OV2722_8BIT, 0x3612, 0x0b},
725 	{OV2722_8BIT, 0x3618, 0x04},
726 	{OV2722_8BIT, 0x3a08, 0x01},
727 	{OV2722_8BIT, 0x3a09, 0x50},
728 	{OV2722_8BIT, 0x3a0a, 0x01},
729 	{OV2722_8BIT, 0x3a0b, 0x18},
730 	{OV2722_8BIT, 0x3a0d, 0x03},
731 	{OV2722_8BIT, 0x3a0e, 0x03},
732 	{OV2722_8BIT, 0x4520, 0x00},
733 	{OV2722_8BIT, 0x4837, 0x1b},
734 	{OV2722_8BIT, 0x3600, 0x08},
735 	{OV2722_8BIT, 0x3621, 0xc0},
736 	{OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */
737 	{OV2722_8BIT, 0x3633, 0x23},
738 	{OV2722_8BIT, 0x3634, 0x54},
739 	{OV2722_8BIT, 0x3f01, 0x0c},
740 	{OV2722_8BIT, 0x5001, 0xc1},
741 	{OV2722_8BIT, 0x3614, 0xf0},
742 	{OV2722_8BIT, 0x3630, 0x2d},
743 	{OV2722_8BIT, 0x370b, 0x62},
744 	{OV2722_8BIT, 0x3706, 0x61},
745 	{OV2722_8BIT, 0x4000, 0x02},
746 	{OV2722_8BIT, 0x4002, 0xc5},
747 	{OV2722_8BIT, 0x4005, 0x08},
748 	{OV2722_8BIT, 0x404f, 0x84},
749 	{OV2722_8BIT, 0x4051, 0x00},
750 	{OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */
751 	{OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */
752 	{OV2722_8BIT, 0x3a18, 0x00},
753 	{OV2722_8BIT, 0x3a19, 0x80},
754 	{OV2722_8BIT, 0x4521, 0x00},
755 	{OV2722_8BIT, 0x5183, 0xb0},
756 	{OV2722_8BIT, 0x5184, 0xb0},
757 	{OV2722_8BIT, 0x5185, 0xb0},
758 	{OV2722_8BIT, 0x370c, 0x0c},
759 	{OV2722_8BIT, 0x3035, 0x00},
760 	{OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */
761 	{OV2722_8BIT, 0x3037, 0xa1},
762 	{OV2722_8BIT, 0x303e, 0x19},
763 	{OV2722_8BIT, 0x3038, 0x06},
764 	{OV2722_8BIT, 0x3018, 0x04},
765 	{OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */
766 	{OV2722_8BIT, 0x3001, 0x00},
767 	{OV2722_8BIT, 0x3002, 0x00},
768 	{OV2722_8BIT, 0x3a0f, 0x40},
769 	{OV2722_8BIT, 0x3a10, 0x38},
770 	{OV2722_8BIT, 0x3a1b, 0x48},
771 	{OV2722_8BIT, 0x3a1e, 0x30},
772 	{OV2722_8BIT, 0x3a11, 0x90},
773 	{OV2722_8BIT, 0x3a1f, 0x10},
774 	{OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */
775 	{OV2722_8BIT, 0x3500, 0x00},
776 	{OV2722_8BIT, 0x3501, 0x3F},
777 	{OV2722_8BIT, 0x3502, 0x00},
778 	{OV2722_8BIT, 0x3508, 0x00},
779 	{OV2722_8BIT, 0x3509, 0x00},
780 	{OV2722_TOK_TERM, 0, 0}
781 };
782 
783 #if 0
784 static struct ov2722_reg const ov2722_1M3_30fps[] = {
785 	{OV2722_8BIT, 0x3718, 0x10},
786 	{OV2722_8BIT, 0x3702, 0x24},
787 	{OV2722_8BIT, 0x373a, 0x60},
788 	{OV2722_8BIT, 0x3715, 0x01},
789 	{OV2722_8BIT, 0x3703, 0x2e},
790 	{OV2722_8BIT, 0x3705, 0x10},
791 	{OV2722_8BIT, 0x3730, 0x30},
792 	{OV2722_8BIT, 0x3704, 0x62},
793 	{OV2722_8BIT, 0x3f06, 0x3a},
794 	{OV2722_8BIT, 0x371c, 0x00},
795 	{OV2722_8BIT, 0x371d, 0xc4},
796 	{OV2722_8BIT, 0x371e, 0x01},
797 	{OV2722_8BIT, 0x371f, 0x0d},
798 	{OV2722_8BIT, 0x3708, 0x61},
799 	{OV2722_8BIT, 0x3709, 0x12},
800 	{OV2722_8BIT, 0x3800, 0x01},
801 	{OV2722_8BIT, 0x3801, 0x4a},	/* H crop start: 330 */
802 	{OV2722_8BIT, 0x3802, 0x00},
803 	{OV2722_8BIT, 0x3803, 0x03},	/* V crop start: 3 */
804 	{OV2722_8BIT, 0x3804, 0x06},
805 	{OV2722_8BIT, 0x3805, 0xe1},	/* H crop end:  1761 */
806 	{OV2722_8BIT, 0x3806, 0x04},
807 	{OV2722_8BIT, 0x3807, 0x47},	/* V crop end:  1095 */
808 	{OV2722_8BIT, 0x3808, 0x05},
809 	{OV2722_8BIT, 0x3809, 0x88},	/* H output size: 1416 */
810 	{OV2722_8BIT, 0x380a, 0x04},
811 	{OV2722_8BIT, 0x380b, 0x0a},	/* V output size: 1034 */
812 
813 	/* H blank timing */
814 	{OV2722_8BIT, 0x380c, 0x08},
815 	{OV2722_8BIT, 0x380d, 0x00},	/* H total size: 2048 */
816 	{OV2722_8BIT, 0x380e, 0x04},
817 	{OV2722_8BIT, 0x380f, 0xa0},	/* V total size: 1184 */
818 	{OV2722_8BIT, 0x3810, 0x00},
819 	{OV2722_8BIT, 0x3811, 0x05},	/* H window offset: 5 */
820 	{OV2722_8BIT, 0x3812, 0x00},
821 	{OV2722_8BIT, 0x3813, 0x02},	/* V window offset: 2 */
822 	{OV2722_8BIT, 0x3820, 0x80},
823 	{OV2722_8BIT, 0x3821, 0x06},	/* flip isp */
824 	{OV2722_8BIT, 0x3814, 0x11},
825 	{OV2722_8BIT, 0x3815, 0x11},
826 	{OV2722_8BIT, 0x3612, 0x0b},
827 	{OV2722_8BIT, 0x3618, 0x04},
828 	{OV2722_8BIT, 0x3a08, 0x01},
829 	{OV2722_8BIT, 0x3a09, 0x50},
830 	{OV2722_8BIT, 0x3a0a, 0x01},
831 	{OV2722_8BIT, 0x3a0b, 0x18},
832 	{OV2722_8BIT, 0x3a0d, 0x03},
833 	{OV2722_8BIT, 0x3a0e, 0x03},
834 	{OV2722_8BIT, 0x4520, 0x00},
835 	{OV2722_8BIT, 0x4837, 0x1b},
836 	{OV2722_8BIT, 0x3000, 0xff},
837 	{OV2722_8BIT, 0x3001, 0xff},
838 	{OV2722_8BIT, 0x3002, 0xf0},
839 	{OV2722_8BIT, 0x3600, 0x08},
840 	{OV2722_8BIT, 0x3621, 0xc0},
841 	{OV2722_8BIT, 0x3632, 0xd2},	/* added for power opt */
842 	{OV2722_8BIT, 0x3633, 0x23},
843 	{OV2722_8BIT, 0x3634, 0x54},
844 	{OV2722_8BIT, 0x3f01, 0x0c},
845 	{OV2722_8BIT, 0x5001, 0xc1},	/* v_en, h_en, blc_en */
846 	{OV2722_8BIT, 0x3614, 0xf0},
847 	{OV2722_8BIT, 0x3630, 0x2d},
848 	{OV2722_8BIT, 0x370b, 0x62},
849 	{OV2722_8BIT, 0x3706, 0x61},
850 	{OV2722_8BIT, 0x4000, 0x02},
851 	{OV2722_8BIT, 0x4002, 0xc5},
852 	{OV2722_8BIT, 0x4005, 0x08},
853 	{OV2722_8BIT, 0x404f, 0x84},
854 	{OV2722_8BIT, 0x4051, 0x00},
855 	{OV2722_8BIT, 0x5000, 0xcf},
856 	{OV2722_8BIT, 0x3a18, 0x00},
857 	{OV2722_8BIT, 0x3a19, 0x80},
858 	{OV2722_8BIT, 0x4521, 0x00},
859 	{OV2722_8BIT, 0x5183, 0xb0},	/* AWB red */
860 	{OV2722_8BIT, 0x5184, 0xb0},	/* AWB green */
861 	{OV2722_8BIT, 0x5185, 0xb0},	/* AWB blue */
862 	{OV2722_8BIT, 0x5180, 0x03},	/* AWB manual mode */
863 	{OV2722_8BIT, 0x370c, 0x0c},
864 	{OV2722_8BIT, 0x4800, 0x24},	/* clk lane gate enable */
865 	{OV2722_8BIT, 0x3035, 0x00},
866 	{OV2722_8BIT, 0x3036, 0x26},
867 	{OV2722_8BIT, 0x3037, 0xa1},
868 	{OV2722_8BIT, 0x303e, 0x19},
869 	{OV2722_8BIT, 0x3038, 0x06},
870 	{OV2722_8BIT, 0x3018, 0x04},
871 
872 	/* Added for power optimization */
873 	{OV2722_8BIT, 0x3000, 0x00},
874 	{OV2722_8BIT, 0x3001, 0x00},
875 	{OV2722_8BIT, 0x3002, 0x00},
876 	{OV2722_8BIT, 0x3a0f, 0x40},
877 	{OV2722_8BIT, 0x3a10, 0x38},
878 	{OV2722_8BIT, 0x3a1b, 0x48},
879 	{OV2722_8BIT, 0x3a1e, 0x30},
880 	{OV2722_8BIT, 0x3a11, 0x90},
881 	{OV2722_8BIT, 0x3a1f, 0x10},
882 	{OV2722_8BIT, 0x3503, 0x17},
883 	{OV2722_8BIT, 0x3500, 0x00},
884 	{OV2722_8BIT, 0x3501, 0x46},
885 	{OV2722_8BIT, 0x3502, 0x00},
886 	{OV2722_8BIT, 0x3508, 0x00},
887 	{OV2722_8BIT, 0x3509, 0x10},
888 	{OV2722_TOK_TERM, 0, 0},
889 };
890 #endif
891 
892 static struct ov2722_reg const ov2722_1080p_30fps[] = {
893 	{OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for a whole
894 					frame complete.(vblank) */
895 	{OV2722_8BIT, 0x3718, 0x10},
896 	{OV2722_8BIT, 0x3702, 0x24},
897 	{OV2722_8BIT, 0x373a, 0x60},
898 	{OV2722_8BIT, 0x3715, 0x01},
899 	{OV2722_8BIT, 0x3703, 0x2e},
900 	{OV2722_8BIT, 0x3705, 0x2b},
901 	{OV2722_8BIT, 0x3730, 0x30},
902 	{OV2722_8BIT, 0x3704, 0x62},
903 	{OV2722_8BIT, 0x3f06, 0x3a},
904 	{OV2722_8BIT, 0x371c, 0x00},
905 	{OV2722_8BIT, 0x371d, 0xc4},
906 	{OV2722_8BIT, 0x371e, 0x01},
907 	{OV2722_8BIT, 0x371f, 0x28},
908 	{OV2722_8BIT, 0x3708, 0x61},
909 	{OV2722_8BIT, 0x3709, 0x12},
910 	{OV2722_8BIT, 0x3800, 0x00},
911 	{OV2722_8BIT, 0x3801, 0x08}, /* H crop start: 8 */
912 	{OV2722_8BIT, 0x3802, 0x00},
913 	{OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */
914 	{OV2722_8BIT, 0x3804, 0x07},
915 	{OV2722_8BIT, 0x3805, 0x9b}, /* H crop end: 1947 */
916 	{OV2722_8BIT, 0x3806, 0x04},
917 	{OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */
918 	{OV2722_8BIT, 0x3808, 0x07},
919 	{OV2722_8BIT, 0x3809, 0x8c}, /* H output size: 1932 */
920 	{OV2722_8BIT, 0x380a, 0x04},
921 	{OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */
922 	{OV2722_8BIT, 0x380c, 0x08},
923 	{OV2722_8BIT, 0x380d, 0x14}, /* H timing: 2068 */
924 	{OV2722_8BIT, 0x380e, 0x04},
925 	{OV2722_8BIT, 0x380f, 0x5a}, /* V timing: 1114 */
926 	{OV2722_8BIT, 0x3810, 0x00},
927 	{OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */
928 	{OV2722_8BIT, 0x3812, 0x00},
929 	{OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */
930 	{OV2722_8BIT, 0x3820, 0x80},
931 	{OV2722_8BIT, 0x3821, 0x06}, /*  mirror */
932 	{OV2722_8BIT, 0x3814, 0x11},
933 	{OV2722_8BIT, 0x3815, 0x11},
934 	{OV2722_8BIT, 0x3612, 0x4b},
935 	{OV2722_8BIT, 0x3618, 0x04},
936 	{OV2722_8BIT, 0x3a08, 0x01},
937 	{OV2722_8BIT, 0x3a09, 0x50},
938 	{OV2722_8BIT, 0x3a0a, 0x01},
939 	{OV2722_8BIT, 0x3a0b, 0x18},
940 	{OV2722_8BIT, 0x3a0d, 0x03},
941 	{OV2722_8BIT, 0x3a0e, 0x03},
942 	{OV2722_8BIT, 0x4520, 0x00},
943 	{OV2722_8BIT, 0x4837, 0x1b},
944 	{OV2722_8BIT, 0x3000, 0xff},
945 	{OV2722_8BIT, 0x3001, 0xff},
946 	{OV2722_8BIT, 0x3002, 0xf0},
947 	{OV2722_8BIT, 0x3600, 0x08},
948 	{OV2722_8BIT, 0x3621, 0xc0},
949 	{OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */
950 	{OV2722_8BIT, 0x3633, 0x63},
951 	{OV2722_8BIT, 0x3634, 0x24},
952 	{OV2722_8BIT, 0x3f01, 0x0c},
953 	{OV2722_8BIT, 0x5001, 0xc1},
954 	{OV2722_8BIT, 0x3614, 0xf0},
955 	{OV2722_8BIT, 0x3630, 0x2d},
956 	{OV2722_8BIT, 0x370b, 0x62},
957 	{OV2722_8BIT, 0x3706, 0x61},
958 	{OV2722_8BIT, 0x4000, 0x02},
959 	{OV2722_8BIT, 0x4002, 0xc5},
960 	{OV2722_8BIT, 0x4005, 0x08},
961 	{OV2722_8BIT, 0x404f, 0x84},
962 	{OV2722_8BIT, 0x4051, 0x00},
963 	{OV2722_8BIT, 0x5000, 0xcd}, /* manual 3a */
964 	{OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */
965 	{OV2722_8BIT, 0x3a18, 0x00},
966 	{OV2722_8BIT, 0x3a19, 0x80},
967 	{OV2722_8BIT, 0x3503, 0x17},
968 	{OV2722_8BIT, 0x4521, 0x00},
969 	{OV2722_8BIT, 0x5183, 0xb0},
970 	{OV2722_8BIT, 0x5184, 0xb0},
971 	{OV2722_8BIT, 0x5185, 0xb0},
972 	{OV2722_8BIT, 0x370c, 0x0c},
973 	{OV2722_8BIT, 0x3035, 0x00},
974 	{OV2722_8BIT, 0x3036, 0x24}, /* 345.6 MHz */
975 	{OV2722_8BIT, 0x3037, 0xa1},
976 	{OV2722_8BIT, 0x303e, 0x19},
977 	{OV2722_8BIT, 0x3038, 0x06},
978 	{OV2722_8BIT, 0x3018, 0x04},
979 	{OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */
980 	{OV2722_8BIT, 0x3001, 0x00},
981 	{OV2722_8BIT, 0x3002, 0x00},
982 	{OV2722_8BIT, 0x3a0f, 0x40},
983 	{OV2722_8BIT, 0x3a10, 0x38},
984 	{OV2722_8BIT, 0x3a1b, 0x48},
985 	{OV2722_8BIT, 0x3a1e, 0x30},
986 	{OV2722_8BIT, 0x3a11, 0x90},
987 	{OV2722_8BIT, 0x3a1f, 0x10},
988 	{OV2722_8BIT, 0x3011, 0x22},
989 	{OV2722_8BIT, 0x3500, 0x00},
990 	{OV2722_8BIT, 0x3501, 0x3F},
991 	{OV2722_8BIT, 0x3502, 0x00},
992 	{OV2722_8BIT, 0x3508, 0x00},
993 	{OV2722_8BIT, 0x3509, 0x00},
994 	{OV2722_TOK_TERM, 0, 0}
995 };
996 
997 #if 0 /* Currently unused */
998 static struct ov2722_reg const ov2722_720p_30fps[] = {
999 	{OV2722_8BIT, 0x3021, 0x03},
1000 	{OV2722_8BIT, 0x3718, 0x10},
1001 	{OV2722_8BIT, 0x3702, 0x24},
1002 	{OV2722_8BIT, 0x373a, 0x60},
1003 	{OV2722_8BIT, 0x3715, 0x01},
1004 	{OV2722_8BIT, 0x3703, 0x2e},
1005 	{OV2722_8BIT, 0x3705, 0x10},
1006 	{OV2722_8BIT, 0x3730, 0x30},
1007 	{OV2722_8BIT, 0x3704, 0x62},
1008 	{OV2722_8BIT, 0x3f06, 0x3a},
1009 	{OV2722_8BIT, 0x371c, 0x00},
1010 	{OV2722_8BIT, 0x371d, 0xc4},
1011 	{OV2722_8BIT, 0x371e, 0x01},
1012 	{OV2722_8BIT, 0x371f, 0x0d},
1013 	{OV2722_8BIT, 0x3708, 0x61},
1014 	{OV2722_8BIT, 0x3709, 0x12},
1015 	{OV2722_8BIT, 0x3800, 0x01},
1016 	{OV2722_8BIT, 0x3801, 0x40}, /* H crop start: 320 */
1017 	{OV2722_8BIT, 0x3802, 0x00},
1018 	{OV2722_8BIT, 0x3803, 0xb1}, /* V crop start: 177 */
1019 	{OV2722_8BIT, 0x3804, 0x06},
1020 	{OV2722_8BIT, 0x3805, 0x55}, /* H crop end: 1621 */
1021 	{OV2722_8BIT, 0x3806, 0x03},
1022 	{OV2722_8BIT, 0x3807, 0x95}, /* V crop end: 918 */
1023 	{OV2722_8BIT, 0x3808, 0x05},
1024 	{OV2722_8BIT, 0x3809, 0x10}, /* H output size: 0x0788==1928 */
1025 	{OV2722_8BIT, 0x380a, 0x02},
1026 	{OV2722_8BIT, 0x380b, 0xe0}, /* output size: 0x02DE==734 */
1027 	{OV2722_8BIT, 0x380c, 0x08},
1028 	{OV2722_8BIT, 0x380d, 0x00}, /* H timing: 2048 */
1029 	{OV2722_8BIT, 0x380e, 0x04},
1030 	{OV2722_8BIT, 0x380f, 0xa3}, /* V timing: 1187 */
1031 	{OV2722_8BIT, 0x3810, 0x00},
1032 	{OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */
1033 	{OV2722_8BIT, 0x3812, 0x00},
1034 	{OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */
1035 	{OV2722_8BIT, 0x3820, 0x80},
1036 	{OV2722_8BIT, 0x3821, 0x06}, /* mirror */
1037 	{OV2722_8BIT, 0x3814, 0x11},
1038 	{OV2722_8BIT, 0x3815, 0x11},
1039 	{OV2722_8BIT, 0x3612, 0x0b},
1040 	{OV2722_8BIT, 0x3618, 0x04},
1041 	{OV2722_8BIT, 0x3a08, 0x01},
1042 	{OV2722_8BIT, 0x3a09, 0x50},
1043 	{OV2722_8BIT, 0x3a0a, 0x01},
1044 	{OV2722_8BIT, 0x3a0b, 0x18},
1045 	{OV2722_8BIT, 0x3a0d, 0x03},
1046 	{OV2722_8BIT, 0x3a0e, 0x03},
1047 	{OV2722_8BIT, 0x4520, 0x00},
1048 	{OV2722_8BIT, 0x4837, 0x1b},
1049 	{OV2722_8BIT, 0x3600, 0x08},
1050 	{OV2722_8BIT, 0x3621, 0xc0},
1051 	{OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */
1052 	{OV2722_8BIT, 0x3633, 0x23},
1053 	{OV2722_8BIT, 0x3634, 0x54},
1054 	{OV2722_8BIT, 0x3f01, 0x0c},
1055 	{OV2722_8BIT, 0x5001, 0xc1},
1056 	{OV2722_8BIT, 0x3614, 0xf0},
1057 	{OV2722_8BIT, 0x3630, 0x2d},
1058 	{OV2722_8BIT, 0x370b, 0x62},
1059 	{OV2722_8BIT, 0x3706, 0x61},
1060 	{OV2722_8BIT, 0x4000, 0x02},
1061 	{OV2722_8BIT, 0x4002, 0xc5},
1062 	{OV2722_8BIT, 0x4005, 0x08},
1063 	{OV2722_8BIT, 0x404f, 0x84},
1064 	{OV2722_8BIT, 0x4051, 0x00},
1065 	{OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */
1066 	{OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */
1067 	{OV2722_8BIT, 0x3a18, 0x00},
1068 	{OV2722_8BIT, 0x3a19, 0x80},
1069 	{OV2722_8BIT, 0x4521, 0x00},
1070 	{OV2722_8BIT, 0x5183, 0xb0},
1071 	{OV2722_8BIT, 0x5184, 0xb0},
1072 	{OV2722_8BIT, 0x5185, 0xb0},
1073 	{OV2722_8BIT, 0x370c, 0x0c},
1074 	{OV2722_8BIT, 0x3035, 0x00},
1075 	{OV2722_8BIT, 0x3036, 0x26}, /* {0x3036, 0x2c}, //422.4 MHz */
1076 	{OV2722_8BIT, 0x3037, 0xa1},
1077 	{OV2722_8BIT, 0x303e, 0x19},
1078 	{OV2722_8BIT, 0x3038, 0x06},
1079 	{OV2722_8BIT, 0x3018, 0x04},
1080 	{OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */
1081 	{OV2722_8BIT, 0x3001, 0x00},
1082 	{OV2722_8BIT, 0x3002, 0x00},
1083 	{OV2722_8BIT, 0x3a0f, 0x40},
1084 	{OV2722_8BIT, 0x3a10, 0x38},
1085 	{OV2722_8BIT, 0x3a1b, 0x48},
1086 	{OV2722_8BIT, 0x3a1e, 0x30},
1087 	{OV2722_8BIT, 0x3a11, 0x90},
1088 	{OV2722_8BIT, 0x3a1f, 0x10},
1089 	{OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */
1090 	{OV2722_8BIT, 0x3500, 0x00},
1091 	{OV2722_8BIT, 0x3501, 0x3F},
1092 	{OV2722_8BIT, 0x3502, 0x00},
1093 	{OV2722_8BIT, 0x3508, 0x00},
1094 	{OV2722_8BIT, 0x3509, 0x00},
1095 	{OV2722_TOK_TERM, 0, 0},
1096 };
1097 #endif
1098 
1099 static struct ov2722_resolution ov2722_res_preview[] = {
1100 	{
1101 		.desc = "ov2722_1632_1092_30fps",
1102 		.width = 1632,
1103 		.height = 1092,
1104 		.fps = 30,
1105 		.pix_clk_freq = 85,
1106 		.used = 0,
1107 		.pixels_per_line = 2260,
1108 		.lines_per_frame = 1244,
1109 		.skip_frames = 3,
1110 		.regs = ov2722_1632_1092_30fps,
1111 		.mipi_freq = 422400,
1112 	},
1113 	{
1114 		.desc = "ov2722_1452_1092_30fps",
1115 		.width = 1452,
1116 		.height = 1092,
1117 		.fps = 30,
1118 		.pix_clk_freq = 85,
1119 		.used = 0,
1120 		.pixels_per_line = 2260,
1121 		.lines_per_frame = 1244,
1122 		.skip_frames = 3,
1123 		.regs = ov2722_1452_1092_30fps,
1124 		.mipi_freq = 422400,
1125 	},
1126 	{
1127 		.desc = "ov2722_1080P_30fps",
1128 		.width = 1932,
1129 		.height = 1092,
1130 		.pix_clk_freq = 69,
1131 		.fps = 30,
1132 		.used = 0,
1133 		.pixels_per_line = 2068,
1134 		.lines_per_frame = 1114,
1135 		.skip_frames = 3,
1136 		.regs = ov2722_1080p_30fps,
1137 		.mipi_freq = 345600,
1138 	},
1139 };
1140 
1141 #define N_RES_PREVIEW (ARRAY_SIZE(ov2722_res_preview))
1142 
1143 /*
1144  * Disable non-preview configurations until the configuration selection is
1145  * improved.
1146  */
1147 #if 0
1148 struct ov2722_resolution ov2722_res_still[] = {
1149 	{
1150 		.desc = "ov2722_480P_30fps",
1151 		.width = 1632,
1152 		.height = 1092,
1153 		.fps = 30,
1154 		.pix_clk_freq = 85,
1155 		.used = 0,
1156 		.pixels_per_line = 2260,
1157 		.lines_per_frame = 1244,
1158 		.skip_frames = 3,
1159 		.regs = ov2722_1632_1092_30fps,
1160 		.mipi_freq = 422400,
1161 	},
1162 	{
1163 		.desc = "ov2722_1452_1092_30fps",
1164 		.width = 1452,
1165 		.height = 1092,
1166 		.fps = 30,
1167 		.pix_clk_freq = 85,
1168 		.used = 0,
1169 		.pixels_per_line = 2260,
1170 		.lines_per_frame = 1244,
1171 		.skip_frames = 3,
1172 		.regs = ov2722_1452_1092_30fps,
1173 		.mipi_freq = 422400,
1174 	},
1175 	{
1176 		.desc = "ov2722_1080P_30fps",
1177 		.width = 1932,
1178 		.height = 1092,
1179 		.pix_clk_freq = 69,
1180 		.fps = 30,
1181 		.used = 0,
1182 		.pixels_per_line = 2068,
1183 		.lines_per_frame = 1114,
1184 		.skip_frames = 3,
1185 		.regs = ov2722_1080p_30fps,
1186 		.mipi_freq = 345600,
1187 	},
1188 };
1189 
1190 #define N_RES_STILL (ARRAY_SIZE(ov2722_res_still))
1191 
1192 struct ov2722_resolution ov2722_res_video[] = {
1193 	{
1194 		.desc = "ov2722_QVGA_30fps",
1195 		.width = 336,
1196 		.height = 256,
1197 		.fps = 30,
1198 		.pix_clk_freq = 73,
1199 		.used = 0,
1200 		.pixels_per_line = 2048,
1201 		.lines_per_frame = 1184,
1202 		.skip_frames = 3,
1203 		.regs = ov2722_QVGA_30fps,
1204 		.mipi_freq = 364800,
1205 	},
1206 	{
1207 		.desc = "ov2722_480P_30fps",
1208 		.width = 736,
1209 		.height = 496,
1210 		.fps = 30,
1211 		.pix_clk_freq = 73,
1212 		.used = 0,
1213 		.pixels_per_line = 2048,
1214 		.lines_per_frame = 1184,
1215 		.skip_frames = 3,
1216 		.regs = ov2722_480P_30fps,
1217 	},
1218 	{
1219 		.desc = "ov2722_1080P_30fps",
1220 		.width = 1932,
1221 		.height = 1092,
1222 		.pix_clk_freq = 69,
1223 		.fps = 30,
1224 		.used = 0,
1225 		.pixels_per_line = 2068,
1226 		.lines_per_frame = 1114,
1227 		.skip_frames = 3,
1228 		.regs = ov2722_1080p_30fps,
1229 		.mipi_freq = 345600,
1230 	},
1231 };
1232 
1233 #define N_RES_VIDEO (ARRAY_SIZE(ov2722_res_video))
1234 #endif
1235 
1236 static struct ov2722_resolution *ov2722_res = ov2722_res_preview;
1237 static unsigned long N_RES = N_RES_PREVIEW;
1238 #endif
1239