1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * FB driver for the uPD161704 LCD Controller 4 * 5 * Copyright (C) 2014 Seong-Woo Kim 6 * 7 * Based on fb_ili9325.c by Noralf Tronnes 8 * Based on ili9325.c by Jeroen Domburg 9 * Init code from UTFT library by Henning Karlsen 10 */ 11 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 17 #include "fbtft.h" 18 19 #define DRVNAME "fb_upd161704" 20 #define WIDTH 240 21 #define HEIGHT 320 22 #define BPP 16 23 24 static int init_display(struct fbtft_par *par) 25 { 26 par->fbtftops.reset(par); 27 28 /* Initialization sequence from Lib_UTFT */ 29 30 /* register reset */ 31 write_reg(par, 0x0003, 0x0001); /* Soft reset */ 32 33 /* oscillator start */ 34 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ 35 udelay(100); 36 37 /* y-setting */ 38 write_reg(par, 0x0024, 0x007B); /* amplitude setting */ 39 udelay(10); 40 write_reg(par, 0x0025, 0x003B); /* amplitude setting */ 41 write_reg(par, 0x0026, 0x0034); /* amplitude setting */ 42 udelay(10); 43 write_reg(par, 0x0027, 0x0004); /* amplitude setting */ 44 write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */ 45 udelay(10); 46 write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */ 47 write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */ 48 udelay(10); 49 write_reg(par, 0x0062, 0x002C); /* adjustment V9 negative polarity */ 50 write_reg(par, 0x0063, 0x0022); /* adjustment V34 positive polarity */ 51 udelay(10); 52 write_reg(par, 0x0064, 0x0027); /* adjustment V31 negative polarity */ 53 udelay(10); 54 write_reg(par, 0x0065, 0x0014); /* adjustment V61 negative polarity */ 55 udelay(10); 56 write_reg(par, 0x0066, 0x0010); /* adjustment V61 negative polarity */ 57 58 /* Basical clock for 1 line (BASECOUNT[7:0]) number specified */ 59 write_reg(par, 0x002E, 0x002D); 60 61 /* Power supply setting */ 62 write_reg(par, 0x0019, 0x0000); /* DC/DC output setting */ 63 udelay(200); 64 write_reg(par, 0x001A, 0x1000); /* DC/DC frequency setting */ 65 write_reg(par, 0x001B, 0x0023); /* DC/DC rising setting */ 66 write_reg(par, 0x001C, 0x0C01); /* Regulator voltage setting */ 67 write_reg(par, 0x001D, 0x0000); /* Regulator current setting */ 68 write_reg(par, 0x001E, 0x0009); /* VCOM output setting */ 69 write_reg(par, 0x001F, 0x0035); /* VCOM amplitude setting */ 70 write_reg(par, 0x0020, 0x0015); /* VCOMM cencter setting */ 71 write_reg(par, 0x0018, 0x1E7B); /* DC/DC operation setting */ 72 73 /* windows setting */ 74 write_reg(par, 0x0008, 0x0000); /* Minimum X address */ 75 write_reg(par, 0x0009, 0x00EF); /* Maximum X address */ 76 write_reg(par, 0x000a, 0x0000); /* Minimum Y address */ 77 write_reg(par, 0x000b, 0x013F); /* Maximum Y address */ 78 79 /* LCD display area setting */ 80 write_reg(par, 0x0029, 0x0000); /* [LCDSIZE] X MIN. size set */ 81 write_reg(par, 0x002A, 0x0000); /* [LCDSIZE] Y MIN. size set */ 82 write_reg(par, 0x002B, 0x00EF); /* [LCDSIZE] X MAX. size set */ 83 write_reg(par, 0x002C, 0x013F); /* [LCDSIZE] Y MAX. size set */ 84 85 /* Gate scan setting */ 86 write_reg(par, 0x0032, 0x0002); 87 88 /* n line inversion line number */ 89 write_reg(par, 0x0033, 0x0000); 90 91 /* Line inversion/frame inversion/interlace setting */ 92 write_reg(par, 0x0037, 0x0000); 93 94 /* Gate scan operation setting register */ 95 write_reg(par, 0x003B, 0x0001); 96 97 /* Color mode */ 98 /*GS = 0: 260-k color (64 gray scale), GS = 1: 8 color (2 gray scale) */ 99 write_reg(par, 0x0004, 0x0000); 100 101 /* RAM control register */ 102 write_reg(par, 0x0005, 0x0000); /*Window access 00:Normal, 10:Window */ 103 104 /* Display setting register 2 */ 105 write_reg(par, 0x0001, 0x0000); 106 107 /* display setting */ 108 write_reg(par, 0x0000, 0x0000); /* display on */ 109 110 return 0; 111 } 112 113 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) 114 { 115 switch (par->info->var.rotate) { 116 /* R20h = Horizontal GRAM Start Address */ 117 /* R21h = Vertical GRAM Start Address */ 118 case 0: 119 write_reg(par, 0x0006, xs); 120 write_reg(par, 0x0007, ys); 121 break; 122 case 180: 123 write_reg(par, 0x0006, WIDTH - 1 - xs); 124 write_reg(par, 0x0007, HEIGHT - 1 - ys); 125 break; 126 case 270: 127 write_reg(par, 0x0006, WIDTH - 1 - ys); 128 write_reg(par, 0x0007, xs); 129 break; 130 case 90: 131 write_reg(par, 0x0006, ys); 132 write_reg(par, 0x0007, HEIGHT - 1 - xs); 133 break; 134 } 135 136 write_reg(par, 0x0e); /* Write Data to GRAM */ 137 } 138 139 static int set_var(struct fbtft_par *par) 140 { 141 switch (par->info->var.rotate) { 142 /* AM: GRAM update direction */ 143 case 0: 144 write_reg(par, 0x01, 0x0000); 145 write_reg(par, 0x05, 0x0000); 146 break; 147 case 180: 148 write_reg(par, 0x01, 0x00C0); 149 write_reg(par, 0x05, 0x0000); 150 break; 151 case 270: 152 write_reg(par, 0x01, 0x0080); 153 write_reg(par, 0x05, 0x0001); 154 break; 155 case 90: 156 write_reg(par, 0x01, 0x0040); 157 write_reg(par, 0x05, 0x0001); 158 break; 159 } 160 161 return 0; 162 } 163 164 static struct fbtft_display display = { 165 .regwidth = 16, 166 .width = WIDTH, 167 .height = HEIGHT, 168 .fbtftops = { 169 .init_display = init_display, 170 .set_addr_win = set_addr_win, 171 .set_var = set_var, 172 }, 173 }; 174 175 FBTFT_REGISTER_DRIVER(DRVNAME, "nec,upd161704", &display); 176 177 MODULE_ALIAS("spi:" DRVNAME); 178 MODULE_ALIAS("platform:" DRVNAME); 179 MODULE_ALIAS("spi:upd161704"); 180 MODULE_ALIAS("platform:upd161704"); 181 182 MODULE_DESCRIPTION("FB driver for the uPD161704 LCD Controller"); 183 MODULE_AUTHOR("Seong-Woo Kim"); 184 MODULE_LICENSE("GPL"); 185