1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * FB driver for the S6D02A1 LCD Controller 4 * 5 * Based on fb_st7735r.c by Noralf Tronnes 6 * Init code from UTFT library by Henning Karlsen 7 */ 8 9 #include <linux/module.h> 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <video/mipi_display.h> 13 14 #include "fbtft.h" 15 16 #define DRVNAME "fb_s6d02a1" 17 18 static const s16 default_init_sequence[] = { 19 20 -1, 0xf0, 0x5a, 0x5a, 21 22 -1, 0xfc, 0x5a, 0x5a, 23 24 -1, 0xfa, 0x02, 0x1f, 0x00, 0x10, 0x22, 0x30, 0x38, 0x3A, 0x3A, 0x3A, 0x3A, 0x3A, 0x3d, 0x02, 0x01, 25 26 -1, 0xfb, 0x21, 0x00, 0x02, 0x04, 0x07, 0x0a, 0x0b, 0x0c, 0x0c, 0x16, 0x1e, 0x30, 0x3f, 0x01, 0x02, 27 28 /* power setting sequence */ 29 -1, 0xfd, 0x00, 0x00, 0x00, 0x17, 0x10, 0x00, 0x01, 0x01, 0x00, 0x1f, 0x1f, 30 31 -1, 0xf4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00, 32 33 -1, 0xf5, 0x00, 0x70, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6d, 0x66, 0x06, 34 35 -1, 0xf6, 0x02, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x02, 0x00, 0x06, 0x01, 0x00, 36 37 -1, 0xf2, 0x00, 0x01, 0x03, 0x08, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x04, 0x08, 0x08, 38 39 -1, 0xf8, 0x11, 40 41 -1, 0xf7, 0xc8, 0x20, 0x00, 0x00, 42 43 -1, 0xf3, 0x00, 0x00, 44 45 -1, MIPI_DCS_EXIT_SLEEP_MODE, 46 -2, 50, 47 48 -1, 0xf3, 0x00, 0x01, 49 -2, 50, 50 -1, 0xf3, 0x00, 0x03, 51 -2, 50, 52 -1, 0xf3, 0x00, 0x07, 53 -2, 50, 54 -1, 0xf3, 0x00, 0x0f, 55 -2, 50, 56 57 -1, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00, 58 -2, 50, 59 60 -1, 0xf3, 0x00, 0x1f, 61 -2, 50, 62 -1, 0xf3, 0x00, 0x7f, 63 -2, 50, 64 65 -1, 0xf3, 0x00, 0xff, 66 -2, 50, 67 68 -1, 0xfd, 0x00, 0x00, 0x00, 0x17, 0x10, 0x00, 0x00, 0x01, 0x00, 0x16, 0x16, 69 70 -1, 0xf4, 0x00, 0x09, 0x00, 0x00, 0x00, 0x3f, 0x3f, 0x07, 0x00, 0x3C, 0x36, 0x00, 0x3C, 0x36, 0x00, 71 72 /* initializing sequence */ 73 74 -1, MIPI_DCS_SET_ADDRESS_MODE, 0x08, 75 76 -1, MIPI_DCS_SET_TEAR_ON, 0x00, 77 78 -1, MIPI_DCS_SET_PIXEL_FORMAT, 0x05, 79 80 /* gamma setting - possible values 0x01, 0x02, 0x04, 0x08 */ 81 -1, MIPI_DCS_SET_GAMMA_CURVE, 0x01, 82 83 -2, 150, 84 -1, MIPI_DCS_SET_DISPLAY_ON, 85 -1, MIPI_DCS_WRITE_MEMORY_START, 86 /* end marker */ 87 -3 88 89 }; 90 91 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) 92 { 93 write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS, 94 xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); 95 96 write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS, 97 ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); 98 99 write_reg(par, MIPI_DCS_WRITE_MEMORY_START); 100 } 101 102 #define MY BIT(7) 103 #define MX BIT(6) 104 #define MV BIT(5) 105 static int set_var(struct fbtft_par *par) 106 { 107 /* 108 * Memory data access control (0x36h) 109 * RGB/BGR: 110 * 1. Mode selection pin SRGB 111 * RGB H/W pin for color filter setting: 0=RGB, 1=BGR 112 * 2. MADCTL RGB bit 113 * RGB-BGR ORDER color filter panel: 0=RGB, 1=BGR 114 */ 115 switch (par->info->var.rotate) { 116 case 0: 117 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 118 MX | MY | (par->bgr << 3)); 119 break; 120 case 270: 121 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 122 MY | MV | (par->bgr << 3)); 123 break; 124 case 180: 125 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 126 par->bgr << 3); 127 break; 128 case 90: 129 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 130 MX | MV | (par->bgr << 3)); 131 break; 132 } 133 134 return 0; 135 } 136 137 static struct fbtft_display display = { 138 .regwidth = 8, 139 .width = 128, 140 .height = 160, 141 .init_sequence = default_init_sequence, 142 .fbtftops = { 143 .set_addr_win = set_addr_win, 144 .set_var = set_var, 145 }, 146 }; 147 148 FBTFT_REGISTER_DRIVER(DRVNAME, "samsung,s6d02a1", &display); 149 150 MODULE_ALIAS("spi:" DRVNAME); 151 MODULE_ALIAS("platform:" DRVNAME); 152 MODULE_ALIAS("spi:s6d02a1"); 153 MODULE_ALIAS("platform:s6d02a1"); 154 155 MODULE_DESCRIPTION("FB driver for the S6D02A1 LCD Controller"); 156 MODULE_AUTHOR("WOLFGANG BUENING"); 157 MODULE_LICENSE("GPL"); 158