1 /* 2 * FBTFT driver for the RA8875 LCD Controller 3 * Copyright by Pf@nne & NOTRO 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 21 #include <linux/gpio.h> 22 #include "fbtft.h" 23 24 #define DRVNAME "fb_ra8875" 25 26 static int write_spi(struct fbtft_par *par, void *buf, size_t len) 27 { 28 struct spi_transfer t = { 29 .tx_buf = buf, 30 .len = len, 31 .speed_hz = 1000000, 32 }; 33 struct spi_message m; 34 35 fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len, 36 "%s(len=%d): ", __func__, len); 37 38 if (!par->spi) { 39 dev_err(par->info->device, 40 "%s: par->spi is unexpectedly NULL\n", __func__); 41 return -1; 42 } 43 44 spi_message_init(&m); 45 if (par->txbuf.dma && buf == par->txbuf.buf) { 46 t.tx_dma = par->txbuf.dma; 47 m.is_dma_mapped = 1; 48 } 49 spi_message_add_tail(&t, &m); 50 return spi_sync(par->spi, &m); 51 } 52 53 static int init_display(struct fbtft_par *par) 54 { 55 gpio_set_value(par->gpio.dc, 1); 56 57 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, 58 "%s()\n", __func__); 59 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, 60 "display size %dx%d\n", 61 par->info->var.xres, 62 par->info->var.yres); 63 64 par->fbtftops.reset(par); 65 66 if ((par->info->var.xres == 320) && (par->info->var.yres == 240)) { 67 /* PLL clock frequency */ 68 write_reg(par, 0x88, 0x0A); 69 write_reg(par, 0x89, 0x02); 70 mdelay(10); 71 /* color deep / MCU Interface */ 72 write_reg(par, 0x10, 0x0C); 73 /* pixel clock period */ 74 write_reg(par, 0x04, 0x03); 75 mdelay(1); 76 /* horizontal settings */ 77 write_reg(par, 0x14, 0x27); 78 write_reg(par, 0x15, 0x00); 79 write_reg(par, 0x16, 0x05); 80 write_reg(par, 0x17, 0x04); 81 write_reg(par, 0x18, 0x03); 82 /* vertical settings */ 83 write_reg(par, 0x19, 0xEF); 84 write_reg(par, 0x1A, 0x00); 85 write_reg(par, 0x1B, 0x05); 86 write_reg(par, 0x1C, 0x00); 87 write_reg(par, 0x1D, 0x0E); 88 write_reg(par, 0x1E, 0x00); 89 write_reg(par, 0x1F, 0x02); 90 } else if ((par->info->var.xres == 480) && 91 (par->info->var.yres == 272)) { 92 /* PLL clock frequency */ 93 write_reg(par, 0x88, 0x0A); 94 write_reg(par, 0x89, 0x02); 95 mdelay(10); 96 /* color deep / MCU Interface */ 97 write_reg(par, 0x10, 0x0C); 98 /* pixel clock period */ 99 write_reg(par, 0x04, 0x82); 100 mdelay(1); 101 /* horizontal settings */ 102 write_reg(par, 0x14, 0x3B); 103 write_reg(par, 0x15, 0x00); 104 write_reg(par, 0x16, 0x01); 105 write_reg(par, 0x17, 0x00); 106 write_reg(par, 0x18, 0x05); 107 /* vertical settings */ 108 write_reg(par, 0x19, 0x0F); 109 write_reg(par, 0x1A, 0x01); 110 write_reg(par, 0x1B, 0x02); 111 write_reg(par, 0x1C, 0x00); 112 write_reg(par, 0x1D, 0x07); 113 write_reg(par, 0x1E, 0x00); 114 write_reg(par, 0x1F, 0x09); 115 } else if ((par->info->var.xres == 640) && 116 (par->info->var.yres == 480)) { 117 /* PLL clock frequency */ 118 write_reg(par, 0x88, 0x0B); 119 write_reg(par, 0x89, 0x02); 120 mdelay(10); 121 /* color deep / MCU Interface */ 122 write_reg(par, 0x10, 0x0C); 123 /* pixel clock period */ 124 write_reg(par, 0x04, 0x01); 125 mdelay(1); 126 /* horizontal settings */ 127 write_reg(par, 0x14, 0x4F); 128 write_reg(par, 0x15, 0x05); 129 write_reg(par, 0x16, 0x0F); 130 write_reg(par, 0x17, 0x01); 131 write_reg(par, 0x18, 0x00); 132 /* vertical settings */ 133 write_reg(par, 0x19, 0xDF); 134 write_reg(par, 0x1A, 0x01); 135 write_reg(par, 0x1B, 0x0A); 136 write_reg(par, 0x1C, 0x00); 137 write_reg(par, 0x1D, 0x0E); 138 write_reg(par, 0x1E, 0x00); 139 write_reg(par, 0x1F, 0x01); 140 } else if ((par->info->var.xres == 800) && 141 (par->info->var.yres == 480)) { 142 /* PLL clock frequency */ 143 write_reg(par, 0x88, 0x0B); 144 write_reg(par, 0x89, 0x02); 145 mdelay(10); 146 /* color deep / MCU Interface */ 147 write_reg(par, 0x10, 0x0C); 148 /* pixel clock period */ 149 write_reg(par, 0x04, 0x81); 150 mdelay(1); 151 /* horizontal settings */ 152 write_reg(par, 0x14, 0x63); 153 write_reg(par, 0x15, 0x03); 154 write_reg(par, 0x16, 0x03); 155 write_reg(par, 0x17, 0x02); 156 write_reg(par, 0x18, 0x00); 157 /* vertical settings */ 158 write_reg(par, 0x19, 0xDF); 159 write_reg(par, 0x1A, 0x01); 160 write_reg(par, 0x1B, 0x14); 161 write_reg(par, 0x1C, 0x00); 162 write_reg(par, 0x1D, 0x06); 163 write_reg(par, 0x1E, 0x00); 164 write_reg(par, 0x1F, 0x01); 165 } else { 166 dev_err(par->info->device, "display size is not supported!!"); 167 return -1; 168 } 169 170 /* PWM clock */ 171 write_reg(par, 0x8a, 0x81); 172 write_reg(par, 0x8b, 0xFF); 173 mdelay(10); 174 175 /* Display ON */ 176 write_reg(par, 0x01, 0x80); 177 mdelay(10); 178 179 return 0; 180 } 181 182 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) 183 { 184 /* Set_Active_Window */ 185 write_reg(par, 0x30, xs & 0x00FF); 186 write_reg(par, 0x31, (xs & 0xFF00) >> 8); 187 write_reg(par, 0x32, ys & 0x00FF); 188 write_reg(par, 0x33, (ys & 0xFF00) >> 8); 189 write_reg(par, 0x34, (xs + xe) & 0x00FF); 190 write_reg(par, 0x35, ((xs + xe) & 0xFF00) >> 8); 191 write_reg(par, 0x36, (ys + ye) & 0x00FF); 192 write_reg(par, 0x37, ((ys + ye) & 0xFF00) >> 8); 193 194 /* Set_Memory_Write_Cursor */ 195 write_reg(par, 0x46, xs & 0xff); 196 write_reg(par, 0x47, (xs >> 8) & 0x03); 197 write_reg(par, 0x48, ys & 0xff); 198 write_reg(par, 0x49, (ys >> 8) & 0x01); 199 200 write_reg(par, 0x02); 201 } 202 203 static void write_reg8_bus8(struct fbtft_par *par, int len, ...) 204 { 205 va_list args; 206 int i, ret; 207 u8 *buf = par->buf; 208 209 /* slow down spi-speed for writing registers */ 210 par->fbtftops.write = write_spi; 211 212 if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) { 213 va_start(args, len); 214 for (i = 0; i < len; i++) 215 buf[i] = (u8)va_arg(args, unsigned int); 216 va_end(args); 217 fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par, par->info->device, 218 u8, buf, len, "%s: ", __func__); 219 } 220 221 va_start(args, len); 222 *buf++ = 0x80; 223 *buf = (u8)va_arg(args, unsigned int); 224 ret = par->fbtftops.write(par, par->buf, 2); 225 if (ret < 0) { 226 va_end(args); 227 dev_err(par->info->device, "write() failed and returned %dn", 228 ret); 229 return; 230 } 231 len--; 232 233 udelay(100); 234 235 if (len) { 236 buf = (u8 *)par->buf; 237 *buf++ = 0x00; 238 i = len; 239 while (i--) 240 *buf++ = (u8)va_arg(args, unsigned int); 241 242 ret = par->fbtftops.write(par, par->buf, len + 1); 243 if (ret < 0) { 244 va_end(args); 245 dev_err(par->info->device, 246 "write() failed and returned %dn", ret); 247 return; 248 } 249 } 250 va_end(args); 251 252 /* restore user spi-speed */ 253 par->fbtftops.write = fbtft_write_spi; 254 udelay(100); 255 } 256 257 static int write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len) 258 { 259 u16 *vmem16; 260 u16 *txbuf16 = par->txbuf.buf; 261 size_t remain; 262 size_t to_copy; 263 size_t tx_array_size; 264 int i; 265 int ret = 0; 266 size_t startbyte_size = 0; 267 268 fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s(offset=%zu, len=%zu)\n", 269 __func__, offset, len); 270 271 remain = len / 2; 272 vmem16 = (u16 *)(par->info->screen_buffer + offset); 273 tx_array_size = par->txbuf.len / 2; 274 txbuf16 = par->txbuf.buf + 1; 275 tx_array_size -= 2; 276 *(u8 *)(par->txbuf.buf) = 0x00; 277 startbyte_size = 1; 278 279 while (remain) { 280 to_copy = min(tx_array_size, remain); 281 dev_dbg(par->info->device, " to_copy=%zu, remain=%zu\n", 282 to_copy, remain - to_copy); 283 284 for (i = 0; i < to_copy; i++) 285 txbuf16[i] = cpu_to_be16(vmem16[i]); 286 287 vmem16 = vmem16 + to_copy; 288 ret = par->fbtftops.write(par, par->txbuf.buf, 289 startbyte_size + to_copy * 2); 290 if (ret < 0) 291 return ret; 292 remain -= to_copy; 293 } 294 295 return ret; 296 } 297 298 static struct fbtft_display display = { 299 .regwidth = 8, 300 .fbtftops = { 301 .init_display = init_display, 302 .set_addr_win = set_addr_win, 303 .write_register = write_reg8_bus8, 304 .write_vmem = write_vmem16_bus8, 305 .write = write_spi, 306 }, 307 }; 308 309 FBTFT_REGISTER_DRIVER(DRVNAME, "raio,ra8875", &display); 310 311 MODULE_ALIAS("spi:" DRVNAME); 312 MODULE_ALIAS("platform:" DRVNAME); 313 MODULE_ALIAS("spi:ra8875"); 314 MODULE_ALIAS("platform:ra8875"); 315 316 MODULE_DESCRIPTION("FB driver for the RA8875 LCD Controller"); 317 MODULE_AUTHOR("Pf@nne"); 318 MODULE_LICENSE("GPL"); 319