1 /* 2 * FB driver for the ILI9325 LCD Controller 3 * 4 * Copyright (C) 2013 Noralf Tronnes 5 * 6 * Based on ili9325.c by Jeroen Domburg 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/gpio.h> 23 #include <linux/delay.h> 24 25 #include "fbtft.h" 26 27 #define DRVNAME "fb_ili9325" 28 #define WIDTH 240 29 #define HEIGHT 320 30 #define BPP 16 31 #define FPS 20 32 #define DEFAULT_GAMMA "0F 00 7 2 0 0 6 5 4 1\n" \ 33 "04 16 2 7 6 3 2 1 7 7" 34 35 static unsigned bt = 6; /* VGL=Vci*4 , VGH=Vci*4 */ 36 module_param(bt, uint, 0); 37 MODULE_PARM_DESC(bt, "Sets the factor used in the step-up circuits"); 38 39 static unsigned vc = 0x03; /* Vci1=Vci*0.80 */ 40 module_param(vc, uint, 0); 41 MODULE_PARM_DESC(vc, 42 "Sets the ratio factor of Vci to generate the reference voltages Vci1"); 43 44 static unsigned vrh = 0x0d; /* VREG1OUT=Vci*1.85 */ 45 module_param(vrh, uint, 0); 46 MODULE_PARM_DESC(vrh, 47 "Set the amplifying rate (1.6 ~ 1.9) of Vci applied to output the VREG1OUT"); 48 49 static unsigned vdv = 0x12; /* VCOMH amplitude=VREG1OUT*0.98 */ 50 module_param(vdv, uint, 0); 51 MODULE_PARM_DESC(vdv, 52 "Select the factor of VREG1OUT to set the amplitude of Vcom"); 53 54 static unsigned vcm = 0x0a; /* VCOMH=VREG1OUT*0.735 */ 55 module_param(vcm, uint, 0); 56 MODULE_PARM_DESC(vcm, "Set the internal VcomH voltage"); 57 58 /* 59 * Verify that this configuration is within the Voltage limits 60 * 61 * Display module configuration: Vcc = IOVcc = Vci = 3.3V 62 * 63 * Voltages 64 * ---------- 65 * Vci = 3.3 66 * Vci1 = Vci * 0.80 = 2.64 67 * DDVDH = Vci1 * 2 = 5.28 68 * VCL = -Vci1 = -2.64 69 * VREG1OUT = Vci * 1.85 = 4.88 70 * VCOMH = VREG1OUT * 0.735 = 3.59 71 * VCOM amplitude = VREG1OUT * 0.98 = 4.79 72 * VGH = Vci * 4 = 13.2 73 * VGL = -Vci * 4 = -13.2 74 * 75 * Limits 76 * -------- 77 * Power supplies 78 * 1.65 < IOVcc < 3.30 => 1.65 < 3.3 < 3.30 79 * 2.40 < Vcc < 3.30 => 2.40 < 3.3 < 3.30 80 * 2.50 < Vci < 3.30 => 2.50 < 3.3 < 3.30 81 * 82 * Source/VCOM power supply voltage 83 * 4.50 < DDVDH < 6.0 => 4.50 < 5.28 < 6.0 84 * -3.0 < VCL < -2.0 => -3.0 < -2.64 < -2.0 85 * VCI - VCL < 6.0 => 5.94 < 6.0 86 * 87 * Gate driver output voltage 88 * 10 < VGH < 20 => 10 < 13.2 < 20 89 * -15 < VGL < -5 => -15 < -13.2 < -5 90 * VGH - VGL < 32 => 26.4 < 32 91 * 92 * VCOM driver output voltage 93 * VCOMH - VCOML < 6.0 => 4.79 < 6.0 94 */ 95 96 static int init_display(struct fbtft_par *par) 97 { 98 par->fbtftops.reset(par); 99 100 if (par->gpio.cs != -1) 101 gpio_set_value(par->gpio.cs, 0); /* Activate chip */ 102 103 bt &= 0x07; 104 vc &= 0x07; 105 vrh &= 0x0f; 106 vdv &= 0x1f; 107 vcm &= 0x3f; 108 109 /* Initialization sequence from ILI9325 Application Notes */ 110 111 /* ----------- Start Initial Sequence ----------- */ 112 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ 113 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ 114 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ 115 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ 116 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ 117 write_reg(par, 0x0004, 0x0000); /* Resize register */ 118 write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */ 119 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ 120 write_reg(par, 0x000A, 0x0000); /* FMARK function */ 121 write_reg(par, 0x000C, 0x0000); /* RGB interface setting */ 122 write_reg(par, 0x000D, 0x0000); /* Frame marker Position */ 123 write_reg(par, 0x000F, 0x0000); /* RGB interface polarity */ 124 125 /* ----------- Power On sequence ----------- */ 126 write_reg(par, 0x0010, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ 127 write_reg(par, 0x0011, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ 128 write_reg(par, 0x0012, 0x0000); /* VREG1OUT voltage */ 129 write_reg(par, 0x0013, 0x0000); /* VDV[4:0] for VCOM amplitude */ 130 mdelay(200); /* Dis-charge capacitor power voltage */ 131 write_reg(par, 0x0010, /* SAP, BT[3:0], AP, DSTB, SLP, STB */ 132 (1 << 12) | (bt << 8) | (1 << 7) | (0x01 << 4)); 133 write_reg(par, 0x0011, 0x220 | vc); /* DC1[2:0], DC0[2:0], VC[2:0] */ 134 mdelay(50); /* Delay 50ms */ 135 write_reg(par, 0x0012, vrh); /* Internal reference voltage= Vci; */ 136 mdelay(50); /* Delay 50ms */ 137 write_reg(par, 0x0013, vdv << 8); /* Set VDV[4:0] for VCOM amplitude */ 138 write_reg(par, 0x0029, vcm); /* Set VCM[5:0] for VCOMH */ 139 write_reg(par, 0x002B, 0x000C); /* Set Frame Rate */ 140 mdelay(50); /* Delay 50ms */ 141 write_reg(par, 0x0020, 0x0000); /* GRAM horizontal Address */ 142 write_reg(par, 0x0021, 0x0000); /* GRAM Vertical Address */ 143 144 /*------------------ Set GRAM area --------------- */ 145 write_reg(par, 0x0050, 0x0000); /* Horizontal GRAM Start Address */ 146 write_reg(par, 0x0051, 0x00EF); /* Horizontal GRAM End Address */ 147 write_reg(par, 0x0052, 0x0000); /* Vertical GRAM Start Address */ 148 write_reg(par, 0x0053, 0x013F); /* Vertical GRAM Start Address */ 149 write_reg(par, 0x0060, 0xA700); /* Gate Scan Line */ 150 write_reg(par, 0x0061, 0x0001); /* NDL,VLE, REV */ 151 write_reg(par, 0x006A, 0x0000); /* set scrolling line */ 152 153 /*-------------- Partial Display Control --------- */ 154 write_reg(par, 0x0080, 0x0000); 155 write_reg(par, 0x0081, 0x0000); 156 write_reg(par, 0x0082, 0x0000); 157 write_reg(par, 0x0083, 0x0000); 158 write_reg(par, 0x0084, 0x0000); 159 write_reg(par, 0x0085, 0x0000); 160 161 /*-------------- Panel Control ------------------- */ 162 write_reg(par, 0x0090, 0x0010); 163 write_reg(par, 0x0092, 0x0600); 164 write_reg(par, 0x0007, 0x0133); /* 262K color and display ON */ 165 166 return 0; 167 } 168 169 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) 170 { 171 switch (par->info->var.rotate) { 172 /* R20h = Horizontal GRAM Start Address */ 173 /* R21h = Vertical GRAM Start Address */ 174 case 0: 175 write_reg(par, 0x0020, xs); 176 write_reg(par, 0x0021, ys); 177 break; 178 case 180: 179 write_reg(par, 0x0020, WIDTH - 1 - xs); 180 write_reg(par, 0x0021, HEIGHT - 1 - ys); 181 break; 182 case 270: 183 write_reg(par, 0x0020, WIDTH - 1 - ys); 184 write_reg(par, 0x0021, xs); 185 break; 186 case 90: 187 write_reg(par, 0x0020, ys); 188 write_reg(par, 0x0021, HEIGHT - 1 - xs); 189 break; 190 } 191 write_reg(par, 0x0022); /* Write Data to GRAM */ 192 } 193 194 static int set_var(struct fbtft_par *par) 195 { 196 switch (par->info->var.rotate) { 197 /* AM: GRAM update direction */ 198 case 0: 199 write_reg(par, 0x03, 0x0030 | (par->bgr << 12)); 200 break; 201 case 180: 202 write_reg(par, 0x03, 0x0000 | (par->bgr << 12)); 203 break; 204 case 270: 205 write_reg(par, 0x03, 0x0028 | (par->bgr << 12)); 206 break; 207 case 90: 208 write_reg(par, 0x03, 0x0018 | (par->bgr << 12)); 209 break; 210 } 211 212 return 0; 213 } 214 215 /* 216 * Gamma string format: 217 * VRP0 VRP1 RP0 RP1 KP0 KP1 KP2 KP3 KP4 KP5 218 * VRN0 VRN1 RN0 RN1 KN0 KN1 KN2 KN3 KN4 KN5 219 */ 220 #define CURVE(num, idx) curves[num * par->gamma.num_values + idx] 221 static int set_gamma(struct fbtft_par *par, unsigned long *curves) 222 { 223 unsigned long mask[] = { 224 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 225 0x1f, 0x1f, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 226 }; 227 int i, j; 228 229 /* apply mask */ 230 for (i = 0; i < 2; i++) 231 for (j = 0; j < 10; j++) 232 CURVE(i, j) &= mask[i * par->gamma.num_values + j]; 233 234 write_reg(par, 0x0030, CURVE(0, 5) << 8 | CURVE(0, 4)); 235 write_reg(par, 0x0031, CURVE(0, 7) << 8 | CURVE(0, 6)); 236 write_reg(par, 0x0032, CURVE(0, 9) << 8 | CURVE(0, 8)); 237 write_reg(par, 0x0035, CURVE(0, 3) << 8 | CURVE(0, 2)); 238 write_reg(par, 0x0036, CURVE(0, 1) << 8 | CURVE(0, 0)); 239 240 write_reg(par, 0x0037, CURVE(1, 5) << 8 | CURVE(1, 4)); 241 write_reg(par, 0x0038, CURVE(1, 7) << 8 | CURVE(1, 6)); 242 write_reg(par, 0x0039, CURVE(1, 9) << 8 | CURVE(1, 8)); 243 write_reg(par, 0x003C, CURVE(1, 3) << 8 | CURVE(1, 2)); 244 write_reg(par, 0x003D, CURVE(1, 1) << 8 | CURVE(1, 0)); 245 246 return 0; 247 } 248 249 #undef CURVE 250 251 static struct fbtft_display display = { 252 .regwidth = 16, 253 .width = WIDTH, 254 .height = HEIGHT, 255 .bpp = BPP, 256 .fps = FPS, 257 .gamma_num = 2, 258 .gamma_len = 10, 259 .gamma = DEFAULT_GAMMA, 260 .fbtftops = { 261 .init_display = init_display, 262 .set_addr_win = set_addr_win, 263 .set_var = set_var, 264 .set_gamma = set_gamma, 265 }, 266 }; 267 268 FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9325", &display); 269 270 MODULE_ALIAS("spi:" DRVNAME); 271 MODULE_ALIAS("platform:" DRVNAME); 272 MODULE_ALIAS("spi:ili9325"); 273 MODULE_ALIAS("platform:ili9325"); 274 275 MODULE_DESCRIPTION("FB driver for the ILI9325 LCD Controller"); 276 MODULE_AUTHOR("Noralf Tronnes"); 277 MODULE_LICENSE("GPL"); 278