1 /* 2 * FB driver for the uPD161704 LCD Controller 3 * 4 * Copyright (C) 2014 Seong-Woo Kim 5 * 6 * Based on fb_ili9325.c by Noralf Tronnes 7 * Based on ili9325.c by Jeroen Domburg 8 * Init code from UTFT library by Henning Karlsen 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/kernel.h> 23 #include <linux/init.h> 24 #include <linux/gpio.h> 25 #include <linux/delay.h> 26 27 #include "fbtft.h" 28 29 #define DRVNAME "fb_bd663474" 30 #define WIDTH 240 31 #define HEIGHT 320 32 #define BPP 16 33 34 static int init_display(struct fbtft_par *par) 35 { 36 if (par->gpio.cs != -1) 37 gpio_set_value(par->gpio.cs, 0); /* Activate chip */ 38 39 par->fbtftops.reset(par); 40 41 /* Initialization sequence from Lib_UTFT */ 42 43 /* oscillator start */ 44 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ 45 mdelay(10); 46 47 /* Power settings */ 48 write_reg(par, 0x100, 0x0000); /* power supply setup */ 49 write_reg(par, 0x101, 0x0000); 50 write_reg(par, 0x102, 0x3110); 51 write_reg(par, 0x103, 0xe200); 52 write_reg(par, 0x110, 0x009d); 53 write_reg(par, 0x111, 0x0022); 54 write_reg(par, 0x100, 0x0120); 55 mdelay(20); 56 57 write_reg(par, 0x100, 0x3120); 58 mdelay(80); 59 /* Display control */ 60 write_reg(par, 0x001, 0x0100); 61 write_reg(par, 0x002, 0x0000); 62 write_reg(par, 0x003, 0x1230); 63 write_reg(par, 0x006, 0x0000); 64 write_reg(par, 0x007, 0x0101); 65 write_reg(par, 0x008, 0x0808); 66 write_reg(par, 0x009, 0x0000); 67 write_reg(par, 0x00b, 0x0000); 68 write_reg(par, 0x00c, 0x0000); 69 write_reg(par, 0x00d, 0x0018); 70 /* LTPS control settings */ 71 write_reg(par, 0x012, 0x0000); 72 write_reg(par, 0x013, 0x0000); 73 write_reg(par, 0x018, 0x0000); 74 write_reg(par, 0x019, 0x0000); 75 76 write_reg(par, 0x203, 0x0000); 77 write_reg(par, 0x204, 0x0000); 78 79 write_reg(par, 0x210, 0x0000); 80 write_reg(par, 0x211, 0x00ef); 81 write_reg(par, 0x212, 0x0000); 82 write_reg(par, 0x213, 0x013f); 83 write_reg(par, 0x214, 0x0000); 84 write_reg(par, 0x215, 0x0000); 85 write_reg(par, 0x216, 0x0000); 86 write_reg(par, 0x217, 0x0000); 87 88 /* Gray scale settings */ 89 write_reg(par, 0x300, 0x5343); 90 write_reg(par, 0x301, 0x1021); 91 write_reg(par, 0x302, 0x0003); 92 write_reg(par, 0x303, 0x0011); 93 write_reg(par, 0x304, 0x050a); 94 write_reg(par, 0x305, 0x4342); 95 write_reg(par, 0x306, 0x1100); 96 write_reg(par, 0x307, 0x0003); 97 write_reg(par, 0x308, 0x1201); 98 write_reg(par, 0x309, 0x050a); 99 100 /* RAM access settings */ 101 write_reg(par, 0x400, 0x4027); 102 write_reg(par, 0x401, 0x0000); 103 write_reg(par, 0x402, 0x0000); /* First screen drive position (1) */ 104 write_reg(par, 0x403, 0x013f); /* First screen drive position (2) */ 105 write_reg(par, 0x404, 0x0000); 106 107 write_reg(par, 0x200, 0x0000); 108 write_reg(par, 0x201, 0x0000); 109 write_reg(par, 0x100, 0x7120); 110 write_reg(par, 0x007, 0x0103); 111 mdelay(10); 112 write_reg(par, 0x007, 0x0113); 113 114 return 0; 115 } 116 117 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye) 118 { 119 switch (par->info->var.rotate) { 120 /* R200h = Horizontal GRAM Start Address */ 121 /* R201h = Vertical GRAM Start Address */ 122 case 0: 123 write_reg(par, 0x0200, xs); 124 write_reg(par, 0x0201, ys); 125 break; 126 case 180: 127 write_reg(par, 0x0200, WIDTH - 1 - xs); 128 write_reg(par, 0x0201, HEIGHT - 1 - ys); 129 break; 130 case 270: 131 write_reg(par, 0x0200, WIDTH - 1 - ys); 132 write_reg(par, 0x0201, xs); 133 break; 134 case 90: 135 write_reg(par, 0x0200, ys); 136 write_reg(par, 0x0201, HEIGHT - 1 - xs); 137 break; 138 } 139 write_reg(par, 0x202); /* Write Data to GRAM */ 140 } 141 142 static int set_var(struct fbtft_par *par) 143 { 144 switch (par->info->var.rotate) { 145 /* AM: GRAM update direction */ 146 case 0: 147 write_reg(par, 0x003, 0x1230); 148 break; 149 case 180: 150 write_reg(par, 0x003, 0x1200); 151 break; 152 case 270: 153 write_reg(par, 0x003, 0x1228); 154 break; 155 case 90: 156 write_reg(par, 0x003, 0x1218); 157 break; 158 } 159 160 return 0; 161 } 162 163 static struct fbtft_display display = { 164 .regwidth = 16, 165 .width = WIDTH, 166 .height = HEIGHT, 167 .bpp = BPP, 168 .fbtftops = { 169 .init_display = init_display, 170 .set_addr_win = set_addr_win, 171 .set_var = set_var, 172 }, 173 }; 174 175 FBTFT_REGISTER_DRIVER(DRVNAME, "hitachi,bd663474", &display); 176 177 MODULE_ALIAS("spi:" DRVNAME); 178 MODULE_ALIAS("platform:" DRVNAME); 179 MODULE_ALIAS("spi:bd663474"); 180 MODULE_ALIAS("platform:bd663474"); 181 182 MODULE_DESCRIPTION("FB driver for the uPD161704 LCD Controller"); 183 MODULE_AUTHOR("Seong-Woo Kim"); 184 MODULE_LICENSE("GPL"); 185