1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * EMXX FCD (Function Controller Driver) for USB. 4 * 5 * Copyright (C) 2010 Renesas Electronics Corporation 6 */ 7 8 #ifndef _LINUX_EMXX_H 9 #define _LINUX_EMXX_H 10 11 /*---------------------------------------------------------------------------*/ 12 /*----------------- Default undef */ 13 #if 0 14 #define DEBUG 15 #define UDC_DEBUG_DUMP 16 #endif 17 18 /*----------------- Default define */ 19 #define USE_DMA 1 20 #define USE_SUSPEND_WAIT 1 21 22 #ifndef TRUE 23 #define TRUE 1 24 #define FALSE 0 25 #endif 26 27 /*------------ Board dependence(Resource) */ 28 #define VBUS_VALUE GPIO_VBUS 29 30 /* below hacked up for staging integration */ 31 #define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */ 32 #define INT_VBUS 0 /* IRQ for GPIO_P153 */ 33 34 /*------------ Board dependence(Wait) */ 35 36 /* CHATTERING wait time ms */ 37 #define VBUS_CHATTERING_MDELAY 1 38 /* DMA Abort wait time ms */ 39 #define DMA_DISABLE_TIME 10 40 41 /*------------ Controller dependence */ 42 #define NUM_ENDPOINTS 14 /* Endpoint */ 43 #define REG_EP_NUM 15 /* Endpoint Register */ 44 #define DMA_MAX_COUNT 256 /* DMA Block */ 45 46 #define EPC_RST_DISABLE_TIME 1 /* 1 usec */ 47 #define EPC_DIRPD_DISABLE_TIME 1 /* 1 msec */ 48 #define EPC_PLL_LOCK_COUNT 1000 /* 1000 */ 49 #define IN_DATA_EMPTY_COUNT 1000 /* 1000 */ 50 51 #define CHATGER_TIME 700 /* 700msec */ 52 #define USB_SUSPEND_TIME 2000 /* 2 sec */ 53 54 /* U2F FLAG */ 55 #define U2F_ENABLE 1 56 #define U2F_DISABLE 0 57 58 /*------- BIT */ 59 #define BIT00 0x00000001 60 #define BIT01 0x00000002 61 #define BIT02 0x00000004 62 #define BIT03 0x00000008 63 #define BIT04 0x00000010 64 #define BIT05 0x00000020 65 #define BIT06 0x00000040 66 #define BIT07 0x00000080 67 #define BIT08 0x00000100 68 #define BIT09 0x00000200 69 #define BIT10 0x00000400 70 #define BIT11 0x00000800 71 #define BIT12 0x00001000 72 #define BIT13 0x00002000 73 #define BIT14 0x00004000 74 #define BIT15 0x00008000 75 #define BIT16 0x00010000 76 #define BIT17 0x00020000 77 #define BIT18 0x00040000 78 #define BIT19 0x00080000 79 #define BIT20 0x00100000 80 #define BIT21 0x00200000 81 #define BIT22 0x00400000 82 #define BIT23 0x00800000 83 #define BIT24 0x01000000 84 #define BIT25 0x02000000 85 #define BIT26 0x04000000 86 #define BIT27 0x08000000 87 #define BIT28 0x10000000 88 #define BIT29 0x20000000 89 #define BIT30 0x40000000 90 #define BIT31 0x80000000 91 92 #define TEST_FORCE_ENABLE (BIT18 + BIT16) 93 94 #define INT_SEL BIT10 95 #define CONSTFS BIT09 96 #define SOF_RCV BIT08 97 #define RSUM_IN BIT07 98 #define SUSPEND BIT06 99 #define CONF BIT05 100 #define DEFAULT BIT04 101 #define CONNECTB BIT03 102 #define PUE2 BIT02 103 104 #define MAX_TEST_MODE_NUM 0x05 105 #define TEST_MODE_SHIFT 16 106 107 /*------- (0x0004) USB Status Register */ 108 #define SPEED_MODE BIT06 109 #define HIGH_SPEED BIT06 110 111 #define CONF BIT05 112 #define DEFAULT BIT04 113 #define USB_RST BIT03 114 #define SPND_OUT BIT02 115 #define RSUM_OUT BIT01 116 117 /*------- (0x0008) USB Address Register */ 118 #define USB_ADDR 0x007F0000 119 #define SOF_STATUS BIT15 120 #define UFRAME (BIT14 + BIT13 + BIT12) 121 #define FRAME 0x000007FF 122 123 #define USB_ADRS_SHIFT 16 124 125 /*------- (0x000C) UTMI Characteristic 1 Register */ 126 #define SQUSET (BIT07 + BIT06 + BIT05 + BIT04) 127 128 #define USB_SQUSET (BIT06 + BIT05 + BIT04) 129 130 /*------- (0x0010) TEST Control Register */ 131 #define FORCEHS BIT02 132 #define CS_TESTMODEEN BIT01 133 #define LOOPBACK BIT00 134 135 /*------- (0x0018) Setup Data 0 Register */ 136 /*------- (0x001C) Setup Data 1 Register */ 137 138 /*------- (0x0020) USB Interrupt Status Register */ 139 #define EPN_INT 0x00FFFF00 140 #define EP15_INT BIT23 141 #define EP14_INT BIT22 142 #define EP13_INT BIT21 143 #define EP12_INT BIT20 144 #define EP11_INT BIT19 145 #define EP10_INT BIT18 146 #define EP9_INT BIT17 147 #define EP8_INT BIT16 148 #define EP7_INT BIT15 149 #define EP6_INT BIT14 150 #define EP5_INT BIT13 151 #define EP4_INT BIT12 152 #define EP3_INT BIT11 153 #define EP2_INT BIT10 154 #define EP1_INT BIT09 155 #define EP0_INT BIT08 156 #define SPEED_MODE_INT BIT06 157 #define SOF_ERROR_INT BIT05 158 #define SOF_INT BIT04 159 #define USB_RST_INT BIT03 160 #define SPND_INT BIT02 161 #define RSUM_INT BIT01 162 163 #define USB_INT_STA_RW 0x7E 164 165 /*------- (0x0024) USB Interrupt Enable Register */ 166 #define EP15_0_EN 0x00FFFF00 167 #define EP15_EN BIT23 168 #define EP14_EN BIT22 169 #define EP13_EN BIT21 170 #define EP12_EN BIT20 171 #define EP11_EN BIT19 172 #define EP10_EN BIT18 173 #define EP9_EN BIT17 174 #define EP8_EN BIT16 175 #define EP7_EN BIT15 176 #define EP6_EN BIT14 177 #define EP5_EN BIT13 178 #define EP4_EN BIT12 179 #define EP3_EN BIT11 180 #define EP2_EN BIT10 181 #define EP1_EN BIT09 182 #define EP0_EN BIT08 183 #define SPEED_MODE_EN BIT06 184 #define SOF_ERROR_EN BIT05 185 #define SOF_EN BIT04 186 #define USB_RST_EN BIT03 187 #define SPND_EN BIT02 188 #define RSUM_EN BIT01 189 190 #define USB_INT_EN_BIT \ 191 (EP0_EN | SPEED_MODE_EN | USB_RST_EN | SPND_EN | RSUM_EN) 192 193 /*------- (0x0028) EP0 Control Register */ 194 #define EP0_STGSEL BIT18 195 #define EP0_OVERSEL BIT17 196 #define EP0_AUTO BIT16 197 #define EP0_PIDCLR BIT09 198 #define EP0_BCLR BIT08 199 #define EP0_DEND BIT07 200 #define EP0_DW (BIT06 + BIT05) 201 #define EP0_DW4 0 202 #define EP0_DW3 (BIT06 + BIT05) 203 #define EP0_DW2 BIT06 204 #define EP0_DW1 BIT05 205 206 #define EP0_INAK_EN BIT04 207 #define EP0_PERR_NAK_CLR BIT03 208 #define EP0_STL BIT02 209 #define EP0_INAK BIT01 210 #define EP0_ONAK BIT00 211 212 /*------- (0x002C) EP0 Status Register */ 213 #define EP0_PID BIT18 214 #define EP0_PERR_NAK BIT17 215 #define EP0_PERR_NAK_INT BIT16 216 #define EP0_OUT_NAK_INT BIT15 217 #define EP0_OUT_NULL BIT14 218 #define EP0_OUT_FULL BIT13 219 #define EP0_OUT_EMPTY BIT12 220 #define EP0_IN_NAK_INT BIT11 221 #define EP0_IN_DATA BIT10 222 #define EP0_IN_FULL BIT09 223 #define EP0_IN_EMPTY BIT08 224 #define EP0_OUT_NULL_INT BIT07 225 #define EP0_OUT_OR_INT BIT06 226 #define EP0_OUT_INT BIT05 227 #define EP0_IN_INT BIT04 228 #define EP0_STALL_INT BIT03 229 #define STG_END_INT BIT02 230 #define STG_START_INT BIT01 231 #define SETUP_INT BIT00 232 233 #define EP0_STATUS_RW_BIT (BIT16 | BIT15 | BIT11 | 0xFF) 234 235 /*------- (0x0030) EP0 Interrupt Enable Register */ 236 #define EP0_PERR_NAK_EN BIT16 237 #define EP0_OUT_NAK_EN BIT15 238 239 #define EP0_IN_NAK_EN BIT11 240 241 #define EP0_OUT_NULL_EN BIT07 242 #define EP0_OUT_OR_EN BIT06 243 #define EP0_OUT_EN BIT05 244 #define EP0_IN_EN BIT04 245 #define EP0_STALL_EN BIT03 246 #define STG_END_EN BIT02 247 #define STG_START_EN BIT01 248 #define SETUP_EN BIT00 249 250 #define EP0_INT_EN_BIT \ 251 (EP0_OUT_OR_EN | EP0_OUT_EN | EP0_IN_EN | STG_END_EN | SETUP_EN) 252 253 /*------- (0x0034) EP0 Length Register */ 254 #define EP0_LDATA 0x0000007F 255 256 /*------- (0x0038) EP0 Read Register */ 257 /*------- (0x003C) EP0 Write Register */ 258 259 /*------- (0x0040:) EPN Control Register */ 260 #define EPN_EN BIT31 261 #define EPN_BUF_TYPE BIT30 262 #define EPN_BUF_SINGLE BIT30 263 264 #define EPN_DIR0 BIT26 265 #define EPN_MODE (BIT25 + BIT24) 266 #define EPN_BULK 0 267 #define EPN_INTERRUPT BIT24 268 #define EPN_ISO BIT25 269 270 #define EPN_OVERSEL BIT17 271 #define EPN_AUTO BIT16 272 273 #define EPN_IPIDCLR BIT11 274 #define EPN_OPIDCLR BIT10 275 #define EPN_BCLR BIT09 276 #define EPN_CBCLR BIT08 277 #define EPN_DEND BIT07 278 #define EPN_DW (BIT06 + BIT05) 279 #define EPN_DW4 0 280 #define EPN_DW3 (BIT06 + BIT05) 281 #define EPN_DW2 BIT06 282 #define EPN_DW1 BIT05 283 284 #define EPN_OSTL_EN BIT04 285 #define EPN_ISTL BIT03 286 #define EPN_OSTL BIT02 287 288 #define EPN_ONAK BIT00 289 290 /*------- (0x0044:) EPN Status Register */ 291 #define EPN_ISO_PIDERR BIT29 /* R */ 292 #define EPN_OPID BIT28 /* R */ 293 #define EPN_OUT_NOTKN BIT27 /* R */ 294 #define EPN_ISO_OR BIT26 /* R */ 295 296 #define EPN_ISO_CRC BIT24 /* R */ 297 #define EPN_OUT_END_INT BIT23 /* RW */ 298 #define EPN_OUT_OR_INT BIT22 /* RW */ 299 #define EPN_OUT_NAK_ERR_INT BIT21 /* RW */ 300 #define EPN_OUT_STALL_INT BIT20 /* RW */ 301 #define EPN_OUT_INT BIT19 /* RW */ 302 #define EPN_OUT_NULL_INT BIT18 /* RW */ 303 #define EPN_OUT_FULL BIT17 /* R */ 304 #define EPN_OUT_EMPTY BIT16 /* R */ 305 306 #define EPN_IPID BIT10 /* R */ 307 #define EPN_IN_NOTKN BIT09 /* R */ 308 #define EPN_ISO_UR BIT08 /* R */ 309 #define EPN_IN_END_INT BIT07 /* RW */ 310 311 #define EPN_IN_NAK_ERR_INT BIT05 /* RW */ 312 #define EPN_IN_STALL_INT BIT04 /* RW */ 313 #define EPN_IN_INT BIT03 /* RW */ 314 #define EPN_IN_DATA BIT02 /* R */ 315 #define EPN_IN_FULL BIT01 /* R */ 316 #define EPN_IN_EMPTY BIT00 /* R */ 317 318 #define EPN_INT_EN \ 319 (EPN_OUT_END_INT | EPN_OUT_INT | EPN_IN_END_INT | EPN_IN_INT) 320 321 /*------- (0x0048:) EPN Interrupt Enable Register */ 322 #define EPN_OUT_END_EN BIT23 /* RW */ 323 #define EPN_OUT_OR_EN BIT22 /* RW */ 324 #define EPN_OUT_NAK_ERR_EN BIT21 /* RW */ 325 #define EPN_OUT_STALL_EN BIT20 /* RW */ 326 #define EPN_OUT_EN BIT19 /* RW */ 327 #define EPN_OUT_NULL_EN BIT18 /* RW */ 328 329 #define EPN_IN_END_EN BIT07 /* RW */ 330 331 #define EPN_IN_NAK_ERR_EN BIT05 /* RW */ 332 #define EPN_IN_STALL_EN BIT04 /* RW */ 333 #define EPN_IN_EN BIT03 /* RW */ 334 335 /*------- (0x004C:) EPN Interrupt Enable Register */ 336 #define EPN_STOP_MODE BIT11 337 #define EPN_DEND_SET BIT10 338 #define EPN_BURST_SET BIT09 339 #define EPN_STOP_SET BIT08 340 341 #define EPN_DMA_EN BIT04 342 343 #define EPN_DMAMODE0 BIT00 344 345 /*------- (0x0050:) EPN MaxPacket & BaseAddress Register */ 346 #define EPN_BASEAD 0x1FFF0000 347 #define EPN_MPKT 0x000007FF 348 349 /*------- (0x0054:) EPN Length & DMA Count Register */ 350 #define EPN_DMACNT 0x01FF0000 351 #define EPN_LDATA 0x000007FF 352 353 /*------- (0x0058:) EPN Read Register */ 354 /*------- (0x005C:) EPN Write Register */ 355 356 /*------- (0x1000) AHBSCTR Register */ 357 #define WAIT_MODE BIT00 358 359 /*------- (0x1004) AHBMCTR Register */ 360 #define ARBITER_CTR BIT31 /* RW */ 361 #define MCYCLE_RST BIT12 /* RW */ 362 363 #define ENDIAN_CTR (BIT09 + BIT08) /* RW */ 364 #define ENDIAN_BYTE_SWAP BIT09 365 #define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR 366 367 #define HBUSREQ_MODE BIT05 /* RW */ 368 #define HTRANS_MODE BIT04 /* RW */ 369 370 #define WBURST_TYPE BIT02 /* RW */ 371 #define BURST_TYPE (BIT01 + BIT00) /* RW */ 372 #define BURST_MAX_16 0 373 #define BURST_MAX_8 BIT00 374 #define BURST_MAX_4 BIT01 375 #define BURST_SINGLE BURST_TYPE 376 377 /*------- (0x1008) AHBBINT Register */ 378 #define DMA_ENDINT 0xFFFE0000 /* RW */ 379 380 #define AHB_VBUS_INT BIT13 /* RW */ 381 382 #define MBUS_ERRINT BIT06 /* RW */ 383 384 #define SBUS_ERRINT0 BIT04 /* RW */ 385 #define ERR_MASTER 0x0000000F /* R */ 386 387 /*------- (0x100C) AHBBINTEN Register */ 388 #define DMA_ENDINTEN 0xFFFE0000 /* RW */ 389 390 #define VBUS_INTEN BIT13 /* RW */ 391 392 #define MBUS_ERRINTEN BIT06 /* RW */ 393 394 #define SBUS_ERRINT0EN BIT04 /* RW */ 395 396 /*------- (0x1010) EPCTR Register */ 397 #define DIRPD BIT12 /* RW */ 398 399 #define VBUS_LEVEL BIT08 /* R */ 400 401 #define PLL_RESUME BIT05 /* RW */ 402 #define PLL_LOCK BIT04 /* R */ 403 404 #define EPC_RST BIT00 /* RW */ 405 406 /*------- (0x1014) USBF_EPTEST Register */ 407 #define LINESTATE (BIT09 + BIT08) /* R */ 408 #define DM_LEVEL BIT09 /* R */ 409 #define DP_LEVEL BIT08 /* R */ 410 411 #define PHY_TST BIT01 /* RW */ 412 #define PHY_TSTCLK BIT00 /* RW */ 413 414 /*------- (0x1020) USBSSVER Register */ 415 #define AHBB_VER 0x00FF0000 /* R */ 416 #define EPC_VER 0x0000FF00 /* R */ 417 #define SS_VER 0x000000FF /* R */ 418 419 /*------- (0x1024) USBSSCONF Register */ 420 #define EP_AVAILABLE 0xFFFF0000 /* R */ 421 #define DMA_AVAILABLE 0x0000FFFF /* R */ 422 423 /*------- (0x1110:) EPNDCR1 Register */ 424 #define DCR1_EPN_DMACNT 0x00FF0000 /* RW */ 425 426 #define DCR1_EPN_DIR0 BIT01 /* RW */ 427 #define DCR1_EPN_REQEN BIT00 /* RW */ 428 429 /*------- (0x1114:) EPNDCR2 Register */ 430 #define DCR2_EPN_LMPKT 0x07FF0000 /* RW */ 431 432 #define DCR2_EPN_MPKT 0x000007FF /* RW */ 433 434 /*------- (0x1118:) EPNTADR Register */ 435 #define EPN_TADR 0xFFFFFFFF /* RW */ 436 437 /*===========================================================================*/ 438 /* Struct */ 439 /*------- ep_regs */ 440 struct ep_regs { 441 u32 EP_CONTROL; /* EP Control */ 442 u32 EP_STATUS; /* EP Status */ 443 u32 EP_INT_ENA; /* EP Interrupt Enable */ 444 u32 EP_DMA_CTRL; /* EP DMA Control */ 445 u32 EP_PCKT_ADRS; /* EP Maxpacket & BaseAddress */ 446 u32 EP_LEN_DCNT; /* EP Length & DMA count */ 447 u32 EP_READ; /* EP Read */ 448 u32 EP_WRITE; /* EP Write */ 449 }; 450 451 /*------- ep_dcr */ 452 struct ep_dcr { 453 u32 EP_DCR1; /* EP_DCR1 */ 454 u32 EP_DCR2; /* EP_DCR2 */ 455 u32 EP_TADR; /* EP_TADR */ 456 u32 Reserved; /* Reserved */ 457 }; 458 459 /*------- Function Registers */ 460 struct fc_regs { 461 u32 USB_CONTROL; /* (0x0000) USB Control */ 462 u32 USB_STATUS; /* (0x0004) USB Status */ 463 u32 USB_ADDRESS; /* (0x0008) USB Address */ 464 u32 UTMI_CHARACTER_1; /* (0x000C) UTMI Setting */ 465 u32 TEST_CONTROL; /* (0x0010) TEST Control */ 466 u32 reserved_14; /* (0x0014) Reserved */ 467 u32 SETUP_DATA0; /* (0x0018) Setup Data0 */ 468 u32 SETUP_DATA1; /* (0x001C) Setup Data1 */ 469 u32 USB_INT_STA; /* (0x0020) USB Interrupt Status */ 470 u32 USB_INT_ENA; /* (0x0024) USB Interrupt Enable */ 471 u32 EP0_CONTROL; /* (0x0028) EP0 Control */ 472 u32 EP0_STATUS; /* (0x002C) EP0 Status */ 473 u32 EP0_INT_ENA; /* (0x0030) EP0 Interrupt Enable */ 474 u32 EP0_LENGTH; /* (0x0034) EP0 Length */ 475 u32 EP0_READ; /* (0x0038) EP0 Read */ 476 u32 EP0_WRITE; /* (0x003C) EP0 Write */ 477 478 struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */ 479 480 u8 reserved_220[0x1000 - 0x220]; /* (0x0220:0x0FFF) Reserved */ 481 482 u32 AHBSCTR; /* (0x1000) AHBSCTR */ 483 u32 AHBMCTR; /* (0x1004) AHBMCTR */ 484 u32 AHBBINT; /* (0x1008) AHBBINT */ 485 u32 AHBBINTEN; /* (0x100C) AHBBINTEN */ 486 u32 EPCTR; /* (0x1010) EPCTR */ 487 u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */ 488 489 u8 reserved_1018[0x20 - 0x18]; /* (0x1018:0x101F) Reserved */ 490 491 u32 USBSSVER; /* (0x1020) USBSSVER */ 492 u32 USBSSCONF; /* (0x1024) USBSSCONF */ 493 494 u8 reserved_1028[0x110 - 0x28]; /* (0x1028:0x110F) Reserved */ 495 496 struct ep_dcr EP_DCR[REG_EP_NUM]; /* */ 497 498 u8 reserved_1200[0x1000 - 0x200]; /* Reserved */ 499 } __aligned(32); 500 501 #define EP0_PACKETSIZE 64 502 #define EP_PACKETSIZE 1024 503 504 /* EPN RAM SIZE */ 505 #define D_RAM_SIZE_CTRL 64 506 507 /* EPN Bulk Endpoint Max Packet Size */ 508 #define D_FS_RAM_SIZE_BULK 64 509 #define D_HS_RAM_SIZE_BULK 512 510 511 struct nbu2ss_udc; 512 513 enum ep0_state { 514 EP0_IDLE, 515 EP0_IN_DATA_PHASE, 516 EP0_OUT_DATA_PHASE, 517 EP0_IN_STATUS_PHASE, 518 EP0_OUT_STATUS_PAHSE, 519 EP0_END_XFER, 520 EP0_SUSPEND, 521 EP0_STALL, 522 }; 523 524 struct nbu2ss_req { 525 struct usb_request req; 526 struct list_head queue; 527 528 u32 div_len; 529 bool dma_flag; 530 bool zero; 531 532 bool unaligned; 533 534 unsigned mapped:1; 535 }; 536 537 struct nbu2ss_ep { 538 struct usb_ep ep; 539 struct list_head queue; 540 541 struct nbu2ss_udc *udc; 542 543 const struct usb_endpoint_descriptor *desc; 544 545 u8 epnum; 546 u8 direct; 547 u8 ep_type; 548 549 unsigned wedged:1; 550 unsigned halted:1; 551 unsigned stalled:1; 552 553 u8 *virt_buf; 554 dma_addr_t phys_buf; 555 }; 556 557 struct nbu2ss_udc { 558 struct usb_gadget gadget; 559 struct usb_gadget_driver *driver; 560 struct platform_device *pdev; 561 struct device *dev; 562 spinlock_t lock; /* Protects nbu2ss_udc structure fields */ 563 struct completion *pdone; 564 565 enum ep0_state ep0state; 566 enum usb_device_state devstate; 567 struct usb_ctrlrequest ctrl; 568 struct nbu2ss_req ep0_req; 569 u8 ep0_buf[EP0_PACKETSIZE]; 570 571 struct nbu2ss_ep ep[NUM_ENDPOINTS]; 572 573 unsigned softconnect:1; 574 unsigned vbus_active:1; 575 unsigned linux_suspended:1; 576 unsigned linux_resume:1; 577 unsigned usb_suspended:1; 578 unsigned remote_wakeup:1; 579 unsigned udc_enabled:1; 580 581 unsigned int mA; 582 583 u32 curr_config; /* Current Configuration Number */ 584 585 struct fc_regs *p_regs; 586 }; 587 588 /* USB register access structure */ 589 union usb_reg_access { 590 struct { 591 unsigned char DATA[4]; 592 } byte; 593 unsigned int dw; 594 }; 595 596 /*-------------------------------------------------------------------------*/ 597 598 #endif /* _LINUX_EMXX_H */ 599