1 /*
2  *  drivers/usb/gadget/emxx_udc.c
3  *     EMXX FCD (Function Controller Driver) for USB.
4  *
5  *  Copyright (C) 2010 Renesas Electronics Corporation
6  *
7  *  This program is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License version 2
9  *  as published by the Free Software Foundation.
10  *
11  *  This program is distributed in the hope that it will be useful,
12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  *  GNU General Public License for more details.
15  */
16 
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/ioport.h>
22 #include <linux/slab.h>
23 #include <linux/errno.h>
24 #include <linux/list.h>
25 #include <linux/interrupt.h>
26 #include <linux/proc_fs.h>
27 #include <linux/clk.h>
28 #include <linux/ctype.h>
29 #include <linux/string.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/device.h>
33 
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 
37 #include <linux/irq.h>
38 #include <linux/gpio.h>
39 
40 #include "emxx_udc.h"
41 
42 #define	DMA_ADDR_INVALID	(~(dma_addr_t)0)
43 
44 static const char	driver_name[] = "emxx_udc";
45 
46 /*===========================================================================*/
47 /* Prototype */
48 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *);
49 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *);
50 /*static void _nbu2ss_ep0_disable(struct nbu2ss_udc *);*/
51 static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int);
52 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode);
53 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs);
54 
55 static int _nbu2ss_pullup(struct nbu2ss_udc *, int);
56 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *);
57 
58 /*===========================================================================*/
59 /* Macro */
60 #define	_nbu2ss_zero_len_pkt(udc, epnum)	\
61 	_nbu2ss_ep_in_end(udc, epnum, 0, 0)
62 
63 /*===========================================================================*/
64 /* Global */
65 struct nbu2ss_udc udc_controller;
66 
67 /*-------------------------------------------------------------------------*/
68 /* Read */
69 static inline u32 _nbu2ss_readl(void *address)
70 {
71 	return __raw_readl(address);
72 }
73 
74 /*-------------------------------------------------------------------------*/
75 /* Write */
76 static inline void _nbu2ss_writel(void *address, u32 udata)
77 {
78 	__raw_writel(udata, address);
79 }
80 
81 /*-------------------------------------------------------------------------*/
82 /* Set Bit */
83 static inline void _nbu2ss_bitset(void *address, u32 udata)
84 {
85 	u32	reg_dt = __raw_readl(address) | (udata);
86 
87 	__raw_writel(reg_dt, address);
88 }
89 
90 /*-------------------------------------------------------------------------*/
91 /* Clear Bit */
92 static inline void _nbu2ss_bitclr(void *address, u32 udata)
93 {
94 	u32	reg_dt = __raw_readl(address) & ~(udata);
95 
96 	__raw_writel(reg_dt, address);
97 }
98 
99 #ifdef UDC_DEBUG_DUMP
100 /*-------------------------------------------------------------------------*/
101 static void _nbu2ss_dump_register(struct nbu2ss_udc *udc)
102 {
103 	int		i;
104 	u32 reg_data;
105 
106 	pr_info("=== %s()\n", __func__);
107 
108 	if (!udc) {
109 		pr_err("%s udc == NULL\n", __func__);
110 		return;
111 	}
112 
113 	spin_unlock(&udc->lock);
114 
115 	dev_dbg(&udc->dev, "\n-USB REG-\n");
116 	for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) {
117 		reg_data =   _nbu2ss_readl(
118 			(u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i));
119 		dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data);
120 
121 		reg_data =  _nbu2ss_readl(
122 			(u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 4));
123 		dev_dbg(&udc->dev, " %08x", (int)reg_data);
124 
125 		reg_data =  _nbu2ss_readl(
126 			(u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 8));
127 		dev_dbg(&udc->dev, " %08x", (int)reg_data);
128 
129 		reg_data =  _nbu2ss_readl(
130 			(u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 12));
131 		dev_dbg(&udc->dev, " %08x\n", (int)reg_data);
132 
133 	}
134 
135 	spin_lock(&udc->lock);
136 }
137 #endif /* UDC_DEBUG_DUMP */
138 
139 /*-------------------------------------------------------------------------*/
140 /* Endpoint 0 Callback (Complete) */
141 static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req)
142 {
143 	u8		recipient;
144 	u16		selector;
145 	u32		test_mode;
146 	struct usb_ctrlrequest	*p_ctrl;
147 	struct nbu2ss_udc *udc;
148 
149 	if ((!_ep) || (!_req))
150 		return;
151 
152 	udc = (struct nbu2ss_udc *)_req->context;
153 	p_ctrl = &udc->ctrl;
154 	if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
155 
156 		if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) {
157 			/*-------------------------------------------------*/
158 			/* SET_FEATURE */
159 			recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK);
160 			selector  = p_ctrl->wValue;
161 			if ((recipient == USB_RECIP_DEVICE) &&
162 			    (selector == USB_DEVICE_TEST_MODE)) {
163 				test_mode = (u32)(p_ctrl->wIndex >> 8);
164 				_nbu2ss_set_test_mode(udc, test_mode);
165 			}
166 		}
167 	}
168 }
169 
170 /*-------------------------------------------------------------------------*/
171 /* Initialization usb_request */
172 static void _nbu2ss_create_ep0_packet(
173 	struct nbu2ss_udc *udc,
174 	void *p_buf,
175 	unsigned length
176 )
177 {
178 	udc->ep0_req.req.buf		= p_buf;
179 	udc->ep0_req.req.length		= length;
180 	udc->ep0_req.req.dma		= 0;
181 	udc->ep0_req.req.zero		= TRUE;
182 	udc->ep0_req.req.complete	= _nbu2ss_ep0_complete;
183 	udc->ep0_req.req.status		= -EINPROGRESS;
184 	udc->ep0_req.req.context	= udc;
185 	udc->ep0_req.req.actual		= 0;
186 }
187 
188 /*-------------------------------------------------------------------------*/
189 /* Acquisition of the first address of RAM(FIFO) */
190 static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc)
191 {
192 	u32		num, buf_type;
193 	u32		data, last_ram_adr, use_ram_size;
194 
195 	struct ep_regs *p_ep_regs;
196 
197 	last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2;
198 	use_ram_size = 0;
199 
200 	for (num = 0; num < NUM_ENDPOINTS - 1; num++) {
201 		p_ep_regs = &udc->p_regs->EP_REGS[num];
202 		data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS);
203 		buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPn_BUF_TYPE;
204 		if (buf_type == 0) {
205 			/* Single Buffer */
206 			use_ram_size += (data & EPn_MPKT) / sizeof(u32);
207 		} else {
208 			/* Double Buffer */
209 			use_ram_size += ((data & EPn_MPKT) / sizeof(u32)) * 2;
210 		}
211 
212 		if ((data >> 16) > last_ram_adr)
213 			last_ram_adr = data >> 16;
214 	}
215 
216 	return last_ram_adr + use_ram_size;
217 }
218 
219 /*-------------------------------------------------------------------------*/
220 /* Construction of Endpoint */
221 static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
222 {
223 	u32		num;
224 	u32		data;
225 	u32		begin_adrs;
226 
227 	if (ep->epnum == 0)
228 		return	-EINVAL;
229 
230 	num = ep->epnum - 1;
231 
232 	/*-------------------------------------------------------------*/
233 	/* RAM Transfer Address */
234 	begin_adrs = _nbu2ss_get_begin_ram_address(udc);
235 	data = (begin_adrs << 16) | ep->ep.maxpacket;
236 	_nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data);
237 
238 	/*-------------------------------------------------------------*/
239 	/* Interrupt Enable */
240 	data = 1 << (ep->epnum + 8);
241 	_nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data);
242 
243 	/*-------------------------------------------------------------*/
244 	/* Endpoint Type(Mode) */
245 	/*   Bulk, Interrupt, ISO */
246 	switch (ep->ep_type) {
247 	case USB_ENDPOINT_XFER_BULK:
248 		data = EPn_BULK;
249 		break;
250 
251 	case USB_ENDPOINT_XFER_INT:
252 		data = EPn_BUF_SINGLE | EPn_INTERRUPT;
253 		break;
254 
255 	case USB_ENDPOINT_XFER_ISOC:
256 		data = EPn_ISO;
257 		break;
258 
259 	default:
260 		data = 0;
261 		break;
262 	}
263 
264 	_nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
265 	_nbu2ss_endpoint_toggle_reset(udc, (ep->epnum|ep->direct));
266 
267 	if (ep->direct == USB_DIR_OUT) {
268 		/*---------------------------------------------------------*/
269 		/* OUT */
270 		data = EPn_EN | EPn_BCLR | EPn_DIR0;
271 		_nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
272 
273 		data = EPn_ONAK | EPn_OSTL_EN | EPn_OSTL;
274 		_nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
275 
276 		data = EPn_OUT_EN | EPn_OUT_END_EN;
277 		_nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
278 	} else {
279 		/*---------------------------------------------------------*/
280 		/* IN */
281 		data = EPn_EN | EPn_BCLR | EPn_AUTO;
282 		_nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
283 
284 		data = EPn_ISTL;
285 		_nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
286 
287 		data = EPn_IN_EN | EPn_IN_END_EN;
288 		_nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
289 	}
290 
291 	return 0;
292 }
293 
294 /*-------------------------------------------------------------------------*/
295 /* Release of Endpoint */
296 static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
297 {
298 	u32		num;
299 	u32		data;
300 
301 	if ((ep->epnum == 0) || (udc->vbus_active == 0))
302 		return	-EINVAL;
303 
304 	num = ep->epnum - 1;
305 
306 	/*-------------------------------------------------------------*/
307 	/* RAM Transfer Address */
308 	_nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0);
309 
310 	/*-------------------------------------------------------------*/
311 	/* Interrupt Disable */
312 	data = 1 << (ep->epnum + 8);
313 	_nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data);
314 
315 	if (ep->direct == USB_DIR_OUT) {
316 		/*---------------------------------------------------------*/
317 		/* OUT */
318 		data = EPn_ONAK | EPn_BCLR;
319 		_nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
320 
321 		data = EPn_EN | EPn_DIR0;
322 		_nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
323 
324 		data = EPn_OUT_EN | EPn_OUT_END_EN;
325 		_nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
326 	} else {
327 		/*---------------------------------------------------------*/
328 		/* IN */
329 		data = EPn_BCLR;
330 		_nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
331 
332 		data = EPn_EN | EPn_AUTO;
333 		_nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
334 
335 		data = EPn_IN_EN | EPn_IN_END_EN;
336 		_nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
337 	}
338 
339 	return 0;
340 }
341 
342 /*-------------------------------------------------------------------------*/
343 /* DMA setting (without Endpoint 0) */
344 static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
345 {
346 	u32		num;
347 	u32		data;
348 
349 	data = _nbu2ss_readl(&udc->p_regs->USBSSCONF);
350 	if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0))
351 		return;		/* Not Support DMA */
352 
353 	num = ep->epnum - 1;
354 
355 	if (ep->direct == USB_DIR_OUT) {
356 		/*---------------------------------------------------------*/
357 		/* OUT */
358 		data = ep->ep.maxpacket;
359 		_nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data);
360 
361 		/*---------------------------------------------------------*/
362 		/* Transfer Direct */
363 		data = DCR1_EPn_DIR0;
364 		_nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data);
365 
366 		/*---------------------------------------------------------*/
367 		/* DMA Mode etc. */
368 		data = EPn_STOP_MODE | EPn_STOP_SET  | EPn_DMAMODE0;
369 		_nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
370 	} else {
371 		/*---------------------------------------------------------*/
372 		/* IN */
373 		_nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPn_AUTO);
374 
375 		/*---------------------------------------------------------*/
376 		/* DMA Mode etc. */
377 		data = EPn_BURST_SET | EPn_DMAMODE0;
378 		_nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
379 	}
380 }
381 
382 /*-------------------------------------------------------------------------*/
383 /* DMA setting release */
384 static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
385 {
386 	u32		num;
387 	u32		data;
388 	struct fc_regs	*preg = udc->p_regs;
389 
390 	if (udc->vbus_active == 0)
391 		return;		/* VBUS OFF */
392 
393 	data = _nbu2ss_readl(&preg->USBSSCONF);
394 	if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0))
395 		return;		/* Not Support DMA */
396 
397 	num = ep->epnum - 1;
398 
399 	_nbu2ss_ep_dma_abort(udc, ep);
400 
401 	if (ep->direct == USB_DIR_OUT) {
402 		/*---------------------------------------------------------*/
403 		/* OUT */
404 		_nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0);
405 		_nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_DIR0);
406 		_nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
407 	} else {
408 		/*---------------------------------------------------------*/
409 		/* IN */
410 		_nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
411 		_nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
412 	}
413 }
414 
415 /*-------------------------------------------------------------------------*/
416 /* Abort DMA */
417 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
418 {
419 	struct fc_regs	*preg = udc->p_regs;
420 
421 	_nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPn_REQEN);
422 	mdelay(DMA_DISABLE_TIME);	/* DCR1_EPn_REQEN Clear */
423 	_nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPn_DMA_EN);
424 }
425 
426 /*-------------------------------------------------------------------------*/
427 /* Start IN Transfer */
428 static void _nbu2ss_ep_in_end(
429 	struct nbu2ss_udc *udc,
430 	u32 epnum,
431 	u32 data32,
432 	u32 length
433 )
434 {
435 	u32		data;
436 	u32		num;
437 	struct fc_regs	*preg = udc->p_regs;
438 
439 	if (length >= sizeof(u32))
440 		return;
441 
442 	if (epnum == 0) {
443 		_nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO);
444 
445 		/* Writing of 1-4 bytes */
446 		if (length)
447 			_nbu2ss_writel(&preg->EP0_WRITE, data32);
448 
449 		data = ((length << 5) & EP0_DW) | EP0_DEND;
450 		_nbu2ss_writel(&preg->EP0_CONTROL, data);
451 
452 		_nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO);
453 	} else {
454 		num = epnum - 1;
455 
456 		_nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
457 
458 		/* Writing of 1-4 bytes */
459 		if (length)
460 			_nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32);
461 
462 		data = ((((u32)length) << 5) & EPn_DW) | EPn_DEND;
463 		_nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
464 
465 		_nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO);
466 	}
467 }
468 
469 #ifdef USE_DMA
470 /*-------------------------------------------------------------------------*/
471 static void _nbu2ss_dma_map_single(
472 	struct nbu2ss_udc *udc,
473 	struct nbu2ss_ep *ep,
474 	struct nbu2ss_req *req,
475 	u8		direct
476 )
477 {
478 	if (req->req.dma == DMA_ADDR_INVALID) {
479 		if (req->unaligned)
480 			req->req.dma = ep->phys_buf;
481 		else {
482 			req->req.dma = dma_map_single(
483 				udc->gadget.dev.parent,
484 				req->req.buf,
485 				req->req.length,
486 				(direct == USB_DIR_IN)
487 				? DMA_TO_DEVICE : DMA_FROM_DEVICE);
488 		}
489 		req->mapped = 1;
490 	} else {
491 		if (!req->unaligned)
492 			dma_sync_single_for_device(
493 				udc->gadget.dev.parent,
494 				req->req.dma,
495 				req->req.length,
496 				(direct == USB_DIR_IN)
497 				? DMA_TO_DEVICE : DMA_FROM_DEVICE);
498 
499 		req->mapped = 0;
500 	}
501 }
502 
503 /*-------------------------------------------------------------------------*/
504 static void _nbu2ss_dma_unmap_single(
505 	struct nbu2ss_udc *udc,
506 	struct nbu2ss_ep *ep,
507 	struct nbu2ss_req *req,
508 	u8		direct
509 )
510 {
511 	u8		data[4];
512 	u8		*p;
513 	u32		count = 0;
514 
515 	if (direct == USB_DIR_OUT) {
516 		count = req->req.actual % 4;
517 		if (count) {
518 			p = req->req.buf;
519 			p += (req->req.actual - count);
520 			memcpy(data, p, count);
521 		}
522 	}
523 
524 	if (req->mapped) {
525 		if (req->unaligned) {
526 			if (direct == USB_DIR_OUT)
527 				memcpy(req->req.buf, ep->virt_buf,
528 				       req->req.actual & 0xfffffffc);
529 		} else
530 			dma_unmap_single(udc->gadget.dev.parent,
531 					 req->req.dma, req->req.length,
532 				(direct == USB_DIR_IN)
533 				? DMA_TO_DEVICE
534 				: DMA_FROM_DEVICE);
535 		req->req.dma = DMA_ADDR_INVALID;
536 		req->mapped = 0;
537 	} else {
538 		if (!req->unaligned)
539 			dma_sync_single_for_cpu(udc->gadget.dev.parent,
540 						req->req.dma, req->req.length,
541 				(direct == USB_DIR_IN)
542 				? DMA_TO_DEVICE
543 				: DMA_FROM_DEVICE);
544 	}
545 
546 	if (count) {
547 		p = req->req.buf;
548 		p += (req->req.actual - count);
549 		memcpy(p, data, count);
550 	}
551 }
552 #endif
553 
554 /*-------------------------------------------------------------------------*/
555 /* Endpoint 0 OUT Transfer (PIO) */
556 static int EP0_out_PIO(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
557 {
558 	u32		i;
559 	int		nret   = 0;
560 	u32		iWordLength = 0;
561 	union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf;
562 
563 	/*------------------------------------------------------------*/
564 	/* Read Length */
565 	iWordLength = length / sizeof(u32);
566 
567 	/*------------------------------------------------------------*/
568 	/* PIO Read */
569 	if (iWordLength) {
570 		for (i = 0; i < iWordLength; i++) {
571 			pBuf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
572 			pBuf32++;
573 		}
574 		nret = iWordLength * sizeof(u32);
575 	}
576 
577 	return nret;
578 }
579 
580 /*-------------------------------------------------------------------------*/
581 /* Endpoint 0 OUT Transfer (PIO, OverBytes) */
582 static int EP0_out_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
583 {
584 	u32		i;
585 	u32		iReadSize = 0;
586 	union usb_reg_access  Temp32;
587 	union usb_reg_access  *pBuf32 = (union usb_reg_access *)pBuf;
588 
589 	if ((length > 0) && (length < sizeof(u32))) {
590 		Temp32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
591 		for (i = 0 ; i < length ; i++)
592 			pBuf32->byte.DATA[i] = Temp32.byte.DATA[i];
593 		iReadSize += length;
594 	}
595 
596 	return iReadSize;
597 }
598 
599 /*-------------------------------------------------------------------------*/
600 /* Endpoint 0 IN Transfer (PIO) */
601 static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *pBuf, u32 length)
602 {
603 	u32		i;
604 	u32		iMaxLength   = EP0_PACKETSIZE;
605 	u32		iWordLength  = 0;
606 	u32		iWriteLength = 0;
607 	union usb_reg_access  *pBuf32 = (union usb_reg_access *)pBuf;
608 
609 	/*------------------------------------------------------------*/
610 	/* Transfer Length */
611 	if (iMaxLength < length)
612 		iWordLength = iMaxLength / sizeof(u32);
613 	else
614 		iWordLength = length / sizeof(u32);
615 
616 	/*------------------------------------------------------------*/
617 	/* PIO */
618 	for (i = 0; i < iWordLength; i++) {
619 		_nbu2ss_writel(&udc->p_regs->EP0_WRITE, pBuf32->dw);
620 		pBuf32++;
621 		iWriteLength += sizeof(u32);
622 	}
623 
624 	return iWriteLength;
625 }
626 
627 /*-------------------------------------------------------------------------*/
628 /* Endpoint 0 IN Transfer (PIO, OverBytes) */
629 static int EP0_in_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 iRemainSize)
630 {
631 	u32		i;
632 	union usb_reg_access  Temp32;
633 	union usb_reg_access  *pBuf32 = (union usb_reg_access *)pBuf;
634 
635 	if ((iRemainSize > 0) && (iRemainSize < sizeof(u32))) {
636 		for (i = 0 ; i < iRemainSize ; i++)
637 			Temp32.byte.DATA[i] = pBuf32->byte.DATA[i];
638 		_nbu2ss_ep_in_end(udc, 0, Temp32.dw, iRemainSize);
639 
640 		return iRemainSize;
641 	}
642 
643 	return 0;
644 }
645 
646 /*-------------------------------------------------------------------------*/
647 /* Transfer NULL Packet (Epndoint 0) */
648 static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag)
649 {
650 	u32		data;
651 
652 	data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
653 	data &= ~(u32)EP0_INAK;
654 
655 	if (pid_flag)
656 		data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND);
657 	else
658 		data |= (EP0_INAK_EN | EP0_DEND);
659 
660 	_nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
661 
662 	return 0;
663 }
664 
665 /*-------------------------------------------------------------------------*/
666 /* Receive NULL Packet (Endpoint 0) */
667 static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag)
668 {
669 	u32		data;
670 
671 	data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
672 	data &= ~(u32)EP0_ONAK;
673 
674 	if (pid_flag)
675 		data |= EP0_PIDCLR;
676 
677 	_nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
678 
679 	return 0;
680 }
681 
682 /*-------------------------------------------------------------------------*/
683 static int _nbu2ss_ep0_in_transfer(
684 	struct nbu2ss_udc *udc,
685 	struct nbu2ss_req *req
686 )
687 {
688 	u8		*pBuffer;			/* IN Data Buffer */
689 	u32		data;
690 	u32		iRemainSize = 0;
691 	int		result = 0;
692 
693 	/*-------------------------------------------------------------*/
694 	/* End confirmation */
695 	if (req->req.actual == req->req.length) {
696 		if ((req->req.actual % EP0_PACKETSIZE) == 0) {
697 			if (req->zero) {
698 				req->zero = false;
699 				EP0_send_NULL(udc, FALSE);
700 				return 1;
701 			}
702 		}
703 
704 		return 0;		/* Transfer End */
705 	}
706 
707 	/*-------------------------------------------------------------*/
708 	/* NAK release */
709 	data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
710 	data |= EP0_INAK_EN;
711 	data &= ~(u32)EP0_INAK;
712 	_nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
713 
714 	iRemainSize = req->req.length - req->req.actual;
715 	pBuffer = (u8 *)req->req.buf;
716 	pBuffer += req->req.actual;
717 
718 	/*-------------------------------------------------------------*/
719 	/* Data transfer */
720 	result = EP0_in_PIO(udc, pBuffer, iRemainSize);
721 
722 	req->div_len = result;
723 	iRemainSize -= result;
724 
725 	if (iRemainSize == 0) {
726 		EP0_send_NULL(udc, FALSE);
727 		return result;
728 	}
729 
730 	if ((iRemainSize < sizeof(u32)) && (result != EP0_PACKETSIZE)) {
731 		pBuffer += result;
732 		result += EP0_in_OverBytes(udc, pBuffer, iRemainSize);
733 		req->div_len = result;
734 	}
735 
736 	return result;
737 }
738 
739 /*-------------------------------------------------------------------------*/
740 static int _nbu2ss_ep0_out_transfer(
741 	struct nbu2ss_udc *udc,
742 	struct nbu2ss_req *req
743 )
744 {
745 	u8		*pBuffer;
746 	u32		iRemainSize;
747 	u32		iRecvLength;
748 	int		result = 0;
749 	int		fRcvZero;
750 
751 	/*-------------------------------------------------------------*/
752 	/* Receive data confirmation */
753 	iRecvLength = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA;
754 	if (iRecvLength != 0) {
755 
756 		fRcvZero = 0;
757 
758 		iRemainSize = req->req.length - req->req.actual;
759 		pBuffer = (u8 *)req->req.buf;
760 		pBuffer += req->req.actual;
761 
762 		result = EP0_out_PIO(udc, pBuffer
763 					, min(iRemainSize, iRecvLength));
764 		if (result < 0)
765 			return result;
766 
767 		req->req.actual += result;
768 		iRecvLength -= result;
769 
770 		if ((iRecvLength > 0) && (iRecvLength < sizeof(u32))) {
771 			pBuffer += result;
772 			iRemainSize -= result;
773 
774 			result = EP0_out_OverBytes(udc, pBuffer
775 					, min(iRemainSize, iRecvLength));
776 			req->req.actual += result;
777 		}
778 	} else {
779 		fRcvZero = 1;
780 	}
781 
782 	/*-------------------------------------------------------------*/
783 	/* End confirmation */
784 	if (req->req.actual == req->req.length) {
785 		if ((req->req.actual % EP0_PACKETSIZE) == 0) {
786 			if (req->zero) {
787 				req->zero = false;
788 				EP0_receive_NULL(udc, FALSE);
789 				return 1;
790 			}
791 		}
792 
793 		return 0;		/* Transfer End */
794 	}
795 
796 	if ((req->req.actual % EP0_PACKETSIZE) != 0)
797 		return 0;		/* Short Packet Transfer End */
798 
799 	if (req->req.actual > req->req.length) {
800 		dev_err(udc->dev, " *** Overrun Error\n");
801 		return -EOVERFLOW;
802 	}
803 
804 	if (fRcvZero != 0) {
805 		iRemainSize = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
806 		if (iRemainSize & EP0_ONAK) {
807 			/*---------------------------------------------------*/
808 			/* NACK release */
809 			_nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK);
810 		}
811 		result = 1;
812 	}
813 
814 	return result;
815 }
816 
817 /*-------------------------------------------------------------------------*/
818 static int _nbu2ss_out_dma(
819 	struct nbu2ss_udc *udc,
820 	struct nbu2ss_req *req,
821 	u32		num,
822 	u32		length
823 )
824 {
825 	dma_addr_t	pBuffer;
826 	u32		mpkt;
827 	u32		lmpkt;
828 	u32		dmacnt;
829 	u32		burst = 1;
830 	u32		data;
831 	int		result = -EINVAL;
832 	struct fc_regs	*preg = udc->p_regs;
833 
834 	if (req->dma_flag)
835 		return 1;		/* DMA is forwarded */
836 
837 	req->dma_flag = TRUE;
838 	pBuffer = req->req.dma;
839 	pBuffer += req->req.actual;
840 
841 	/* DMA Address */
842 	_nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer);
843 
844 	/* Number of transfer packets */
845 	mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT;
846 	dmacnt = length / mpkt;
847 	lmpkt = (length % mpkt) & ~(u32)0x03;
848 
849 	if (dmacnt > DMA_MAX_COUNT) {
850 		dmacnt = DMA_MAX_COUNT;
851 		lmpkt = 0;
852 	} else if (lmpkt != 0) {
853 		if (dmacnt == 0)
854 			burst = 0;	/* Burst OFF */
855 		dmacnt++;
856 	}
857 
858 	data = mpkt | (lmpkt << 16);
859 	_nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
860 
861 	data = ((dmacnt & 0xff) << 16) | DCR1_EPn_DIR0 | DCR1_EPn_REQEN;
862 	_nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
863 
864 	if (burst == 0) {
865 		_nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0);
866 		_nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET);
867 	} else {
868 		_nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT
869 				, (dmacnt << 16));
870 		_nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET);
871 	}
872 	_nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN);
873 
874 	result = length & ~(u32)0x03;
875 	req->div_len = result;
876 
877 	return result;
878 }
879 
880 /*-------------------------------------------------------------------------*/
881 static int _nbu2ss_epn_out_pio(
882 	struct nbu2ss_udc *udc,
883 	struct nbu2ss_ep *ep,
884 	struct nbu2ss_req *req,
885 	u32		length
886 )
887 {
888 	u8		*pBuffer;
889 	u32		i;
890 	u32		data;
891 	u32		iWordLength;
892 	union usb_reg_access	Temp32;
893 	union usb_reg_access	*pBuf32;
894 	int		result = 0;
895 	struct fc_regs	*preg = udc->p_regs;
896 
897 	if (req->dma_flag)
898 		return 1;		/* DMA is forwarded */
899 
900 	if (length == 0)
901 		return 0;
902 
903 	pBuffer = (u8 *)req->req.buf;
904 	pBuf32 = (union usb_reg_access *)(pBuffer + req->req.actual);
905 
906 	iWordLength = length / sizeof(u32);
907 	if (iWordLength > 0) {
908 		/*---------------------------------------------------------*/
909 		/* Copy of every four bytes */
910 		for (i = 0; i < iWordLength; i++) {
911 			pBuf32->dw =
912 			_nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
913 			pBuf32++;
914 		}
915 		result = iWordLength * sizeof(u32);
916 	}
917 
918 	data = length - result;
919 	if (data > 0) {
920 		/*---------------------------------------------------------*/
921 		/* Copy of fraction byte */
922 		Temp32.dw = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
923 		for (i = 0 ; i < data ; i++)
924 			pBuf32->byte.DATA[i] = Temp32.byte.DATA[i];
925 		result += data;
926 	}
927 
928 	req->req.actual += result;
929 
930 	if ((req->req.actual == req->req.length)
931 			|| ((req->req.actual % ep->ep.maxpacket) != 0)) {
932 
933 		result = 0;
934 	}
935 
936 	return result;
937 }
938 
939 /*-------------------------------------------------------------------------*/
940 static int _nbu2ss_epn_out_data(
941 	struct nbu2ss_udc *udc,
942 	struct nbu2ss_ep *ep,
943 	struct nbu2ss_req *req,
944 	u32		data_size
945 )
946 {
947 	u32		num;
948 	u32		iBufSize;
949 	int		nret = 1;
950 
951 	if (ep->epnum == 0)
952 		return -EINVAL;
953 
954 	num = ep->epnum - 1;
955 
956 	iBufSize = min((req->req.length - req->req.actual), data_size);
957 
958 	if ((ep->ep_type != USB_ENDPOINT_XFER_INT)
959 		&& (req->req.dma != 0)
960 		&& (iBufSize  >= sizeof(u32))) {
961 		nret = _nbu2ss_out_dma(udc, req, num, iBufSize);
962 	} else {
963 		iBufSize = min_t(u32, iBufSize, ep->ep.maxpacket);
964 		nret = _nbu2ss_epn_out_pio(udc, ep, req, iBufSize);
965 	}
966 
967 	return nret;
968 }
969 
970 /*-------------------------------------------------------------------------*/
971 static int _nbu2ss_epn_out_transfer(
972 	struct nbu2ss_udc *udc,
973 	struct nbu2ss_ep *ep,
974 	struct nbu2ss_req *req
975 )
976 {
977 	u32		num;
978 	u32		iRecvLength;
979 	int		result = 1;
980 	struct fc_regs	*preg = udc->p_regs;
981 
982 	if (ep->epnum == 0)
983 		return -EINVAL;
984 
985 	num = ep->epnum - 1;
986 
987 	/*-------------------------------------------------------------*/
988 	/* Receive Length */
989 	iRecvLength
990 		= _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPn_LDATA;
991 
992 	if (iRecvLength != 0) {
993 		result = _nbu2ss_epn_out_data(udc, ep, req, iRecvLength);
994 		if (iRecvLength < ep->ep.maxpacket) {
995 			if (iRecvLength == result) {
996 				req->req.actual += result;
997 				result = 0;
998 			}
999 		}
1000 	} else {
1001 		if ((req->req.actual == req->req.length)
1002 			|| ((req->req.actual % ep->ep.maxpacket) != 0)) {
1003 
1004 			result = 0;
1005 		}
1006 	}
1007 
1008 	if (result == 0) {
1009 		if ((req->req.actual % ep->ep.maxpacket) == 0) {
1010 			if (req->zero) {
1011 				req->zero = false;
1012 				return 1;
1013 			}
1014 		}
1015 	}
1016 
1017 	if (req->req.actual > req->req.length) {
1018 		dev_err(udc->dev, " Overrun Error\n");
1019 		dev_err(udc->dev, " actual = %d, length = %d\n",
1020 			req->req.actual, req->req.length);
1021 		result = -EOVERFLOW;
1022 	}
1023 
1024 	return result;
1025 }
1026 
1027 /*-------------------------------------------------------------------------*/
1028 static int _nbu2ss_in_dma(
1029 	struct nbu2ss_udc *udc,
1030 	struct nbu2ss_ep *ep,
1031 	struct nbu2ss_req *req,
1032 	u32		num,
1033 	u32		length
1034 )
1035 {
1036 	dma_addr_t	pBuffer;
1037 	u32		mpkt;		/* MaxPacketSize */
1038 	u32		lmpkt;		/* Last Packet Data Size */
1039 	u32		dmacnt;		/* IN Data Size */
1040 	u32		iWriteLength;
1041 	u32		data;
1042 	int		result = -EINVAL;
1043 	struct fc_regs	*preg = udc->p_regs;
1044 
1045 	if (req->dma_flag)
1046 		return 1;		/* DMA is forwarded */
1047 
1048 #ifdef USE_DMA
1049 	if (req->req.actual == 0)
1050 		_nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN);
1051 #endif
1052 	req->dma_flag = TRUE;
1053 
1054 	/* MAX Packet Size */
1055 	mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT;
1056 
1057 	if ((DMA_MAX_COUNT * mpkt) < length)
1058 		iWriteLength = DMA_MAX_COUNT * mpkt;
1059 	else
1060 		iWriteLength = length;
1061 
1062 	/*------------------------------------------------------------*/
1063 	/* Number of transmission packets */
1064 	if (mpkt < iWriteLength) {
1065 		dmacnt = iWriteLength / mpkt;
1066 		lmpkt  = (iWriteLength % mpkt) & ~(u32)0x3;
1067 		if (lmpkt != 0)
1068 			dmacnt++;
1069 		else
1070 			lmpkt = mpkt & ~(u32)0x3;
1071 
1072 	} else {
1073 		dmacnt = 1;
1074 		lmpkt  = iWriteLength & ~(u32)0x3;
1075 	}
1076 
1077 	/* Packet setting */
1078 	data = mpkt | (lmpkt << 16);
1079 	_nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
1080 
1081 	/* Address setting */
1082 	pBuffer = req->req.dma;
1083 	pBuffer += req->req.actual;
1084 	_nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer);
1085 
1086 	/* Packet and DMA setting */
1087 	data = ((dmacnt & 0xff) << 16) | DCR1_EPn_REQEN;
1088 	_nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
1089 
1090 	/* Packet setting of EPC */
1091 	data = dmacnt << 16;
1092 	_nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data);
1093 
1094 	/*DMA setting of EPC */
1095 	_nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN);
1096 
1097 	result = iWriteLength & ~(u32)0x3;
1098 	req->div_len = result;
1099 
1100 	return result;
1101 }
1102 
1103 /*-------------------------------------------------------------------------*/
1104 static int _nbu2ss_epn_in_pio(
1105 	struct nbu2ss_udc *udc,
1106 	struct nbu2ss_ep *ep,
1107 	struct nbu2ss_req *req,
1108 	u32		length
1109 )
1110 {
1111 	u8		*pBuffer;
1112 	u32		i;
1113 	u32		data;
1114 	u32		iWordLength;
1115 	union usb_reg_access	Temp32;
1116 	union usb_reg_access	*pBuf32 = NULL;
1117 	int		result = 0;
1118 	struct fc_regs	*preg = udc->p_regs;
1119 
1120 	if (req->dma_flag)
1121 		return 1;		/* DMA is forwarded */
1122 
1123 	if (length > 0) {
1124 		pBuffer = (u8 *)req->req.buf;
1125 		pBuf32 = (union usb_reg_access *)(pBuffer + req->req.actual);
1126 
1127 		iWordLength = length / sizeof(u32);
1128 		if (iWordLength > 0) {
1129 			for (i = 0; i < iWordLength; i++) {
1130 				_nbu2ss_writel(
1131 					&preg->EP_REGS[ep->epnum - 1].EP_WRITE
1132 					, pBuf32->dw
1133 				);
1134 
1135 				pBuf32++;
1136 			}
1137 			result = iWordLength * sizeof(u32);
1138 		}
1139 	}
1140 
1141 	if (result != ep->ep.maxpacket) {
1142 		data = length - result;
1143 		Temp32.dw = 0;
1144 		for (i = 0 ; i < data ; i++)
1145 			Temp32.byte.DATA[i] = pBuf32->byte.DATA[i];
1146 
1147 		_nbu2ss_ep_in_end(udc, ep->epnum, Temp32.dw, data);
1148 		result += data;
1149 	}
1150 
1151 	req->div_len = result;
1152 
1153 	return result;
1154 }
1155 
1156 /*-------------------------------------------------------------------------*/
1157 static int _nbu2ss_epn_in_data(
1158 	struct nbu2ss_udc *udc,
1159 	struct nbu2ss_ep *ep,
1160 	struct nbu2ss_req *req,
1161 	u32		data_size
1162 )
1163 {
1164 	u32		num;
1165 	int		nret = 1;
1166 
1167 	if (ep->epnum == 0)
1168 		return -EINVAL;
1169 
1170 	num = ep->epnum - 1;
1171 
1172 	if ((ep->ep_type != USB_ENDPOINT_XFER_INT)
1173 		&& (req->req.dma != 0)
1174 		&& (data_size >= sizeof(u32))) {
1175 		nret = _nbu2ss_in_dma(udc, ep, req, num, data_size);
1176 	} else {
1177 		data_size = min_t(u32, data_size, ep->ep.maxpacket);
1178 		nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size);
1179 	}
1180 
1181 	return nret;
1182 }
1183 
1184 /*-------------------------------------------------------------------------*/
1185 static int _nbu2ss_epn_in_transfer(
1186 	struct nbu2ss_udc *udc,
1187 	struct nbu2ss_ep *ep,
1188 	struct nbu2ss_req *req
1189 )
1190 {
1191 	u32		num;
1192 	u32		iBufSize;
1193 	int		result = 0;
1194 	u32		status;
1195 
1196 	if (ep->epnum == 0)
1197 		return -EINVAL;
1198 
1199 	num = ep->epnum - 1;
1200 
1201 	status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
1202 
1203 	/*-------------------------------------------------------------*/
1204 	/* State confirmation of FIFO */
1205 	if (req->req.actual == 0) {
1206 		if ((status & EPn_IN_EMPTY) == 0)
1207 			return 1;	/* Not Empty */
1208 
1209 	} else {
1210 		if ((status & EPn_IN_FULL) != 0)
1211 			return 1;	/* Not Empty */
1212 	}
1213 
1214 	/*-------------------------------------------------------------*/
1215 	/* Start transfer */
1216 	iBufSize = req->req.length - req->req.actual;
1217 	if (iBufSize > 0)
1218 		result = _nbu2ss_epn_in_data(udc, ep, req, iBufSize);
1219 	else if (req->req.length == 0)
1220 		_nbu2ss_zero_len_pkt(udc, ep->epnum);
1221 
1222 	return result;
1223 }
1224 
1225 /*-------------------------------------------------------------------------*/
1226 static int _nbu2ss_start_transfer(
1227 	struct nbu2ss_udc *udc,
1228 	struct nbu2ss_ep *ep,
1229 	struct nbu2ss_req *req,
1230 	bool	bflag)
1231 {
1232 	int		nret = -EINVAL;
1233 
1234 	req->dma_flag = FALSE;
1235 	req->div_len = 0;
1236 
1237 	if (req->req.length == 0)
1238 		req->zero = false;
1239 	else {
1240 		if ((req->req.length % ep->ep.maxpacket) == 0)
1241 			req->zero = req->req.zero;
1242 		else
1243 			req->zero = false;
1244 	}
1245 
1246 	if (ep->epnum == 0) {
1247 		/* EP0 */
1248 		switch (udc->ep0state) {
1249 		case EP0_IN_DATA_PHASE:
1250 			nret = _nbu2ss_ep0_in_transfer(udc, req);
1251 			break;
1252 
1253 		case EP0_OUT_DATA_PHASE:
1254 			nret = _nbu2ss_ep0_out_transfer(udc, req);
1255 			break;
1256 
1257 		case EP0_IN_STATUS_PHASE:
1258 			nret = EP0_send_NULL(udc, TRUE);
1259 			break;
1260 
1261 		default:
1262 			break;
1263 		}
1264 
1265 	} else {
1266 		/* EPn */
1267 		if (ep->direct == USB_DIR_OUT) {
1268 			/* OUT */
1269 			if (!bflag)
1270 				nret = _nbu2ss_epn_out_transfer(udc, ep, req);
1271 		} else {
1272 			/* IN */
1273 			nret = _nbu2ss_epn_in_transfer(udc, ep, req);
1274 		}
1275 	}
1276 
1277 	return nret;
1278 }
1279 
1280 /*-------------------------------------------------------------------------*/
1281 static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep)
1282 {
1283 	u32		length;
1284 	bool	bflag = FALSE;
1285 	struct nbu2ss_req *req;
1286 
1287 	req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1288 	if (!req)
1289 		return;
1290 
1291 	if (ep->epnum > 0) {
1292 		length = _nbu2ss_readl(
1293 			&ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT);
1294 
1295 		length &= EPn_LDATA;
1296 		if (length < ep->ep.maxpacket)
1297 			bflag = TRUE;
1298 	}
1299 
1300 	_nbu2ss_start_transfer(ep->udc, ep, req, bflag);
1301 }
1302 
1303 /*-------------------------------------------------------------------------*/
1304 /*	Endpoint Toggle Reset */
1305 static void _nbu2ss_endpoint_toggle_reset(
1306 	struct nbu2ss_udc *udc,
1307 	u8 ep_adrs)
1308 {
1309 	u8		num;
1310 	u32		data;
1311 
1312 	if ((ep_adrs == 0) || (ep_adrs == 0x80))
1313 		return;
1314 
1315 	num = (ep_adrs & 0x7F) - 1;
1316 
1317 	if (ep_adrs & USB_DIR_IN)
1318 		data = EPn_IPIDCLR;
1319 	else
1320 		data = EPn_BCLR | EPn_OPIDCLR;
1321 
1322 	_nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
1323 }
1324 
1325 /*-------------------------------------------------------------------------*/
1326 /*	Endpoint STALL set */
1327 static void _nbu2ss_set_endpoint_stall(
1328 	struct nbu2ss_udc *udc,
1329 	u8 ep_adrs,
1330 	bool bstall)
1331 {
1332 	u8		num, epnum;
1333 	u32		data;
1334 	struct nbu2ss_ep *ep;
1335 	struct fc_regs	*preg = udc->p_regs;
1336 
1337 	if ((ep_adrs == 0) || (ep_adrs == 0x80)) {
1338 		if (bstall) {
1339 			/* Set STALL */
1340 			_nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL);
1341 		} else {
1342 			/* Clear STALL */
1343 			_nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL);
1344 		}
1345 	} else {
1346 		epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK;
1347 		num = epnum - 1;
1348 		ep = &udc->ep[epnum];
1349 
1350 		if (bstall) {
1351 			/* Set STALL */
1352 			ep->halted = TRUE;
1353 
1354 			if (ep_adrs & USB_DIR_IN)
1355 				data = EPn_BCLR | EPn_ISTL;
1356 			else
1357 				data = EPn_OSTL_EN | EPn_OSTL;
1358 
1359 			_nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
1360 		} else {
1361 			/* Clear STALL */
1362 			ep->stalled = FALSE;
1363 			if (ep_adrs & USB_DIR_IN) {
1364 				_nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL
1365 						, EPn_ISTL);
1366 			} else {
1367 				data =
1368 				_nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL);
1369 
1370 				data &= ~EPn_OSTL;
1371 				data |= EPn_OSTL_EN;
1372 
1373 				_nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL
1374 						, data);
1375 			}
1376 
1377 			ep->stalled = FALSE;
1378 			if (ep->halted) {
1379 				ep->halted = FALSE;
1380 				_nbu2ss_restert_transfer(ep);
1381 			}
1382 		}
1383 	}
1384 }
1385 
1386 /*-------------------------------------------------------------------------*/
1387 /* Device Descriptor */
1388 static struct usb_device_descriptor device_desc = {
1389 	.bLength              = sizeof(device_desc),
1390 	.bDescriptorType      = USB_DT_DEVICE,
1391 	.bcdUSB               = cpu_to_le16(0x0200),
1392 	.bDeviceClass         = USB_CLASS_VENDOR_SPEC,
1393 	.bDeviceSubClass      = 0x00,
1394 	.bDeviceProtocol      = 0x00,
1395 	.bMaxPacketSize0      = 64,
1396 	.idVendor             = cpu_to_le16(0x0409),
1397 	.idProduct            = cpu_to_le16(0xfff0),
1398 	.bcdDevice            = 0xffff,
1399 	.iManufacturer        = 0x00,
1400 	.iProduct             = 0x00,
1401 	.iSerialNumber        = 0x00,
1402 	.bNumConfigurations   = 0x01,
1403 };
1404 
1405 /*-------------------------------------------------------------------------*/
1406 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode)
1407 {
1408 	u32		data;
1409 
1410 	if (mode > MAX_TEST_MODE_NUM)
1411 		return;
1412 
1413 	dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode);
1414 
1415 	data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL);
1416 	data &= ~TEST_FORCE_ENABLE;
1417 	data |= mode << TEST_MODE_SHIFT;
1418 
1419 	_nbu2ss_writel(&udc->p_regs->USB_CONTROL, data);
1420 	_nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN);
1421 }
1422 
1423 /*-------------------------------------------------------------------------*/
1424 static int _nbu2ss_set_feature_device(
1425 	struct nbu2ss_udc *udc,
1426 	u16 selector,
1427 	u16 wIndex
1428 )
1429 {
1430 	int	result = -EOPNOTSUPP;
1431 
1432 	switch (selector) {
1433 	case USB_DEVICE_REMOTE_WAKEUP:
1434 		if (wIndex == 0x0000) {
1435 			udc->remote_wakeup = U2F_ENABLE;
1436 			result = 0;
1437 		}
1438 		break;
1439 
1440 	case USB_DEVICE_TEST_MODE:
1441 		wIndex >>= 8;
1442 		if (wIndex <= MAX_TEST_MODE_NUM)
1443 			result = 0;
1444 		break;
1445 
1446 	default:
1447 		break;
1448 	}
1449 
1450 	return result;
1451 }
1452 
1453 /*-------------------------------------------------------------------------*/
1454 static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs)
1455 {
1456 	u8		epnum;
1457 	u32		data = 0, bit_data;
1458 	struct fc_regs	*preg = udc->p_regs;
1459 
1460 	epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK;
1461 	if (epnum == 0) {
1462 		data = _nbu2ss_readl(&preg->EP0_CONTROL);
1463 		bit_data = EP0_STL;
1464 
1465 	} else {
1466 		data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL);
1467 		if ((data & EPn_EN) == 0)
1468 			return -1;
1469 
1470 		if (ep_adrs & USB_ENDPOINT_DIR_MASK)
1471 			bit_data = EPn_ISTL;
1472 		else
1473 			bit_data = EPn_OSTL;
1474 	}
1475 
1476 	if ((data & bit_data) == 0)
1477 		return 0;
1478 	return 1;
1479 }
1480 
1481 /*-------------------------------------------------------------------------*/
1482 static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset)
1483 {
1484 	u8	recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1485 	u8	direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1486 	u16	selector  = udc->ctrl.wValue;
1487 	u16	wIndex    = udc->ctrl.wIndex;
1488 	u8	ep_adrs;
1489 	int	result = -EOPNOTSUPP;
1490 
1491 	if ((udc->ctrl.wLength != 0x0000) ||
1492 	    (direction != USB_DIR_OUT)) {
1493 		return -EINVAL;
1494 	}
1495 
1496 	switch (recipient) {
1497 	case USB_RECIP_DEVICE:
1498 		if (bset)
1499 			result =
1500 			_nbu2ss_set_feature_device(udc, selector, wIndex);
1501 		break;
1502 
1503 	case USB_RECIP_ENDPOINT:
1504 		if (0x0000 == (wIndex & 0xFF70)) {
1505 			if (selector == USB_ENDPOINT_HALT) {
1506 				ep_adrs = wIndex & 0xFF;
1507 				if (!bset) {
1508 					_nbu2ss_endpoint_toggle_reset(
1509 						udc, ep_adrs);
1510 				}
1511 
1512 				_nbu2ss_set_endpoint_stall(
1513 					udc, ep_adrs, bset);
1514 
1515 				result = 0;
1516 			}
1517 		}
1518 		break;
1519 
1520 	default:
1521 		break;
1522 	}
1523 
1524 	if (result >= 0)
1525 		_nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1526 
1527 	return result;
1528 }
1529 
1530 /*-------------------------------------------------------------------------*/
1531 static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc)
1532 {
1533 	u32		data;
1534 	enum usb_device_speed speed = USB_SPEED_FULL;
1535 
1536 	data = _nbu2ss_readl(&udc->p_regs->USB_STATUS);
1537 	if (data & HIGH_SPEED)
1538 		speed = USB_SPEED_HIGH;
1539 
1540 	return speed;
1541 }
1542 
1543 /*-------------------------------------------------------------------------*/
1544 static void _nbu2ss_epn_set_stall(
1545 	struct nbu2ss_udc *udc,
1546 	struct nbu2ss_ep *ep
1547 )
1548 {
1549 	u8	ep_adrs;
1550 	u32	regdata;
1551 	int	limit_cnt = 0;
1552 
1553 	struct fc_regs	*preg = udc->p_regs;
1554 
1555 	if (ep->direct == USB_DIR_IN) {
1556 		for (limit_cnt = 0
1557 			; limit_cnt < IN_DATA_EMPTY_COUNT
1558 			; limit_cnt++) {
1559 
1560 			regdata = _nbu2ss_readl(
1561 				&preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1562 
1563 			if ((regdata & EPn_IN_DATA) == 0)
1564 				break;
1565 
1566 			mdelay(1);
1567 		}
1568 	}
1569 
1570 	ep_adrs = ep->epnum | ep->direct;
1571 	_nbu2ss_set_endpoint_stall(udc, ep_adrs, 1);
1572 }
1573 
1574 /*-------------------------------------------------------------------------*/
1575 static int std_req_get_status(struct nbu2ss_udc *udc)
1576 {
1577 	u32	length;
1578 	u16	status_data = 0;
1579 	u8	recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1580 	u8	direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1581 	u8	ep_adrs;
1582 	int	result = -EINVAL;
1583 
1584 	if ((udc->ctrl.wValue != 0x0000)
1585 		|| (direction != USB_DIR_IN)) {
1586 
1587 		return result;
1588 	}
1589 
1590 	length = min_t(u16, udc->ctrl.wLength, sizeof(status_data));
1591 
1592 	switch (recipient) {
1593 	case USB_RECIP_DEVICE:
1594 		if (udc->ctrl.wIndex == 0x0000) {
1595 			if (udc->gadget.is_selfpowered)
1596 				status_data |= (1 << USB_DEVICE_SELF_POWERED);
1597 
1598 			if (udc->remote_wakeup)
1599 				status_data |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1600 
1601 			result = 0;
1602 		}
1603 		break;
1604 
1605 	case USB_RECIP_ENDPOINT:
1606 		if (0x0000 == (udc->ctrl.wIndex & 0xFF70)) {
1607 			ep_adrs = (u8)(udc->ctrl.wIndex & 0xFF);
1608 			result = _nbu2ss_get_ep_stall(udc, ep_adrs);
1609 
1610 			if (result > 0)
1611 				status_data |= (1 << USB_ENDPOINT_HALT);
1612 		}
1613 		break;
1614 
1615 	default:
1616 		break;
1617 	}
1618 
1619 	if (result >= 0) {
1620 		memcpy(udc->ep0_buf, &status_data, length);
1621 		_nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length);
1622 		_nbu2ss_ep0_in_transfer(udc, &udc->ep0_req);
1623 
1624 	} else {
1625 		dev_err(udc->dev, " Error GET_STATUS\n");
1626 	}
1627 
1628 	return result;
1629 }
1630 
1631 /*-------------------------------------------------------------------------*/
1632 static int std_req_clear_feature(struct nbu2ss_udc *udc)
1633 {
1634 	return _nbu2ss_req_feature(udc, FALSE);
1635 }
1636 
1637 /*-------------------------------------------------------------------------*/
1638 static int std_req_set_feature(struct nbu2ss_udc *udc)
1639 {
1640 	return _nbu2ss_req_feature(udc, TRUE);
1641 }
1642 
1643 /*-------------------------------------------------------------------------*/
1644 static int std_req_set_address(struct nbu2ss_udc *udc)
1645 {
1646 	int		result = 0;
1647 	u32		wValue = udc->ctrl.wValue;
1648 
1649 	if ((udc->ctrl.bRequestType != 0x00)	||
1650 	    (udc->ctrl.wIndex != 0x0000)	||
1651 		(udc->ctrl.wLength != 0x0000)) {
1652 		return -EINVAL;
1653 	}
1654 
1655 	if (wValue != (wValue & 0x007F))
1656 		return -EINVAL;
1657 
1658 	wValue <<= USB_ADRS_SHIFT;
1659 
1660 	_nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue);
1661 	_nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1662 
1663 	return result;
1664 }
1665 
1666 /*-------------------------------------------------------------------------*/
1667 static int std_req_set_configuration(struct nbu2ss_udc *udc)
1668 {
1669 	u32 ConfigValue = (u32)(udc->ctrl.wValue & 0x00ff);
1670 
1671 	if ((udc->ctrl.wIndex != 0x0000)	||
1672 	    (udc->ctrl.wLength != 0x0000)	||
1673 		(udc->ctrl.bRequestType != 0x00)) {
1674 		return -EINVAL;
1675 	}
1676 
1677 	udc->curr_config = ConfigValue;
1678 
1679 	if (ConfigValue > 0) {
1680 		_nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF);
1681 		udc->devstate = USB_STATE_CONFIGURED;
1682 
1683 	} else {
1684 		_nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF);
1685 		udc->devstate = USB_STATE_ADDRESS;
1686 	}
1687 
1688 	return 0;
1689 }
1690 
1691 /*-------------------------------------------------------------------------*/
1692 static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata)
1693 {
1694 	if ((!udc) && (!pdata))
1695 		return;
1696 
1697 	*pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0);
1698 	pdata++;
1699 	*pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1);
1700 }
1701 
1702 /*-------------------------------------------------------------------------*/
1703 static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc)
1704 {
1705 	bool			bcall_back = TRUE;
1706 	int			nret = -EINVAL;
1707 	struct usb_ctrlrequest	*p_ctrl;
1708 
1709 	p_ctrl = &udc->ctrl;
1710 	_nbu2ss_read_request_data(udc, (u32 *)p_ctrl);
1711 
1712 	/* ep0 state control */
1713 	if (p_ctrl->wLength == 0) {
1714 		udc->ep0state = EP0_IN_STATUS_PHASE;
1715 
1716 	} else {
1717 		if (p_ctrl->bRequestType & USB_DIR_IN)
1718 			udc->ep0state = EP0_IN_DATA_PHASE;
1719 		else
1720 			udc->ep0state = EP0_OUT_DATA_PHASE;
1721 	}
1722 
1723 	if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1724 		switch (p_ctrl->bRequest) {
1725 		case USB_REQ_GET_STATUS:
1726 			nret = std_req_get_status(udc);
1727 			bcall_back = FALSE;
1728 			break;
1729 
1730 		case USB_REQ_CLEAR_FEATURE:
1731 			nret = std_req_clear_feature(udc);
1732 			bcall_back = FALSE;
1733 			break;
1734 
1735 		case USB_REQ_SET_FEATURE:
1736 			nret = std_req_set_feature(udc);
1737 			bcall_back = FALSE;
1738 			break;
1739 
1740 		case USB_REQ_SET_ADDRESS:
1741 			nret = std_req_set_address(udc);
1742 			bcall_back = FALSE;
1743 			break;
1744 
1745 		case USB_REQ_SET_CONFIGURATION:
1746 			nret = std_req_set_configuration(udc);
1747 			break;
1748 
1749 		default:
1750 			break;
1751 		}
1752 	}
1753 
1754 	if (!bcall_back) {
1755 		if (udc->ep0state == EP0_IN_STATUS_PHASE) {
1756 			if (nret >= 0) {
1757 				/*--------------------------------------*/
1758 				/* Status Stage */
1759 				nret = EP0_send_NULL(udc, TRUE);
1760 			}
1761 		}
1762 
1763 	} else {
1764 		spin_unlock(&udc->lock);
1765 		nret = udc->driver->setup(&udc->gadget, &udc->ctrl);
1766 		spin_lock(&udc->lock);
1767 	}
1768 
1769 	if (nret < 0)
1770 		udc->ep0state = EP0_IDLE;
1771 
1772 	return nret;
1773 }
1774 
1775 /*-------------------------------------------------------------------------*/
1776 static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc)
1777 {
1778 	int			nret;
1779 	struct nbu2ss_req	*req;
1780 	struct nbu2ss_ep	*ep = &udc->ep[0];
1781 
1782 	req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1783 	if (!req)
1784 		req = &udc->ep0_req;
1785 
1786 	req->req.actual += req->div_len;
1787 	req->div_len = 0;
1788 
1789 	nret = _nbu2ss_ep0_in_transfer(udc, req);
1790 	if (nret == 0) {
1791 		udc->ep0state = EP0_OUT_STATUS_PAHSE;
1792 		EP0_receive_NULL(udc, TRUE);
1793 	}
1794 
1795 	return 0;
1796 }
1797 
1798 /*-------------------------------------------------------------------------*/
1799 static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc)
1800 {
1801 	int			nret;
1802 	struct nbu2ss_req	*req;
1803 	struct nbu2ss_ep	*ep = &udc->ep[0];
1804 
1805 	req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1806 	if (!req)
1807 		req = &udc->ep0_req;
1808 
1809 	nret = _nbu2ss_ep0_out_transfer(udc, req);
1810 	if (nret == 0) {
1811 		udc->ep0state = EP0_IN_STATUS_PHASE;
1812 		EP0_send_NULL(udc, TRUE);
1813 
1814 	} else if (nret < 0) {
1815 		_nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR);
1816 		req->req.status = nret;
1817 	}
1818 
1819 	return 0;
1820 }
1821 
1822 /*-------------------------------------------------------------------------*/
1823 static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc)
1824 {
1825 	struct nbu2ss_req	*req;
1826 	struct nbu2ss_ep	*ep = &udc->ep[0];
1827 
1828 	req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1829 	if (!req) {
1830 		req = &udc->ep0_req;
1831 		if (req->req.complete)
1832 			req->req.complete(&ep->ep, &req->req);
1833 
1834 	} else {
1835 		if (req->req.complete)
1836 			_nbu2ss_ep_done(ep, req, 0);
1837 	}
1838 
1839 	udc->ep0state = EP0_IDLE;
1840 
1841 	return 0;
1842 }
1843 
1844 /*-------------------------------------------------------------------------*/
1845 static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc)
1846 {
1847 	int		i;
1848 	u32		status;
1849 	u32		intr;
1850 	int		nret = -1;
1851 
1852 	status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS);
1853 	intr = status & EP0_STATUS_RW_BIT;
1854 	_nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~(u32)intr);
1855 
1856 	status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT
1857 			| STG_END_INT | EP0_OUT_NULL_INT);
1858 
1859 	if (status == 0) {
1860 		dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__);
1861 		dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr);
1862 		return;
1863 	}
1864 
1865 	if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1866 		udc->gadget.speed = _nbu2ss_get_speed(udc);
1867 
1868 	for (i = 0; i < EP0_END_XFER; i++) {
1869 		switch (udc->ep0state) {
1870 		case EP0_IDLE:
1871 			if (status & SETUP_INT) {
1872 				status = 0;
1873 				nret = _nbu2ss_decode_request(udc);
1874 			}
1875 			break;
1876 
1877 		case EP0_IN_DATA_PHASE:
1878 			if (status & EP0_IN_INT) {
1879 				status &= ~EP0_IN_INT;
1880 				nret = _nbu2ss_ep0_in_data_stage(udc);
1881 			}
1882 			break;
1883 
1884 		case EP0_OUT_DATA_PHASE:
1885 			if (status & EP0_OUT_INT) {
1886 				status &= ~EP0_OUT_INT;
1887 				nret = _nbu2ss_ep0_out_data_stage(udc);
1888 			}
1889 			break;
1890 
1891 		case EP0_IN_STATUS_PHASE:
1892 			if ((status & STG_END_INT) || (status & SETUP_INT)) {
1893 				status &= ~(STG_END_INT | EP0_IN_INT);
1894 				nret = _nbu2ss_ep0_status_stage(udc);
1895 			}
1896 			break;
1897 
1898 		case EP0_OUT_STATUS_PAHSE:
1899 			if ((status & STG_END_INT)
1900 			|| (status & SETUP_INT)
1901 			|| (status & EP0_OUT_NULL_INT)) {
1902 				status &= ~(STG_END_INT
1903 						| EP0_OUT_INT
1904 						| EP0_OUT_NULL_INT);
1905 
1906 				nret = _nbu2ss_ep0_status_stage(udc);
1907 			}
1908 
1909 			break;
1910 
1911 		default:
1912 			status = 0;
1913 			break;
1914 		}
1915 
1916 		if (status == 0)
1917 			break;
1918 	}
1919 
1920 	if (nret < 0) {
1921 		/* Send Stall */
1922 		_nbu2ss_set_endpoint_stall(udc, 0, TRUE);
1923 	}
1924 }
1925 
1926 /*-------------------------------------------------------------------------*/
1927 static void _nbu2ss_ep_done(
1928 	struct nbu2ss_ep *ep,
1929 	struct nbu2ss_req *req,
1930 	int status)
1931 {
1932 	struct nbu2ss_udc *udc = ep->udc;
1933 
1934 	list_del_init(&req->queue);
1935 
1936 	if (status == -ECONNRESET)
1937 		_nbu2ss_fifo_flush(udc, ep);
1938 
1939 	if (likely(req->req.status == -EINPROGRESS))
1940 		req->req.status = status;
1941 
1942 	if (ep->stalled)
1943 		_nbu2ss_epn_set_stall(udc, ep);
1944 	else {
1945 		if (!list_empty(&ep->queue))
1946 			_nbu2ss_restert_transfer(ep);
1947 	}
1948 
1949 #ifdef USE_DMA
1950 	if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) &&
1951 	    (req->req.dma != 0))
1952 		_nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT);
1953 #endif
1954 
1955 	spin_unlock(&udc->lock);
1956 	req->req.complete(&ep->ep, &req->req);
1957 	spin_lock(&udc->lock);
1958 }
1959 
1960 /*-------------------------------------------------------------------------*/
1961 static inline void _nbu2ss_epn_in_int(
1962 	struct nbu2ss_udc *udc,
1963 	struct nbu2ss_ep *ep,
1964 	struct nbu2ss_req *req)
1965 {
1966 	int	result = 0;
1967 	u32	status;
1968 
1969 	struct fc_regs	*preg = udc->p_regs;
1970 
1971 	if (req->dma_flag)
1972 		return;		/* DMA is forwarded */
1973 
1974 	req->req.actual += req->div_len;
1975 	req->div_len = 0;
1976 
1977 	if (req->req.actual != req->req.length) {
1978 		/*---------------------------------------------------------*/
1979 		/* remainder of data */
1980 		result = _nbu2ss_epn_in_transfer(udc, ep, req);
1981 
1982 	} else {
1983 		if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) {
1984 
1985 			status =
1986 			_nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1987 
1988 			if ((status & EPn_IN_FULL) == 0) {
1989 				/*-----------------------------------------*/
1990 				/* 0 Length Packet */
1991 				req->zero = false;
1992 				_nbu2ss_zero_len_pkt(udc, ep->epnum);
1993 			}
1994 			return;
1995 		}
1996 	}
1997 
1998 	if (result <= 0) {
1999 		/*---------------------------------------------------------*/
2000 		/* Complete */
2001 		_nbu2ss_ep_done(ep, req, result);
2002 	}
2003 }
2004 
2005 /*-------------------------------------------------------------------------*/
2006 static inline void _nbu2ss_epn_out_int(
2007 	struct nbu2ss_udc *udc,
2008 	struct nbu2ss_ep *ep,
2009 	struct nbu2ss_req *req)
2010 {
2011 	int	result;
2012 
2013 	result = _nbu2ss_epn_out_transfer(udc, ep, req);
2014 	if (result <= 0)
2015 		_nbu2ss_ep_done(ep, req, result);
2016 }
2017 
2018 /*-------------------------------------------------------------------------*/
2019 static inline void _nbu2ss_epn_in_dma_int(
2020 	struct nbu2ss_udc *udc,
2021 	struct nbu2ss_ep *ep,
2022 	struct nbu2ss_req *req)
2023 {
2024 	u32		mpkt;
2025 	u32		size;
2026 	struct usb_request *preq;
2027 
2028 	preq = &req->req;
2029 
2030 	if (!req->dma_flag)
2031 		return;
2032 
2033 	preq->actual += req->div_len;
2034 	req->div_len = 0;
2035 	req->dma_flag = FALSE;
2036 
2037 #ifdef USE_DMA
2038 	_nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN);
2039 #endif
2040 
2041 	if (preq->actual != preq->length) {
2042 		_nbu2ss_epn_in_transfer(udc, ep, req);
2043 	} else {
2044 		mpkt = ep->ep.maxpacket;
2045 		size = preq->actual % mpkt;
2046 		if (size > 0) {
2047 			if (((preq->actual & 0x03) == 0) && (size < mpkt))
2048 				_nbu2ss_ep_in_end(udc, ep->epnum, 0, 0);
2049 		} else {
2050 			_nbu2ss_epn_in_int(udc, ep, req);
2051 		}
2052 	}
2053 }
2054 
2055 /*-------------------------------------------------------------------------*/
2056 static inline void _nbu2ss_epn_out_dma_int(
2057 	struct nbu2ss_udc *udc,
2058 	struct nbu2ss_ep *ep,
2059 	struct nbu2ss_req *req)
2060 {
2061 	int		i;
2062 	u32		num;
2063 	u32		dmacnt, ep_dmacnt;
2064 	u32		mpkt;
2065 	struct fc_regs	*preg = udc->p_regs;
2066 
2067 	num = ep->epnum - 1;
2068 
2069 	if (req->req.actual == req->req.length) {
2070 		if ((req->req.length % ep->ep.maxpacket) && !req->zero) {
2071 			req->div_len = 0;
2072 			req->dma_flag = FALSE;
2073 			_nbu2ss_ep_done(ep, req, 0);
2074 			return;
2075 		}
2076 	}
2077 
2078 	ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT)
2079 		 & EPn_DMACNT;
2080 	ep_dmacnt >>= 16;
2081 
2082 	for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
2083 		dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1)
2084 			 & DCR1_EPn_DMACNT;
2085 		dmacnt >>= 16;
2086 		if (ep_dmacnt == dmacnt)
2087 			break;
2088 	}
2089 
2090 	_nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_REQEN);
2091 
2092 	if (dmacnt != 0) {
2093 		mpkt = ep->ep.maxpacket;
2094 		if ((req->div_len % mpkt) == 0)
2095 			req->div_len -= mpkt * dmacnt;
2096 	}
2097 
2098 	if ((req->req.actual % ep->ep.maxpacket) > 0) {
2099 		if (req->req.actual == req->div_len) {
2100 			req->div_len = 0;
2101 			req->dma_flag = FALSE;
2102 			_nbu2ss_ep_done(ep, req, 0);
2103 			return;
2104 		}
2105 	}
2106 
2107 	req->req.actual += req->div_len;
2108 	req->div_len = 0;
2109 	req->dma_flag = FALSE;
2110 
2111 	_nbu2ss_epn_out_int(udc, ep, req);
2112 }
2113 
2114 /*-------------------------------------------------------------------------*/
2115 static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum)
2116 {
2117 	u32	num;
2118 	u32	status;
2119 
2120 	struct nbu2ss_req	*req;
2121 	struct nbu2ss_ep	*ep = &udc->ep[epnum];
2122 
2123 	num = epnum - 1;
2124 
2125 	/* Interrupt Status */
2126 	status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
2127 
2128 	/* Interrupt Clear */
2129 	_nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~(u32)status);
2130 
2131 	req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
2132 	if (!req) {
2133 		/* pr_warn("=== %s(%d) req == NULL\n", __func__, epnum); */
2134 		return;
2135 	}
2136 
2137 	if (status & EPn_OUT_END_INT) {
2138 		status &= ~EPn_OUT_INT;
2139 		_nbu2ss_epn_out_dma_int(udc, ep, req);
2140 	}
2141 
2142 	if (status & EPn_OUT_INT)
2143 		_nbu2ss_epn_out_int(udc, ep, req);
2144 
2145 	if (status & EPn_IN_END_INT) {
2146 		status &= ~EPn_IN_INT;
2147 		_nbu2ss_epn_in_dma_int(udc, ep, req);
2148 	}
2149 
2150 	if (status & EPn_IN_INT)
2151 		_nbu2ss_epn_in_int(udc, ep, req);
2152 }
2153 
2154 /*-------------------------------------------------------------------------*/
2155 static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum)
2156 {
2157 	if (epnum == 0)
2158 		_nbu2ss_ep0_int(udc);
2159 	else
2160 		_nbu2ss_epn_int(udc, epnum);
2161 }
2162 
2163 /*-------------------------------------------------------------------------*/
2164 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc)
2165 {
2166 	_nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR));
2167 	_nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT);
2168 }
2169 
2170 /*-------------------------------------------------------------------------*/
2171 static int _nbu2ss_nuke(struct nbu2ss_udc *udc,
2172 			struct nbu2ss_ep *ep,
2173 			int status)
2174 {
2175 	struct nbu2ss_req *req;
2176 
2177 	/* Endpoint Disable */
2178 	_nbu2ss_epn_exit(udc, ep);
2179 
2180 	/* DMA Disable */
2181 	_nbu2ss_ep_dma_exit(udc, ep);
2182 
2183 	if (list_empty(&ep->queue))
2184 		return 0;
2185 
2186 	/* called with irqs blocked */
2187 	list_for_each_entry(req, &ep->queue, queue) {
2188 		_nbu2ss_ep_done(ep, req, status);
2189 	}
2190 
2191 	return 0;
2192 }
2193 
2194 /*-------------------------------------------------------------------------*/
2195 static void _nbu2ss_quiesce(struct nbu2ss_udc *udc)
2196 {
2197 	struct nbu2ss_ep	*ep;
2198 
2199 	udc->gadget.speed = USB_SPEED_UNKNOWN;
2200 
2201 	_nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN);
2202 
2203 	/* Endpoint n */
2204 	list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2205 		_nbu2ss_nuke(udc, ep, -ESHUTDOWN);
2206 	}
2207 }
2208 
2209 /*-------------------------------------------------------------------------*/
2210 static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on)
2211 {
2212 	u32	reg_dt;
2213 
2214 	if (udc->vbus_active == 0)
2215 		return -ESHUTDOWN;
2216 
2217 	if (is_on) {
2218 		/* D+ Pullup */
2219 		if (udc->driver) {
2220 			reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL)
2221 				| PUE2) & ~(u32)CONNECTB;
2222 
2223 			_nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2224 		}
2225 
2226 	} else {
2227 		/* D+ Pulldown */
2228 		reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB)
2229 			& ~(u32)PUE2;
2230 
2231 		_nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2232 		udc->gadget.speed = USB_SPEED_UNKNOWN;
2233 	}
2234 
2235 	return 0;
2236 }
2237 
2238 /*-------------------------------------------------------------------------*/
2239 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
2240 {
2241 	struct fc_regs	*p = udc->p_regs;
2242 
2243 	if (udc->vbus_active == 0)
2244 		return;
2245 
2246 	if (ep->epnum == 0) {
2247 		/* EP0 */
2248 		_nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR);
2249 
2250 	} else {
2251 		/* EPn */
2252 		_nbu2ss_ep_dma_abort(udc, ep);
2253 		_nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPn_BCLR);
2254 	}
2255 }
2256 
2257 /*-------------------------------------------------------------------------*/
2258 static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc)
2259 {
2260 	int	waitcnt = 0;
2261 
2262 	if (udc->udc_enabled)
2263 		return 0;
2264 
2265 	/*
2266 		Reset
2267 	*/
2268 	_nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2269 	udelay(EPC_RST_DISABLE_TIME);	/* 1us wait */
2270 
2271 	_nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD);
2272 	mdelay(EPC_DIRPD_DISABLE_TIME);	/* 1ms wait */
2273 
2274 	_nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2275 
2276 	_nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE);
2277 
2278 		_nbu2ss_writel(&udc->p_regs->AHBMCTR,
2279 			       HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE);
2280 
2281 	while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) {
2282 		waitcnt++;
2283 		udelay(1);	/* 1us wait */
2284 		if (waitcnt == EPC_PLL_LOCK_COUNT) {
2285 			dev_err(udc->dev, "*** Reset Cancel failed\n");
2286 			return -EINVAL;
2287 		}
2288 	}
2289 
2290 		_nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET);
2291 
2292 	_nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV));
2293 
2294 	/* EP0 */
2295 	_nbu2ss_ep0_enable(udc);
2296 
2297 	/* USB Interrupt Enable */
2298 	_nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT);
2299 
2300 	udc->udc_enabled = TRUE;
2301 
2302 	return 0;
2303 }
2304 
2305 /*-------------------------------------------------------------------------*/
2306 static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc)
2307 {
2308 	_nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST);
2309 	_nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2310 }
2311 
2312 /*-------------------------------------------------------------------------*/
2313 static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc)
2314 {
2315 	if (udc->udc_enabled) {
2316 		udc->udc_enabled = FALSE;
2317 		_nbu2ss_reset_controller(udc);
2318 		_nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2319 	}
2320 }
2321 
2322 /*-------------------------------------------------------------------------*/
2323 static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc)
2324 {
2325 	int	nret;
2326 	u32	reg_dt;
2327 
2328 	/* chattering */
2329 	mdelay(VBUS_CHATTERING_MDELAY);		/* wait (ms) */
2330 
2331 	/* VBUS ON Check*/
2332 	reg_dt = gpio_get_value(VBUS_VALUE);
2333 	if (reg_dt == 0) {
2334 
2335 		udc->linux_suspended = 0;
2336 
2337 		_nbu2ss_reset_controller(udc);
2338 		dev_info(udc->dev, " ----- VBUS OFF\n");
2339 
2340 		if (udc->vbus_active == 1) {
2341 			/* VBUS OFF */
2342 			udc->vbus_active = 0;
2343 			if (udc->usb_suspended) {
2344 				udc->usb_suspended = 0;
2345 				/* _nbu2ss_reset_controller(udc); */
2346 			}
2347 			udc->devstate = USB_STATE_NOTATTACHED;
2348 
2349 			_nbu2ss_quiesce(udc);
2350 			if (udc->driver) {
2351 				spin_unlock(&udc->lock);
2352 				udc->driver->disconnect(&udc->gadget);
2353 				spin_lock(&udc->lock);
2354 			}
2355 
2356 			_nbu2ss_disable_controller(udc);
2357 		}
2358 	} else {
2359 		mdelay(5);		/* wait (5ms) */
2360 		reg_dt = gpio_get_value(VBUS_VALUE);
2361 		if (reg_dt == 0)
2362 			return;
2363 
2364 		dev_info(udc->dev, " ----- VBUS ON\n");
2365 
2366 		if (udc->linux_suspended)
2367 			return;
2368 
2369 		if (udc->vbus_active == 0) {
2370 			/* VBUS ON */
2371 			udc->vbus_active = 1;
2372 			udc->devstate = USB_STATE_POWERED;
2373 
2374 			nret = _nbu2ss_enable_controller(udc);
2375 			if (nret < 0) {
2376 				_nbu2ss_disable_controller(udc);
2377 				udc->vbus_active = 0;
2378 				return;
2379 			}
2380 
2381 			_nbu2ss_pullup(udc, 1);
2382 
2383 #ifdef UDC_DEBUG_DUMP
2384 			_nbu2ss_dump_register(udc);
2385 #endif /* UDC_DEBUG_DUMP */
2386 
2387 		} else {
2388 			if (udc->devstate == USB_STATE_POWERED)
2389 				_nbu2ss_pullup(udc, 1);
2390 		}
2391 	}
2392 }
2393 
2394 /*-------------------------------------------------------------------------*/
2395 static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc)
2396 {
2397 	udc->devstate		= USB_STATE_DEFAULT;
2398 	udc->remote_wakeup	= 0;
2399 
2400 	_nbu2ss_quiesce(udc);
2401 
2402 	udc->ep0state = EP0_IDLE;
2403 }
2404 
2405 /*-------------------------------------------------------------------------*/
2406 static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc)
2407 {
2408 	if (udc->usb_suspended == 1) {
2409 		udc->usb_suspended = 0;
2410 		if (udc->driver && udc->driver->resume) {
2411 			spin_unlock(&udc->lock);
2412 			udc->driver->resume(&udc->gadget);
2413 			spin_lock(&udc->lock);
2414 		}
2415 	}
2416 }
2417 
2418 /*-------------------------------------------------------------------------*/
2419 static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc)
2420 {
2421 	u32	reg_dt;
2422 
2423 	if (udc->usb_suspended == 0) {
2424 		reg_dt = gpio_get_value(VBUS_VALUE);
2425 
2426 		if (reg_dt == 0)
2427 			return;
2428 
2429 		udc->usb_suspended = 1;
2430 		if (udc->driver && udc->driver->suspend) {
2431 			spin_unlock(&udc->lock);
2432 			udc->driver->suspend(&udc->gadget);
2433 			spin_lock(&udc->lock);
2434 		}
2435 
2436 		_nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND);
2437 	}
2438 }
2439 
2440 /*-------------------------------------------------------------------------*/
2441 /* VBUS (GPIO153) Interrupt */
2442 static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc)
2443 {
2444 	struct nbu2ss_udc	*udc = (struct nbu2ss_udc *)_udc;
2445 
2446 	spin_lock(&udc->lock);
2447 	_nbu2ss_check_vbus(udc);
2448 	spin_unlock(&udc->lock);
2449 
2450 	return IRQ_HANDLED;
2451 }
2452 
2453 /*-------------------------------------------------------------------------*/
2454 /* Interrupt (udc) */
2455 static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc)
2456 {
2457 	u8	suspend_flag = 0;
2458 	u32	status;
2459 	u32	epnum, int_bit;
2460 
2461 	struct nbu2ss_udc	*udc = (struct nbu2ss_udc *)_udc;
2462 	struct fc_regs	*preg = udc->p_regs;
2463 
2464 	if (gpio_get_value(VBUS_VALUE) == 0) {
2465 		_nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2466 		_nbu2ss_writel(&preg->USB_INT_ENA, 0);
2467 		return IRQ_HANDLED;
2468 	}
2469 
2470 	spin_lock(&udc->lock);
2471 
2472 	for (;;) {
2473 		if (gpio_get_value(VBUS_VALUE) == 0) {
2474 			_nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2475 			_nbu2ss_writel(&preg->USB_INT_ENA, 0);
2476 			status = 0;
2477 		} else
2478 			status = _nbu2ss_readl(&preg->USB_INT_STA);
2479 
2480 		if (status == 0)
2481 			break;
2482 
2483 		_nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW));
2484 
2485 		if (status & USB_RST_INT) {
2486 			/* USB Reset */
2487 			_nbu2ss_int_bus_reset(udc);
2488 		}
2489 
2490 		if (status & RSUM_INT) {
2491 			/* Resume */
2492 			_nbu2ss_int_usb_resume(udc);
2493 		}
2494 
2495 		if (status & SPND_INT) {
2496 			/* Suspend */
2497 			suspend_flag = 1;
2498 		}
2499 
2500 		if (status & EPn_INT) {
2501 			/* EP INT */
2502 			int_bit = status >> 8;
2503 
2504 			for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) {
2505 
2506 				if (0x01 & int_bit)
2507 					_nbu2ss_ep_int(udc, epnum);
2508 
2509 				int_bit >>= 1;
2510 
2511 				if (int_bit == 0)
2512 					break;
2513 			}
2514 		}
2515 	}
2516 
2517 	if (suspend_flag)
2518 		_nbu2ss_int_usb_suspend(udc);
2519 
2520 	spin_unlock(&udc->lock);
2521 
2522 	return IRQ_HANDLED;
2523 }
2524 
2525 /*-------------------------------------------------------------------------*/
2526 /* usb_ep_ops */
2527 static int nbu2ss_ep_enable(
2528 	struct usb_ep *_ep,
2529 	const struct usb_endpoint_descriptor *desc)
2530 {
2531 	u8		ep_type;
2532 	unsigned long	flags;
2533 
2534 	struct nbu2ss_ep	*ep;
2535 	struct nbu2ss_udc	*udc;
2536 
2537 	if ((!_ep) || (!desc)) {
2538 		pr_err(" *** %s, bad param\n", __func__);
2539 		return -EINVAL;
2540 	}
2541 
2542 	ep = container_of(_ep, struct nbu2ss_ep, ep);
2543 	if ((!ep) || (!ep->udc)) {
2544 		pr_err(" *** %s, ep == NULL !!\n", __func__);
2545 		return -EINVAL;
2546 	}
2547 
2548 	ep_type = usb_endpoint_type(desc);
2549 	if ((ep_type == USB_ENDPOINT_XFER_CONTROL)
2550 		|| (ep_type == USB_ENDPOINT_XFER_ISOC)) {
2551 
2552 		pr_err(" *** %s, bat bmAttributes\n", __func__);
2553 		return -EINVAL;
2554 	}
2555 
2556 	udc = ep->udc;
2557 	if (udc->vbus_active == 0)
2558 		return -ESHUTDOWN;
2559 
2560 	if ((!udc->driver)
2561 		|| (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
2562 
2563 		dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__);
2564 		return -ESHUTDOWN;
2565 	}
2566 
2567 	spin_lock_irqsave(&udc->lock, flags);
2568 
2569 	ep->desc = desc;
2570 	ep->epnum = usb_endpoint_num(desc);
2571 	ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
2572 	ep->ep_type = ep_type;
2573 	ep->wedged = 0;
2574 	ep->halted = FALSE;
2575 	ep->stalled = FALSE;
2576 
2577 	ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
2578 
2579 	/* DMA setting */
2580 	_nbu2ss_ep_dma_init(udc, ep);
2581 
2582 	/* Endpoint setting */
2583 	_nbu2ss_ep_init(udc, ep);
2584 
2585 	spin_unlock_irqrestore(&udc->lock, flags);
2586 
2587 	return 0;
2588 }
2589 
2590 /*-------------------------------------------------------------------------*/
2591 static int nbu2ss_ep_disable(struct usb_ep *_ep)
2592 {
2593 	struct nbu2ss_ep	*ep;
2594 	struct nbu2ss_udc	*udc;
2595 	unsigned long		flags;
2596 
2597 	if (!_ep) {
2598 		pr_err(" *** %s, bad param\n", __func__);
2599 		return -EINVAL;
2600 	}
2601 
2602 	ep = container_of(_ep, struct nbu2ss_ep, ep);
2603 	if ((!ep) || (!ep->udc)) {
2604 		pr_err("udc: *** %s, ep == NULL !!\n", __func__);
2605 		return -EINVAL;
2606 	}
2607 
2608 	udc = ep->udc;
2609 	if (udc->vbus_active == 0)
2610 		return -ESHUTDOWN;
2611 
2612 	spin_lock_irqsave(&udc->lock, flags);
2613 	_nbu2ss_nuke(udc, ep, -EINPROGRESS);		/* dequeue request */
2614 	spin_unlock_irqrestore(&udc->lock, flags);
2615 
2616 	return 0;
2617 }
2618 
2619 /*-------------------------------------------------------------------------*/
2620 static struct usb_request *nbu2ss_ep_alloc_request(
2621 	struct usb_ep *ep,
2622 	gfp_t gfp_flags)
2623 {
2624 	struct nbu2ss_req *req;
2625 
2626 	req = kzalloc(sizeof(*req), gfp_flags);
2627 	if (!req)
2628 		return NULL;
2629 
2630 #ifdef USE_DMA
2631 	req->req.dma = DMA_ADDR_INVALID;
2632 #endif
2633 	INIT_LIST_HEAD(&req->queue);
2634 
2635 	return &req->req;
2636 }
2637 
2638 /*-------------------------------------------------------------------------*/
2639 static void nbu2ss_ep_free_request(
2640 	struct usb_ep *_ep,
2641 	struct usb_request *_req)
2642 {
2643 	struct nbu2ss_req *req;
2644 
2645 	if (_req) {
2646 		req = container_of(_req, struct nbu2ss_req, req);
2647 
2648 		kfree(req);
2649 	}
2650 }
2651 
2652 /*-------------------------------------------------------------------------*/
2653 static int nbu2ss_ep_queue(
2654 	struct usb_ep *_ep,
2655 	struct usb_request *_req,
2656 	gfp_t gfp_flags)
2657 {
2658 	struct nbu2ss_req	*req;
2659 	struct nbu2ss_ep	*ep;
2660 	struct nbu2ss_udc	*udc;
2661 	unsigned long		flags;
2662 	bool			bflag;
2663 	int			result = -EINVAL;
2664 
2665 	/* catch various bogus parameters */
2666 	if ((!_ep) || (!_req)) {
2667 		if (!_ep)
2668 			pr_err("udc: %s --- _ep == NULL\n", __func__);
2669 
2670 		if (!_req)
2671 			pr_err("udc: %s --- _req == NULL\n", __func__);
2672 
2673 		return -EINVAL;
2674 	}
2675 
2676 	req = container_of(_req, struct nbu2ss_req, req);
2677 	if (unlikely
2678 	    (!_req->complete || !_req->buf
2679 	     || !list_empty(&req->queue))) {
2680 
2681 		if (!_req->complete)
2682 			pr_err("udc: %s --- !_req->complete\n", __func__);
2683 
2684 		if (!_req->buf)
2685 			pr_err("udc:%s --- !_req->buf\n", __func__);
2686 
2687 		if (!list_empty(&req->queue))
2688 			pr_err("%s --- !list_empty(&req->queue)\n", __func__);
2689 
2690 		return -EINVAL;
2691 	}
2692 
2693 	ep = container_of(_ep, struct nbu2ss_ep, ep);
2694 	udc = ep->udc;
2695 
2696 	if (udc->vbus_active == 0) {
2697 		dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n");
2698 		return -ESHUTDOWN;
2699 	}
2700 
2701 	if (unlikely(!udc->driver)) {
2702 		dev_err(udc->dev, "%s, bogus device state %p\n", __func__,
2703 			udc->driver);
2704 		return -ESHUTDOWN;
2705 	}
2706 
2707 	spin_lock_irqsave(&udc->lock, flags);
2708 
2709 #ifdef USE_DMA
2710 	if ((uintptr_t)req->req.buf & 0x3)
2711 		req->unaligned = TRUE;
2712 	else
2713 		req->unaligned = FALSE;
2714 
2715 	if (req->unaligned) {
2716 		if (!ep->virt_buf)
2717 			ep->virt_buf = (u8 *)dma_alloc_coherent(
2718 				NULL, PAGE_SIZE,
2719 				&ep->phys_buf, GFP_ATOMIC | GFP_DMA);
2720 		if (ep->epnum > 0)  {
2721 			if (ep->direct == USB_DIR_IN)
2722 				memcpy(ep->virt_buf, req->req.buf,
2723 				       req->req.length);
2724 		}
2725 	}
2726 
2727 	if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) &&
2728 	    (req->req.dma != 0))
2729 		_nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT);
2730 #endif
2731 
2732 	_req->status = -EINPROGRESS;
2733 	_req->actual = 0;
2734 
2735 	bflag = list_empty(&ep->queue);
2736 	list_add_tail(&req->queue, &ep->queue);
2737 
2738 	if (bflag && !ep->stalled) {
2739 
2740 		result = _nbu2ss_start_transfer(udc, ep, req, FALSE);
2741 		if (result < 0) {
2742 			dev_err(udc->dev, " *** %s, result = %d\n", __func__,
2743 				result);
2744 			list_del(&req->queue);
2745 		} else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) {
2746 #ifdef USE_DMA
2747 			if (req->req.length < 4 &&
2748 			    req->req.length == req->req.actual)
2749 #else
2750 			if (req->req.length == req->req.actual)
2751 #endif
2752 				_nbu2ss_ep_done(ep, req, result);
2753 		}
2754 	}
2755 
2756 	spin_unlock_irqrestore(&udc->lock, flags);
2757 
2758 	return 0;
2759 }
2760 
2761 /*-------------------------------------------------------------------------*/
2762 static int nbu2ss_ep_dequeue(
2763 	struct usb_ep *_ep,
2764 	struct usb_request *_req)
2765 {
2766 	struct nbu2ss_req	*req;
2767 	struct nbu2ss_ep	*ep;
2768 	struct nbu2ss_udc	*udc;
2769 	unsigned long flags;
2770 
2771 	/* catch various bogus parameters */
2772 	if ((!_ep) || (!_req)) {
2773 		/* pr_err("%s, bad param(1)\n", __func__); */
2774 		return -EINVAL;
2775 	}
2776 
2777 	ep = container_of(_ep, struct nbu2ss_ep, ep);
2778 	if (!ep) {
2779 		pr_err("%s, ep == NULL !!\n", __func__);
2780 		return -EINVAL;
2781 	}
2782 
2783 	udc = ep->udc;
2784 	if (!udc)
2785 		return -EINVAL;
2786 
2787 	spin_lock_irqsave(&udc->lock, flags);
2788 
2789 	/* make sure it's actually queued on this endpoint */
2790 	list_for_each_entry(req, &ep->queue, queue) {
2791 		if (&req->req == _req)
2792 			break;
2793 	}
2794 	if (&req->req != _req) {
2795 		spin_unlock_irqrestore(&udc->lock, flags);
2796 		pr_debug("%s no queue(EINVAL)\n", __func__);
2797 		return -EINVAL;
2798 	}
2799 
2800 	_nbu2ss_ep_done(ep, req, -ECONNRESET);
2801 
2802 	spin_unlock_irqrestore(&udc->lock, flags);
2803 
2804 	return 0;
2805 }
2806 
2807 /*-------------------------------------------------------------------------*/
2808 static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value)
2809 {
2810 	u8		ep_adrs;
2811 	unsigned long	flags;
2812 
2813 	struct nbu2ss_ep	*ep;
2814 	struct nbu2ss_udc	*udc;
2815 
2816 	if (!_ep) {
2817 		pr_err("%s, bad param\n", __func__);
2818 		return -EINVAL;
2819 	}
2820 
2821 	ep = container_of(_ep, struct nbu2ss_ep, ep);
2822 	if (!ep) {
2823 		pr_err("%s, bad ep\n", __func__);
2824 		return -EINVAL;
2825 	}
2826 
2827 	udc = ep->udc;
2828 	if (!udc) {
2829 		dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__);
2830 		return -EINVAL;
2831 	}
2832 
2833 	spin_lock_irqsave(&udc->lock, flags);
2834 
2835 	ep_adrs = ep->epnum | ep->direct;
2836 	if (value == 0) {
2837 		_nbu2ss_set_endpoint_stall(udc, ep_adrs, value);
2838 		ep->stalled = FALSE;
2839 	} else {
2840 		if (list_empty(&ep->queue))
2841 			_nbu2ss_epn_set_stall(udc, ep);
2842 		else
2843 			ep->stalled = TRUE;
2844 	}
2845 
2846 	if (value == 0)
2847 		ep->wedged = 0;
2848 
2849 	spin_unlock_irqrestore(&udc->lock, flags);
2850 
2851 	return 0;
2852 }
2853 
2854 static int nbu2ss_ep_set_wedge(struct usb_ep *_ep)
2855 {
2856 	return nbu2ss_ep_set_halt(_ep, 1);
2857 }
2858 
2859 /*-------------------------------------------------------------------------*/
2860 static int nbu2ss_ep_fifo_status(struct usb_ep *_ep)
2861 {
2862 	u32		data;
2863 	struct nbu2ss_ep	*ep;
2864 	struct nbu2ss_udc	*udc;
2865 	unsigned long		flags;
2866 	struct fc_regs		*preg;
2867 
2868 	if (!_ep) {
2869 		pr_err("%s, bad param\n", __func__);
2870 		return -EINVAL;
2871 	}
2872 
2873 	ep = container_of(_ep, struct nbu2ss_ep, ep);
2874 	if (!ep) {
2875 		pr_err("%s, bad ep\n", __func__);
2876 		return -EINVAL;
2877 	}
2878 
2879 	udc = ep->udc;
2880 	if (!udc) {
2881 		dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2882 		return -EINVAL;
2883 	}
2884 
2885 	preg = udc->p_regs;
2886 
2887 	data = gpio_get_value(VBUS_VALUE);
2888 	if (data == 0)
2889 		return -EINVAL;
2890 
2891 	spin_lock_irqsave(&udc->lock, flags);
2892 
2893 	if (ep->epnum == 0) {
2894 		data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA;
2895 
2896 	} else {
2897 		data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT)
2898 			& EPn_LDATA;
2899 	}
2900 
2901 	spin_unlock_irqrestore(&udc->lock, flags);
2902 
2903 	return 0;
2904 }
2905 
2906 /*-------------------------------------------------------------------------*/
2907 static void  nbu2ss_ep_fifo_flush(struct usb_ep *_ep)
2908 {
2909 	u32			data;
2910 	struct nbu2ss_ep	*ep;
2911 	struct nbu2ss_udc	*udc;
2912 	unsigned long		flags;
2913 
2914 	if (!_ep) {
2915 		pr_err("udc: %s, bad param\n", __func__);
2916 		return;
2917 	}
2918 
2919 	ep = container_of(_ep, struct nbu2ss_ep, ep);
2920 	if (!ep) {
2921 		pr_err("udc: %s, bad ep\n", __func__);
2922 		return;
2923 	}
2924 
2925 	udc = ep->udc;
2926 	if (!udc) {
2927 		dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2928 		return;
2929 	}
2930 
2931 	data = gpio_get_value(VBUS_VALUE);
2932 	if (data == 0)
2933 		return;
2934 
2935 	spin_lock_irqsave(&udc->lock, flags);
2936 	_nbu2ss_fifo_flush(udc, ep);
2937 	spin_unlock_irqrestore(&udc->lock, flags);
2938 }
2939 
2940 /*-------------------------------------------------------------------------*/
2941 static struct usb_ep_ops nbu2ss_ep_ops = {
2942 	.enable		= nbu2ss_ep_enable,
2943 	.disable	= nbu2ss_ep_disable,
2944 
2945 	.alloc_request	= nbu2ss_ep_alloc_request,
2946 	.free_request	= nbu2ss_ep_free_request,
2947 
2948 	.queue		= nbu2ss_ep_queue,
2949 	.dequeue	= nbu2ss_ep_dequeue,
2950 
2951 	.set_halt	= nbu2ss_ep_set_halt,
2952 	.set_wedge	= nbu2ss_ep_set_wedge,
2953 
2954 	.fifo_status	= nbu2ss_ep_fifo_status,
2955 	.fifo_flush	= nbu2ss_ep_fifo_flush,
2956 };
2957 
2958 /*-------------------------------------------------------------------------*/
2959 /* usb_gadget_ops */
2960 
2961 /*-------------------------------------------------------------------------*/
2962 static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget)
2963 {
2964 	u32			data;
2965 	struct nbu2ss_udc	*udc;
2966 
2967 	if (!pgadget) {
2968 		pr_err("udc: %s, bad param\n", __func__);
2969 		return -EINVAL;
2970 	}
2971 
2972 	udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2973 	if (!udc) {
2974 		dev_err(&pgadget->dev, "%s, udc == NULL\n", __func__);
2975 		return -EINVAL;
2976 	}
2977 
2978 	data = gpio_get_value(VBUS_VALUE);
2979 	if (data == 0)
2980 		return -EINVAL;
2981 
2982 	data = _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME;
2983 
2984 	return data;
2985 }
2986 
2987 /*-------------------------------------------------------------------------*/
2988 static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget)
2989 {
2990 	int	i;
2991 	u32	data;
2992 
2993 	struct nbu2ss_udc	*udc;
2994 
2995 	if (!pgadget) {
2996 		pr_err("%s, bad param\n", __func__);
2997 		return -EINVAL;
2998 	}
2999 
3000 	udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3001 	if (!udc) {
3002 		dev_err(&pgadget->dev, "%s, udc == NULL\n", __func__);
3003 		return -EINVAL;
3004 	}
3005 
3006 	data = gpio_get_value(VBUS_VALUE);
3007 	if (data == 0) {
3008 		dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data);
3009 		return -EINVAL;
3010 	}
3011 
3012 	_nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME);
3013 
3014 	for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
3015 		data = _nbu2ss_readl(&udc->p_regs->EPCTR);
3016 
3017 		if (data & PLL_LOCK)
3018 			break;
3019 	}
3020 
3021 	_nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME);
3022 
3023 	return 0;
3024 }
3025 
3026 /*-------------------------------------------------------------------------*/
3027 static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget,
3028 				      int is_selfpowered)
3029 {
3030 	struct nbu2ss_udc       *udc;
3031 	unsigned long		flags;
3032 
3033 	if (!pgadget) {
3034 		pr_err("%s, bad param\n", __func__);
3035 		return -EINVAL;
3036 	}
3037 
3038 	udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3039 
3040 	spin_lock_irqsave(&udc->lock, flags);
3041 	pgadget->is_selfpowered = (is_selfpowered != 0);
3042 	spin_unlock_irqrestore(&udc->lock, flags);
3043 
3044 	return 0;
3045 }
3046 
3047 /*-------------------------------------------------------------------------*/
3048 static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active)
3049 {
3050 	return 0;
3051 }
3052 
3053 /*-------------------------------------------------------------------------*/
3054 static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned int mA)
3055 {
3056 	struct nbu2ss_udc	*udc;
3057 	unsigned long		flags;
3058 
3059 	if (!pgadget) {
3060 		pr_err("%s, bad param\n", __func__);
3061 		return -EINVAL;
3062 	}
3063 
3064 	udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3065 
3066 	spin_lock_irqsave(&udc->lock, flags);
3067 	udc->mA = mA;
3068 	spin_unlock_irqrestore(&udc->lock, flags);
3069 
3070 	return 0;
3071 }
3072 
3073 /*-------------------------------------------------------------------------*/
3074 static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on)
3075 {
3076 	struct nbu2ss_udc	*udc;
3077 	unsigned long		flags;
3078 
3079 	if (!pgadget) {
3080 		pr_err("%s, bad param\n", __func__);
3081 		return -EINVAL;
3082 	}
3083 
3084 	udc = container_of(pgadget, struct nbu2ss_udc, gadget);
3085 
3086 	if (!udc->driver) {
3087 		pr_warn("%s, Not Regist Driver\n", __func__);
3088 		return -EINVAL;
3089 	}
3090 
3091 	if (udc->vbus_active == 0)
3092 		return -ESHUTDOWN;
3093 
3094 	spin_lock_irqsave(&udc->lock, flags);
3095 	_nbu2ss_pullup(udc, is_on);
3096 	spin_unlock_irqrestore(&udc->lock, flags);
3097 
3098 	return 0;
3099 }
3100 
3101 /*-------------------------------------------------------------------------*/
3102 static int nbu2ss_gad_ioctl(
3103 	struct usb_gadget *pgadget,
3104 	unsigned int code,
3105 	unsigned long param)
3106 {
3107 	return 0;
3108 }
3109 
3110 static const struct usb_gadget_ops nbu2ss_gadget_ops = {
3111 	.get_frame		= nbu2ss_gad_get_frame,
3112 	.wakeup			= nbu2ss_gad_wakeup,
3113 	.set_selfpowered	= nbu2ss_gad_set_selfpowered,
3114 	.vbus_session		= nbu2ss_gad_vbus_session,
3115 	.vbus_draw		= nbu2ss_gad_vbus_draw,
3116 	.pullup			= nbu2ss_gad_pullup,
3117 	.ioctl			= nbu2ss_gad_ioctl,
3118 };
3119 
3120 static const struct {
3121 	const char *name;
3122 	const struct usb_ep_caps caps;
3123 } ep_info[NUM_ENDPOINTS] = {
3124 #define EP_INFO(_name, _caps) \
3125 	{ \
3126 		.name = _name, \
3127 		.caps = _caps, \
3128 	}
3129 
3130 	EP_INFO("ep0",
3131 		USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)),
3132 	EP_INFO("ep1-bulk",
3133 		USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3134 	EP_INFO("ep2-bulk",
3135 		USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3136 	EP_INFO("ep3in-int",
3137 		USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3138 	EP_INFO("ep4-iso",
3139 		USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3140 	EP_INFO("ep5-iso",
3141 		USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3142 	EP_INFO("ep6-bulk",
3143 		USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3144 	EP_INFO("ep7-bulk",
3145 		USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3146 	EP_INFO("ep8in-int",
3147 		USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3148 	EP_INFO("ep9-iso",
3149 		USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3150 	EP_INFO("epa-iso",
3151 		USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
3152 	EP_INFO("epb-bulk",
3153 		USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3154 	EP_INFO("epc-bulk",
3155 		USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3156 	EP_INFO("epdin-int",
3157 		USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3158 
3159 #undef EP_INFO
3160 };
3161 
3162 /*-------------------------------------------------------------------------*/
3163 static void __init nbu2ss_drv_ep_init(struct nbu2ss_udc *udc)
3164 {
3165 	int	i;
3166 
3167 	INIT_LIST_HEAD(&udc->gadget.ep_list);
3168 	udc->gadget.ep0 = &udc->ep[0].ep;
3169 
3170 	for (i = 0; i < NUM_ENDPOINTS; i++) {
3171 		struct nbu2ss_ep *ep = &udc->ep[i];
3172 
3173 		ep->udc = udc;
3174 		ep->desc = NULL;
3175 
3176 		ep->ep.driver_data = NULL;
3177 		ep->ep.name = ep_info[i].name;
3178 		ep->ep.caps = ep_info[i].caps;
3179 		ep->ep.ops = &nbu2ss_ep_ops;
3180 
3181 		usb_ep_set_maxpacket_limit(&ep->ep,
3182 					   i == 0 ? EP0_PACKETSIZE
3183 					   : EP_PACKETSIZE);
3184 
3185 		list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
3186 		INIT_LIST_HEAD(&ep->queue);
3187 	}
3188 
3189 	list_del_init(&udc->ep[0].ep.ep_list);
3190 }
3191 
3192 /*-------------------------------------------------------------------------*/
3193 /* platform_driver */
3194 static int __init nbu2ss_drv_contest_init(
3195 	struct platform_device *pdev,
3196 	struct nbu2ss_udc *udc)
3197 {
3198 	spin_lock_init(&udc->lock);
3199 	udc->dev = &pdev->dev;
3200 
3201 	udc->gadget.is_selfpowered = 1;
3202 	udc->devstate = USB_STATE_NOTATTACHED;
3203 	udc->pdev = pdev;
3204 	udc->mA = 0;
3205 
3206 	udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3207 
3208 	/* init Endpoint */
3209 	nbu2ss_drv_ep_init(udc);
3210 
3211 	/* init Gadget */
3212 	udc->gadget.ops = &nbu2ss_gadget_ops;
3213 	udc->gadget.ep0 = &udc->ep[0].ep;
3214 	udc->gadget.speed = USB_SPEED_UNKNOWN;
3215 	udc->gadget.name = driver_name;
3216 	/* udc->gadget.is_dualspeed = 1; */
3217 
3218 	device_initialize(&udc->gadget.dev);
3219 
3220 	dev_set_name(&udc->gadget.dev, "gadget");
3221 	udc->gadget.dev.parent = &pdev->dev;
3222 	udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
3223 
3224 	return 0;
3225 }
3226 
3227 /*
3228  *	probe - binds to the platform device
3229  */
3230 static int nbu2ss_drv_probe(struct platform_device *pdev)
3231 {
3232 	int	status = -ENODEV;
3233 	struct nbu2ss_udc	*udc;
3234 	struct resource *r;
3235 	int irq;
3236 	void __iomem *mmio_base;
3237 
3238 	udc = &udc_controller;
3239 	memset(udc, 0, sizeof(struct nbu2ss_udc));
3240 
3241 	platform_set_drvdata(pdev, udc);
3242 
3243 	/* require I/O memory and IRQ to be provided as resources */
3244 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3245 	mmio_base = devm_ioremap_resource(&pdev->dev, r);
3246 	if (IS_ERR(mmio_base))
3247 		return PTR_ERR(mmio_base);
3248 
3249 	irq = platform_get_irq(pdev, 0);
3250 	if (irq < 0) {
3251 		dev_err(&pdev->dev, "failed to get IRQ\n");
3252 		return irq;
3253 	}
3254 	status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq,
3255 				  0, driver_name, udc);
3256 
3257 	/* IO Memory */
3258 	udc->p_regs = (struct fc_regs *)mmio_base;
3259 
3260 	/* USB Function Controller Interrupt */
3261 	if (status != 0) {
3262 		dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n");
3263 		return status;
3264 	}
3265 
3266 	/* Driver Initialization */
3267 	status = nbu2ss_drv_contest_init(pdev, udc);
3268 	if (status < 0) {
3269 		/* Error */
3270 		return status;
3271 	}
3272 
3273 	/* VBUS Interrupt */
3274 	irq_set_irq_type(INT_VBUS, IRQ_TYPE_EDGE_BOTH);
3275 	status = request_irq(INT_VBUS,
3276 			     _nbu2ss_vbus_irq, IRQF_SHARED, driver_name, udc);
3277 
3278 	if (status != 0) {
3279 		dev_err(udc->dev, "request_irq(INT_VBUS) failed\n");
3280 		return status;
3281 	}
3282 
3283 	return status;
3284 }
3285 
3286 /*-------------------------------------------------------------------------*/
3287 static void nbu2ss_drv_shutdown(struct platform_device *pdev)
3288 {
3289 	struct nbu2ss_udc	*udc;
3290 
3291 	udc = platform_get_drvdata(pdev);
3292 	if (!udc)
3293 		return;
3294 
3295 	_nbu2ss_disable_controller(udc);
3296 }
3297 
3298 /*-------------------------------------------------------------------------*/
3299 static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state)
3300 {
3301 	struct nbu2ss_udc	*udc;
3302 
3303 	udc = platform_get_drvdata(pdev);
3304 	if (!udc)
3305 		return 0;
3306 
3307 	if (udc->vbus_active) {
3308 		udc->vbus_active = 0;
3309 		udc->devstate = USB_STATE_NOTATTACHED;
3310 		udc->linux_suspended = 1;
3311 
3312 		if (udc->usb_suspended) {
3313 			udc->usb_suspended = 0;
3314 			_nbu2ss_reset_controller(udc);
3315 		}
3316 
3317 		_nbu2ss_quiesce(udc);
3318 	}
3319 	_nbu2ss_disable_controller(udc);
3320 
3321 	return 0;
3322 }
3323 
3324 /*-------------------------------------------------------------------------*/
3325 static int nbu2ss_drv_resume(struct platform_device *pdev)
3326 {
3327 	u32	data;
3328 	struct nbu2ss_udc	*udc;
3329 
3330 	udc = platform_get_drvdata(pdev);
3331 	if (!udc)
3332 		return 0;
3333 
3334 	data = gpio_get_value(VBUS_VALUE);
3335 	if (data) {
3336 		udc->vbus_active = 1;
3337 		udc->devstate = USB_STATE_POWERED;
3338 		_nbu2ss_enable_controller(udc);
3339 		_nbu2ss_pullup(udc, 1);
3340 	}
3341 
3342 	udc->linux_suspended = 0;
3343 
3344 	return 0;
3345 }
3346 
3347 static struct platform_driver udc_driver = {
3348 	.probe		= nbu2ss_drv_probe,
3349 	.shutdown	= nbu2ss_drv_shutdown,
3350 	.suspend	= nbu2ss_drv_suspend,
3351 	.resume		= nbu2ss_drv_resume,
3352 	.driver		= {
3353 		.name			= driver_name,
3354 		.suppress_bind_attrs	= true,
3355 	},
3356 };
3357 
3358 builtin_platform_driver(udc_driver);
3359