1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/usb/gadget/emxx_udc.c 4 * EMXX FCD (Function Controller Driver) for USB. 5 * 6 * Copyright (C) 2010 Renesas Electronics Corporation 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/delay.h> 13 #include <linux/ioport.h> 14 #include <linux/slab.h> 15 #include <linux/errno.h> 16 #include <linux/list.h> 17 #include <linux/interrupt.h> 18 #include <linux/proc_fs.h> 19 #include <linux/clk.h> 20 #include <linux/ctype.h> 21 #include <linux/string.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/workqueue.h> 24 #include <linux/device.h> 25 26 #include <linux/usb/ch9.h> 27 #include <linux/usb/gadget.h> 28 29 #include <linux/irq.h> 30 #include <linux/gpio/consumer.h> 31 32 #include "emxx_udc.h" 33 34 #define DRIVER_DESC "EMXX UDC driver" 35 #define DMA_ADDR_INVALID (~(dma_addr_t)0) 36 37 static struct gpio_desc *vbus_gpio; 38 static int vbus_irq; 39 40 static const char driver_name[] = "emxx_udc"; 41 42 /*===========================================================================*/ 43 /* Prototype */ 44 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *); 45 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *); 46 /*static void _nbu2ss_ep0_disable(struct nbu2ss_udc *);*/ 47 static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int); 48 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode); 49 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs); 50 51 static int _nbu2ss_pullup(struct nbu2ss_udc *, int); 52 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *); 53 54 /*===========================================================================*/ 55 /* Macro */ 56 #define _nbu2ss_zero_len_pkt(udc, epnum) \ 57 _nbu2ss_ep_in_end(udc, epnum, 0, 0) 58 59 /*===========================================================================*/ 60 /* Global */ 61 static struct nbu2ss_udc udc_controller; 62 63 /*-------------------------------------------------------------------------*/ 64 /* Read */ 65 static inline u32 _nbu2ss_readl(void __iomem *address) 66 { 67 return __raw_readl(address); 68 } 69 70 /*-------------------------------------------------------------------------*/ 71 /* Write */ 72 static inline void _nbu2ss_writel(void __iomem *address, u32 udata) 73 { 74 __raw_writel(udata, address); 75 } 76 77 /*-------------------------------------------------------------------------*/ 78 /* Set Bit */ 79 static inline void _nbu2ss_bitset(void __iomem *address, u32 udata) 80 { 81 u32 reg_dt = __raw_readl(address) | (udata); 82 83 __raw_writel(reg_dt, address); 84 } 85 86 /*-------------------------------------------------------------------------*/ 87 /* Clear Bit */ 88 static inline void _nbu2ss_bitclr(void __iomem *address, u32 udata) 89 { 90 u32 reg_dt = __raw_readl(address) & ~(udata); 91 92 __raw_writel(reg_dt, address); 93 } 94 95 #ifdef UDC_DEBUG_DUMP 96 /*-------------------------------------------------------------------------*/ 97 static void _nbu2ss_dump_register(struct nbu2ss_udc *udc) 98 { 99 int i; 100 u32 reg_data; 101 102 pr_info("=== %s()\n", __func__); 103 104 if (!udc) { 105 pr_err("%s udc == NULL\n", __func__); 106 return; 107 } 108 109 spin_unlock(&udc->lock); 110 111 dev_dbg(&udc->dev, "\n-USB REG-\n"); 112 for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) { 113 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i)); 114 dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data); 115 116 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 4)); 117 dev_dbg(&udc->dev, " %08x", (int)reg_data); 118 119 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 8)); 120 dev_dbg(&udc->dev, " %08x", (int)reg_data); 121 122 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 12)); 123 dev_dbg(&udc->dev, " %08x\n", (int)reg_data); 124 } 125 126 spin_lock(&udc->lock); 127 } 128 #endif /* UDC_DEBUG_DUMP */ 129 130 /*-------------------------------------------------------------------------*/ 131 /* Endpoint 0 Callback (Complete) */ 132 static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req) 133 { 134 u8 recipient; 135 u16 selector; 136 u16 wIndex; 137 u32 test_mode; 138 struct usb_ctrlrequest *p_ctrl; 139 struct nbu2ss_udc *udc; 140 141 if (!_ep || !_req) 142 return; 143 144 udc = (struct nbu2ss_udc *)_req->context; 145 p_ctrl = &udc->ctrl; 146 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 147 if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) { 148 /*-------------------------------------------------*/ 149 /* SET_FEATURE */ 150 recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK); 151 selector = le16_to_cpu(p_ctrl->wValue); 152 if ((recipient == USB_RECIP_DEVICE) && 153 (selector == USB_DEVICE_TEST_MODE)) { 154 wIndex = le16_to_cpu(p_ctrl->wIndex); 155 test_mode = (u32)(wIndex >> 8); 156 _nbu2ss_set_test_mode(udc, test_mode); 157 } 158 } 159 } 160 } 161 162 /*-------------------------------------------------------------------------*/ 163 /* Initialization usb_request */ 164 static void _nbu2ss_create_ep0_packet(struct nbu2ss_udc *udc, 165 void *p_buf, unsigned int length) 166 { 167 udc->ep0_req.req.buf = p_buf; 168 udc->ep0_req.req.length = length; 169 udc->ep0_req.req.dma = 0; 170 udc->ep0_req.req.zero = true; 171 udc->ep0_req.req.complete = _nbu2ss_ep0_complete; 172 udc->ep0_req.req.status = -EINPROGRESS; 173 udc->ep0_req.req.context = udc; 174 udc->ep0_req.req.actual = 0; 175 } 176 177 /*-------------------------------------------------------------------------*/ 178 /* Acquisition of the first address of RAM(FIFO) */ 179 static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc) 180 { 181 u32 num, buf_type; 182 u32 data, last_ram_adr, use_ram_size; 183 184 struct ep_regs __iomem *p_ep_regs; 185 186 last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2; 187 use_ram_size = 0; 188 189 for (num = 0; num < NUM_ENDPOINTS - 1; num++) { 190 p_ep_regs = &udc->p_regs->EP_REGS[num]; 191 data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS); 192 buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPN_BUF_TYPE; 193 if (buf_type == 0) { 194 /* Single Buffer */ 195 use_ram_size += (data & EPN_MPKT) / sizeof(u32); 196 } else { 197 /* Double Buffer */ 198 use_ram_size += ((data & EPN_MPKT) / sizeof(u32)) * 2; 199 } 200 201 if ((data >> 16) > last_ram_adr) 202 last_ram_adr = data >> 16; 203 } 204 205 return last_ram_adr + use_ram_size; 206 } 207 208 /*-------------------------------------------------------------------------*/ 209 /* Construction of Endpoint */ 210 static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 211 { 212 u32 num; 213 u32 data; 214 u32 begin_adrs; 215 216 if (ep->epnum == 0) 217 return -EINVAL; 218 219 num = ep->epnum - 1; 220 221 /*-------------------------------------------------------------*/ 222 /* RAM Transfer Address */ 223 begin_adrs = _nbu2ss_get_begin_ram_address(udc); 224 data = (begin_adrs << 16) | ep->ep.maxpacket; 225 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data); 226 227 /*-------------------------------------------------------------*/ 228 /* Interrupt Enable */ 229 data = 1 << (ep->epnum + 8); 230 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data); 231 232 /*-------------------------------------------------------------*/ 233 /* Endpoint Type(Mode) */ 234 /* Bulk, Interrupt, ISO */ 235 switch (ep->ep_type) { 236 case USB_ENDPOINT_XFER_BULK: 237 data = EPN_BULK; 238 break; 239 240 case USB_ENDPOINT_XFER_INT: 241 data = EPN_BUF_SINGLE | EPN_INTERRUPT; 242 break; 243 244 case USB_ENDPOINT_XFER_ISOC: 245 data = EPN_ISO; 246 break; 247 248 default: 249 data = 0; 250 break; 251 } 252 253 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 254 _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum | ep->direct)); 255 256 if (ep->direct == USB_DIR_OUT) { 257 /*---------------------------------------------------------*/ 258 /* OUT */ 259 data = EPN_EN | EPN_BCLR | EPN_DIR0; 260 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 261 262 data = EPN_ONAK | EPN_OSTL_EN | EPN_OSTL; 263 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 264 265 data = EPN_OUT_EN | EPN_OUT_END_EN; 266 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 267 } else { 268 /*---------------------------------------------------------*/ 269 /* IN */ 270 data = EPN_EN | EPN_BCLR | EPN_AUTO; 271 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 272 273 data = EPN_ISTL; 274 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 275 276 data = EPN_IN_EN | EPN_IN_END_EN; 277 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 278 } 279 280 return 0; 281 } 282 283 /*-------------------------------------------------------------------------*/ 284 /* Release of Endpoint */ 285 static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 286 { 287 u32 num; 288 u32 data; 289 290 if ((ep->epnum == 0) || (udc->vbus_active == 0)) 291 return -EINVAL; 292 293 num = ep->epnum - 1; 294 295 /*-------------------------------------------------------------*/ 296 /* RAM Transfer Address */ 297 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0); 298 299 /*-------------------------------------------------------------*/ 300 /* Interrupt Disable */ 301 data = 1 << (ep->epnum + 8); 302 _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data); 303 304 if (ep->direct == USB_DIR_OUT) { 305 /*---------------------------------------------------------*/ 306 /* OUT */ 307 data = EPN_ONAK | EPN_BCLR; 308 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 309 310 data = EPN_EN | EPN_DIR0; 311 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 312 313 data = EPN_OUT_EN | EPN_OUT_END_EN; 314 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 315 } else { 316 /*---------------------------------------------------------*/ 317 /* IN */ 318 data = EPN_BCLR; 319 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 320 321 data = EPN_EN | EPN_AUTO; 322 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 323 324 data = EPN_IN_EN | EPN_IN_END_EN; 325 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 326 } 327 328 return 0; 329 } 330 331 /*-------------------------------------------------------------------------*/ 332 /* DMA setting (without Endpoint 0) */ 333 static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 334 { 335 u32 num; 336 u32 data; 337 338 data = _nbu2ss_readl(&udc->p_regs->USBSSCONF); 339 if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0)) 340 return; /* Not Support DMA */ 341 342 num = ep->epnum - 1; 343 344 if (ep->direct == USB_DIR_OUT) { 345 /*---------------------------------------------------------*/ 346 /* OUT */ 347 data = ep->ep.maxpacket; 348 _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data); 349 350 /*---------------------------------------------------------*/ 351 /* Transfer Direct */ 352 data = DCR1_EPN_DIR0; 353 _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data); 354 355 /*---------------------------------------------------------*/ 356 /* DMA Mode etc. */ 357 data = EPN_STOP_MODE | EPN_STOP_SET | EPN_DMAMODE0; 358 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data); 359 } else { 360 /*---------------------------------------------------------*/ 361 /* IN */ 362 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPN_AUTO); 363 364 /*---------------------------------------------------------*/ 365 /* DMA Mode etc. */ 366 data = EPN_BURST_SET | EPN_DMAMODE0; 367 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data); 368 } 369 } 370 371 /*-------------------------------------------------------------------------*/ 372 /* DMA setting release */ 373 static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 374 { 375 u32 num; 376 u32 data; 377 struct fc_regs __iomem *preg = udc->p_regs; 378 379 if (udc->vbus_active == 0) 380 return; /* VBUS OFF */ 381 382 data = _nbu2ss_readl(&preg->USBSSCONF); 383 if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0)) 384 return; /* Not Support DMA */ 385 386 num = ep->epnum - 1; 387 388 _nbu2ss_ep_dma_abort(udc, ep); 389 390 if (ep->direct == USB_DIR_OUT) { 391 /*---------------------------------------------------------*/ 392 /* OUT */ 393 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0); 394 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_DIR0); 395 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); 396 } else { 397 /*---------------------------------------------------------*/ 398 /* IN */ 399 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); 400 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); 401 } 402 } 403 404 /*-------------------------------------------------------------------------*/ 405 /* Abort DMA */ 406 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 407 { 408 struct fc_regs __iomem *preg = udc->p_regs; 409 410 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPN_REQEN); 411 mdelay(DMA_DISABLE_TIME); /* DCR1_EPN_REQEN Clear */ 412 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPN_DMA_EN); 413 } 414 415 /*-------------------------------------------------------------------------*/ 416 /* Start IN Transfer */ 417 static void _nbu2ss_ep_in_end(struct nbu2ss_udc *udc, 418 u32 epnum, u32 data32, u32 length) 419 { 420 u32 data; 421 u32 num; 422 struct fc_regs __iomem *preg = udc->p_regs; 423 424 if (length >= sizeof(u32)) 425 return; 426 427 if (epnum == 0) { 428 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO); 429 430 /* Writing of 1-4 bytes */ 431 if (length) 432 _nbu2ss_writel(&preg->EP0_WRITE, data32); 433 434 data = ((length << 5) & EP0_DW) | EP0_DEND; 435 _nbu2ss_writel(&preg->EP0_CONTROL, data); 436 437 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO); 438 } else { 439 num = epnum - 1; 440 441 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); 442 443 /* Writing of 1-4 bytes */ 444 if (length) 445 _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32); 446 447 data = (((length) << 5) & EPN_DW) | EPN_DEND; 448 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data); 449 450 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); 451 } 452 } 453 454 #ifdef USE_DMA 455 /*-------------------------------------------------------------------------*/ 456 static void _nbu2ss_dma_map_single(struct nbu2ss_udc *udc, 457 struct nbu2ss_ep *ep, 458 struct nbu2ss_req *req, u8 direct) 459 { 460 if (req->req.dma == DMA_ADDR_INVALID) { 461 if (req->unaligned) { 462 req->req.dma = ep->phys_buf; 463 } else { 464 req->req.dma = dma_map_single(udc->gadget.dev.parent, 465 req->req.buf, 466 req->req.length, 467 (direct == USB_DIR_IN) 468 ? DMA_TO_DEVICE 469 : DMA_FROM_DEVICE); 470 } 471 req->mapped = 1; 472 } else { 473 if (!req->unaligned) 474 dma_sync_single_for_device(udc->gadget.dev.parent, 475 req->req.dma, 476 req->req.length, 477 (direct == USB_DIR_IN) 478 ? DMA_TO_DEVICE 479 : DMA_FROM_DEVICE); 480 481 req->mapped = 0; 482 } 483 } 484 485 /*-------------------------------------------------------------------------*/ 486 static void _nbu2ss_dma_unmap_single(struct nbu2ss_udc *udc, 487 struct nbu2ss_ep *ep, 488 struct nbu2ss_req *req, u8 direct) 489 { 490 u8 data[4]; 491 u8 *p; 492 u32 count = 0; 493 494 if (direct == USB_DIR_OUT) { 495 count = req->req.actual % 4; 496 if (count) { 497 p = req->req.buf; 498 p += (req->req.actual - count); 499 memcpy(data, p, count); 500 } 501 } 502 503 if (req->mapped) { 504 if (req->unaligned) { 505 if (direct == USB_DIR_OUT) 506 memcpy(req->req.buf, ep->virt_buf, 507 req->req.actual & 0xfffffffc); 508 } else { 509 dma_unmap_single(udc->gadget.dev.parent, 510 req->req.dma, req->req.length, 511 (direct == USB_DIR_IN) 512 ? DMA_TO_DEVICE 513 : DMA_FROM_DEVICE); 514 } 515 req->req.dma = DMA_ADDR_INVALID; 516 req->mapped = 0; 517 } else { 518 if (!req->unaligned) 519 dma_sync_single_for_cpu(udc->gadget.dev.parent, 520 req->req.dma, req->req.length, 521 (direct == USB_DIR_IN) 522 ? DMA_TO_DEVICE 523 : DMA_FROM_DEVICE); 524 } 525 526 if (count) { 527 p = req->req.buf; 528 p += (req->req.actual - count); 529 memcpy(p, data, count); 530 } 531 } 532 #endif 533 534 /*-------------------------------------------------------------------------*/ 535 /* Endpoint 0 OUT Transfer (PIO) */ 536 static int ep0_out_pio(struct nbu2ss_udc *udc, u8 *buf, u32 length) 537 { 538 u32 i; 539 u32 numreads = length / sizeof(u32); 540 union usb_reg_access *buf32 = (union usb_reg_access *)buf; 541 542 if (!numreads) 543 return 0; 544 545 /* PIO Read */ 546 for (i = 0; i < numreads; i++) { 547 buf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ); 548 buf32++; 549 } 550 551 return numreads * sizeof(u32); 552 } 553 554 /*-------------------------------------------------------------------------*/ 555 /* Endpoint 0 OUT Transfer (PIO, OverBytes) */ 556 static int ep0_out_overbytes(struct nbu2ss_udc *udc, u8 *p_buf, u32 length) 557 { 558 u32 i; 559 u32 i_read_size = 0; 560 union usb_reg_access temp_32; 561 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; 562 563 if ((length > 0) && (length < sizeof(u32))) { 564 temp_32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ); 565 for (i = 0 ; i < length ; i++) 566 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i]; 567 i_read_size += length; 568 } 569 570 return i_read_size; 571 } 572 573 /*-------------------------------------------------------------------------*/ 574 /* Endpoint 0 IN Transfer (PIO) */ 575 static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *p_buf, u32 length) 576 { 577 u32 i; 578 u32 i_max_length = EP0_PACKETSIZE; 579 u32 i_word_length = 0; 580 u32 i_write_length = 0; 581 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; 582 583 /*------------------------------------------------------------*/ 584 /* Transfer Length */ 585 if (i_max_length < length) 586 i_word_length = i_max_length / sizeof(u32); 587 else 588 i_word_length = length / sizeof(u32); 589 590 /*------------------------------------------------------------*/ 591 /* PIO */ 592 for (i = 0; i < i_word_length; i++) { 593 _nbu2ss_writel(&udc->p_regs->EP0_WRITE, p_buf_32->dw); 594 p_buf_32++; 595 i_write_length += sizeof(u32); 596 } 597 598 return i_write_length; 599 } 600 601 /*-------------------------------------------------------------------------*/ 602 /* Endpoint 0 IN Transfer (PIO, OverBytes) */ 603 static int ep0_in_overbytes(struct nbu2ss_udc *udc, 604 u8 *p_buf, 605 u32 i_remain_size) 606 { 607 u32 i; 608 union usb_reg_access temp_32; 609 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; 610 611 if ((i_remain_size > 0) && (i_remain_size < sizeof(u32))) { 612 for (i = 0 ; i < i_remain_size ; i++) 613 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i]; 614 _nbu2ss_ep_in_end(udc, 0, temp_32.dw, i_remain_size); 615 616 return i_remain_size; 617 } 618 619 return 0; 620 } 621 622 /*-------------------------------------------------------------------------*/ 623 /* Transfer NULL Packet (Epndoint 0) */ 624 static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag) 625 { 626 u32 data; 627 628 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 629 data &= ~(u32)EP0_INAK; 630 631 if (pid_flag) 632 data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND); 633 else 634 data |= (EP0_INAK_EN | EP0_DEND); 635 636 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); 637 638 return 0; 639 } 640 641 /*-------------------------------------------------------------------------*/ 642 /* Receive NULL Packet (Endpoint 0) */ 643 static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag) 644 { 645 u32 data; 646 647 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 648 data &= ~(u32)EP0_ONAK; 649 650 if (pid_flag) 651 data |= EP0_PIDCLR; 652 653 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); 654 655 return 0; 656 } 657 658 /*-------------------------------------------------------------------------*/ 659 static int _nbu2ss_ep0_in_transfer(struct nbu2ss_udc *udc, 660 struct nbu2ss_req *req) 661 { 662 u8 *p_buffer; /* IN Data Buffer */ 663 u32 data; 664 u32 i_remain_size = 0; 665 int result = 0; 666 667 /*-------------------------------------------------------------*/ 668 /* End confirmation */ 669 if (req->req.actual == req->req.length) { 670 if ((req->req.actual % EP0_PACKETSIZE) == 0) { 671 if (req->zero) { 672 req->zero = false; 673 EP0_send_NULL(udc, false); 674 return 1; 675 } 676 } 677 678 return 0; /* Transfer End */ 679 } 680 681 /*-------------------------------------------------------------*/ 682 /* NAK release */ 683 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 684 data |= EP0_INAK_EN; 685 data &= ~(u32)EP0_INAK; 686 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); 687 688 i_remain_size = req->req.length - req->req.actual; 689 p_buffer = (u8 *)req->req.buf; 690 p_buffer += req->req.actual; 691 692 /*-------------------------------------------------------------*/ 693 /* Data transfer */ 694 result = EP0_in_PIO(udc, p_buffer, i_remain_size); 695 696 req->div_len = result; 697 i_remain_size -= result; 698 699 if (i_remain_size == 0) { 700 EP0_send_NULL(udc, false); 701 return result; 702 } 703 704 if ((i_remain_size < sizeof(u32)) && (result != EP0_PACKETSIZE)) { 705 p_buffer += result; 706 result += ep0_in_overbytes(udc, p_buffer, i_remain_size); 707 req->div_len = result; 708 } 709 710 return result; 711 } 712 713 /*-------------------------------------------------------------------------*/ 714 static int _nbu2ss_ep0_out_transfer(struct nbu2ss_udc *udc, 715 struct nbu2ss_req *req) 716 { 717 u8 *p_buffer; 718 u32 i_remain_size; 719 u32 i_recv_length; 720 int result = 0; 721 int f_rcv_zero; 722 723 /*-------------------------------------------------------------*/ 724 /* Receive data confirmation */ 725 i_recv_length = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA; 726 if (i_recv_length != 0) { 727 f_rcv_zero = 0; 728 729 i_remain_size = req->req.length - req->req.actual; 730 p_buffer = (u8 *)req->req.buf; 731 p_buffer += req->req.actual; 732 733 result = ep0_out_pio(udc, p_buffer 734 , min(i_remain_size, i_recv_length)); 735 if (result < 0) 736 return result; 737 738 req->req.actual += result; 739 i_recv_length -= result; 740 741 if ((i_recv_length > 0) && (i_recv_length < sizeof(u32))) { 742 p_buffer += result; 743 i_remain_size -= result; 744 745 result = ep0_out_overbytes(udc, p_buffer 746 , min(i_remain_size, i_recv_length)); 747 req->req.actual += result; 748 } 749 } else { 750 f_rcv_zero = 1; 751 } 752 753 /*-------------------------------------------------------------*/ 754 /* End confirmation */ 755 if (req->req.actual == req->req.length) { 756 if ((req->req.actual % EP0_PACKETSIZE) == 0) { 757 if (req->zero) { 758 req->zero = false; 759 EP0_receive_NULL(udc, false); 760 return 1; 761 } 762 } 763 764 return 0; /* Transfer End */ 765 } 766 767 if ((req->req.actual % EP0_PACKETSIZE) != 0) 768 return 0; /* Short Packet Transfer End */ 769 770 if (req->req.actual > req->req.length) { 771 dev_err(udc->dev, " *** Overrun Error\n"); 772 return -EOVERFLOW; 773 } 774 775 if (f_rcv_zero != 0) { 776 i_remain_size = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 777 if (i_remain_size & EP0_ONAK) { 778 /*---------------------------------------------------*/ 779 /* NACK release */ 780 _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK); 781 } 782 result = 1; 783 } 784 785 return result; 786 } 787 788 /*-------------------------------------------------------------------------*/ 789 static int _nbu2ss_out_dma(struct nbu2ss_udc *udc, struct nbu2ss_req *req, 790 u32 num, u32 length) 791 { 792 dma_addr_t p_buffer; 793 u32 mpkt; 794 u32 lmpkt; 795 u32 dmacnt; 796 u32 burst = 1; 797 u32 data; 798 int result; 799 struct fc_regs __iomem *preg = udc->p_regs; 800 801 if (req->dma_flag) 802 return 1; /* DMA is forwarded */ 803 804 req->dma_flag = true; 805 p_buffer = req->req.dma; 806 p_buffer += req->req.actual; 807 808 /* DMA Address */ 809 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer); 810 811 /* Number of transfer packets */ 812 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT; 813 dmacnt = length / mpkt; 814 lmpkt = (length % mpkt) & ~(u32)0x03; 815 816 if (dmacnt > DMA_MAX_COUNT) { 817 dmacnt = DMA_MAX_COUNT; 818 lmpkt = 0; 819 } else if (lmpkt != 0) { 820 if (dmacnt == 0) 821 burst = 0; /* Burst OFF */ 822 dmacnt++; 823 } 824 825 data = mpkt | (lmpkt << 16); 826 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data); 827 828 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_DIR0 | DCR1_EPN_REQEN; 829 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data); 830 831 if (burst == 0) { 832 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0); 833 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET); 834 } else { 835 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT 836 , (dmacnt << 16)); 837 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET); 838 } 839 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN); 840 841 result = length & ~(u32)0x03; 842 req->div_len = result; 843 844 return result; 845 } 846 847 /*-------------------------------------------------------------------------*/ 848 static int _nbu2ss_epn_out_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep, 849 struct nbu2ss_req *req, u32 length) 850 { 851 u8 *p_buffer; 852 u32 i; 853 u32 data; 854 u32 i_word_length; 855 union usb_reg_access temp_32; 856 union usb_reg_access *p_buf_32; 857 int result = 0; 858 struct fc_regs __iomem *preg = udc->p_regs; 859 860 if (req->dma_flag) 861 return 1; /* DMA is forwarded */ 862 863 if (length == 0) 864 return 0; 865 866 p_buffer = (u8 *)req->req.buf; 867 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual); 868 869 i_word_length = length / sizeof(u32); 870 if (i_word_length > 0) { 871 /*---------------------------------------------------------*/ 872 /* Copy of every four bytes */ 873 for (i = 0; i < i_word_length; i++) { 874 p_buf_32->dw = 875 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ); 876 p_buf_32++; 877 } 878 result = i_word_length * sizeof(u32); 879 } 880 881 data = length - result; 882 if (data > 0) { 883 /*---------------------------------------------------------*/ 884 /* Copy of fraction byte */ 885 temp_32.dw = 886 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ); 887 for (i = 0 ; i < data ; i++) 888 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i]; 889 result += data; 890 } 891 892 req->req.actual += result; 893 894 if ((req->req.actual == req->req.length) || 895 ((req->req.actual % ep->ep.maxpacket) != 0)) { 896 result = 0; 897 } 898 899 return result; 900 } 901 902 /*-------------------------------------------------------------------------*/ 903 static int _nbu2ss_epn_out_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep, 904 struct nbu2ss_req *req, u32 data_size) 905 { 906 u32 num; 907 u32 i_buf_size; 908 int nret = 1; 909 910 if (ep->epnum == 0) 911 return -EINVAL; 912 913 num = ep->epnum - 1; 914 915 i_buf_size = min((req->req.length - req->req.actual), data_size); 916 917 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) && 918 (i_buf_size >= sizeof(u32))) { 919 nret = _nbu2ss_out_dma(udc, req, num, i_buf_size); 920 } else { 921 i_buf_size = min_t(u32, i_buf_size, ep->ep.maxpacket); 922 nret = _nbu2ss_epn_out_pio(udc, ep, req, i_buf_size); 923 } 924 925 return nret; 926 } 927 928 /*-------------------------------------------------------------------------*/ 929 static int _nbu2ss_epn_out_transfer(struct nbu2ss_udc *udc, 930 struct nbu2ss_ep *ep, 931 struct nbu2ss_req *req) 932 { 933 u32 num; 934 u32 i_recv_length; 935 int result = 1; 936 struct fc_regs __iomem *preg = udc->p_regs; 937 938 if (ep->epnum == 0) 939 return -EINVAL; 940 941 num = ep->epnum - 1; 942 943 /*-------------------------------------------------------------*/ 944 /* Receive Length */ 945 i_recv_length = 946 _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPN_LDATA; 947 948 if (i_recv_length != 0) { 949 result = _nbu2ss_epn_out_data(udc, ep, req, i_recv_length); 950 if (i_recv_length < ep->ep.maxpacket) { 951 if (i_recv_length == result) { 952 req->req.actual += result; 953 result = 0; 954 } 955 } 956 } else { 957 if ((req->req.actual == req->req.length) || 958 ((req->req.actual % ep->ep.maxpacket) != 0)) { 959 result = 0; 960 } 961 } 962 963 if (result == 0) { 964 if ((req->req.actual % ep->ep.maxpacket) == 0) { 965 if (req->zero) { 966 req->zero = false; 967 return 1; 968 } 969 } 970 } 971 972 if (req->req.actual > req->req.length) { 973 dev_err(udc->dev, " Overrun Error\n"); 974 dev_err(udc->dev, " actual = %d, length = %d\n", 975 req->req.actual, req->req.length); 976 result = -EOVERFLOW; 977 } 978 979 return result; 980 } 981 982 /*-------------------------------------------------------------------------*/ 983 static int _nbu2ss_in_dma(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep, 984 struct nbu2ss_req *req, u32 num, u32 length) 985 { 986 dma_addr_t p_buffer; 987 u32 mpkt; /* MaxPacketSize */ 988 u32 lmpkt; /* Last Packet Data Size */ 989 u32 dmacnt; /* IN Data Size */ 990 u32 i_write_length; 991 u32 data; 992 int result = -EINVAL; 993 struct fc_regs __iomem *preg = udc->p_regs; 994 995 if (req->dma_flag) 996 return 1; /* DMA is forwarded */ 997 998 #ifdef USE_DMA 999 if (req->req.actual == 0) 1000 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN); 1001 #endif 1002 req->dma_flag = true; 1003 1004 /* MAX Packet Size */ 1005 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT; 1006 1007 if ((DMA_MAX_COUNT * mpkt) < length) 1008 i_write_length = DMA_MAX_COUNT * mpkt; 1009 else 1010 i_write_length = length; 1011 1012 /*------------------------------------------------------------*/ 1013 /* Number of transmission packets */ 1014 if (mpkt < i_write_length) { 1015 dmacnt = i_write_length / mpkt; 1016 lmpkt = (i_write_length % mpkt) & ~(u32)0x3; 1017 if (lmpkt != 0) 1018 dmacnt++; 1019 else 1020 lmpkt = mpkt & ~(u32)0x3; 1021 1022 } else { 1023 dmacnt = 1; 1024 lmpkt = i_write_length & ~(u32)0x3; 1025 } 1026 1027 /* Packet setting */ 1028 data = mpkt | (lmpkt << 16); 1029 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data); 1030 1031 /* Address setting */ 1032 p_buffer = req->req.dma; 1033 p_buffer += req->req.actual; 1034 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer); 1035 1036 /* Packet and DMA setting */ 1037 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_REQEN; 1038 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data); 1039 1040 /* Packet setting of EPC */ 1041 data = dmacnt << 16; 1042 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data); 1043 1044 /*DMA setting of EPC */ 1045 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN); 1046 1047 result = i_write_length & ~(u32)0x3; 1048 req->div_len = result; 1049 1050 return result; 1051 } 1052 1053 /*-------------------------------------------------------------------------*/ 1054 static int _nbu2ss_epn_in_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep, 1055 struct nbu2ss_req *req, u32 length) 1056 { 1057 u8 *p_buffer; 1058 u32 i; 1059 u32 data; 1060 u32 i_word_length; 1061 union usb_reg_access temp_32; 1062 union usb_reg_access *p_buf_32 = NULL; 1063 int result = 0; 1064 struct fc_regs __iomem *preg = udc->p_regs; 1065 1066 if (req->dma_flag) 1067 return 1; /* DMA is forwarded */ 1068 1069 if (length > 0) { 1070 p_buffer = (u8 *)req->req.buf; 1071 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual); 1072 1073 i_word_length = length / sizeof(u32); 1074 if (i_word_length > 0) { 1075 for (i = 0; i < i_word_length; i++) { 1076 _nbu2ss_writel( 1077 &preg->EP_REGS[ep->epnum - 1].EP_WRITE, 1078 p_buf_32->dw); 1079 1080 p_buf_32++; 1081 } 1082 result = i_word_length * sizeof(u32); 1083 } 1084 } 1085 1086 if (result != ep->ep.maxpacket) { 1087 data = length - result; 1088 temp_32.dw = 0; 1089 for (i = 0 ; i < data ; i++) 1090 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i]; 1091 1092 _nbu2ss_ep_in_end(udc, ep->epnum, temp_32.dw, data); 1093 result += data; 1094 } 1095 1096 req->div_len = result; 1097 1098 return result; 1099 } 1100 1101 /*-------------------------------------------------------------------------*/ 1102 static int _nbu2ss_epn_in_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep, 1103 struct nbu2ss_req *req, u32 data_size) 1104 { 1105 u32 num; 1106 int nret = 1; 1107 1108 if (ep->epnum == 0) 1109 return -EINVAL; 1110 1111 num = ep->epnum - 1; 1112 1113 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) && 1114 (data_size >= sizeof(u32))) { 1115 nret = _nbu2ss_in_dma(udc, ep, req, num, data_size); 1116 } else { 1117 data_size = min_t(u32, data_size, ep->ep.maxpacket); 1118 nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size); 1119 } 1120 1121 return nret; 1122 } 1123 1124 /*-------------------------------------------------------------------------*/ 1125 static int _nbu2ss_epn_in_transfer(struct nbu2ss_udc *udc, 1126 struct nbu2ss_ep *ep, struct nbu2ss_req *req) 1127 { 1128 u32 num; 1129 u32 i_buf_size; 1130 int result = 0; 1131 u32 status; 1132 1133 if (ep->epnum == 0) 1134 return -EINVAL; 1135 1136 num = ep->epnum - 1; 1137 1138 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS); 1139 1140 /*-------------------------------------------------------------*/ 1141 /* State confirmation of FIFO */ 1142 if (req->req.actual == 0) { 1143 if ((status & EPN_IN_EMPTY) == 0) 1144 return 1; /* Not Empty */ 1145 1146 } else { 1147 if ((status & EPN_IN_FULL) != 0) 1148 return 1; /* Not Empty */ 1149 } 1150 1151 /*-------------------------------------------------------------*/ 1152 /* Start transfer */ 1153 i_buf_size = req->req.length - req->req.actual; 1154 if (i_buf_size > 0) 1155 result = _nbu2ss_epn_in_data(udc, ep, req, i_buf_size); 1156 else if (req->req.length == 0) 1157 _nbu2ss_zero_len_pkt(udc, ep->epnum); 1158 1159 return result; 1160 } 1161 1162 /*-------------------------------------------------------------------------*/ 1163 static int _nbu2ss_start_transfer(struct nbu2ss_udc *udc, 1164 struct nbu2ss_ep *ep, 1165 struct nbu2ss_req *req, 1166 bool bflag) 1167 { 1168 int nret = -EINVAL; 1169 1170 req->dma_flag = false; 1171 req->div_len = 0; 1172 1173 if (req->req.length == 0) { 1174 req->zero = false; 1175 } else { 1176 if ((req->req.length % ep->ep.maxpacket) == 0) 1177 req->zero = req->req.zero; 1178 else 1179 req->zero = false; 1180 } 1181 1182 if (ep->epnum == 0) { 1183 /* EP0 */ 1184 switch (udc->ep0state) { 1185 case EP0_IN_DATA_PHASE: 1186 nret = _nbu2ss_ep0_in_transfer(udc, req); 1187 break; 1188 1189 case EP0_OUT_DATA_PHASE: 1190 nret = _nbu2ss_ep0_out_transfer(udc, req); 1191 break; 1192 1193 case EP0_IN_STATUS_PHASE: 1194 nret = EP0_send_NULL(udc, true); 1195 break; 1196 1197 default: 1198 break; 1199 } 1200 1201 } else { 1202 /* EPN */ 1203 if (ep->direct == USB_DIR_OUT) { 1204 /* OUT */ 1205 if (!bflag) 1206 nret = _nbu2ss_epn_out_transfer(udc, ep, req); 1207 } else { 1208 /* IN */ 1209 nret = _nbu2ss_epn_in_transfer(udc, ep, req); 1210 } 1211 } 1212 1213 return nret; 1214 } 1215 1216 /*-------------------------------------------------------------------------*/ 1217 static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep) 1218 { 1219 u32 length; 1220 bool bflag = false; 1221 struct nbu2ss_req *req; 1222 1223 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1224 if (!req) 1225 return; 1226 1227 if (ep->epnum > 0) { 1228 length = _nbu2ss_readl( 1229 &ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT); 1230 1231 length &= EPN_LDATA; 1232 if (length < ep->ep.maxpacket) 1233 bflag = true; 1234 } 1235 1236 _nbu2ss_start_transfer(ep->udc, ep, req, bflag); 1237 } 1238 1239 /*-------------------------------------------------------------------------*/ 1240 /* Endpoint Toggle Reset */ 1241 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs) 1242 { 1243 u8 num; 1244 u32 data; 1245 1246 if ((ep_adrs == 0) || (ep_adrs == 0x80)) 1247 return; 1248 1249 num = (ep_adrs & 0x7F) - 1; 1250 1251 if (ep_adrs & USB_DIR_IN) 1252 data = EPN_IPIDCLR; 1253 else 1254 data = EPN_BCLR | EPN_OPIDCLR; 1255 1256 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 1257 } 1258 1259 /*-------------------------------------------------------------------------*/ 1260 /* Endpoint STALL set */ 1261 static void _nbu2ss_set_endpoint_stall(struct nbu2ss_udc *udc, 1262 u8 ep_adrs, bool bstall) 1263 { 1264 u8 num, epnum; 1265 u32 data; 1266 struct nbu2ss_ep *ep; 1267 struct fc_regs __iomem *preg = udc->p_regs; 1268 1269 if ((ep_adrs == 0) || (ep_adrs == 0x80)) { 1270 if (bstall) { 1271 /* Set STALL */ 1272 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL); 1273 } else { 1274 /* Clear STALL */ 1275 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL); 1276 } 1277 } else { 1278 epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK; 1279 num = epnum - 1; 1280 ep = &udc->ep[epnum]; 1281 1282 if (bstall) { 1283 /* Set STALL */ 1284 ep->halted = true; 1285 1286 if (ep_adrs & USB_DIR_IN) 1287 data = EPN_BCLR | EPN_ISTL; 1288 else 1289 data = EPN_OSTL_EN | EPN_OSTL; 1290 1291 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data); 1292 } else { 1293 if (ep_adrs & USB_DIR_IN) { 1294 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL 1295 , EPN_ISTL); 1296 } else { 1297 data = 1298 _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL); 1299 1300 data &= ~EPN_OSTL; 1301 data |= EPN_OSTL_EN; 1302 1303 _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL 1304 , data); 1305 } 1306 1307 /* Clear STALL */ 1308 ep->stalled = false; 1309 if (ep->halted) { 1310 ep->halted = false; 1311 _nbu2ss_restert_transfer(ep); 1312 } 1313 } 1314 } 1315 } 1316 1317 /*-------------------------------------------------------------------------*/ 1318 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode) 1319 { 1320 u32 data; 1321 1322 if (mode > MAX_TEST_MODE_NUM) 1323 return; 1324 1325 dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode); 1326 1327 data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL); 1328 data &= ~TEST_FORCE_ENABLE; 1329 data |= mode << TEST_MODE_SHIFT; 1330 1331 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data); 1332 _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN); 1333 } 1334 1335 /*-------------------------------------------------------------------------*/ 1336 static int _nbu2ss_set_feature_device(struct nbu2ss_udc *udc, 1337 u16 selector, u16 wIndex) 1338 { 1339 int result = -EOPNOTSUPP; 1340 1341 switch (selector) { 1342 case USB_DEVICE_REMOTE_WAKEUP: 1343 if (wIndex == 0x0000) { 1344 udc->remote_wakeup = U2F_ENABLE; 1345 result = 0; 1346 } 1347 break; 1348 1349 case USB_DEVICE_TEST_MODE: 1350 wIndex >>= 8; 1351 if (wIndex <= MAX_TEST_MODE_NUM) 1352 result = 0; 1353 break; 1354 1355 default: 1356 break; 1357 } 1358 1359 return result; 1360 } 1361 1362 /*-------------------------------------------------------------------------*/ 1363 static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs) 1364 { 1365 u8 epnum; 1366 u32 data = 0, bit_data; 1367 struct fc_regs __iomem *preg = udc->p_regs; 1368 1369 epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK; 1370 if (epnum == 0) { 1371 data = _nbu2ss_readl(&preg->EP0_CONTROL); 1372 bit_data = EP0_STL; 1373 1374 } else { 1375 data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL); 1376 if ((data & EPN_EN) == 0) 1377 return -1; 1378 1379 if (ep_adrs & USB_ENDPOINT_DIR_MASK) 1380 bit_data = EPN_ISTL; 1381 else 1382 bit_data = EPN_OSTL; 1383 } 1384 1385 if ((data & bit_data) == 0) 1386 return 0; 1387 return 1; 1388 } 1389 1390 /*-------------------------------------------------------------------------*/ 1391 static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset) 1392 { 1393 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK); 1394 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN); 1395 u16 selector = le16_to_cpu(udc->ctrl.wValue); 1396 u16 wIndex = le16_to_cpu(udc->ctrl.wIndex); 1397 u8 ep_adrs; 1398 int result = -EOPNOTSUPP; 1399 1400 if ((udc->ctrl.wLength != 0x0000) || 1401 (direction != USB_DIR_OUT)) { 1402 return -EINVAL; 1403 } 1404 1405 switch (recipient) { 1406 case USB_RECIP_DEVICE: 1407 if (bset) 1408 result = 1409 _nbu2ss_set_feature_device(udc, selector, wIndex); 1410 break; 1411 1412 case USB_RECIP_ENDPOINT: 1413 if (0x0000 == (wIndex & 0xFF70)) { 1414 if (selector == USB_ENDPOINT_HALT) { 1415 ep_adrs = wIndex & 0xFF; 1416 if (!bset) { 1417 _nbu2ss_endpoint_toggle_reset(udc, 1418 ep_adrs); 1419 } 1420 1421 _nbu2ss_set_endpoint_stall(udc, ep_adrs, bset); 1422 1423 result = 0; 1424 } 1425 } 1426 break; 1427 1428 default: 1429 break; 1430 } 1431 1432 if (result >= 0) 1433 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0); 1434 1435 return result; 1436 } 1437 1438 /*-------------------------------------------------------------------------*/ 1439 static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc) 1440 { 1441 u32 data; 1442 enum usb_device_speed speed = USB_SPEED_FULL; 1443 1444 data = _nbu2ss_readl(&udc->p_regs->USB_STATUS); 1445 if (data & HIGH_SPEED) 1446 speed = USB_SPEED_HIGH; 1447 1448 return speed; 1449 } 1450 1451 /*-------------------------------------------------------------------------*/ 1452 static void _nbu2ss_epn_set_stall(struct nbu2ss_udc *udc, 1453 struct nbu2ss_ep *ep) 1454 { 1455 u8 ep_adrs; 1456 u32 regdata; 1457 int limit_cnt = 0; 1458 1459 struct fc_regs __iomem *preg = udc->p_regs; 1460 1461 if (ep->direct == USB_DIR_IN) { 1462 for (limit_cnt = 0 1463 ; limit_cnt < IN_DATA_EMPTY_COUNT 1464 ; limit_cnt++) { 1465 regdata = _nbu2ss_readl( 1466 &preg->EP_REGS[ep->epnum - 1].EP_STATUS); 1467 1468 if ((regdata & EPN_IN_DATA) == 0) 1469 break; 1470 1471 mdelay(1); 1472 } 1473 } 1474 1475 ep_adrs = ep->epnum | ep->direct; 1476 _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1); 1477 } 1478 1479 /*-------------------------------------------------------------------------*/ 1480 static int std_req_get_status(struct nbu2ss_udc *udc) 1481 { 1482 u32 length; 1483 u16 status_data = 0; 1484 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK); 1485 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN); 1486 u8 ep_adrs; 1487 int result = -EINVAL; 1488 1489 if ((udc->ctrl.wValue != 0x0000) || (direction != USB_DIR_IN)) 1490 return result; 1491 1492 length = 1493 min_t(u16, le16_to_cpu(udc->ctrl.wLength), sizeof(status_data)); 1494 switch (recipient) { 1495 case USB_RECIP_DEVICE: 1496 if (udc->ctrl.wIndex == 0x0000) { 1497 if (udc->gadget.is_selfpowered) 1498 status_data |= BIT(USB_DEVICE_SELF_POWERED); 1499 1500 if (udc->remote_wakeup) 1501 status_data |= BIT(USB_DEVICE_REMOTE_WAKEUP); 1502 1503 result = 0; 1504 } 1505 break; 1506 1507 case USB_RECIP_ENDPOINT: 1508 if (0x0000 == (le16_to_cpu(udc->ctrl.wIndex) & 0xFF70)) { 1509 ep_adrs = (u8)(le16_to_cpu(udc->ctrl.wIndex) & 0xFF); 1510 result = _nbu2ss_get_ep_stall(udc, ep_adrs); 1511 1512 if (result > 0) 1513 status_data |= BIT(USB_ENDPOINT_HALT); 1514 } 1515 break; 1516 1517 default: 1518 break; 1519 } 1520 1521 if (result >= 0) { 1522 memcpy(udc->ep0_buf, &status_data, length); 1523 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length); 1524 _nbu2ss_ep0_in_transfer(udc, &udc->ep0_req); 1525 1526 } else { 1527 dev_err(udc->dev, " Error GET_STATUS\n"); 1528 } 1529 1530 return result; 1531 } 1532 1533 /*-------------------------------------------------------------------------*/ 1534 static int std_req_clear_feature(struct nbu2ss_udc *udc) 1535 { 1536 return _nbu2ss_req_feature(udc, false); 1537 } 1538 1539 /*-------------------------------------------------------------------------*/ 1540 static int std_req_set_feature(struct nbu2ss_udc *udc) 1541 { 1542 return _nbu2ss_req_feature(udc, true); 1543 } 1544 1545 /*-------------------------------------------------------------------------*/ 1546 static int std_req_set_address(struct nbu2ss_udc *udc) 1547 { 1548 int result = 0; 1549 u32 wValue = le16_to_cpu(udc->ctrl.wValue); 1550 1551 if ((udc->ctrl.bRequestType != 0x00) || 1552 (udc->ctrl.wIndex != 0x0000) || 1553 (udc->ctrl.wLength != 0x0000)) { 1554 return -EINVAL; 1555 } 1556 1557 if (wValue != (wValue & 0x007F)) 1558 return -EINVAL; 1559 1560 wValue <<= USB_ADRS_SHIFT; 1561 1562 _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue); 1563 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0); 1564 1565 return result; 1566 } 1567 1568 /*-------------------------------------------------------------------------*/ 1569 static int std_req_set_configuration(struct nbu2ss_udc *udc) 1570 { 1571 u32 config_value = (u32)(le16_to_cpu(udc->ctrl.wValue) & 0x00ff); 1572 1573 if ((udc->ctrl.wIndex != 0x0000) || 1574 (udc->ctrl.wLength != 0x0000) || 1575 (udc->ctrl.bRequestType != 0x00)) { 1576 return -EINVAL; 1577 } 1578 1579 udc->curr_config = config_value; 1580 1581 if (config_value > 0) { 1582 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF); 1583 udc->devstate = USB_STATE_CONFIGURED; 1584 1585 } else { 1586 _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF); 1587 udc->devstate = USB_STATE_ADDRESS; 1588 } 1589 1590 return 0; 1591 } 1592 1593 /*-------------------------------------------------------------------------*/ 1594 static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata) 1595 { 1596 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0); 1597 pdata++; 1598 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1); 1599 } 1600 1601 /*-------------------------------------------------------------------------*/ 1602 static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc) 1603 { 1604 bool bcall_back = true; 1605 int nret = -EINVAL; 1606 struct usb_ctrlrequest *p_ctrl; 1607 1608 p_ctrl = &udc->ctrl; 1609 _nbu2ss_read_request_data(udc, (u32 *)p_ctrl); 1610 1611 /* ep0 state control */ 1612 if (p_ctrl->wLength == 0) { 1613 udc->ep0state = EP0_IN_STATUS_PHASE; 1614 1615 } else { 1616 if (p_ctrl->bRequestType & USB_DIR_IN) 1617 udc->ep0state = EP0_IN_DATA_PHASE; 1618 else 1619 udc->ep0state = EP0_OUT_DATA_PHASE; 1620 } 1621 1622 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 1623 switch (p_ctrl->bRequest) { 1624 case USB_REQ_GET_STATUS: 1625 nret = std_req_get_status(udc); 1626 bcall_back = false; 1627 break; 1628 1629 case USB_REQ_CLEAR_FEATURE: 1630 nret = std_req_clear_feature(udc); 1631 bcall_back = false; 1632 break; 1633 1634 case USB_REQ_SET_FEATURE: 1635 nret = std_req_set_feature(udc); 1636 bcall_back = false; 1637 break; 1638 1639 case USB_REQ_SET_ADDRESS: 1640 nret = std_req_set_address(udc); 1641 bcall_back = false; 1642 break; 1643 1644 case USB_REQ_SET_CONFIGURATION: 1645 nret = std_req_set_configuration(udc); 1646 break; 1647 1648 default: 1649 break; 1650 } 1651 } 1652 1653 if (!bcall_back) { 1654 if (udc->ep0state == EP0_IN_STATUS_PHASE) { 1655 if (nret >= 0) { 1656 /*--------------------------------------*/ 1657 /* Status Stage */ 1658 nret = EP0_send_NULL(udc, true); 1659 } 1660 } 1661 1662 } else { 1663 spin_unlock(&udc->lock); 1664 nret = udc->driver->setup(&udc->gadget, &udc->ctrl); 1665 spin_lock(&udc->lock); 1666 } 1667 1668 if (nret < 0) 1669 udc->ep0state = EP0_IDLE; 1670 1671 return nret; 1672 } 1673 1674 /*-------------------------------------------------------------------------*/ 1675 static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc) 1676 { 1677 int nret; 1678 struct nbu2ss_req *req; 1679 struct nbu2ss_ep *ep = &udc->ep[0]; 1680 1681 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1682 if (!req) 1683 req = &udc->ep0_req; 1684 1685 req->req.actual += req->div_len; 1686 req->div_len = 0; 1687 1688 nret = _nbu2ss_ep0_in_transfer(udc, req); 1689 if (nret == 0) { 1690 udc->ep0state = EP0_OUT_STATUS_PAHSE; 1691 EP0_receive_NULL(udc, true); 1692 } 1693 1694 return 0; 1695 } 1696 1697 /*-------------------------------------------------------------------------*/ 1698 static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc) 1699 { 1700 int nret; 1701 struct nbu2ss_req *req; 1702 struct nbu2ss_ep *ep = &udc->ep[0]; 1703 1704 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1705 if (!req) 1706 req = &udc->ep0_req; 1707 1708 nret = _nbu2ss_ep0_out_transfer(udc, req); 1709 if (nret == 0) { 1710 udc->ep0state = EP0_IN_STATUS_PHASE; 1711 EP0_send_NULL(udc, true); 1712 1713 } else if (nret < 0) { 1714 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR); 1715 req->req.status = nret; 1716 } 1717 1718 return 0; 1719 } 1720 1721 /*-------------------------------------------------------------------------*/ 1722 static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc) 1723 { 1724 struct nbu2ss_req *req; 1725 struct nbu2ss_ep *ep = &udc->ep[0]; 1726 1727 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1728 if (!req) { 1729 req = &udc->ep0_req; 1730 if (req->req.complete) 1731 req->req.complete(&ep->ep, &req->req); 1732 1733 } else { 1734 if (req->req.complete) 1735 _nbu2ss_ep_done(ep, req, 0); 1736 } 1737 1738 udc->ep0state = EP0_IDLE; 1739 1740 return 0; 1741 } 1742 1743 /*-------------------------------------------------------------------------*/ 1744 static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc) 1745 { 1746 int i; 1747 u32 status; 1748 u32 intr; 1749 int nret = -1; 1750 1751 status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS); 1752 intr = status & EP0_STATUS_RW_BIT; 1753 _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~intr); 1754 1755 status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT 1756 | STG_END_INT | EP0_OUT_NULL_INT); 1757 1758 if (status == 0) { 1759 dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__); 1760 dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr); 1761 return; 1762 } 1763 1764 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1765 udc->gadget.speed = _nbu2ss_get_speed(udc); 1766 1767 for (i = 0; i < EP0_END_XFER; i++) { 1768 switch (udc->ep0state) { 1769 case EP0_IDLE: 1770 if (status & SETUP_INT) { 1771 status = 0; 1772 nret = _nbu2ss_decode_request(udc); 1773 } 1774 break; 1775 1776 case EP0_IN_DATA_PHASE: 1777 if (status & EP0_IN_INT) { 1778 status &= ~EP0_IN_INT; 1779 nret = _nbu2ss_ep0_in_data_stage(udc); 1780 } 1781 break; 1782 1783 case EP0_OUT_DATA_PHASE: 1784 if (status & EP0_OUT_INT) { 1785 status &= ~EP0_OUT_INT; 1786 nret = _nbu2ss_ep0_out_data_stage(udc); 1787 } 1788 break; 1789 1790 case EP0_IN_STATUS_PHASE: 1791 if ((status & STG_END_INT) || (status & SETUP_INT)) { 1792 status &= ~(STG_END_INT | EP0_IN_INT); 1793 nret = _nbu2ss_ep0_status_stage(udc); 1794 } 1795 break; 1796 1797 case EP0_OUT_STATUS_PAHSE: 1798 if ((status & STG_END_INT) || (status & SETUP_INT) || 1799 (status & EP0_OUT_NULL_INT)) { 1800 status &= ~(STG_END_INT 1801 | EP0_OUT_INT 1802 | EP0_OUT_NULL_INT); 1803 1804 nret = _nbu2ss_ep0_status_stage(udc); 1805 } 1806 1807 break; 1808 1809 default: 1810 status = 0; 1811 break; 1812 } 1813 1814 if (status == 0) 1815 break; 1816 } 1817 1818 if (nret < 0) { 1819 /* Send Stall */ 1820 _nbu2ss_set_endpoint_stall(udc, 0, true); 1821 } 1822 } 1823 1824 /*-------------------------------------------------------------------------*/ 1825 static void _nbu2ss_ep_done(struct nbu2ss_ep *ep, 1826 struct nbu2ss_req *req, 1827 int status) 1828 { 1829 struct nbu2ss_udc *udc = ep->udc; 1830 1831 list_del_init(&req->queue); 1832 1833 if (status == -ECONNRESET) 1834 _nbu2ss_fifo_flush(udc, ep); 1835 1836 if (likely(req->req.status == -EINPROGRESS)) 1837 req->req.status = status; 1838 1839 if (ep->stalled) { 1840 _nbu2ss_epn_set_stall(udc, ep); 1841 } else { 1842 if (!list_empty(&ep->queue)) 1843 _nbu2ss_restert_transfer(ep); 1844 } 1845 1846 #ifdef USE_DMA 1847 if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) && 1848 (req->req.dma != 0)) 1849 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT); 1850 #endif 1851 1852 spin_unlock(&udc->lock); 1853 req->req.complete(&ep->ep, &req->req); 1854 spin_lock(&udc->lock); 1855 } 1856 1857 /*-------------------------------------------------------------------------*/ 1858 static inline void _nbu2ss_epn_in_int(struct nbu2ss_udc *udc, 1859 struct nbu2ss_ep *ep, 1860 struct nbu2ss_req *req) 1861 { 1862 int result = 0; 1863 u32 status; 1864 1865 struct fc_regs __iomem *preg = udc->p_regs; 1866 1867 if (req->dma_flag) 1868 return; /* DMA is forwarded */ 1869 1870 req->req.actual += req->div_len; 1871 req->div_len = 0; 1872 1873 if (req->req.actual != req->req.length) { 1874 /*---------------------------------------------------------*/ 1875 /* remainder of data */ 1876 result = _nbu2ss_epn_in_transfer(udc, ep, req); 1877 1878 } else { 1879 if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) { 1880 status = 1881 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS); 1882 1883 if ((status & EPN_IN_FULL) == 0) { 1884 /*-----------------------------------------*/ 1885 /* 0 Length Packet */ 1886 req->zero = false; 1887 _nbu2ss_zero_len_pkt(udc, ep->epnum); 1888 } 1889 return; 1890 } 1891 } 1892 1893 if (result <= 0) { 1894 /*---------------------------------------------------------*/ 1895 /* Complete */ 1896 _nbu2ss_ep_done(ep, req, result); 1897 } 1898 } 1899 1900 /*-------------------------------------------------------------------------*/ 1901 static inline void _nbu2ss_epn_out_int(struct nbu2ss_udc *udc, 1902 struct nbu2ss_ep *ep, 1903 struct nbu2ss_req *req) 1904 { 1905 int result; 1906 1907 result = _nbu2ss_epn_out_transfer(udc, ep, req); 1908 if (result <= 0) 1909 _nbu2ss_ep_done(ep, req, result); 1910 } 1911 1912 /*-------------------------------------------------------------------------*/ 1913 static inline void _nbu2ss_epn_in_dma_int(struct nbu2ss_udc *udc, 1914 struct nbu2ss_ep *ep, 1915 struct nbu2ss_req *req) 1916 { 1917 u32 mpkt; 1918 u32 size; 1919 struct usb_request *preq; 1920 1921 preq = &req->req; 1922 1923 if (!req->dma_flag) 1924 return; 1925 1926 preq->actual += req->div_len; 1927 req->div_len = 0; 1928 req->dma_flag = false; 1929 1930 #ifdef USE_DMA 1931 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN); 1932 #endif 1933 1934 if (preq->actual != preq->length) { 1935 _nbu2ss_epn_in_transfer(udc, ep, req); 1936 } else { 1937 mpkt = ep->ep.maxpacket; 1938 size = preq->actual % mpkt; 1939 if (size > 0) { 1940 if (((preq->actual & 0x03) == 0) && (size < mpkt)) 1941 _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0); 1942 } else { 1943 _nbu2ss_epn_in_int(udc, ep, req); 1944 } 1945 } 1946 } 1947 1948 /*-------------------------------------------------------------------------*/ 1949 static inline void _nbu2ss_epn_out_dma_int(struct nbu2ss_udc *udc, 1950 struct nbu2ss_ep *ep, 1951 struct nbu2ss_req *req) 1952 { 1953 int i; 1954 u32 num; 1955 u32 dmacnt, ep_dmacnt; 1956 u32 mpkt; 1957 struct fc_regs __iomem *preg = udc->p_regs; 1958 1959 num = ep->epnum - 1; 1960 1961 if (req->req.actual == req->req.length) { 1962 if ((req->req.length % ep->ep.maxpacket) && !req->zero) { 1963 req->div_len = 0; 1964 req->dma_flag = false; 1965 _nbu2ss_ep_done(ep, req, 0); 1966 return; 1967 } 1968 } 1969 1970 ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) 1971 & EPN_DMACNT; 1972 ep_dmacnt >>= 16; 1973 1974 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) { 1975 dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1) 1976 & DCR1_EPN_DMACNT; 1977 dmacnt >>= 16; 1978 if (ep_dmacnt == dmacnt) 1979 break; 1980 } 1981 1982 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_REQEN); 1983 1984 if (dmacnt != 0) { 1985 mpkt = ep->ep.maxpacket; 1986 if ((req->div_len % mpkt) == 0) 1987 req->div_len -= mpkt * dmacnt; 1988 } 1989 1990 if ((req->req.actual % ep->ep.maxpacket) > 0) { 1991 if (req->req.actual == req->div_len) { 1992 req->div_len = 0; 1993 req->dma_flag = false; 1994 _nbu2ss_ep_done(ep, req, 0); 1995 return; 1996 } 1997 } 1998 1999 req->req.actual += req->div_len; 2000 req->div_len = 0; 2001 req->dma_flag = false; 2002 2003 _nbu2ss_epn_out_int(udc, ep, req); 2004 } 2005 2006 /*-------------------------------------------------------------------------*/ 2007 static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum) 2008 { 2009 u32 num; 2010 u32 status; 2011 2012 struct nbu2ss_req *req; 2013 struct nbu2ss_ep *ep = &udc->ep[epnum]; 2014 2015 num = epnum - 1; 2016 2017 /* Interrupt Status */ 2018 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS); 2019 2020 /* Interrupt Clear */ 2021 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~status); 2022 2023 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 2024 if (!req) { 2025 /* pr_warn("=== %s(%d) req == NULL\n", __func__, epnum); */ 2026 return; 2027 } 2028 2029 if (status & EPN_OUT_END_INT) { 2030 status &= ~EPN_OUT_INT; 2031 _nbu2ss_epn_out_dma_int(udc, ep, req); 2032 } 2033 2034 if (status & EPN_OUT_INT) 2035 _nbu2ss_epn_out_int(udc, ep, req); 2036 2037 if (status & EPN_IN_END_INT) { 2038 status &= ~EPN_IN_INT; 2039 _nbu2ss_epn_in_dma_int(udc, ep, req); 2040 } 2041 2042 if (status & EPN_IN_INT) 2043 _nbu2ss_epn_in_int(udc, ep, req); 2044 } 2045 2046 /*-------------------------------------------------------------------------*/ 2047 static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum) 2048 { 2049 if (epnum == 0) 2050 _nbu2ss_ep0_int(udc); 2051 else 2052 _nbu2ss_epn_int(udc, epnum); 2053 } 2054 2055 /*-------------------------------------------------------------------------*/ 2056 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc) 2057 { 2058 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR)); 2059 _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT); 2060 } 2061 2062 /*-------------------------------------------------------------------------*/ 2063 static int _nbu2ss_nuke(struct nbu2ss_udc *udc, 2064 struct nbu2ss_ep *ep, 2065 int status) 2066 { 2067 struct nbu2ss_req *req; 2068 2069 /* Endpoint Disable */ 2070 _nbu2ss_epn_exit(udc, ep); 2071 2072 /* DMA Disable */ 2073 _nbu2ss_ep_dma_exit(udc, ep); 2074 2075 if (list_empty(&ep->queue)) 2076 return 0; 2077 2078 /* called with irqs blocked */ 2079 list_for_each_entry(req, &ep->queue, queue) { 2080 _nbu2ss_ep_done(ep, req, status); 2081 } 2082 2083 return 0; 2084 } 2085 2086 /*-------------------------------------------------------------------------*/ 2087 static void _nbu2ss_quiesce(struct nbu2ss_udc *udc) 2088 { 2089 struct nbu2ss_ep *ep; 2090 2091 udc->gadget.speed = USB_SPEED_UNKNOWN; 2092 2093 _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN); 2094 2095 /* Endpoint n */ 2096 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { 2097 _nbu2ss_nuke(udc, ep, -ESHUTDOWN); 2098 } 2099 } 2100 2101 /*-------------------------------------------------------------------------*/ 2102 static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on) 2103 { 2104 u32 reg_dt; 2105 2106 if (udc->vbus_active == 0) 2107 return -ESHUTDOWN; 2108 2109 if (is_on) { 2110 /* D+ Pullup */ 2111 if (udc->driver) { 2112 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) 2113 | PUE2) & ~(u32)CONNECTB; 2114 2115 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt); 2116 } 2117 2118 } else { 2119 /* D+ Pulldown */ 2120 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB) 2121 & ~(u32)PUE2; 2122 2123 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt); 2124 udc->gadget.speed = USB_SPEED_UNKNOWN; 2125 } 2126 2127 return 0; 2128 } 2129 2130 /*-------------------------------------------------------------------------*/ 2131 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 2132 { 2133 struct fc_regs __iomem *p = udc->p_regs; 2134 2135 if (udc->vbus_active == 0) 2136 return; 2137 2138 if (ep->epnum == 0) { 2139 /* EP0 */ 2140 _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR); 2141 2142 } else { 2143 /* EPN */ 2144 _nbu2ss_ep_dma_abort(udc, ep); 2145 _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPN_BCLR); 2146 } 2147 } 2148 2149 /*-------------------------------------------------------------------------*/ 2150 static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc) 2151 { 2152 int waitcnt = 0; 2153 2154 if (udc->udc_enabled) 2155 return 0; 2156 2157 /* Reset */ 2158 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST)); 2159 udelay(EPC_RST_DISABLE_TIME); /* 1us wait */ 2160 2161 _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD); 2162 mdelay(EPC_DIRPD_DISABLE_TIME); /* 1ms wait */ 2163 2164 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST); 2165 2166 _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE); 2167 2168 _nbu2ss_writel(&udc->p_regs->AHBMCTR, 2169 HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE); 2170 2171 while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) { 2172 waitcnt++; 2173 udelay(1); /* 1us wait */ 2174 if (waitcnt == EPC_PLL_LOCK_COUNT) { 2175 dev_err(udc->dev, "*** Reset Cancel failed\n"); 2176 return -EINVAL; 2177 } 2178 } 2179 2180 _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET); 2181 2182 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV)); 2183 2184 /* EP0 */ 2185 _nbu2ss_ep0_enable(udc); 2186 2187 /* USB Interrupt Enable */ 2188 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT); 2189 2190 udc->udc_enabled = true; 2191 2192 return 0; 2193 } 2194 2195 /*-------------------------------------------------------------------------*/ 2196 static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc) 2197 { 2198 _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST); 2199 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST); 2200 } 2201 2202 /*-------------------------------------------------------------------------*/ 2203 static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc) 2204 { 2205 if (udc->udc_enabled) { 2206 udc->udc_enabled = false; 2207 _nbu2ss_reset_controller(udc); 2208 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST)); 2209 } 2210 } 2211 2212 /*-------------------------------------------------------------------------*/ 2213 static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc) 2214 { 2215 int nret; 2216 u32 reg_dt; 2217 2218 /* chattering */ 2219 mdelay(VBUS_CHATTERING_MDELAY); /* wait (ms) */ 2220 2221 /* VBUS ON Check*/ 2222 reg_dt = gpiod_get_value(vbus_gpio); 2223 if (reg_dt == 0) { 2224 udc->linux_suspended = 0; 2225 2226 _nbu2ss_reset_controller(udc); 2227 dev_info(udc->dev, " ----- VBUS OFF\n"); 2228 2229 if (udc->vbus_active == 1) { 2230 /* VBUS OFF */ 2231 udc->vbus_active = 0; 2232 if (udc->usb_suspended) { 2233 udc->usb_suspended = 0; 2234 /* _nbu2ss_reset_controller(udc); */ 2235 } 2236 udc->devstate = USB_STATE_NOTATTACHED; 2237 2238 _nbu2ss_quiesce(udc); 2239 if (udc->driver) { 2240 spin_unlock(&udc->lock); 2241 udc->driver->disconnect(&udc->gadget); 2242 spin_lock(&udc->lock); 2243 } 2244 2245 _nbu2ss_disable_controller(udc); 2246 } 2247 } else { 2248 mdelay(5); /* wait (5ms) */ 2249 reg_dt = gpiod_get_value(vbus_gpio); 2250 if (reg_dt == 0) 2251 return; 2252 2253 dev_info(udc->dev, " ----- VBUS ON\n"); 2254 2255 if (udc->linux_suspended) 2256 return; 2257 2258 if (udc->vbus_active == 0) { 2259 /* VBUS ON */ 2260 udc->vbus_active = 1; 2261 udc->devstate = USB_STATE_POWERED; 2262 2263 nret = _nbu2ss_enable_controller(udc); 2264 if (nret < 0) { 2265 _nbu2ss_disable_controller(udc); 2266 udc->vbus_active = 0; 2267 return; 2268 } 2269 2270 _nbu2ss_pullup(udc, 1); 2271 2272 #ifdef UDC_DEBUG_DUMP 2273 _nbu2ss_dump_register(udc); 2274 #endif /* UDC_DEBUG_DUMP */ 2275 2276 } else { 2277 if (udc->devstate == USB_STATE_POWERED) 2278 _nbu2ss_pullup(udc, 1); 2279 } 2280 } 2281 } 2282 2283 /*-------------------------------------------------------------------------*/ 2284 static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc) 2285 { 2286 udc->devstate = USB_STATE_DEFAULT; 2287 udc->remote_wakeup = 0; 2288 2289 _nbu2ss_quiesce(udc); 2290 2291 udc->ep0state = EP0_IDLE; 2292 } 2293 2294 /*-------------------------------------------------------------------------*/ 2295 static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc) 2296 { 2297 if (udc->usb_suspended == 1) { 2298 udc->usb_suspended = 0; 2299 if (udc->driver && udc->driver->resume) { 2300 spin_unlock(&udc->lock); 2301 udc->driver->resume(&udc->gadget); 2302 spin_lock(&udc->lock); 2303 } 2304 } 2305 } 2306 2307 /*-------------------------------------------------------------------------*/ 2308 static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc) 2309 { 2310 u32 reg_dt; 2311 2312 if (udc->usb_suspended == 0) { 2313 reg_dt = gpiod_get_value(vbus_gpio); 2314 2315 if (reg_dt == 0) 2316 return; 2317 2318 udc->usb_suspended = 1; 2319 if (udc->driver && udc->driver->suspend) { 2320 spin_unlock(&udc->lock); 2321 udc->driver->suspend(&udc->gadget); 2322 spin_lock(&udc->lock); 2323 } 2324 2325 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND); 2326 } 2327 } 2328 2329 /*-------------------------------------------------------------------------*/ 2330 /* VBUS (GPIO153) Interrupt */ 2331 static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc) 2332 { 2333 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc; 2334 2335 spin_lock(&udc->lock); 2336 _nbu2ss_check_vbus(udc); 2337 spin_unlock(&udc->lock); 2338 2339 return IRQ_HANDLED; 2340 } 2341 2342 /*-------------------------------------------------------------------------*/ 2343 /* Interrupt (udc) */ 2344 static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc) 2345 { 2346 u8 suspend_flag = 0; 2347 u32 status; 2348 u32 epnum, int_bit; 2349 2350 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc; 2351 struct fc_regs __iomem *preg = udc->p_regs; 2352 2353 if (gpiod_get_value(vbus_gpio) == 0) { 2354 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW); 2355 _nbu2ss_writel(&preg->USB_INT_ENA, 0); 2356 return IRQ_HANDLED; 2357 } 2358 2359 spin_lock(&udc->lock); 2360 2361 for (;;) { 2362 if (gpiod_get_value(vbus_gpio) == 0) { 2363 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW); 2364 _nbu2ss_writel(&preg->USB_INT_ENA, 0); 2365 status = 0; 2366 } else { 2367 status = _nbu2ss_readl(&preg->USB_INT_STA); 2368 } 2369 2370 if (status == 0) 2371 break; 2372 2373 _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW)); 2374 2375 if (status & USB_RST_INT) { 2376 /* USB Reset */ 2377 _nbu2ss_int_bus_reset(udc); 2378 } 2379 2380 if (status & RSUM_INT) { 2381 /* Resume */ 2382 _nbu2ss_int_usb_resume(udc); 2383 } 2384 2385 if (status & SPND_INT) { 2386 /* Suspend */ 2387 suspend_flag = 1; 2388 } 2389 2390 if (status & EPN_INT) { 2391 /* EP INT */ 2392 int_bit = status >> 8; 2393 2394 for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) { 2395 if (0x01 & int_bit) 2396 _nbu2ss_ep_int(udc, epnum); 2397 2398 int_bit >>= 1; 2399 2400 if (int_bit == 0) 2401 break; 2402 } 2403 } 2404 } 2405 2406 if (suspend_flag) 2407 _nbu2ss_int_usb_suspend(udc); 2408 2409 spin_unlock(&udc->lock); 2410 2411 return IRQ_HANDLED; 2412 } 2413 2414 /*-------------------------------------------------------------------------*/ 2415 /* usb_ep_ops */ 2416 static int nbu2ss_ep_enable(struct usb_ep *_ep, 2417 const struct usb_endpoint_descriptor *desc) 2418 { 2419 u8 ep_type; 2420 unsigned long flags; 2421 2422 struct nbu2ss_ep *ep; 2423 struct nbu2ss_udc *udc; 2424 2425 if (!_ep || !desc) { 2426 pr_err(" *** %s, bad param\n", __func__); 2427 return -EINVAL; 2428 } 2429 2430 ep = container_of(_ep, struct nbu2ss_ep, ep); 2431 if (!ep->udc) { 2432 pr_err(" *** %s, ep == NULL !!\n", __func__); 2433 return -EINVAL; 2434 } 2435 2436 ep_type = usb_endpoint_type(desc); 2437 if ((ep_type == USB_ENDPOINT_XFER_CONTROL) || 2438 (ep_type == USB_ENDPOINT_XFER_ISOC)) { 2439 pr_err(" *** %s, bat bmAttributes\n", __func__); 2440 return -EINVAL; 2441 } 2442 2443 udc = ep->udc; 2444 if (udc->vbus_active == 0) 2445 return -ESHUTDOWN; 2446 2447 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { 2448 dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__); 2449 return -ESHUTDOWN; 2450 } 2451 2452 spin_lock_irqsave(&udc->lock, flags); 2453 2454 ep->desc = desc; 2455 ep->epnum = usb_endpoint_num(desc); 2456 ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK; 2457 ep->ep_type = ep_type; 2458 ep->wedged = 0; 2459 ep->halted = false; 2460 ep->stalled = false; 2461 2462 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize); 2463 2464 /* DMA setting */ 2465 _nbu2ss_ep_dma_init(udc, ep); 2466 2467 /* Endpoint setting */ 2468 _nbu2ss_ep_init(udc, ep); 2469 2470 spin_unlock_irqrestore(&udc->lock, flags); 2471 2472 return 0; 2473 } 2474 2475 /*-------------------------------------------------------------------------*/ 2476 static int nbu2ss_ep_disable(struct usb_ep *_ep) 2477 { 2478 struct nbu2ss_ep *ep; 2479 struct nbu2ss_udc *udc; 2480 unsigned long flags; 2481 2482 if (!_ep) { 2483 pr_err(" *** %s, bad param\n", __func__); 2484 return -EINVAL; 2485 } 2486 2487 ep = container_of(_ep, struct nbu2ss_ep, ep); 2488 if (!ep->udc) { 2489 pr_err("udc: *** %s, ep == NULL !!\n", __func__); 2490 return -EINVAL; 2491 } 2492 2493 udc = ep->udc; 2494 if (udc->vbus_active == 0) 2495 return -ESHUTDOWN; 2496 2497 spin_lock_irqsave(&udc->lock, flags); 2498 _nbu2ss_nuke(udc, ep, -EINPROGRESS); /* dequeue request */ 2499 spin_unlock_irqrestore(&udc->lock, flags); 2500 2501 return 0; 2502 } 2503 2504 /*-------------------------------------------------------------------------*/ 2505 static struct usb_request *nbu2ss_ep_alloc_request(struct usb_ep *ep, 2506 gfp_t gfp_flags) 2507 { 2508 struct nbu2ss_req *req; 2509 2510 req = kzalloc(sizeof(*req), gfp_flags); 2511 if (!req) 2512 return NULL; 2513 2514 #ifdef USE_DMA 2515 req->req.dma = DMA_ADDR_INVALID; 2516 #endif 2517 INIT_LIST_HEAD(&req->queue); 2518 2519 return &req->req; 2520 } 2521 2522 /*-------------------------------------------------------------------------*/ 2523 static void nbu2ss_ep_free_request(struct usb_ep *_ep, 2524 struct usb_request *_req) 2525 { 2526 struct nbu2ss_req *req; 2527 2528 if (_req) { 2529 req = container_of(_req, struct nbu2ss_req, req); 2530 2531 kfree(req); 2532 } 2533 } 2534 2535 /*-------------------------------------------------------------------------*/ 2536 static int nbu2ss_ep_queue(struct usb_ep *_ep, 2537 struct usb_request *_req, gfp_t gfp_flags) 2538 { 2539 struct nbu2ss_req *req; 2540 struct nbu2ss_ep *ep; 2541 struct nbu2ss_udc *udc; 2542 unsigned long flags; 2543 bool bflag; 2544 int result = -EINVAL; 2545 2546 /* catch various bogus parameters */ 2547 if (!_ep || !_req) { 2548 if (!_ep) 2549 pr_err("udc: %s --- _ep == NULL\n", __func__); 2550 2551 if (!_req) 2552 pr_err("udc: %s --- _req == NULL\n", __func__); 2553 2554 return -EINVAL; 2555 } 2556 2557 req = container_of(_req, struct nbu2ss_req, req); 2558 if (unlikely(!_req->complete || 2559 !_req->buf || 2560 !list_empty(&req->queue))) { 2561 if (!_req->complete) 2562 pr_err("udc: %s --- !_req->complete\n", __func__); 2563 2564 if (!_req->buf) 2565 pr_err("udc:%s --- !_req->buf\n", __func__); 2566 2567 if (!list_empty(&req->queue)) 2568 pr_err("%s --- !list_empty(&req->queue)\n", __func__); 2569 2570 return -EINVAL; 2571 } 2572 2573 ep = container_of(_ep, struct nbu2ss_ep, ep); 2574 udc = ep->udc; 2575 2576 if (udc->vbus_active == 0) { 2577 dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n"); 2578 return -ESHUTDOWN; 2579 } 2580 2581 if (unlikely(!udc->driver)) { 2582 dev_err(udc->dev, "%s, bogus device state %p\n", __func__, 2583 udc->driver); 2584 return -ESHUTDOWN; 2585 } 2586 2587 spin_lock_irqsave(&udc->lock, flags); 2588 2589 #ifdef USE_DMA 2590 if ((uintptr_t)req->req.buf & 0x3) 2591 req->unaligned = true; 2592 else 2593 req->unaligned = false; 2594 2595 if (req->unaligned) { 2596 if (!ep->virt_buf) 2597 ep->virt_buf = dma_alloc_coherent(udc->dev, PAGE_SIZE, 2598 &ep->phys_buf, 2599 GFP_ATOMIC | GFP_DMA); 2600 if (ep->epnum > 0) { 2601 if (ep->direct == USB_DIR_IN) 2602 memcpy(ep->virt_buf, req->req.buf, 2603 req->req.length); 2604 } 2605 } 2606 2607 if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) && 2608 (req->req.dma != 0)) 2609 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT); 2610 #endif 2611 2612 _req->status = -EINPROGRESS; 2613 _req->actual = 0; 2614 2615 bflag = list_empty(&ep->queue); 2616 list_add_tail(&req->queue, &ep->queue); 2617 2618 if (bflag && !ep->stalled) { 2619 result = _nbu2ss_start_transfer(udc, ep, req, false); 2620 if (result < 0) { 2621 dev_err(udc->dev, " *** %s, result = %d\n", __func__, 2622 result); 2623 list_del(&req->queue); 2624 } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) { 2625 #ifdef USE_DMA 2626 if (req->req.length < 4 && 2627 req->req.length == req->req.actual) 2628 #else 2629 if (req->req.length == req->req.actual) 2630 #endif 2631 _nbu2ss_ep_done(ep, req, result); 2632 } 2633 } 2634 2635 spin_unlock_irqrestore(&udc->lock, flags); 2636 2637 return 0; 2638 } 2639 2640 /*-------------------------------------------------------------------------*/ 2641 static int nbu2ss_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 2642 { 2643 struct nbu2ss_req *req; 2644 struct nbu2ss_ep *ep; 2645 struct nbu2ss_udc *udc; 2646 unsigned long flags; 2647 2648 /* catch various bogus parameters */ 2649 if (!_ep || !_req) { 2650 /* pr_err("%s, bad param(1)\n", __func__); */ 2651 return -EINVAL; 2652 } 2653 2654 ep = container_of(_ep, struct nbu2ss_ep, ep); 2655 2656 udc = ep->udc; 2657 if (!udc) 2658 return -EINVAL; 2659 2660 spin_lock_irqsave(&udc->lock, flags); 2661 2662 /* make sure it's actually queued on this endpoint */ 2663 list_for_each_entry(req, &ep->queue, queue) { 2664 if (&req->req == _req) { 2665 _nbu2ss_ep_done(ep, req, -ECONNRESET); 2666 spin_unlock_irqrestore(&udc->lock, flags); 2667 return 0; 2668 } 2669 } 2670 2671 spin_unlock_irqrestore(&udc->lock, flags); 2672 2673 pr_debug("%s no queue(EINVAL)\n", __func__); 2674 2675 return -EINVAL; 2676 } 2677 2678 /*-------------------------------------------------------------------------*/ 2679 static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value) 2680 { 2681 u8 ep_adrs; 2682 unsigned long flags; 2683 2684 struct nbu2ss_ep *ep; 2685 struct nbu2ss_udc *udc; 2686 2687 if (!_ep) { 2688 pr_err("%s, bad param\n", __func__); 2689 return -EINVAL; 2690 } 2691 2692 ep = container_of(_ep, struct nbu2ss_ep, ep); 2693 2694 udc = ep->udc; 2695 if (!udc) { 2696 dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__); 2697 return -EINVAL; 2698 } 2699 2700 spin_lock_irqsave(&udc->lock, flags); 2701 2702 ep_adrs = ep->epnum | ep->direct; 2703 if (value == 0) { 2704 _nbu2ss_set_endpoint_stall(udc, ep_adrs, value); 2705 ep->stalled = false; 2706 } else { 2707 if (list_empty(&ep->queue)) 2708 _nbu2ss_epn_set_stall(udc, ep); 2709 else 2710 ep->stalled = true; 2711 } 2712 2713 if (value == 0) 2714 ep->wedged = 0; 2715 2716 spin_unlock_irqrestore(&udc->lock, flags); 2717 2718 return 0; 2719 } 2720 2721 static int nbu2ss_ep_set_wedge(struct usb_ep *_ep) 2722 { 2723 return nbu2ss_ep_set_halt(_ep, 1); 2724 } 2725 2726 /*-------------------------------------------------------------------------*/ 2727 static int nbu2ss_ep_fifo_status(struct usb_ep *_ep) 2728 { 2729 u32 data; 2730 struct nbu2ss_ep *ep; 2731 struct nbu2ss_udc *udc; 2732 unsigned long flags; 2733 struct fc_regs __iomem *preg; 2734 2735 if (!_ep) { 2736 pr_err("%s, bad param\n", __func__); 2737 return -EINVAL; 2738 } 2739 2740 ep = container_of(_ep, struct nbu2ss_ep, ep); 2741 2742 udc = ep->udc; 2743 if (!udc) { 2744 dev_err(ep->udc->dev, "%s, bad udc\n", __func__); 2745 return -EINVAL; 2746 } 2747 2748 preg = udc->p_regs; 2749 2750 data = gpiod_get_value(vbus_gpio); 2751 if (data == 0) 2752 return -EINVAL; 2753 2754 spin_lock_irqsave(&udc->lock, flags); 2755 2756 if (ep->epnum == 0) { 2757 data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA; 2758 2759 } else { 2760 data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT) 2761 & EPN_LDATA; 2762 } 2763 2764 spin_unlock_irqrestore(&udc->lock, flags); 2765 2766 return 0; 2767 } 2768 2769 /*-------------------------------------------------------------------------*/ 2770 static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep) 2771 { 2772 u32 data; 2773 struct nbu2ss_ep *ep; 2774 struct nbu2ss_udc *udc; 2775 unsigned long flags; 2776 2777 if (!_ep) { 2778 pr_err("udc: %s, bad param\n", __func__); 2779 return; 2780 } 2781 2782 ep = container_of(_ep, struct nbu2ss_ep, ep); 2783 2784 udc = ep->udc; 2785 if (!udc) { 2786 dev_err(ep->udc->dev, "%s, bad udc\n", __func__); 2787 return; 2788 } 2789 2790 data = gpiod_get_value(vbus_gpio); 2791 if (data == 0) 2792 return; 2793 2794 spin_lock_irqsave(&udc->lock, flags); 2795 _nbu2ss_fifo_flush(udc, ep); 2796 spin_unlock_irqrestore(&udc->lock, flags); 2797 } 2798 2799 /*-------------------------------------------------------------------------*/ 2800 static const struct usb_ep_ops nbu2ss_ep_ops = { 2801 .enable = nbu2ss_ep_enable, 2802 .disable = nbu2ss_ep_disable, 2803 2804 .alloc_request = nbu2ss_ep_alloc_request, 2805 .free_request = nbu2ss_ep_free_request, 2806 2807 .queue = nbu2ss_ep_queue, 2808 .dequeue = nbu2ss_ep_dequeue, 2809 2810 .set_halt = nbu2ss_ep_set_halt, 2811 .set_wedge = nbu2ss_ep_set_wedge, 2812 2813 .fifo_status = nbu2ss_ep_fifo_status, 2814 .fifo_flush = nbu2ss_ep_fifo_flush, 2815 }; 2816 2817 /*-------------------------------------------------------------------------*/ 2818 /* usb_gadget_ops */ 2819 2820 /*-------------------------------------------------------------------------*/ 2821 static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget) 2822 { 2823 u32 data; 2824 struct nbu2ss_udc *udc; 2825 2826 if (!pgadget) { 2827 pr_err("udc: %s, bad param\n", __func__); 2828 return -EINVAL; 2829 } 2830 2831 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2832 data = gpiod_get_value(vbus_gpio); 2833 if (data == 0) 2834 return -EINVAL; 2835 2836 return _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME; 2837 } 2838 2839 /*-------------------------------------------------------------------------*/ 2840 static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget) 2841 { 2842 int i; 2843 u32 data; 2844 2845 struct nbu2ss_udc *udc; 2846 2847 if (!pgadget) { 2848 pr_err("%s, bad param\n", __func__); 2849 return -EINVAL; 2850 } 2851 2852 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2853 2854 data = gpiod_get_value(vbus_gpio); 2855 if (data == 0) { 2856 dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data); 2857 return -EINVAL; 2858 } 2859 2860 _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME); 2861 2862 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) { 2863 data = _nbu2ss_readl(&udc->p_regs->EPCTR); 2864 2865 if (data & PLL_LOCK) 2866 break; 2867 } 2868 2869 _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME); 2870 2871 return 0; 2872 } 2873 2874 /*-------------------------------------------------------------------------*/ 2875 static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget, 2876 int is_selfpowered) 2877 { 2878 struct nbu2ss_udc *udc; 2879 unsigned long flags; 2880 2881 if (!pgadget) { 2882 pr_err("%s, bad param\n", __func__); 2883 return -EINVAL; 2884 } 2885 2886 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2887 2888 spin_lock_irqsave(&udc->lock, flags); 2889 pgadget->is_selfpowered = (is_selfpowered != 0); 2890 spin_unlock_irqrestore(&udc->lock, flags); 2891 2892 return 0; 2893 } 2894 2895 /*-------------------------------------------------------------------------*/ 2896 static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active) 2897 { 2898 return 0; 2899 } 2900 2901 /*-------------------------------------------------------------------------*/ 2902 static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned int mA) 2903 { 2904 struct nbu2ss_udc *udc; 2905 unsigned long flags; 2906 2907 if (!pgadget) { 2908 pr_err("%s, bad param\n", __func__); 2909 return -EINVAL; 2910 } 2911 2912 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2913 2914 spin_lock_irqsave(&udc->lock, flags); 2915 udc->mA = mA; 2916 spin_unlock_irqrestore(&udc->lock, flags); 2917 2918 return 0; 2919 } 2920 2921 /*-------------------------------------------------------------------------*/ 2922 static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on) 2923 { 2924 struct nbu2ss_udc *udc; 2925 unsigned long flags; 2926 2927 if (!pgadget) { 2928 pr_err("%s, bad param\n", __func__); 2929 return -EINVAL; 2930 } 2931 2932 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2933 2934 if (!udc->driver) { 2935 pr_warn("%s, Not Regist Driver\n", __func__); 2936 return -EINVAL; 2937 } 2938 2939 if (udc->vbus_active == 0) 2940 return -ESHUTDOWN; 2941 2942 spin_lock_irqsave(&udc->lock, flags); 2943 _nbu2ss_pullup(udc, is_on); 2944 spin_unlock_irqrestore(&udc->lock, flags); 2945 2946 return 0; 2947 } 2948 2949 /*-------------------------------------------------------------------------*/ 2950 static int nbu2ss_gad_ioctl(struct usb_gadget *pgadget, 2951 unsigned int code, unsigned long param) 2952 { 2953 return 0; 2954 } 2955 2956 static const struct usb_gadget_ops nbu2ss_gadget_ops = { 2957 .get_frame = nbu2ss_gad_get_frame, 2958 .wakeup = nbu2ss_gad_wakeup, 2959 .set_selfpowered = nbu2ss_gad_set_selfpowered, 2960 .vbus_session = nbu2ss_gad_vbus_session, 2961 .vbus_draw = nbu2ss_gad_vbus_draw, 2962 .pullup = nbu2ss_gad_pullup, 2963 .ioctl = nbu2ss_gad_ioctl, 2964 }; 2965 2966 static const struct { 2967 const char *name; 2968 const struct usb_ep_caps caps; 2969 } ep_info[NUM_ENDPOINTS] = { 2970 #define EP_INFO(_name, _caps) \ 2971 { \ 2972 .name = _name, \ 2973 .caps = _caps, \ 2974 } 2975 2976 EP_INFO("ep0", 2977 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)), 2978 EP_INFO("ep1-bulk", 2979 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 2980 EP_INFO("ep2-bulk", 2981 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 2982 EP_INFO("ep3in-int", 2983 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)), 2984 EP_INFO("ep4-iso", 2985 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 2986 EP_INFO("ep5-iso", 2987 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 2988 EP_INFO("ep6-bulk", 2989 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 2990 EP_INFO("ep7-bulk", 2991 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 2992 EP_INFO("ep8in-int", 2993 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)), 2994 EP_INFO("ep9-iso", 2995 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 2996 EP_INFO("epa-iso", 2997 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 2998 EP_INFO("epb-bulk", 2999 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 3000 EP_INFO("epc-bulk", 3001 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 3002 EP_INFO("epdin-int", 3003 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)), 3004 3005 #undef EP_INFO 3006 }; 3007 3008 /*-------------------------------------------------------------------------*/ 3009 static void nbu2ss_drv_ep_init(struct nbu2ss_udc *udc) 3010 { 3011 int i; 3012 3013 INIT_LIST_HEAD(&udc->gadget.ep_list); 3014 udc->gadget.ep0 = &udc->ep[0].ep; 3015 3016 for (i = 0; i < NUM_ENDPOINTS; i++) { 3017 struct nbu2ss_ep *ep = &udc->ep[i]; 3018 3019 ep->udc = udc; 3020 ep->desc = NULL; 3021 3022 ep->ep.driver_data = NULL; 3023 ep->ep.name = ep_info[i].name; 3024 ep->ep.caps = ep_info[i].caps; 3025 ep->ep.ops = &nbu2ss_ep_ops; 3026 3027 usb_ep_set_maxpacket_limit(&ep->ep, 3028 i == 0 ? EP0_PACKETSIZE 3029 : EP_PACKETSIZE); 3030 3031 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 3032 INIT_LIST_HEAD(&ep->queue); 3033 } 3034 3035 list_del_init(&udc->ep[0].ep.ep_list); 3036 } 3037 3038 /*-------------------------------------------------------------------------*/ 3039 /* platform_driver */ 3040 static int nbu2ss_drv_contest_init(struct platform_device *pdev, 3041 struct nbu2ss_udc *udc) 3042 { 3043 spin_lock_init(&udc->lock); 3044 udc->dev = &pdev->dev; 3045 3046 udc->gadget.is_selfpowered = 1; 3047 udc->devstate = USB_STATE_NOTATTACHED; 3048 udc->pdev = pdev; 3049 udc->mA = 0; 3050 3051 udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 3052 3053 /* init Endpoint */ 3054 nbu2ss_drv_ep_init(udc); 3055 3056 /* init Gadget */ 3057 udc->gadget.ops = &nbu2ss_gadget_ops; 3058 udc->gadget.ep0 = &udc->ep[0].ep; 3059 udc->gadget.speed = USB_SPEED_UNKNOWN; 3060 udc->gadget.name = driver_name; 3061 /* udc->gadget.is_dualspeed = 1; */ 3062 3063 device_initialize(&udc->gadget.dev); 3064 3065 dev_set_name(&udc->gadget.dev, "gadget"); 3066 udc->gadget.dev.parent = &pdev->dev; 3067 udc->gadget.dev.dma_mask = pdev->dev.dma_mask; 3068 3069 return 0; 3070 } 3071 3072 /* 3073 * probe - binds to the platform device 3074 */ 3075 static int nbu2ss_drv_probe(struct platform_device *pdev) 3076 { 3077 int status; 3078 struct nbu2ss_udc *udc; 3079 int irq; 3080 void __iomem *mmio_base; 3081 3082 udc = &udc_controller; 3083 memset(udc, 0, sizeof(struct nbu2ss_udc)); 3084 3085 platform_set_drvdata(pdev, udc); 3086 3087 /* require I/O memory and IRQ to be provided as resources */ 3088 mmio_base = devm_platform_ioremap_resource(pdev, 0); 3089 if (IS_ERR(mmio_base)) 3090 return PTR_ERR(mmio_base); 3091 3092 irq = platform_get_irq(pdev, 0); 3093 if (irq < 0) 3094 return irq; 3095 status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq, 3096 0, driver_name, udc); 3097 3098 /* IO Memory */ 3099 udc->p_regs = (struct fc_regs __iomem *)mmio_base; 3100 3101 /* USB Function Controller Interrupt */ 3102 if (status != 0) { 3103 dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n"); 3104 return status; 3105 } 3106 3107 /* Driver Initialization */ 3108 status = nbu2ss_drv_contest_init(pdev, udc); 3109 if (status < 0) { 3110 /* Error */ 3111 return status; 3112 } 3113 3114 /* VBUS Interrupt */ 3115 vbus_irq = gpiod_to_irq(vbus_gpio); 3116 irq_set_irq_type(vbus_irq, IRQ_TYPE_EDGE_BOTH); 3117 status = request_irq(vbus_irq, 3118 _nbu2ss_vbus_irq, IRQF_SHARED, driver_name, udc); 3119 3120 if (status != 0) { 3121 dev_err(udc->dev, "request_irq(vbus_irq) failed\n"); 3122 return status; 3123 } 3124 3125 return status; 3126 } 3127 3128 /*-------------------------------------------------------------------------*/ 3129 static void nbu2ss_drv_shutdown(struct platform_device *pdev) 3130 { 3131 struct nbu2ss_udc *udc; 3132 3133 udc = platform_get_drvdata(pdev); 3134 if (!udc) 3135 return; 3136 3137 _nbu2ss_disable_controller(udc); 3138 } 3139 3140 /*-------------------------------------------------------------------------*/ 3141 static int nbu2ss_drv_remove(struct platform_device *pdev) 3142 { 3143 struct nbu2ss_udc *udc; 3144 struct nbu2ss_ep *ep; 3145 int i; 3146 3147 udc = &udc_controller; 3148 3149 for (i = 0; i < NUM_ENDPOINTS; i++) { 3150 ep = &udc->ep[i]; 3151 if (ep->virt_buf) 3152 dma_free_coherent(udc->dev, PAGE_SIZE, (void *)ep->virt_buf, 3153 ep->phys_buf); 3154 } 3155 3156 /* Interrupt Handler - Release */ 3157 free_irq(vbus_irq, udc); 3158 3159 return 0; 3160 } 3161 3162 /*-------------------------------------------------------------------------*/ 3163 static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state) 3164 { 3165 struct nbu2ss_udc *udc; 3166 3167 udc = platform_get_drvdata(pdev); 3168 if (!udc) 3169 return 0; 3170 3171 if (udc->vbus_active) { 3172 udc->vbus_active = 0; 3173 udc->devstate = USB_STATE_NOTATTACHED; 3174 udc->linux_suspended = 1; 3175 3176 if (udc->usb_suspended) { 3177 udc->usb_suspended = 0; 3178 _nbu2ss_reset_controller(udc); 3179 } 3180 3181 _nbu2ss_quiesce(udc); 3182 } 3183 _nbu2ss_disable_controller(udc); 3184 3185 return 0; 3186 } 3187 3188 /*-------------------------------------------------------------------------*/ 3189 static int nbu2ss_drv_resume(struct platform_device *pdev) 3190 { 3191 u32 data; 3192 struct nbu2ss_udc *udc; 3193 3194 udc = platform_get_drvdata(pdev); 3195 if (!udc) 3196 return 0; 3197 3198 data = gpiod_get_value(vbus_gpio); 3199 if (data) { 3200 udc->vbus_active = 1; 3201 udc->devstate = USB_STATE_POWERED; 3202 _nbu2ss_enable_controller(udc); 3203 _nbu2ss_pullup(udc, 1); 3204 } 3205 3206 udc->linux_suspended = 0; 3207 3208 return 0; 3209 } 3210 3211 static struct platform_driver udc_driver = { 3212 .probe = nbu2ss_drv_probe, 3213 .shutdown = nbu2ss_drv_shutdown, 3214 .remove = nbu2ss_drv_remove, 3215 .suspend = nbu2ss_drv_suspend, 3216 .resume = nbu2ss_drv_resume, 3217 .driver = { 3218 .name = driver_name, 3219 }, 3220 }; 3221 3222 module_platform_driver(udc_driver); 3223 3224 MODULE_DESCRIPTION(DRIVER_DESC); 3225 MODULE_AUTHOR("Renesas Electronics Corporation"); 3226 MODULE_LICENSE("GPL"); 3227