1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/usb/gadget/emxx_udc.c 4 * EMXX FCD (Function Controller Driver) for USB. 5 * 6 * Copyright (C) 2010 Renesas Electronics Corporation 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/delay.h> 13 #include <linux/ioport.h> 14 #include <linux/slab.h> 15 #include <linux/errno.h> 16 #include <linux/list.h> 17 #include <linux/interrupt.h> 18 #include <linux/proc_fs.h> 19 #include <linux/clk.h> 20 #include <linux/ctype.h> 21 #include <linux/string.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/workqueue.h> 24 #include <linux/device.h> 25 26 #include <linux/usb/ch9.h> 27 #include <linux/usb/gadget.h> 28 29 #include <linux/irq.h> 30 #include <linux/gpio/consumer.h> 31 32 #include "emxx_udc.h" 33 34 #define DRIVER_DESC "EMXX UDC driver" 35 #define DMA_ADDR_INVALID (~(dma_addr_t)0) 36 37 static const char driver_name[] = "emxx_udc"; 38 static const char driver_desc[] = DRIVER_DESC; 39 40 /*===========================================================================*/ 41 /* Prototype */ 42 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *); 43 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *); 44 /*static void _nbu2ss_ep0_disable(struct nbu2ss_udc *);*/ 45 static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int); 46 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode); 47 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs); 48 49 static int _nbu2ss_pullup(struct nbu2ss_udc *, int); 50 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *); 51 52 /*===========================================================================*/ 53 /* Macro */ 54 #define _nbu2ss_zero_len_pkt(udc, epnum) \ 55 _nbu2ss_ep_in_end(udc, epnum, 0, 0) 56 57 /*===========================================================================*/ 58 /* Global */ 59 static struct nbu2ss_udc udc_controller; 60 61 /*-------------------------------------------------------------------------*/ 62 /* Read */ 63 static inline u32 _nbu2ss_readl(void __iomem *address) 64 { 65 return __raw_readl(address); 66 } 67 68 /*-------------------------------------------------------------------------*/ 69 /* Write */ 70 static inline void _nbu2ss_writel(void __iomem *address, u32 udata) 71 { 72 __raw_writel(udata, address); 73 } 74 75 /*-------------------------------------------------------------------------*/ 76 /* Set Bit */ 77 static inline void _nbu2ss_bitset(void __iomem *address, u32 udata) 78 { 79 u32 reg_dt = __raw_readl(address) | (udata); 80 81 __raw_writel(reg_dt, address); 82 } 83 84 /*-------------------------------------------------------------------------*/ 85 /* Clear Bit */ 86 static inline void _nbu2ss_bitclr(void __iomem *address, u32 udata) 87 { 88 u32 reg_dt = __raw_readl(address) & ~(udata); 89 90 __raw_writel(reg_dt, address); 91 } 92 93 #ifdef UDC_DEBUG_DUMP 94 /*-------------------------------------------------------------------------*/ 95 static void _nbu2ss_dump_register(struct nbu2ss_udc *udc) 96 { 97 int i; 98 u32 reg_data; 99 100 pr_info("=== %s()\n", __func__); 101 102 if (!udc) { 103 pr_err("%s udc == NULL\n", __func__); 104 return; 105 } 106 107 spin_unlock(&udc->lock); 108 109 dev_dbg(&udc->dev, "\n-USB REG-\n"); 110 for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) { 111 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i)); 112 dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data); 113 114 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 4)); 115 dev_dbg(&udc->dev, " %08x", (int)reg_data); 116 117 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 8)); 118 dev_dbg(&udc->dev, " %08x", (int)reg_data); 119 120 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 12)); 121 dev_dbg(&udc->dev, " %08x\n", (int)reg_data); 122 } 123 124 spin_lock(&udc->lock); 125 } 126 #endif /* UDC_DEBUG_DUMP */ 127 128 /*-------------------------------------------------------------------------*/ 129 /* Endpoint 0 Callback (Complete) */ 130 static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req) 131 { 132 u8 recipient; 133 u16 selector; 134 u16 wIndex; 135 u32 test_mode; 136 struct usb_ctrlrequest *p_ctrl; 137 struct nbu2ss_udc *udc; 138 139 if (!_ep || !_req) 140 return; 141 142 udc = (struct nbu2ss_udc *)_req->context; 143 p_ctrl = &udc->ctrl; 144 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 145 if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) { 146 /*-------------------------------------------------*/ 147 /* SET_FEATURE */ 148 recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK); 149 selector = le16_to_cpu(p_ctrl->wValue); 150 if ((recipient == USB_RECIP_DEVICE) && 151 (selector == USB_DEVICE_TEST_MODE)) { 152 wIndex = le16_to_cpu(p_ctrl->wIndex); 153 test_mode = (u32)(wIndex >> 8); 154 _nbu2ss_set_test_mode(udc, test_mode); 155 } 156 } 157 } 158 } 159 160 /*-------------------------------------------------------------------------*/ 161 /* Initialization usb_request */ 162 static void _nbu2ss_create_ep0_packet(struct nbu2ss_udc *udc, 163 void *p_buf, unsigned int length) 164 { 165 udc->ep0_req.req.buf = p_buf; 166 udc->ep0_req.req.length = length; 167 udc->ep0_req.req.dma = 0; 168 udc->ep0_req.req.zero = true; 169 udc->ep0_req.req.complete = _nbu2ss_ep0_complete; 170 udc->ep0_req.req.status = -EINPROGRESS; 171 udc->ep0_req.req.context = udc; 172 udc->ep0_req.req.actual = 0; 173 } 174 175 /*-------------------------------------------------------------------------*/ 176 /* Acquisition of the first address of RAM(FIFO) */ 177 static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc) 178 { 179 u32 num, buf_type; 180 u32 data, last_ram_adr, use_ram_size; 181 182 struct ep_regs __iomem *p_ep_regs; 183 184 last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2; 185 use_ram_size = 0; 186 187 for (num = 0; num < NUM_ENDPOINTS - 1; num++) { 188 p_ep_regs = &udc->p_regs->EP_REGS[num]; 189 data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS); 190 buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPN_BUF_TYPE; 191 if (buf_type == 0) { 192 /* Single Buffer */ 193 use_ram_size += (data & EPN_MPKT) / sizeof(u32); 194 } else { 195 /* Double Buffer */ 196 use_ram_size += ((data & EPN_MPKT) / sizeof(u32)) * 2; 197 } 198 199 if ((data >> 16) > last_ram_adr) 200 last_ram_adr = data >> 16; 201 } 202 203 return last_ram_adr + use_ram_size; 204 } 205 206 /*-------------------------------------------------------------------------*/ 207 /* Construction of Endpoint */ 208 static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 209 { 210 u32 num; 211 u32 data; 212 u32 begin_adrs; 213 214 if (ep->epnum == 0) 215 return -EINVAL; 216 217 num = ep->epnum - 1; 218 219 /*-------------------------------------------------------------*/ 220 /* RAM Transfer Address */ 221 begin_adrs = _nbu2ss_get_begin_ram_address(udc); 222 data = (begin_adrs << 16) | ep->ep.maxpacket; 223 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data); 224 225 /*-------------------------------------------------------------*/ 226 /* Interrupt Enable */ 227 data = 1 << (ep->epnum + 8); 228 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data); 229 230 /*-------------------------------------------------------------*/ 231 /* Endpoint Type(Mode) */ 232 /* Bulk, Interrupt, ISO */ 233 switch (ep->ep_type) { 234 case USB_ENDPOINT_XFER_BULK: 235 data = EPN_BULK; 236 break; 237 238 case USB_ENDPOINT_XFER_INT: 239 data = EPN_BUF_SINGLE | EPN_INTERRUPT; 240 break; 241 242 case USB_ENDPOINT_XFER_ISOC: 243 data = EPN_ISO; 244 break; 245 246 default: 247 data = 0; 248 break; 249 } 250 251 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 252 _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum | ep->direct)); 253 254 if (ep->direct == USB_DIR_OUT) { 255 /*---------------------------------------------------------*/ 256 /* OUT */ 257 data = EPN_EN | EPN_BCLR | EPN_DIR0; 258 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 259 260 data = EPN_ONAK | EPN_OSTL_EN | EPN_OSTL; 261 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 262 263 data = EPN_OUT_EN | EPN_OUT_END_EN; 264 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 265 } else { 266 /*---------------------------------------------------------*/ 267 /* IN */ 268 data = EPN_EN | EPN_BCLR | EPN_AUTO; 269 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 270 271 data = EPN_ISTL; 272 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 273 274 data = EPN_IN_EN | EPN_IN_END_EN; 275 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 276 } 277 278 return 0; 279 } 280 281 /*-------------------------------------------------------------------------*/ 282 /* Release of Endpoint */ 283 static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 284 { 285 u32 num; 286 u32 data; 287 288 if ((ep->epnum == 0) || (udc->vbus_active == 0)) 289 return -EINVAL; 290 291 num = ep->epnum - 1; 292 293 /*-------------------------------------------------------------*/ 294 /* RAM Transfer Address */ 295 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0); 296 297 /*-------------------------------------------------------------*/ 298 /* Interrupt Disable */ 299 data = 1 << (ep->epnum + 8); 300 _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data); 301 302 if (ep->direct == USB_DIR_OUT) { 303 /*---------------------------------------------------------*/ 304 /* OUT */ 305 data = EPN_ONAK | EPN_BCLR; 306 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 307 308 data = EPN_EN | EPN_DIR0; 309 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 310 311 data = EPN_OUT_EN | EPN_OUT_END_EN; 312 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 313 } else { 314 /*---------------------------------------------------------*/ 315 /* IN */ 316 data = EPN_BCLR; 317 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 318 319 data = EPN_EN | EPN_AUTO; 320 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 321 322 data = EPN_IN_EN | EPN_IN_END_EN; 323 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 324 } 325 326 return 0; 327 } 328 329 /*-------------------------------------------------------------------------*/ 330 /* DMA setting (without Endpoint 0) */ 331 static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 332 { 333 u32 num; 334 u32 data; 335 336 data = _nbu2ss_readl(&udc->p_regs->USBSSCONF); 337 if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0)) 338 return; /* Not Support DMA */ 339 340 num = ep->epnum - 1; 341 342 if (ep->direct == USB_DIR_OUT) { 343 /*---------------------------------------------------------*/ 344 /* OUT */ 345 data = ep->ep.maxpacket; 346 _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data); 347 348 /*---------------------------------------------------------*/ 349 /* Transfer Direct */ 350 data = DCR1_EPN_DIR0; 351 _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data); 352 353 /*---------------------------------------------------------*/ 354 /* DMA Mode etc. */ 355 data = EPN_STOP_MODE | EPN_STOP_SET | EPN_DMAMODE0; 356 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data); 357 } else { 358 /*---------------------------------------------------------*/ 359 /* IN */ 360 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPN_AUTO); 361 362 /*---------------------------------------------------------*/ 363 /* DMA Mode etc. */ 364 data = EPN_BURST_SET | EPN_DMAMODE0; 365 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data); 366 } 367 } 368 369 /*-------------------------------------------------------------------------*/ 370 /* DMA setting release */ 371 static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 372 { 373 u32 num; 374 u32 data; 375 struct fc_regs __iomem *preg = udc->p_regs; 376 377 if (udc->vbus_active == 0) 378 return; /* VBUS OFF */ 379 380 data = _nbu2ss_readl(&preg->USBSSCONF); 381 if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0)) 382 return; /* Not Support DMA */ 383 384 num = ep->epnum - 1; 385 386 _nbu2ss_ep_dma_abort(udc, ep); 387 388 if (ep->direct == USB_DIR_OUT) { 389 /*---------------------------------------------------------*/ 390 /* OUT */ 391 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0); 392 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_DIR0); 393 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); 394 } else { 395 /*---------------------------------------------------------*/ 396 /* IN */ 397 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); 398 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); 399 } 400 } 401 402 /*-------------------------------------------------------------------------*/ 403 /* Abort DMA */ 404 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 405 { 406 struct fc_regs __iomem *preg = udc->p_regs; 407 408 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPN_REQEN); 409 mdelay(DMA_DISABLE_TIME); /* DCR1_EPN_REQEN Clear */ 410 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPN_DMA_EN); 411 } 412 413 /*-------------------------------------------------------------------------*/ 414 /* Start IN Transfer */ 415 static void _nbu2ss_ep_in_end(struct nbu2ss_udc *udc, 416 u32 epnum, u32 data32, u32 length) 417 { 418 u32 data; 419 u32 num; 420 struct fc_regs __iomem *preg = udc->p_regs; 421 422 if (length >= sizeof(u32)) 423 return; 424 425 if (epnum == 0) { 426 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO); 427 428 /* Writing of 1-4 bytes */ 429 if (length) 430 _nbu2ss_writel(&preg->EP0_WRITE, data32); 431 432 data = ((length << 5) & EP0_DW) | EP0_DEND; 433 _nbu2ss_writel(&preg->EP0_CONTROL, data); 434 435 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO); 436 } else { 437 num = epnum - 1; 438 439 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); 440 441 /* Writing of 1-4 bytes */ 442 if (length) 443 _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32); 444 445 data = (((length) << 5) & EPN_DW) | EPN_DEND; 446 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data); 447 448 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); 449 } 450 } 451 452 #ifdef USE_DMA 453 /*-------------------------------------------------------------------------*/ 454 static void _nbu2ss_dma_map_single(struct nbu2ss_udc *udc, 455 struct nbu2ss_ep *ep, 456 struct nbu2ss_req *req, u8 direct) 457 { 458 if (req->req.dma == DMA_ADDR_INVALID) { 459 if (req->unaligned) { 460 req->req.dma = ep->phys_buf; 461 } else { 462 req->req.dma = dma_map_single(udc->gadget.dev.parent, 463 req->req.buf, 464 req->req.length, 465 (direct == USB_DIR_IN) 466 ? DMA_TO_DEVICE 467 : DMA_FROM_DEVICE); 468 } 469 req->mapped = 1; 470 } else { 471 if (!req->unaligned) 472 dma_sync_single_for_device(udc->gadget.dev.parent, 473 req->req.dma, 474 req->req.length, 475 (direct == USB_DIR_IN) 476 ? DMA_TO_DEVICE 477 : DMA_FROM_DEVICE); 478 479 req->mapped = 0; 480 } 481 } 482 483 /*-------------------------------------------------------------------------*/ 484 static void _nbu2ss_dma_unmap_single(struct nbu2ss_udc *udc, 485 struct nbu2ss_ep *ep, 486 struct nbu2ss_req *req, u8 direct) 487 { 488 u8 data[4]; 489 u8 *p; 490 u32 count = 0; 491 492 if (direct == USB_DIR_OUT) { 493 count = req->req.actual % 4; 494 if (count) { 495 p = req->req.buf; 496 p += (req->req.actual - count); 497 memcpy(data, p, count); 498 } 499 } 500 501 if (req->mapped) { 502 if (req->unaligned) { 503 if (direct == USB_DIR_OUT) 504 memcpy(req->req.buf, ep->virt_buf, 505 req->req.actual & 0xfffffffc); 506 } else { 507 dma_unmap_single(udc->gadget.dev.parent, 508 req->req.dma, req->req.length, 509 (direct == USB_DIR_IN) 510 ? DMA_TO_DEVICE 511 : DMA_FROM_DEVICE); 512 } 513 req->req.dma = DMA_ADDR_INVALID; 514 req->mapped = 0; 515 } else { 516 if (!req->unaligned) 517 dma_sync_single_for_cpu(udc->gadget.dev.parent, 518 req->req.dma, req->req.length, 519 (direct == USB_DIR_IN) 520 ? DMA_TO_DEVICE 521 : DMA_FROM_DEVICE); 522 } 523 524 if (count) { 525 p = req->req.buf; 526 p += (req->req.actual - count); 527 memcpy(p, data, count); 528 } 529 } 530 #endif 531 532 /*-------------------------------------------------------------------------*/ 533 /* Endpoint 0 OUT Transfer (PIO) */ 534 static int ep0_out_pio(struct nbu2ss_udc *udc, u8 *buf, u32 length) 535 { 536 u32 i; 537 u32 numreads = length / sizeof(u32); 538 union usb_reg_access *buf32 = (union usb_reg_access *)buf; 539 540 if (!numreads) 541 return 0; 542 543 /* PIO Read */ 544 for (i = 0; i < numreads; i++) { 545 buf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ); 546 buf32++; 547 } 548 549 return numreads * sizeof(u32); 550 } 551 552 /*-------------------------------------------------------------------------*/ 553 /* Endpoint 0 OUT Transfer (PIO, OverBytes) */ 554 static int ep0_out_overbytes(struct nbu2ss_udc *udc, u8 *p_buf, u32 length) 555 { 556 u32 i; 557 u32 i_read_size = 0; 558 union usb_reg_access temp_32; 559 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; 560 561 if ((length > 0) && (length < sizeof(u32))) { 562 temp_32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ); 563 for (i = 0 ; i < length ; i++) 564 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i]; 565 i_read_size += length; 566 } 567 568 return i_read_size; 569 } 570 571 /*-------------------------------------------------------------------------*/ 572 /* Endpoint 0 IN Transfer (PIO) */ 573 static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *p_buf, u32 length) 574 { 575 u32 i; 576 u32 i_max_length = EP0_PACKETSIZE; 577 u32 i_word_length = 0; 578 u32 i_write_length = 0; 579 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; 580 581 /*------------------------------------------------------------*/ 582 /* Transfer Length */ 583 if (i_max_length < length) 584 i_word_length = i_max_length / sizeof(u32); 585 else 586 i_word_length = length / sizeof(u32); 587 588 /*------------------------------------------------------------*/ 589 /* PIO */ 590 for (i = 0; i < i_word_length; i++) { 591 _nbu2ss_writel(&udc->p_regs->EP0_WRITE, p_buf_32->dw); 592 p_buf_32++; 593 i_write_length += sizeof(u32); 594 } 595 596 return i_write_length; 597 } 598 599 /*-------------------------------------------------------------------------*/ 600 /* Endpoint 0 IN Transfer (PIO, OverBytes) */ 601 static int ep0_in_overbytes(struct nbu2ss_udc *udc, 602 u8 *p_buf, 603 u32 i_remain_size) 604 { 605 u32 i; 606 union usb_reg_access temp_32; 607 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; 608 609 if ((i_remain_size > 0) && (i_remain_size < sizeof(u32))) { 610 for (i = 0 ; i < i_remain_size ; i++) 611 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i]; 612 _nbu2ss_ep_in_end(udc, 0, temp_32.dw, i_remain_size); 613 614 return i_remain_size; 615 } 616 617 return 0; 618 } 619 620 /*-------------------------------------------------------------------------*/ 621 /* Transfer NULL Packet (Epndoint 0) */ 622 static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag) 623 { 624 u32 data; 625 626 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 627 data &= ~(u32)EP0_INAK; 628 629 if (pid_flag) 630 data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND); 631 else 632 data |= (EP0_INAK_EN | EP0_DEND); 633 634 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); 635 636 return 0; 637 } 638 639 /*-------------------------------------------------------------------------*/ 640 /* Receive NULL Packet (Endpoint 0) */ 641 static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag) 642 { 643 u32 data; 644 645 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 646 data &= ~(u32)EP0_ONAK; 647 648 if (pid_flag) 649 data |= EP0_PIDCLR; 650 651 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); 652 653 return 0; 654 } 655 656 /*-------------------------------------------------------------------------*/ 657 static int _nbu2ss_ep0_in_transfer(struct nbu2ss_udc *udc, 658 struct nbu2ss_req *req) 659 { 660 u8 *p_buffer; /* IN Data Buffer */ 661 u32 data; 662 u32 i_remain_size = 0; 663 int result = 0; 664 665 /*-------------------------------------------------------------*/ 666 /* End confirmation */ 667 if (req->req.actual == req->req.length) { 668 if ((req->req.actual % EP0_PACKETSIZE) == 0) { 669 if (req->zero) { 670 req->zero = false; 671 EP0_send_NULL(udc, false); 672 return 1; 673 } 674 } 675 676 return 0; /* Transfer End */ 677 } 678 679 /*-------------------------------------------------------------*/ 680 /* NAK release */ 681 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 682 data |= EP0_INAK_EN; 683 data &= ~(u32)EP0_INAK; 684 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); 685 686 i_remain_size = req->req.length - req->req.actual; 687 p_buffer = (u8 *)req->req.buf; 688 p_buffer += req->req.actual; 689 690 /*-------------------------------------------------------------*/ 691 /* Data transfer */ 692 result = EP0_in_PIO(udc, p_buffer, i_remain_size); 693 694 req->div_len = result; 695 i_remain_size -= result; 696 697 if (i_remain_size == 0) { 698 EP0_send_NULL(udc, false); 699 return result; 700 } 701 702 if ((i_remain_size < sizeof(u32)) && (result != EP0_PACKETSIZE)) { 703 p_buffer += result; 704 result += ep0_in_overbytes(udc, p_buffer, i_remain_size); 705 req->div_len = result; 706 } 707 708 return result; 709 } 710 711 /*-------------------------------------------------------------------------*/ 712 static int _nbu2ss_ep0_out_transfer(struct nbu2ss_udc *udc, 713 struct nbu2ss_req *req) 714 { 715 u8 *p_buffer; 716 u32 i_remain_size; 717 u32 i_recv_length; 718 int result = 0; 719 int f_rcv_zero; 720 721 /*-------------------------------------------------------------*/ 722 /* Receive data confirmation */ 723 i_recv_length = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA; 724 if (i_recv_length != 0) { 725 f_rcv_zero = 0; 726 727 i_remain_size = req->req.length - req->req.actual; 728 p_buffer = (u8 *)req->req.buf; 729 p_buffer += req->req.actual; 730 731 result = ep0_out_pio(udc, p_buffer 732 , min(i_remain_size, i_recv_length)); 733 if (result < 0) 734 return result; 735 736 req->req.actual += result; 737 i_recv_length -= result; 738 739 if ((i_recv_length > 0) && (i_recv_length < sizeof(u32))) { 740 p_buffer += result; 741 i_remain_size -= result; 742 743 result = ep0_out_overbytes(udc, p_buffer 744 , min(i_remain_size, i_recv_length)); 745 req->req.actual += result; 746 } 747 } else { 748 f_rcv_zero = 1; 749 } 750 751 /*-------------------------------------------------------------*/ 752 /* End confirmation */ 753 if (req->req.actual == req->req.length) { 754 if ((req->req.actual % EP0_PACKETSIZE) == 0) { 755 if (req->zero) { 756 req->zero = false; 757 EP0_receive_NULL(udc, false); 758 return 1; 759 } 760 } 761 762 return 0; /* Transfer End */ 763 } 764 765 if ((req->req.actual % EP0_PACKETSIZE) != 0) 766 return 0; /* Short Packet Transfer End */ 767 768 if (req->req.actual > req->req.length) { 769 dev_err(udc->dev, " *** Overrun Error\n"); 770 return -EOVERFLOW; 771 } 772 773 if (f_rcv_zero != 0) { 774 i_remain_size = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 775 if (i_remain_size & EP0_ONAK) { 776 /*---------------------------------------------------*/ 777 /* NACK release */ 778 _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK); 779 } 780 result = 1; 781 } 782 783 return result; 784 } 785 786 /*-------------------------------------------------------------------------*/ 787 static int _nbu2ss_out_dma(struct nbu2ss_udc *udc, struct nbu2ss_req *req, 788 u32 num, u32 length) 789 { 790 dma_addr_t p_buffer; 791 u32 mpkt; 792 u32 lmpkt; 793 u32 dmacnt; 794 u32 burst = 1; 795 u32 data; 796 int result; 797 struct fc_regs __iomem *preg = udc->p_regs; 798 799 if (req->dma_flag) 800 return 1; /* DMA is forwarded */ 801 802 req->dma_flag = true; 803 p_buffer = req->req.dma; 804 p_buffer += req->req.actual; 805 806 /* DMA Address */ 807 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer); 808 809 /* Number of transfer packets */ 810 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT; 811 dmacnt = length / mpkt; 812 lmpkt = (length % mpkt) & ~(u32)0x03; 813 814 if (dmacnt > DMA_MAX_COUNT) { 815 dmacnt = DMA_MAX_COUNT; 816 lmpkt = 0; 817 } else if (lmpkt != 0) { 818 if (dmacnt == 0) 819 burst = 0; /* Burst OFF */ 820 dmacnt++; 821 } 822 823 data = mpkt | (lmpkt << 16); 824 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data); 825 826 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_DIR0 | DCR1_EPN_REQEN; 827 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data); 828 829 if (burst == 0) { 830 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0); 831 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET); 832 } else { 833 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT 834 , (dmacnt << 16)); 835 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET); 836 } 837 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN); 838 839 result = length & ~(u32)0x03; 840 req->div_len = result; 841 842 return result; 843 } 844 845 /*-------------------------------------------------------------------------*/ 846 static int _nbu2ss_epn_out_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep, 847 struct nbu2ss_req *req, u32 length) 848 { 849 u8 *p_buffer; 850 u32 i; 851 u32 data; 852 u32 i_word_length; 853 union usb_reg_access temp_32; 854 union usb_reg_access *p_buf_32; 855 int result = 0; 856 struct fc_regs __iomem *preg = udc->p_regs; 857 858 if (req->dma_flag) 859 return 1; /* DMA is forwarded */ 860 861 if (length == 0) 862 return 0; 863 864 p_buffer = (u8 *)req->req.buf; 865 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual); 866 867 i_word_length = length / sizeof(u32); 868 if (i_word_length > 0) { 869 /*---------------------------------------------------------*/ 870 /* Copy of every four bytes */ 871 for (i = 0; i < i_word_length; i++) { 872 p_buf_32->dw = 873 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ); 874 p_buf_32++; 875 } 876 result = i_word_length * sizeof(u32); 877 } 878 879 data = length - result; 880 if (data > 0) { 881 /*---------------------------------------------------------*/ 882 /* Copy of fraction byte */ 883 temp_32.dw = 884 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ); 885 for (i = 0 ; i < data ; i++) 886 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i]; 887 result += data; 888 } 889 890 req->req.actual += result; 891 892 if ((req->req.actual == req->req.length) || 893 ((req->req.actual % ep->ep.maxpacket) != 0)) { 894 result = 0; 895 } 896 897 return result; 898 } 899 900 /*-------------------------------------------------------------------------*/ 901 static int _nbu2ss_epn_out_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep, 902 struct nbu2ss_req *req, u32 data_size) 903 { 904 u32 num; 905 u32 i_buf_size; 906 int nret = 1; 907 908 if (ep->epnum == 0) 909 return -EINVAL; 910 911 num = ep->epnum - 1; 912 913 i_buf_size = min((req->req.length - req->req.actual), data_size); 914 915 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) && 916 (i_buf_size >= sizeof(u32))) { 917 nret = _nbu2ss_out_dma(udc, req, num, i_buf_size); 918 } else { 919 i_buf_size = min_t(u32, i_buf_size, ep->ep.maxpacket); 920 nret = _nbu2ss_epn_out_pio(udc, ep, req, i_buf_size); 921 } 922 923 return nret; 924 } 925 926 /*-------------------------------------------------------------------------*/ 927 static int _nbu2ss_epn_out_transfer(struct nbu2ss_udc *udc, 928 struct nbu2ss_ep *ep, 929 struct nbu2ss_req *req) 930 { 931 u32 num; 932 u32 i_recv_length; 933 int result = 1; 934 struct fc_regs __iomem *preg = udc->p_regs; 935 936 if (ep->epnum == 0) 937 return -EINVAL; 938 939 num = ep->epnum - 1; 940 941 /*-------------------------------------------------------------*/ 942 /* Receive Length */ 943 i_recv_length = 944 _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPN_LDATA; 945 946 if (i_recv_length != 0) { 947 result = _nbu2ss_epn_out_data(udc, ep, req, i_recv_length); 948 if (i_recv_length < ep->ep.maxpacket) { 949 if (i_recv_length == result) { 950 req->req.actual += result; 951 result = 0; 952 } 953 } 954 } else { 955 if ((req->req.actual == req->req.length) || 956 ((req->req.actual % ep->ep.maxpacket) != 0)) { 957 result = 0; 958 } 959 } 960 961 if (result == 0) { 962 if ((req->req.actual % ep->ep.maxpacket) == 0) { 963 if (req->zero) { 964 req->zero = false; 965 return 1; 966 } 967 } 968 } 969 970 if (req->req.actual > req->req.length) { 971 dev_err(udc->dev, " Overrun Error\n"); 972 dev_err(udc->dev, " actual = %d, length = %d\n", 973 req->req.actual, req->req.length); 974 result = -EOVERFLOW; 975 } 976 977 return result; 978 } 979 980 /*-------------------------------------------------------------------------*/ 981 static int _nbu2ss_in_dma(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep, 982 struct nbu2ss_req *req, u32 num, u32 length) 983 { 984 dma_addr_t p_buffer; 985 u32 mpkt; /* MaxPacketSize */ 986 u32 lmpkt; /* Last Packet Data Size */ 987 u32 dmacnt; /* IN Data Size */ 988 u32 i_write_length; 989 u32 data; 990 int result = -EINVAL; 991 struct fc_regs __iomem *preg = udc->p_regs; 992 993 if (req->dma_flag) 994 return 1; /* DMA is forwarded */ 995 996 #ifdef USE_DMA 997 if (req->req.actual == 0) 998 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN); 999 #endif 1000 req->dma_flag = true; 1001 1002 /* MAX Packet Size */ 1003 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT; 1004 1005 if ((DMA_MAX_COUNT * mpkt) < length) 1006 i_write_length = DMA_MAX_COUNT * mpkt; 1007 else 1008 i_write_length = length; 1009 1010 /*------------------------------------------------------------*/ 1011 /* Number of transmission packets */ 1012 if (mpkt < i_write_length) { 1013 dmacnt = i_write_length / mpkt; 1014 lmpkt = (i_write_length % mpkt) & ~(u32)0x3; 1015 if (lmpkt != 0) 1016 dmacnt++; 1017 else 1018 lmpkt = mpkt & ~(u32)0x3; 1019 1020 } else { 1021 dmacnt = 1; 1022 lmpkt = i_write_length & ~(u32)0x3; 1023 } 1024 1025 /* Packet setting */ 1026 data = mpkt | (lmpkt << 16); 1027 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data); 1028 1029 /* Address setting */ 1030 p_buffer = req->req.dma; 1031 p_buffer += req->req.actual; 1032 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer); 1033 1034 /* Packet and DMA setting */ 1035 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_REQEN; 1036 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data); 1037 1038 /* Packet setting of EPC */ 1039 data = dmacnt << 16; 1040 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data); 1041 1042 /*DMA setting of EPC */ 1043 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN); 1044 1045 result = i_write_length & ~(u32)0x3; 1046 req->div_len = result; 1047 1048 return result; 1049 } 1050 1051 /*-------------------------------------------------------------------------*/ 1052 static int _nbu2ss_epn_in_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep, 1053 struct nbu2ss_req *req, u32 length) 1054 { 1055 u8 *p_buffer; 1056 u32 i; 1057 u32 data; 1058 u32 i_word_length; 1059 union usb_reg_access temp_32; 1060 union usb_reg_access *p_buf_32 = NULL; 1061 int result = 0; 1062 struct fc_regs __iomem *preg = udc->p_regs; 1063 1064 if (req->dma_flag) 1065 return 1; /* DMA is forwarded */ 1066 1067 if (length > 0) { 1068 p_buffer = (u8 *)req->req.buf; 1069 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual); 1070 1071 i_word_length = length / sizeof(u32); 1072 if (i_word_length > 0) { 1073 for (i = 0; i < i_word_length; i++) { 1074 _nbu2ss_writel( 1075 &preg->EP_REGS[ep->epnum - 1].EP_WRITE, 1076 p_buf_32->dw); 1077 1078 p_buf_32++; 1079 } 1080 result = i_word_length * sizeof(u32); 1081 } 1082 } 1083 1084 if (result != ep->ep.maxpacket) { 1085 data = length - result; 1086 temp_32.dw = 0; 1087 for (i = 0 ; i < data ; i++) 1088 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i]; 1089 1090 _nbu2ss_ep_in_end(udc, ep->epnum, temp_32.dw, data); 1091 result += data; 1092 } 1093 1094 req->div_len = result; 1095 1096 return result; 1097 } 1098 1099 /*-------------------------------------------------------------------------*/ 1100 static int _nbu2ss_epn_in_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep, 1101 struct nbu2ss_req *req, u32 data_size) 1102 { 1103 u32 num; 1104 int nret = 1; 1105 1106 if (ep->epnum == 0) 1107 return -EINVAL; 1108 1109 num = ep->epnum - 1; 1110 1111 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) && 1112 (data_size >= sizeof(u32))) { 1113 nret = _nbu2ss_in_dma(udc, ep, req, num, data_size); 1114 } else { 1115 data_size = min_t(u32, data_size, ep->ep.maxpacket); 1116 nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size); 1117 } 1118 1119 return nret; 1120 } 1121 1122 /*-------------------------------------------------------------------------*/ 1123 static int _nbu2ss_epn_in_transfer(struct nbu2ss_udc *udc, 1124 struct nbu2ss_ep *ep, struct nbu2ss_req *req) 1125 { 1126 u32 num; 1127 u32 i_buf_size; 1128 int result = 0; 1129 u32 status; 1130 1131 if (ep->epnum == 0) 1132 return -EINVAL; 1133 1134 num = ep->epnum - 1; 1135 1136 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS); 1137 1138 /*-------------------------------------------------------------*/ 1139 /* State confirmation of FIFO */ 1140 if (req->req.actual == 0) { 1141 if ((status & EPN_IN_EMPTY) == 0) 1142 return 1; /* Not Empty */ 1143 1144 } else { 1145 if ((status & EPN_IN_FULL) != 0) 1146 return 1; /* Not Empty */ 1147 } 1148 1149 /*-------------------------------------------------------------*/ 1150 /* Start transfer */ 1151 i_buf_size = req->req.length - req->req.actual; 1152 if (i_buf_size > 0) 1153 result = _nbu2ss_epn_in_data(udc, ep, req, i_buf_size); 1154 else if (req->req.length == 0) 1155 _nbu2ss_zero_len_pkt(udc, ep->epnum); 1156 1157 return result; 1158 } 1159 1160 /*-------------------------------------------------------------------------*/ 1161 static int _nbu2ss_start_transfer(struct nbu2ss_udc *udc, 1162 struct nbu2ss_ep *ep, 1163 struct nbu2ss_req *req, 1164 bool bflag) 1165 { 1166 int nret = -EINVAL; 1167 1168 req->dma_flag = false; 1169 req->div_len = 0; 1170 1171 if (req->req.length == 0) { 1172 req->zero = false; 1173 } else { 1174 if ((req->req.length % ep->ep.maxpacket) == 0) 1175 req->zero = req->req.zero; 1176 else 1177 req->zero = false; 1178 } 1179 1180 if (ep->epnum == 0) { 1181 /* EP0 */ 1182 switch (udc->ep0state) { 1183 case EP0_IN_DATA_PHASE: 1184 nret = _nbu2ss_ep0_in_transfer(udc, req); 1185 break; 1186 1187 case EP0_OUT_DATA_PHASE: 1188 nret = _nbu2ss_ep0_out_transfer(udc, req); 1189 break; 1190 1191 case EP0_IN_STATUS_PHASE: 1192 nret = EP0_send_NULL(udc, true); 1193 break; 1194 1195 default: 1196 break; 1197 } 1198 1199 } else { 1200 /* EPN */ 1201 if (ep->direct == USB_DIR_OUT) { 1202 /* OUT */ 1203 if (!bflag) 1204 nret = _nbu2ss_epn_out_transfer(udc, ep, req); 1205 } else { 1206 /* IN */ 1207 nret = _nbu2ss_epn_in_transfer(udc, ep, req); 1208 } 1209 } 1210 1211 return nret; 1212 } 1213 1214 /*-------------------------------------------------------------------------*/ 1215 static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep) 1216 { 1217 u32 length; 1218 bool bflag = false; 1219 struct nbu2ss_req *req; 1220 1221 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1222 if (!req) 1223 return; 1224 1225 if (ep->epnum > 0) { 1226 length = _nbu2ss_readl( 1227 &ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT); 1228 1229 length &= EPN_LDATA; 1230 if (length < ep->ep.maxpacket) 1231 bflag = true; 1232 } 1233 1234 _nbu2ss_start_transfer(ep->udc, ep, req, bflag); 1235 } 1236 1237 /*-------------------------------------------------------------------------*/ 1238 /* Endpoint Toggle Reset */ 1239 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs) 1240 { 1241 u8 num; 1242 u32 data; 1243 1244 if ((ep_adrs == 0) || (ep_adrs == 0x80)) 1245 return; 1246 1247 num = (ep_adrs & 0x7F) - 1; 1248 1249 if (ep_adrs & USB_DIR_IN) 1250 data = EPN_IPIDCLR; 1251 else 1252 data = EPN_BCLR | EPN_OPIDCLR; 1253 1254 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 1255 } 1256 1257 /*-------------------------------------------------------------------------*/ 1258 /* Endpoint STALL set */ 1259 static void _nbu2ss_set_endpoint_stall(struct nbu2ss_udc *udc, 1260 u8 ep_adrs, bool bstall) 1261 { 1262 u8 num, epnum; 1263 u32 data; 1264 struct nbu2ss_ep *ep; 1265 struct fc_regs __iomem *preg = udc->p_regs; 1266 1267 if ((ep_adrs == 0) || (ep_adrs == 0x80)) { 1268 if (bstall) { 1269 /* Set STALL */ 1270 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL); 1271 } else { 1272 /* Clear STALL */ 1273 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL); 1274 } 1275 } else { 1276 epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK; 1277 num = epnum - 1; 1278 ep = &udc->ep[epnum]; 1279 1280 if (bstall) { 1281 /* Set STALL */ 1282 ep->halted = true; 1283 1284 if (ep_adrs & USB_DIR_IN) 1285 data = EPN_BCLR | EPN_ISTL; 1286 else 1287 data = EPN_OSTL_EN | EPN_OSTL; 1288 1289 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data); 1290 } else { 1291 if (ep_adrs & USB_DIR_IN) { 1292 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL 1293 , EPN_ISTL); 1294 } else { 1295 data = 1296 _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL); 1297 1298 data &= ~EPN_OSTL; 1299 data |= EPN_OSTL_EN; 1300 1301 _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL 1302 , data); 1303 } 1304 1305 /* Clear STALL */ 1306 ep->stalled = false; 1307 if (ep->halted) { 1308 ep->halted = false; 1309 _nbu2ss_restert_transfer(ep); 1310 } 1311 } 1312 } 1313 } 1314 1315 /*-------------------------------------------------------------------------*/ 1316 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode) 1317 { 1318 u32 data; 1319 1320 if (mode > MAX_TEST_MODE_NUM) 1321 return; 1322 1323 dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode); 1324 1325 data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL); 1326 data &= ~TEST_FORCE_ENABLE; 1327 data |= mode << TEST_MODE_SHIFT; 1328 1329 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data); 1330 _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN); 1331 } 1332 1333 /*-------------------------------------------------------------------------*/ 1334 static int _nbu2ss_set_feature_device(struct nbu2ss_udc *udc, 1335 u16 selector, u16 wIndex) 1336 { 1337 int result = -EOPNOTSUPP; 1338 1339 switch (selector) { 1340 case USB_DEVICE_REMOTE_WAKEUP: 1341 if (wIndex == 0x0000) { 1342 udc->remote_wakeup = U2F_ENABLE; 1343 result = 0; 1344 } 1345 break; 1346 1347 case USB_DEVICE_TEST_MODE: 1348 wIndex >>= 8; 1349 if (wIndex <= MAX_TEST_MODE_NUM) 1350 result = 0; 1351 break; 1352 1353 default: 1354 break; 1355 } 1356 1357 return result; 1358 } 1359 1360 /*-------------------------------------------------------------------------*/ 1361 static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs) 1362 { 1363 u8 epnum; 1364 u32 data = 0, bit_data; 1365 struct fc_regs __iomem *preg = udc->p_regs; 1366 1367 epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK; 1368 if (epnum == 0) { 1369 data = _nbu2ss_readl(&preg->EP0_CONTROL); 1370 bit_data = EP0_STL; 1371 1372 } else { 1373 data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL); 1374 if ((data & EPN_EN) == 0) 1375 return -1; 1376 1377 if (ep_adrs & USB_ENDPOINT_DIR_MASK) 1378 bit_data = EPN_ISTL; 1379 else 1380 bit_data = EPN_OSTL; 1381 } 1382 1383 if ((data & bit_data) == 0) 1384 return 0; 1385 return 1; 1386 } 1387 1388 /*-------------------------------------------------------------------------*/ 1389 static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset) 1390 { 1391 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK); 1392 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN); 1393 u16 selector = le16_to_cpu(udc->ctrl.wValue); 1394 u16 wIndex = le16_to_cpu(udc->ctrl.wIndex); 1395 u8 ep_adrs; 1396 int result = -EOPNOTSUPP; 1397 1398 if ((udc->ctrl.wLength != 0x0000) || 1399 (direction != USB_DIR_OUT)) { 1400 return -EINVAL; 1401 } 1402 1403 switch (recipient) { 1404 case USB_RECIP_DEVICE: 1405 if (bset) 1406 result = 1407 _nbu2ss_set_feature_device(udc, selector, wIndex); 1408 break; 1409 1410 case USB_RECIP_ENDPOINT: 1411 if (0x0000 == (wIndex & 0xFF70)) { 1412 if (selector == USB_ENDPOINT_HALT) { 1413 ep_adrs = wIndex & 0xFF; 1414 if (!bset) { 1415 _nbu2ss_endpoint_toggle_reset(udc, 1416 ep_adrs); 1417 } 1418 1419 _nbu2ss_set_endpoint_stall(udc, ep_adrs, bset); 1420 1421 result = 0; 1422 } 1423 } 1424 break; 1425 1426 default: 1427 break; 1428 } 1429 1430 if (result >= 0) 1431 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0); 1432 1433 return result; 1434 } 1435 1436 /*-------------------------------------------------------------------------*/ 1437 static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc) 1438 { 1439 u32 data; 1440 enum usb_device_speed speed = USB_SPEED_FULL; 1441 1442 data = _nbu2ss_readl(&udc->p_regs->USB_STATUS); 1443 if (data & HIGH_SPEED) 1444 speed = USB_SPEED_HIGH; 1445 1446 return speed; 1447 } 1448 1449 /*-------------------------------------------------------------------------*/ 1450 static void _nbu2ss_epn_set_stall(struct nbu2ss_udc *udc, 1451 struct nbu2ss_ep *ep) 1452 { 1453 u8 ep_adrs; 1454 u32 regdata; 1455 int limit_cnt = 0; 1456 1457 struct fc_regs __iomem *preg = udc->p_regs; 1458 1459 if (ep->direct == USB_DIR_IN) { 1460 for (limit_cnt = 0 1461 ; limit_cnt < IN_DATA_EMPTY_COUNT 1462 ; limit_cnt++) { 1463 regdata = _nbu2ss_readl( 1464 &preg->EP_REGS[ep->epnum - 1].EP_STATUS); 1465 1466 if ((regdata & EPN_IN_DATA) == 0) 1467 break; 1468 1469 mdelay(1); 1470 } 1471 } 1472 1473 ep_adrs = ep->epnum | ep->direct; 1474 _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1); 1475 } 1476 1477 /*-------------------------------------------------------------------------*/ 1478 static int std_req_get_status(struct nbu2ss_udc *udc) 1479 { 1480 u32 length; 1481 u16 status_data = 0; 1482 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK); 1483 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN); 1484 u8 ep_adrs; 1485 int result = -EINVAL; 1486 1487 if ((udc->ctrl.wValue != 0x0000) || (direction != USB_DIR_IN)) 1488 return result; 1489 1490 length = 1491 min_t(u16, le16_to_cpu(udc->ctrl.wLength), sizeof(status_data)); 1492 switch (recipient) { 1493 case USB_RECIP_DEVICE: 1494 if (udc->ctrl.wIndex == 0x0000) { 1495 if (udc->gadget.is_selfpowered) 1496 status_data |= BIT(USB_DEVICE_SELF_POWERED); 1497 1498 if (udc->remote_wakeup) 1499 status_data |= BIT(USB_DEVICE_REMOTE_WAKEUP); 1500 1501 result = 0; 1502 } 1503 break; 1504 1505 case USB_RECIP_ENDPOINT: 1506 if (0x0000 == (le16_to_cpu(udc->ctrl.wIndex) & 0xFF70)) { 1507 ep_adrs = (u8)(le16_to_cpu(udc->ctrl.wIndex) & 0xFF); 1508 result = _nbu2ss_get_ep_stall(udc, ep_adrs); 1509 1510 if (result > 0) 1511 status_data |= BIT(USB_ENDPOINT_HALT); 1512 } 1513 break; 1514 1515 default: 1516 break; 1517 } 1518 1519 if (result >= 0) { 1520 memcpy(udc->ep0_buf, &status_data, length); 1521 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length); 1522 _nbu2ss_ep0_in_transfer(udc, &udc->ep0_req); 1523 1524 } else { 1525 dev_err(udc->dev, " Error GET_STATUS\n"); 1526 } 1527 1528 return result; 1529 } 1530 1531 /*-------------------------------------------------------------------------*/ 1532 static int std_req_clear_feature(struct nbu2ss_udc *udc) 1533 { 1534 return _nbu2ss_req_feature(udc, false); 1535 } 1536 1537 /*-------------------------------------------------------------------------*/ 1538 static int std_req_set_feature(struct nbu2ss_udc *udc) 1539 { 1540 return _nbu2ss_req_feature(udc, true); 1541 } 1542 1543 /*-------------------------------------------------------------------------*/ 1544 static int std_req_set_address(struct nbu2ss_udc *udc) 1545 { 1546 int result = 0; 1547 u32 wValue = le16_to_cpu(udc->ctrl.wValue); 1548 1549 if ((udc->ctrl.bRequestType != 0x00) || 1550 (udc->ctrl.wIndex != 0x0000) || 1551 (udc->ctrl.wLength != 0x0000)) { 1552 return -EINVAL; 1553 } 1554 1555 if (wValue != (wValue & 0x007F)) 1556 return -EINVAL; 1557 1558 wValue <<= USB_ADRS_SHIFT; 1559 1560 _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue); 1561 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0); 1562 1563 return result; 1564 } 1565 1566 /*-------------------------------------------------------------------------*/ 1567 static int std_req_set_configuration(struct nbu2ss_udc *udc) 1568 { 1569 u32 config_value = (u32)(le16_to_cpu(udc->ctrl.wValue) & 0x00ff); 1570 1571 if ((udc->ctrl.wIndex != 0x0000) || 1572 (udc->ctrl.wLength != 0x0000) || 1573 (udc->ctrl.bRequestType != 0x00)) { 1574 return -EINVAL; 1575 } 1576 1577 udc->curr_config = config_value; 1578 1579 if (config_value > 0) { 1580 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF); 1581 udc->devstate = USB_STATE_CONFIGURED; 1582 1583 } else { 1584 _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF); 1585 udc->devstate = USB_STATE_ADDRESS; 1586 } 1587 1588 return 0; 1589 } 1590 1591 /*-------------------------------------------------------------------------*/ 1592 static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata) 1593 { 1594 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0); 1595 pdata++; 1596 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1); 1597 } 1598 1599 /*-------------------------------------------------------------------------*/ 1600 static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc) 1601 { 1602 bool bcall_back = true; 1603 int nret = -EINVAL; 1604 struct usb_ctrlrequest *p_ctrl; 1605 1606 p_ctrl = &udc->ctrl; 1607 _nbu2ss_read_request_data(udc, (u32 *)p_ctrl); 1608 1609 /* ep0 state control */ 1610 if (p_ctrl->wLength == 0) { 1611 udc->ep0state = EP0_IN_STATUS_PHASE; 1612 1613 } else { 1614 if (p_ctrl->bRequestType & USB_DIR_IN) 1615 udc->ep0state = EP0_IN_DATA_PHASE; 1616 else 1617 udc->ep0state = EP0_OUT_DATA_PHASE; 1618 } 1619 1620 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 1621 switch (p_ctrl->bRequest) { 1622 case USB_REQ_GET_STATUS: 1623 nret = std_req_get_status(udc); 1624 bcall_back = false; 1625 break; 1626 1627 case USB_REQ_CLEAR_FEATURE: 1628 nret = std_req_clear_feature(udc); 1629 bcall_back = false; 1630 break; 1631 1632 case USB_REQ_SET_FEATURE: 1633 nret = std_req_set_feature(udc); 1634 bcall_back = false; 1635 break; 1636 1637 case USB_REQ_SET_ADDRESS: 1638 nret = std_req_set_address(udc); 1639 bcall_back = false; 1640 break; 1641 1642 case USB_REQ_SET_CONFIGURATION: 1643 nret = std_req_set_configuration(udc); 1644 break; 1645 1646 default: 1647 break; 1648 } 1649 } 1650 1651 if (!bcall_back) { 1652 if (udc->ep0state == EP0_IN_STATUS_PHASE) { 1653 if (nret >= 0) { 1654 /*--------------------------------------*/ 1655 /* Status Stage */ 1656 nret = EP0_send_NULL(udc, true); 1657 } 1658 } 1659 1660 } else { 1661 spin_unlock(&udc->lock); 1662 nret = udc->driver->setup(&udc->gadget, &udc->ctrl); 1663 spin_lock(&udc->lock); 1664 } 1665 1666 if (nret < 0) 1667 udc->ep0state = EP0_IDLE; 1668 1669 return nret; 1670 } 1671 1672 /*-------------------------------------------------------------------------*/ 1673 static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc) 1674 { 1675 int nret; 1676 struct nbu2ss_req *req; 1677 struct nbu2ss_ep *ep = &udc->ep[0]; 1678 1679 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1680 if (!req) 1681 req = &udc->ep0_req; 1682 1683 req->req.actual += req->div_len; 1684 req->div_len = 0; 1685 1686 nret = _nbu2ss_ep0_in_transfer(udc, req); 1687 if (nret == 0) { 1688 udc->ep0state = EP0_OUT_STATUS_PAHSE; 1689 EP0_receive_NULL(udc, true); 1690 } 1691 1692 return 0; 1693 } 1694 1695 /*-------------------------------------------------------------------------*/ 1696 static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc) 1697 { 1698 int nret; 1699 struct nbu2ss_req *req; 1700 struct nbu2ss_ep *ep = &udc->ep[0]; 1701 1702 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1703 if (!req) 1704 req = &udc->ep0_req; 1705 1706 nret = _nbu2ss_ep0_out_transfer(udc, req); 1707 if (nret == 0) { 1708 udc->ep0state = EP0_IN_STATUS_PHASE; 1709 EP0_send_NULL(udc, true); 1710 1711 } else if (nret < 0) { 1712 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR); 1713 req->req.status = nret; 1714 } 1715 1716 return 0; 1717 } 1718 1719 /*-------------------------------------------------------------------------*/ 1720 static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc) 1721 { 1722 struct nbu2ss_req *req; 1723 struct nbu2ss_ep *ep = &udc->ep[0]; 1724 1725 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1726 if (!req) { 1727 req = &udc->ep0_req; 1728 if (req->req.complete) 1729 req->req.complete(&ep->ep, &req->req); 1730 1731 } else { 1732 if (req->req.complete) 1733 _nbu2ss_ep_done(ep, req, 0); 1734 } 1735 1736 udc->ep0state = EP0_IDLE; 1737 1738 return 0; 1739 } 1740 1741 /*-------------------------------------------------------------------------*/ 1742 static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc) 1743 { 1744 int i; 1745 u32 status; 1746 u32 intr; 1747 int nret = -1; 1748 1749 status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS); 1750 intr = status & EP0_STATUS_RW_BIT; 1751 _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~intr); 1752 1753 status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT 1754 | STG_END_INT | EP0_OUT_NULL_INT); 1755 1756 if (status == 0) { 1757 dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__); 1758 dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr); 1759 return; 1760 } 1761 1762 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1763 udc->gadget.speed = _nbu2ss_get_speed(udc); 1764 1765 for (i = 0; i < EP0_END_XFER; i++) { 1766 switch (udc->ep0state) { 1767 case EP0_IDLE: 1768 if (status & SETUP_INT) { 1769 status = 0; 1770 nret = _nbu2ss_decode_request(udc); 1771 } 1772 break; 1773 1774 case EP0_IN_DATA_PHASE: 1775 if (status & EP0_IN_INT) { 1776 status &= ~EP0_IN_INT; 1777 nret = _nbu2ss_ep0_in_data_stage(udc); 1778 } 1779 break; 1780 1781 case EP0_OUT_DATA_PHASE: 1782 if (status & EP0_OUT_INT) { 1783 status &= ~EP0_OUT_INT; 1784 nret = _nbu2ss_ep0_out_data_stage(udc); 1785 } 1786 break; 1787 1788 case EP0_IN_STATUS_PHASE: 1789 if ((status & STG_END_INT) || (status & SETUP_INT)) { 1790 status &= ~(STG_END_INT | EP0_IN_INT); 1791 nret = _nbu2ss_ep0_status_stage(udc); 1792 } 1793 break; 1794 1795 case EP0_OUT_STATUS_PAHSE: 1796 if ((status & STG_END_INT) || (status & SETUP_INT) || 1797 (status & EP0_OUT_NULL_INT)) { 1798 status &= ~(STG_END_INT 1799 | EP0_OUT_INT 1800 | EP0_OUT_NULL_INT); 1801 1802 nret = _nbu2ss_ep0_status_stage(udc); 1803 } 1804 1805 break; 1806 1807 default: 1808 status = 0; 1809 break; 1810 } 1811 1812 if (status == 0) 1813 break; 1814 } 1815 1816 if (nret < 0) { 1817 /* Send Stall */ 1818 _nbu2ss_set_endpoint_stall(udc, 0, true); 1819 } 1820 } 1821 1822 /*-------------------------------------------------------------------------*/ 1823 static void _nbu2ss_ep_done(struct nbu2ss_ep *ep, 1824 struct nbu2ss_req *req, 1825 int status) 1826 { 1827 struct nbu2ss_udc *udc = ep->udc; 1828 1829 list_del_init(&req->queue); 1830 1831 if (status == -ECONNRESET) 1832 _nbu2ss_fifo_flush(udc, ep); 1833 1834 if (likely(req->req.status == -EINPROGRESS)) 1835 req->req.status = status; 1836 1837 if (ep->stalled) { 1838 _nbu2ss_epn_set_stall(udc, ep); 1839 } else { 1840 if (!list_empty(&ep->queue)) 1841 _nbu2ss_restert_transfer(ep); 1842 } 1843 1844 #ifdef USE_DMA 1845 if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) && 1846 (req->req.dma != 0)) 1847 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT); 1848 #endif 1849 1850 spin_unlock(&udc->lock); 1851 req->req.complete(&ep->ep, &req->req); 1852 spin_lock(&udc->lock); 1853 } 1854 1855 /*-------------------------------------------------------------------------*/ 1856 static inline void _nbu2ss_epn_in_int(struct nbu2ss_udc *udc, 1857 struct nbu2ss_ep *ep, 1858 struct nbu2ss_req *req) 1859 { 1860 int result = 0; 1861 u32 status; 1862 1863 struct fc_regs __iomem *preg = udc->p_regs; 1864 1865 if (req->dma_flag) 1866 return; /* DMA is forwarded */ 1867 1868 req->req.actual += req->div_len; 1869 req->div_len = 0; 1870 1871 if (req->req.actual != req->req.length) { 1872 /*---------------------------------------------------------*/ 1873 /* remainder of data */ 1874 result = _nbu2ss_epn_in_transfer(udc, ep, req); 1875 1876 } else { 1877 if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) { 1878 status = 1879 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS); 1880 1881 if ((status & EPN_IN_FULL) == 0) { 1882 /*-----------------------------------------*/ 1883 /* 0 Length Packet */ 1884 req->zero = false; 1885 _nbu2ss_zero_len_pkt(udc, ep->epnum); 1886 } 1887 return; 1888 } 1889 } 1890 1891 if (result <= 0) { 1892 /*---------------------------------------------------------*/ 1893 /* Complete */ 1894 _nbu2ss_ep_done(ep, req, result); 1895 } 1896 } 1897 1898 /*-------------------------------------------------------------------------*/ 1899 static inline void _nbu2ss_epn_out_int(struct nbu2ss_udc *udc, 1900 struct nbu2ss_ep *ep, 1901 struct nbu2ss_req *req) 1902 { 1903 int result; 1904 1905 result = _nbu2ss_epn_out_transfer(udc, ep, req); 1906 if (result <= 0) 1907 _nbu2ss_ep_done(ep, req, result); 1908 } 1909 1910 /*-------------------------------------------------------------------------*/ 1911 static inline void _nbu2ss_epn_in_dma_int(struct nbu2ss_udc *udc, 1912 struct nbu2ss_ep *ep, 1913 struct nbu2ss_req *req) 1914 { 1915 u32 mpkt; 1916 u32 size; 1917 struct usb_request *preq; 1918 1919 preq = &req->req; 1920 1921 if (!req->dma_flag) 1922 return; 1923 1924 preq->actual += req->div_len; 1925 req->div_len = 0; 1926 req->dma_flag = false; 1927 1928 #ifdef USE_DMA 1929 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN); 1930 #endif 1931 1932 if (preq->actual != preq->length) { 1933 _nbu2ss_epn_in_transfer(udc, ep, req); 1934 } else { 1935 mpkt = ep->ep.maxpacket; 1936 size = preq->actual % mpkt; 1937 if (size > 0) { 1938 if (((preq->actual & 0x03) == 0) && (size < mpkt)) 1939 _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0); 1940 } else { 1941 _nbu2ss_epn_in_int(udc, ep, req); 1942 } 1943 } 1944 } 1945 1946 /*-------------------------------------------------------------------------*/ 1947 static inline void _nbu2ss_epn_out_dma_int(struct nbu2ss_udc *udc, 1948 struct nbu2ss_ep *ep, 1949 struct nbu2ss_req *req) 1950 { 1951 int i; 1952 u32 num; 1953 u32 dmacnt, ep_dmacnt; 1954 u32 mpkt; 1955 struct fc_regs __iomem *preg = udc->p_regs; 1956 1957 num = ep->epnum - 1; 1958 1959 if (req->req.actual == req->req.length) { 1960 if ((req->req.length % ep->ep.maxpacket) && !req->zero) { 1961 req->div_len = 0; 1962 req->dma_flag = false; 1963 _nbu2ss_ep_done(ep, req, 0); 1964 return; 1965 } 1966 } 1967 1968 ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) 1969 & EPN_DMACNT; 1970 ep_dmacnt >>= 16; 1971 1972 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) { 1973 dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1) 1974 & DCR1_EPN_DMACNT; 1975 dmacnt >>= 16; 1976 if (ep_dmacnt == dmacnt) 1977 break; 1978 } 1979 1980 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_REQEN); 1981 1982 if (dmacnt != 0) { 1983 mpkt = ep->ep.maxpacket; 1984 if ((req->div_len % mpkt) == 0) 1985 req->div_len -= mpkt * dmacnt; 1986 } 1987 1988 if ((req->req.actual % ep->ep.maxpacket) > 0) { 1989 if (req->req.actual == req->div_len) { 1990 req->div_len = 0; 1991 req->dma_flag = false; 1992 _nbu2ss_ep_done(ep, req, 0); 1993 return; 1994 } 1995 } 1996 1997 req->req.actual += req->div_len; 1998 req->div_len = 0; 1999 req->dma_flag = false; 2000 2001 _nbu2ss_epn_out_int(udc, ep, req); 2002 } 2003 2004 /*-------------------------------------------------------------------------*/ 2005 static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum) 2006 { 2007 u32 num; 2008 u32 status; 2009 2010 struct nbu2ss_req *req; 2011 struct nbu2ss_ep *ep = &udc->ep[epnum]; 2012 2013 num = epnum - 1; 2014 2015 /* Interrupt Status */ 2016 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS); 2017 2018 /* Interrupt Clear */ 2019 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~status); 2020 2021 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 2022 if (!req) { 2023 /* pr_warn("=== %s(%d) req == NULL\n", __func__, epnum); */ 2024 return; 2025 } 2026 2027 if (status & EPN_OUT_END_INT) { 2028 status &= ~EPN_OUT_INT; 2029 _nbu2ss_epn_out_dma_int(udc, ep, req); 2030 } 2031 2032 if (status & EPN_OUT_INT) 2033 _nbu2ss_epn_out_int(udc, ep, req); 2034 2035 if (status & EPN_IN_END_INT) { 2036 status &= ~EPN_IN_INT; 2037 _nbu2ss_epn_in_dma_int(udc, ep, req); 2038 } 2039 2040 if (status & EPN_IN_INT) 2041 _nbu2ss_epn_in_int(udc, ep, req); 2042 } 2043 2044 /*-------------------------------------------------------------------------*/ 2045 static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum) 2046 { 2047 if (epnum == 0) 2048 _nbu2ss_ep0_int(udc); 2049 else 2050 _nbu2ss_epn_int(udc, epnum); 2051 } 2052 2053 /*-------------------------------------------------------------------------*/ 2054 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc) 2055 { 2056 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR)); 2057 _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT); 2058 } 2059 2060 /*-------------------------------------------------------------------------*/ 2061 static int _nbu2ss_nuke(struct nbu2ss_udc *udc, 2062 struct nbu2ss_ep *ep, 2063 int status) 2064 { 2065 struct nbu2ss_req *req; 2066 2067 /* Endpoint Disable */ 2068 _nbu2ss_epn_exit(udc, ep); 2069 2070 /* DMA Disable */ 2071 _nbu2ss_ep_dma_exit(udc, ep); 2072 2073 if (list_empty(&ep->queue)) 2074 return 0; 2075 2076 /* called with irqs blocked */ 2077 list_for_each_entry(req, &ep->queue, queue) { 2078 _nbu2ss_ep_done(ep, req, status); 2079 } 2080 2081 return 0; 2082 } 2083 2084 /*-------------------------------------------------------------------------*/ 2085 static void _nbu2ss_quiesce(struct nbu2ss_udc *udc) 2086 { 2087 struct nbu2ss_ep *ep; 2088 2089 udc->gadget.speed = USB_SPEED_UNKNOWN; 2090 2091 _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN); 2092 2093 /* Endpoint n */ 2094 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { 2095 _nbu2ss_nuke(udc, ep, -ESHUTDOWN); 2096 } 2097 } 2098 2099 /*-------------------------------------------------------------------------*/ 2100 static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on) 2101 { 2102 u32 reg_dt; 2103 2104 if (udc->vbus_active == 0) 2105 return -ESHUTDOWN; 2106 2107 if (is_on) { 2108 /* D+ Pullup */ 2109 if (udc->driver) { 2110 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) 2111 | PUE2) & ~(u32)CONNECTB; 2112 2113 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt); 2114 } 2115 2116 } else { 2117 /* D+ Pulldown */ 2118 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB) 2119 & ~(u32)PUE2; 2120 2121 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt); 2122 udc->gadget.speed = USB_SPEED_UNKNOWN; 2123 } 2124 2125 return 0; 2126 } 2127 2128 /*-------------------------------------------------------------------------*/ 2129 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 2130 { 2131 struct fc_regs __iomem *p = udc->p_regs; 2132 2133 if (udc->vbus_active == 0) 2134 return; 2135 2136 if (ep->epnum == 0) { 2137 /* EP0 */ 2138 _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR); 2139 2140 } else { 2141 /* EPN */ 2142 _nbu2ss_ep_dma_abort(udc, ep); 2143 _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPN_BCLR); 2144 } 2145 } 2146 2147 /*-------------------------------------------------------------------------*/ 2148 static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc) 2149 { 2150 int waitcnt = 0; 2151 2152 if (udc->udc_enabled) 2153 return 0; 2154 2155 /* Reset */ 2156 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST)); 2157 udelay(EPC_RST_DISABLE_TIME); /* 1us wait */ 2158 2159 _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD); 2160 mdelay(EPC_DIRPD_DISABLE_TIME); /* 1ms wait */ 2161 2162 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST); 2163 2164 _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE); 2165 2166 _nbu2ss_writel(&udc->p_regs->AHBMCTR, 2167 HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE); 2168 2169 while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) { 2170 waitcnt++; 2171 udelay(1); /* 1us wait */ 2172 if (waitcnt == EPC_PLL_LOCK_COUNT) { 2173 dev_err(udc->dev, "*** Reset Cancel failed\n"); 2174 return -EINVAL; 2175 } 2176 } 2177 2178 _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET); 2179 2180 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV)); 2181 2182 /* EP0 */ 2183 _nbu2ss_ep0_enable(udc); 2184 2185 /* USB Interrupt Enable */ 2186 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT); 2187 2188 udc->udc_enabled = true; 2189 2190 return 0; 2191 } 2192 2193 /*-------------------------------------------------------------------------*/ 2194 static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc) 2195 { 2196 _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST); 2197 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST); 2198 } 2199 2200 /*-------------------------------------------------------------------------*/ 2201 static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc) 2202 { 2203 if (udc->udc_enabled) { 2204 udc->udc_enabled = false; 2205 _nbu2ss_reset_controller(udc); 2206 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST)); 2207 } 2208 } 2209 2210 /*-------------------------------------------------------------------------*/ 2211 static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc) 2212 { 2213 int nret; 2214 u32 reg_dt; 2215 2216 /* chattering */ 2217 mdelay(VBUS_CHATTERING_MDELAY); /* wait (ms) */ 2218 2219 /* VBUS ON Check*/ 2220 reg_dt = gpiod_get_value(vbus_gpio); 2221 if (reg_dt == 0) { 2222 udc->linux_suspended = 0; 2223 2224 _nbu2ss_reset_controller(udc); 2225 dev_info(udc->dev, " ----- VBUS OFF\n"); 2226 2227 if (udc->vbus_active == 1) { 2228 /* VBUS OFF */ 2229 udc->vbus_active = 0; 2230 if (udc->usb_suspended) { 2231 udc->usb_suspended = 0; 2232 /* _nbu2ss_reset_controller(udc); */ 2233 } 2234 udc->devstate = USB_STATE_NOTATTACHED; 2235 2236 _nbu2ss_quiesce(udc); 2237 if (udc->driver) { 2238 spin_unlock(&udc->lock); 2239 udc->driver->disconnect(&udc->gadget); 2240 spin_lock(&udc->lock); 2241 } 2242 2243 _nbu2ss_disable_controller(udc); 2244 } 2245 } else { 2246 mdelay(5); /* wait (5ms) */ 2247 reg_dt = gpiod_get_value(vbus_gpio); 2248 if (reg_dt == 0) 2249 return; 2250 2251 dev_info(udc->dev, " ----- VBUS ON\n"); 2252 2253 if (udc->linux_suspended) 2254 return; 2255 2256 if (udc->vbus_active == 0) { 2257 /* VBUS ON */ 2258 udc->vbus_active = 1; 2259 udc->devstate = USB_STATE_POWERED; 2260 2261 nret = _nbu2ss_enable_controller(udc); 2262 if (nret < 0) { 2263 _nbu2ss_disable_controller(udc); 2264 udc->vbus_active = 0; 2265 return; 2266 } 2267 2268 _nbu2ss_pullup(udc, 1); 2269 2270 #ifdef UDC_DEBUG_DUMP 2271 _nbu2ss_dump_register(udc); 2272 #endif /* UDC_DEBUG_DUMP */ 2273 2274 } else { 2275 if (udc->devstate == USB_STATE_POWERED) 2276 _nbu2ss_pullup(udc, 1); 2277 } 2278 } 2279 } 2280 2281 /*-------------------------------------------------------------------------*/ 2282 static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc) 2283 { 2284 udc->devstate = USB_STATE_DEFAULT; 2285 udc->remote_wakeup = 0; 2286 2287 _nbu2ss_quiesce(udc); 2288 2289 udc->ep0state = EP0_IDLE; 2290 } 2291 2292 /*-------------------------------------------------------------------------*/ 2293 static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc) 2294 { 2295 if (udc->usb_suspended == 1) { 2296 udc->usb_suspended = 0; 2297 if (udc->driver && udc->driver->resume) { 2298 spin_unlock(&udc->lock); 2299 udc->driver->resume(&udc->gadget); 2300 spin_lock(&udc->lock); 2301 } 2302 } 2303 } 2304 2305 /*-------------------------------------------------------------------------*/ 2306 static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc) 2307 { 2308 u32 reg_dt; 2309 2310 if (udc->usb_suspended == 0) { 2311 reg_dt = gpiod_get_value(vbus_gpio); 2312 2313 if (reg_dt == 0) 2314 return; 2315 2316 udc->usb_suspended = 1; 2317 if (udc->driver && udc->driver->suspend) { 2318 spin_unlock(&udc->lock); 2319 udc->driver->suspend(&udc->gadget); 2320 spin_lock(&udc->lock); 2321 } 2322 2323 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND); 2324 } 2325 } 2326 2327 /*-------------------------------------------------------------------------*/ 2328 /* VBUS (GPIO153) Interrupt */ 2329 static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc) 2330 { 2331 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc; 2332 2333 spin_lock(&udc->lock); 2334 _nbu2ss_check_vbus(udc); 2335 spin_unlock(&udc->lock); 2336 2337 return IRQ_HANDLED; 2338 } 2339 2340 /*-------------------------------------------------------------------------*/ 2341 /* Interrupt (udc) */ 2342 static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc) 2343 { 2344 u8 suspend_flag = 0; 2345 u32 status; 2346 u32 epnum, int_bit; 2347 2348 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc; 2349 struct fc_regs __iomem *preg = udc->p_regs; 2350 2351 if (gpiod_get_value(vbus_gpio) == 0) { 2352 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW); 2353 _nbu2ss_writel(&preg->USB_INT_ENA, 0); 2354 return IRQ_HANDLED; 2355 } 2356 2357 spin_lock(&udc->lock); 2358 2359 for (;;) { 2360 if (gpiod_get_value(vbus_gpio) == 0) { 2361 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW); 2362 _nbu2ss_writel(&preg->USB_INT_ENA, 0); 2363 status = 0; 2364 } else { 2365 status = _nbu2ss_readl(&preg->USB_INT_STA); 2366 } 2367 2368 if (status == 0) 2369 break; 2370 2371 _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW)); 2372 2373 if (status & USB_RST_INT) { 2374 /* USB Reset */ 2375 _nbu2ss_int_bus_reset(udc); 2376 } 2377 2378 if (status & RSUM_INT) { 2379 /* Resume */ 2380 _nbu2ss_int_usb_resume(udc); 2381 } 2382 2383 if (status & SPND_INT) { 2384 /* Suspend */ 2385 suspend_flag = 1; 2386 } 2387 2388 if (status & EPN_INT) { 2389 /* EP INT */ 2390 int_bit = status >> 8; 2391 2392 for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) { 2393 if (0x01 & int_bit) 2394 _nbu2ss_ep_int(udc, epnum); 2395 2396 int_bit >>= 1; 2397 2398 if (int_bit == 0) 2399 break; 2400 } 2401 } 2402 } 2403 2404 if (suspend_flag) 2405 _nbu2ss_int_usb_suspend(udc); 2406 2407 spin_unlock(&udc->lock); 2408 2409 return IRQ_HANDLED; 2410 } 2411 2412 /*-------------------------------------------------------------------------*/ 2413 /* usb_ep_ops */ 2414 static int nbu2ss_ep_enable(struct usb_ep *_ep, 2415 const struct usb_endpoint_descriptor *desc) 2416 { 2417 u8 ep_type; 2418 unsigned long flags; 2419 2420 struct nbu2ss_ep *ep; 2421 struct nbu2ss_udc *udc; 2422 2423 if (!_ep || !desc) { 2424 pr_err(" *** %s, bad param\n", __func__); 2425 return -EINVAL; 2426 } 2427 2428 ep = container_of(_ep, struct nbu2ss_ep, ep); 2429 if (!ep->udc) { 2430 pr_err(" *** %s, ep == NULL !!\n", __func__); 2431 return -EINVAL; 2432 } 2433 2434 ep_type = usb_endpoint_type(desc); 2435 if ((ep_type == USB_ENDPOINT_XFER_CONTROL) || 2436 (ep_type == USB_ENDPOINT_XFER_ISOC)) { 2437 pr_err(" *** %s, bat bmAttributes\n", __func__); 2438 return -EINVAL; 2439 } 2440 2441 udc = ep->udc; 2442 if (udc->vbus_active == 0) 2443 return -ESHUTDOWN; 2444 2445 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { 2446 dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__); 2447 return -ESHUTDOWN; 2448 } 2449 2450 spin_lock_irqsave(&udc->lock, flags); 2451 2452 ep->desc = desc; 2453 ep->epnum = usb_endpoint_num(desc); 2454 ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK; 2455 ep->ep_type = ep_type; 2456 ep->wedged = 0; 2457 ep->halted = false; 2458 ep->stalled = false; 2459 2460 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize); 2461 2462 /* DMA setting */ 2463 _nbu2ss_ep_dma_init(udc, ep); 2464 2465 /* Endpoint setting */ 2466 _nbu2ss_ep_init(udc, ep); 2467 2468 spin_unlock_irqrestore(&udc->lock, flags); 2469 2470 return 0; 2471 } 2472 2473 /*-------------------------------------------------------------------------*/ 2474 static int nbu2ss_ep_disable(struct usb_ep *_ep) 2475 { 2476 struct nbu2ss_ep *ep; 2477 struct nbu2ss_udc *udc; 2478 unsigned long flags; 2479 2480 if (!_ep) { 2481 pr_err(" *** %s, bad param\n", __func__); 2482 return -EINVAL; 2483 } 2484 2485 ep = container_of(_ep, struct nbu2ss_ep, ep); 2486 if (!ep->udc) { 2487 pr_err("udc: *** %s, ep == NULL !!\n", __func__); 2488 return -EINVAL; 2489 } 2490 2491 udc = ep->udc; 2492 if (udc->vbus_active == 0) 2493 return -ESHUTDOWN; 2494 2495 spin_lock_irqsave(&udc->lock, flags); 2496 _nbu2ss_nuke(udc, ep, -EINPROGRESS); /* dequeue request */ 2497 spin_unlock_irqrestore(&udc->lock, flags); 2498 2499 return 0; 2500 } 2501 2502 /*-------------------------------------------------------------------------*/ 2503 static struct usb_request *nbu2ss_ep_alloc_request(struct usb_ep *ep, 2504 gfp_t gfp_flags) 2505 { 2506 struct nbu2ss_req *req; 2507 2508 req = kzalloc(sizeof(*req), gfp_flags); 2509 if (!req) 2510 return NULL; 2511 2512 #ifdef USE_DMA 2513 req->req.dma = DMA_ADDR_INVALID; 2514 #endif 2515 INIT_LIST_HEAD(&req->queue); 2516 2517 return &req->req; 2518 } 2519 2520 /*-------------------------------------------------------------------------*/ 2521 static void nbu2ss_ep_free_request(struct usb_ep *_ep, 2522 struct usb_request *_req) 2523 { 2524 struct nbu2ss_req *req; 2525 2526 if (_req) { 2527 req = container_of(_req, struct nbu2ss_req, req); 2528 2529 kfree(req); 2530 } 2531 } 2532 2533 /*-------------------------------------------------------------------------*/ 2534 static int nbu2ss_ep_queue(struct usb_ep *_ep, 2535 struct usb_request *_req, gfp_t gfp_flags) 2536 { 2537 struct nbu2ss_req *req; 2538 struct nbu2ss_ep *ep; 2539 struct nbu2ss_udc *udc; 2540 unsigned long flags; 2541 bool bflag; 2542 int result = -EINVAL; 2543 2544 /* catch various bogus parameters */ 2545 if (!_ep || !_req) { 2546 if (!_ep) 2547 pr_err("udc: %s --- _ep == NULL\n", __func__); 2548 2549 if (!_req) 2550 pr_err("udc: %s --- _req == NULL\n", __func__); 2551 2552 return -EINVAL; 2553 } 2554 2555 req = container_of(_req, struct nbu2ss_req, req); 2556 if (unlikely(!_req->complete || 2557 !_req->buf || 2558 !list_empty(&req->queue))) { 2559 if (!_req->complete) 2560 pr_err("udc: %s --- !_req->complete\n", __func__); 2561 2562 if (!_req->buf) 2563 pr_err("udc:%s --- !_req->buf\n", __func__); 2564 2565 if (!list_empty(&req->queue)) 2566 pr_err("%s --- !list_empty(&req->queue)\n", __func__); 2567 2568 return -EINVAL; 2569 } 2570 2571 ep = container_of(_ep, struct nbu2ss_ep, ep); 2572 udc = ep->udc; 2573 2574 if (udc->vbus_active == 0) { 2575 dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n"); 2576 return -ESHUTDOWN; 2577 } 2578 2579 if (unlikely(!udc->driver)) { 2580 dev_err(udc->dev, "%s, bogus device state %p\n", __func__, 2581 udc->driver); 2582 return -ESHUTDOWN; 2583 } 2584 2585 spin_lock_irqsave(&udc->lock, flags); 2586 2587 #ifdef USE_DMA 2588 if ((uintptr_t)req->req.buf & 0x3) 2589 req->unaligned = true; 2590 else 2591 req->unaligned = false; 2592 2593 if (req->unaligned) { 2594 if (!ep->virt_buf) 2595 ep->virt_buf = dma_alloc_coherent(udc->dev, PAGE_SIZE, 2596 &ep->phys_buf, 2597 GFP_ATOMIC | GFP_DMA); 2598 if (ep->epnum > 0) { 2599 if (ep->direct == USB_DIR_IN) 2600 memcpy(ep->virt_buf, req->req.buf, 2601 req->req.length); 2602 } 2603 } 2604 2605 if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) && 2606 (req->req.dma != 0)) 2607 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT); 2608 #endif 2609 2610 _req->status = -EINPROGRESS; 2611 _req->actual = 0; 2612 2613 bflag = list_empty(&ep->queue); 2614 list_add_tail(&req->queue, &ep->queue); 2615 2616 if (bflag && !ep->stalled) { 2617 result = _nbu2ss_start_transfer(udc, ep, req, false); 2618 if (result < 0) { 2619 dev_err(udc->dev, " *** %s, result = %d\n", __func__, 2620 result); 2621 list_del(&req->queue); 2622 } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) { 2623 #ifdef USE_DMA 2624 if (req->req.length < 4 && 2625 req->req.length == req->req.actual) 2626 #else 2627 if (req->req.length == req->req.actual) 2628 #endif 2629 _nbu2ss_ep_done(ep, req, result); 2630 } 2631 } 2632 2633 spin_unlock_irqrestore(&udc->lock, flags); 2634 2635 return 0; 2636 } 2637 2638 /*-------------------------------------------------------------------------*/ 2639 static int nbu2ss_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 2640 { 2641 struct nbu2ss_req *req; 2642 struct nbu2ss_ep *ep; 2643 struct nbu2ss_udc *udc; 2644 unsigned long flags; 2645 2646 /* catch various bogus parameters */ 2647 if (!_ep || !_req) { 2648 /* pr_err("%s, bad param(1)\n", __func__); */ 2649 return -EINVAL; 2650 } 2651 2652 ep = container_of(_ep, struct nbu2ss_ep, ep); 2653 2654 udc = ep->udc; 2655 if (!udc) 2656 return -EINVAL; 2657 2658 spin_lock_irqsave(&udc->lock, flags); 2659 2660 /* make sure it's actually queued on this endpoint */ 2661 list_for_each_entry(req, &ep->queue, queue) { 2662 if (&req->req == _req) { 2663 _nbu2ss_ep_done(ep, req, -ECONNRESET); 2664 spin_unlock_irqrestore(&udc->lock, flags); 2665 return 0; 2666 } 2667 } 2668 2669 spin_unlock_irqrestore(&udc->lock, flags); 2670 2671 pr_debug("%s no queue(EINVAL)\n", __func__); 2672 2673 return -EINVAL; 2674 } 2675 2676 /*-------------------------------------------------------------------------*/ 2677 static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value) 2678 { 2679 u8 ep_adrs; 2680 unsigned long flags; 2681 2682 struct nbu2ss_ep *ep; 2683 struct nbu2ss_udc *udc; 2684 2685 if (!_ep) { 2686 pr_err("%s, bad param\n", __func__); 2687 return -EINVAL; 2688 } 2689 2690 ep = container_of(_ep, struct nbu2ss_ep, ep); 2691 2692 udc = ep->udc; 2693 if (!udc) { 2694 dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__); 2695 return -EINVAL; 2696 } 2697 2698 spin_lock_irqsave(&udc->lock, flags); 2699 2700 ep_adrs = ep->epnum | ep->direct; 2701 if (value == 0) { 2702 _nbu2ss_set_endpoint_stall(udc, ep_adrs, value); 2703 ep->stalled = false; 2704 } else { 2705 if (list_empty(&ep->queue)) 2706 _nbu2ss_epn_set_stall(udc, ep); 2707 else 2708 ep->stalled = true; 2709 } 2710 2711 if (value == 0) 2712 ep->wedged = 0; 2713 2714 spin_unlock_irqrestore(&udc->lock, flags); 2715 2716 return 0; 2717 } 2718 2719 static int nbu2ss_ep_set_wedge(struct usb_ep *_ep) 2720 { 2721 return nbu2ss_ep_set_halt(_ep, 1); 2722 } 2723 2724 /*-------------------------------------------------------------------------*/ 2725 static int nbu2ss_ep_fifo_status(struct usb_ep *_ep) 2726 { 2727 u32 data; 2728 struct nbu2ss_ep *ep; 2729 struct nbu2ss_udc *udc; 2730 unsigned long flags; 2731 struct fc_regs __iomem *preg; 2732 2733 if (!_ep) { 2734 pr_err("%s, bad param\n", __func__); 2735 return -EINVAL; 2736 } 2737 2738 ep = container_of(_ep, struct nbu2ss_ep, ep); 2739 2740 udc = ep->udc; 2741 if (!udc) { 2742 dev_err(ep->udc->dev, "%s, bad udc\n", __func__); 2743 return -EINVAL; 2744 } 2745 2746 preg = udc->p_regs; 2747 2748 data = gpiod_get_value(vbus_gpio); 2749 if (data == 0) 2750 return -EINVAL; 2751 2752 spin_lock_irqsave(&udc->lock, flags); 2753 2754 if (ep->epnum == 0) { 2755 data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA; 2756 2757 } else { 2758 data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT) 2759 & EPN_LDATA; 2760 } 2761 2762 spin_unlock_irqrestore(&udc->lock, flags); 2763 2764 return 0; 2765 } 2766 2767 /*-------------------------------------------------------------------------*/ 2768 static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep) 2769 { 2770 u32 data; 2771 struct nbu2ss_ep *ep; 2772 struct nbu2ss_udc *udc; 2773 unsigned long flags; 2774 2775 if (!_ep) { 2776 pr_err("udc: %s, bad param\n", __func__); 2777 return; 2778 } 2779 2780 ep = container_of(_ep, struct nbu2ss_ep, ep); 2781 2782 udc = ep->udc; 2783 if (!udc) { 2784 dev_err(ep->udc->dev, "%s, bad udc\n", __func__); 2785 return; 2786 } 2787 2788 data = gpiod_get_value(vbus_gpio); 2789 if (data == 0) 2790 return; 2791 2792 spin_lock_irqsave(&udc->lock, flags); 2793 _nbu2ss_fifo_flush(udc, ep); 2794 spin_unlock_irqrestore(&udc->lock, flags); 2795 } 2796 2797 /*-------------------------------------------------------------------------*/ 2798 static const struct usb_ep_ops nbu2ss_ep_ops = { 2799 .enable = nbu2ss_ep_enable, 2800 .disable = nbu2ss_ep_disable, 2801 2802 .alloc_request = nbu2ss_ep_alloc_request, 2803 .free_request = nbu2ss_ep_free_request, 2804 2805 .queue = nbu2ss_ep_queue, 2806 .dequeue = nbu2ss_ep_dequeue, 2807 2808 .set_halt = nbu2ss_ep_set_halt, 2809 .set_wedge = nbu2ss_ep_set_wedge, 2810 2811 .fifo_status = nbu2ss_ep_fifo_status, 2812 .fifo_flush = nbu2ss_ep_fifo_flush, 2813 }; 2814 2815 /*-------------------------------------------------------------------------*/ 2816 /* usb_gadget_ops */ 2817 2818 /*-------------------------------------------------------------------------*/ 2819 static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget) 2820 { 2821 u32 data; 2822 struct nbu2ss_udc *udc; 2823 2824 if (!pgadget) { 2825 pr_err("udc: %s, bad param\n", __func__); 2826 return -EINVAL; 2827 } 2828 2829 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2830 data = gpiod_get_value(vbus_gpio); 2831 if (data == 0) 2832 return -EINVAL; 2833 2834 return _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME; 2835 } 2836 2837 /*-------------------------------------------------------------------------*/ 2838 static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget) 2839 { 2840 int i; 2841 u32 data; 2842 2843 struct nbu2ss_udc *udc; 2844 2845 if (!pgadget) { 2846 pr_err("%s, bad param\n", __func__); 2847 return -EINVAL; 2848 } 2849 2850 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2851 2852 data = gpiod_get_value(vbus_gpio); 2853 if (data == 0) { 2854 dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data); 2855 return -EINVAL; 2856 } 2857 2858 _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME); 2859 2860 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) { 2861 data = _nbu2ss_readl(&udc->p_regs->EPCTR); 2862 2863 if (data & PLL_LOCK) 2864 break; 2865 } 2866 2867 _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME); 2868 2869 return 0; 2870 } 2871 2872 /*-------------------------------------------------------------------------*/ 2873 static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget, 2874 int is_selfpowered) 2875 { 2876 struct nbu2ss_udc *udc; 2877 unsigned long flags; 2878 2879 if (!pgadget) { 2880 pr_err("%s, bad param\n", __func__); 2881 return -EINVAL; 2882 } 2883 2884 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2885 2886 spin_lock_irqsave(&udc->lock, flags); 2887 pgadget->is_selfpowered = (is_selfpowered != 0); 2888 spin_unlock_irqrestore(&udc->lock, flags); 2889 2890 return 0; 2891 } 2892 2893 /*-------------------------------------------------------------------------*/ 2894 static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active) 2895 { 2896 return 0; 2897 } 2898 2899 /*-------------------------------------------------------------------------*/ 2900 static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned int mA) 2901 { 2902 struct nbu2ss_udc *udc; 2903 unsigned long flags; 2904 2905 if (!pgadget) { 2906 pr_err("%s, bad param\n", __func__); 2907 return -EINVAL; 2908 } 2909 2910 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2911 2912 spin_lock_irqsave(&udc->lock, flags); 2913 udc->mA = mA; 2914 spin_unlock_irqrestore(&udc->lock, flags); 2915 2916 return 0; 2917 } 2918 2919 /*-------------------------------------------------------------------------*/ 2920 static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on) 2921 { 2922 struct nbu2ss_udc *udc; 2923 unsigned long flags; 2924 2925 if (!pgadget) { 2926 pr_err("%s, bad param\n", __func__); 2927 return -EINVAL; 2928 } 2929 2930 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2931 2932 if (!udc->driver) { 2933 pr_warn("%s, Not Regist Driver\n", __func__); 2934 return -EINVAL; 2935 } 2936 2937 if (udc->vbus_active == 0) 2938 return -ESHUTDOWN; 2939 2940 spin_lock_irqsave(&udc->lock, flags); 2941 _nbu2ss_pullup(udc, is_on); 2942 spin_unlock_irqrestore(&udc->lock, flags); 2943 2944 return 0; 2945 } 2946 2947 /*-------------------------------------------------------------------------*/ 2948 static int nbu2ss_gad_ioctl(struct usb_gadget *pgadget, 2949 unsigned int code, unsigned long param) 2950 { 2951 return 0; 2952 } 2953 2954 static const struct usb_gadget_ops nbu2ss_gadget_ops = { 2955 .get_frame = nbu2ss_gad_get_frame, 2956 .wakeup = nbu2ss_gad_wakeup, 2957 .set_selfpowered = nbu2ss_gad_set_selfpowered, 2958 .vbus_session = nbu2ss_gad_vbus_session, 2959 .vbus_draw = nbu2ss_gad_vbus_draw, 2960 .pullup = nbu2ss_gad_pullup, 2961 .ioctl = nbu2ss_gad_ioctl, 2962 }; 2963 2964 static const struct { 2965 const char *name; 2966 const struct usb_ep_caps caps; 2967 } ep_info[NUM_ENDPOINTS] = { 2968 #define EP_INFO(_name, _caps) \ 2969 { \ 2970 .name = _name, \ 2971 .caps = _caps, \ 2972 } 2973 2974 EP_INFO("ep0", 2975 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)), 2976 EP_INFO("ep1-bulk", 2977 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 2978 EP_INFO("ep2-bulk", 2979 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 2980 EP_INFO("ep3in-int", 2981 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)), 2982 EP_INFO("ep4-iso", 2983 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 2984 EP_INFO("ep5-iso", 2985 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 2986 EP_INFO("ep6-bulk", 2987 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 2988 EP_INFO("ep7-bulk", 2989 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 2990 EP_INFO("ep8in-int", 2991 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)), 2992 EP_INFO("ep9-iso", 2993 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 2994 EP_INFO("epa-iso", 2995 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 2996 EP_INFO("epb-bulk", 2997 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 2998 EP_INFO("epc-bulk", 2999 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 3000 EP_INFO("epdin-int", 3001 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)), 3002 3003 #undef EP_INFO 3004 }; 3005 3006 /*-------------------------------------------------------------------------*/ 3007 static void nbu2ss_drv_ep_init(struct nbu2ss_udc *udc) 3008 { 3009 int i; 3010 3011 INIT_LIST_HEAD(&udc->gadget.ep_list); 3012 udc->gadget.ep0 = &udc->ep[0].ep; 3013 3014 for (i = 0; i < NUM_ENDPOINTS; i++) { 3015 struct nbu2ss_ep *ep = &udc->ep[i]; 3016 3017 ep->udc = udc; 3018 ep->desc = NULL; 3019 3020 ep->ep.driver_data = NULL; 3021 ep->ep.name = ep_info[i].name; 3022 ep->ep.caps = ep_info[i].caps; 3023 ep->ep.ops = &nbu2ss_ep_ops; 3024 3025 usb_ep_set_maxpacket_limit(&ep->ep, 3026 i == 0 ? EP0_PACKETSIZE 3027 : EP_PACKETSIZE); 3028 3029 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 3030 INIT_LIST_HEAD(&ep->queue); 3031 } 3032 3033 list_del_init(&udc->ep[0].ep.ep_list); 3034 } 3035 3036 /*-------------------------------------------------------------------------*/ 3037 /* platform_driver */ 3038 static int nbu2ss_drv_contest_init(struct platform_device *pdev, 3039 struct nbu2ss_udc *udc) 3040 { 3041 spin_lock_init(&udc->lock); 3042 udc->dev = &pdev->dev; 3043 3044 udc->gadget.is_selfpowered = 1; 3045 udc->devstate = USB_STATE_NOTATTACHED; 3046 udc->pdev = pdev; 3047 udc->mA = 0; 3048 3049 udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 3050 3051 /* init Endpoint */ 3052 nbu2ss_drv_ep_init(udc); 3053 3054 /* init Gadget */ 3055 udc->gadget.ops = &nbu2ss_gadget_ops; 3056 udc->gadget.ep0 = &udc->ep[0].ep; 3057 udc->gadget.speed = USB_SPEED_UNKNOWN; 3058 udc->gadget.name = driver_name; 3059 /* udc->gadget.is_dualspeed = 1; */ 3060 3061 device_initialize(&udc->gadget.dev); 3062 3063 dev_set_name(&udc->gadget.dev, "gadget"); 3064 udc->gadget.dev.parent = &pdev->dev; 3065 udc->gadget.dev.dma_mask = pdev->dev.dma_mask; 3066 3067 return 0; 3068 } 3069 3070 /* 3071 * probe - binds to the platform device 3072 */ 3073 static int nbu2ss_drv_probe(struct platform_device *pdev) 3074 { 3075 int status; 3076 struct nbu2ss_udc *udc; 3077 int irq; 3078 void __iomem *mmio_base; 3079 3080 udc = &udc_controller; 3081 memset(udc, 0, sizeof(struct nbu2ss_udc)); 3082 3083 platform_set_drvdata(pdev, udc); 3084 3085 /* require I/O memory and IRQ to be provided as resources */ 3086 mmio_base = devm_platform_ioremap_resource(pdev, 0); 3087 if (IS_ERR(mmio_base)) 3088 return PTR_ERR(mmio_base); 3089 3090 irq = platform_get_irq(pdev, 0); 3091 if (irq < 0) 3092 return irq; 3093 status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq, 3094 0, driver_name, udc); 3095 3096 /* IO Memory */ 3097 udc->p_regs = (struct fc_regs __iomem *)mmio_base; 3098 3099 /* USB Function Controller Interrupt */ 3100 if (status != 0) { 3101 dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n"); 3102 return status; 3103 } 3104 3105 /* Driver Initialization */ 3106 status = nbu2ss_drv_contest_init(pdev, udc); 3107 if (status < 0) { 3108 /* Error */ 3109 return status; 3110 } 3111 3112 /* VBUS Interrupt */ 3113 vbus_irq = gpiod_to_irq(vbus_gpio); 3114 irq_set_irq_type(vbus_irq, IRQ_TYPE_EDGE_BOTH); 3115 status = request_irq(vbus_irq, 3116 _nbu2ss_vbus_irq, IRQF_SHARED, driver_name, udc); 3117 3118 if (status != 0) { 3119 dev_err(udc->dev, "request_irq(vbus_irq) failed\n"); 3120 return status; 3121 } 3122 3123 return status; 3124 } 3125 3126 /*-------------------------------------------------------------------------*/ 3127 static void nbu2ss_drv_shutdown(struct platform_device *pdev) 3128 { 3129 struct nbu2ss_udc *udc; 3130 3131 udc = platform_get_drvdata(pdev); 3132 if (!udc) 3133 return; 3134 3135 _nbu2ss_disable_controller(udc); 3136 } 3137 3138 /*-------------------------------------------------------------------------*/ 3139 static int nbu2ss_drv_remove(struct platform_device *pdev) 3140 { 3141 struct nbu2ss_udc *udc; 3142 struct nbu2ss_ep *ep; 3143 int i; 3144 3145 udc = &udc_controller; 3146 3147 for (i = 0; i < NUM_ENDPOINTS; i++) { 3148 ep = &udc->ep[i]; 3149 if (ep->virt_buf) 3150 dma_free_coherent(udc->dev, PAGE_SIZE, (void *)ep->virt_buf, 3151 ep->phys_buf); 3152 } 3153 3154 /* Interrupt Handler - Release */ 3155 free_irq(vbus_irq, udc); 3156 3157 return 0; 3158 } 3159 3160 /*-------------------------------------------------------------------------*/ 3161 static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state) 3162 { 3163 struct nbu2ss_udc *udc; 3164 3165 udc = platform_get_drvdata(pdev); 3166 if (!udc) 3167 return 0; 3168 3169 if (udc->vbus_active) { 3170 udc->vbus_active = 0; 3171 udc->devstate = USB_STATE_NOTATTACHED; 3172 udc->linux_suspended = 1; 3173 3174 if (udc->usb_suspended) { 3175 udc->usb_suspended = 0; 3176 _nbu2ss_reset_controller(udc); 3177 } 3178 3179 _nbu2ss_quiesce(udc); 3180 } 3181 _nbu2ss_disable_controller(udc); 3182 3183 return 0; 3184 } 3185 3186 /*-------------------------------------------------------------------------*/ 3187 static int nbu2ss_drv_resume(struct platform_device *pdev) 3188 { 3189 u32 data; 3190 struct nbu2ss_udc *udc; 3191 3192 udc = platform_get_drvdata(pdev); 3193 if (!udc) 3194 return 0; 3195 3196 data = gpiod_get_value(vbus_gpio); 3197 if (data) { 3198 udc->vbus_active = 1; 3199 udc->devstate = USB_STATE_POWERED; 3200 _nbu2ss_enable_controller(udc); 3201 _nbu2ss_pullup(udc, 1); 3202 } 3203 3204 udc->linux_suspended = 0; 3205 3206 return 0; 3207 } 3208 3209 static struct platform_driver udc_driver = { 3210 .probe = nbu2ss_drv_probe, 3211 .shutdown = nbu2ss_drv_shutdown, 3212 .remove = nbu2ss_drv_remove, 3213 .suspend = nbu2ss_drv_suspend, 3214 .resume = nbu2ss_drv_resume, 3215 .driver = { 3216 .name = driver_name, 3217 }, 3218 }; 3219 3220 module_platform_driver(udc_driver); 3221 3222 MODULE_DESCRIPTION(DRIVER_DESC); 3223 MODULE_AUTHOR("Renesas Electronics Corporation"); 3224 MODULE_LICENSE("GPL"); 3225