1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/usb/gadget/emxx_udc.c 4 * EMXX FCD (Function Controller Driver) for USB. 5 * 6 * Copyright (C) 2010 Renesas Electronics Corporation 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/delay.h> 13 #include <linux/ioport.h> 14 #include <linux/slab.h> 15 #include <linux/errno.h> 16 #include <linux/list.h> 17 #include <linux/interrupt.h> 18 #include <linux/proc_fs.h> 19 #include <linux/clk.h> 20 #include <linux/ctype.h> 21 #include <linux/string.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/workqueue.h> 24 #include <linux/device.h> 25 26 #include <linux/usb/ch9.h> 27 #include <linux/usb/gadget.h> 28 29 #include <linux/irq.h> 30 #include <linux/gpio.h> 31 32 #include "emxx_udc.h" 33 34 #define DRIVER_DESC "EMXX UDC driver" 35 #define DMA_ADDR_INVALID (~(dma_addr_t)0) 36 37 static const char driver_name[] = "emxx_udc"; 38 static const char driver_desc[] = DRIVER_DESC; 39 40 /*===========================================================================*/ 41 /* Prototype */ 42 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *); 43 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *); 44 /*static void _nbu2ss_ep0_disable(struct nbu2ss_udc *);*/ 45 static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int); 46 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode); 47 static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs); 48 49 static int _nbu2ss_pullup(struct nbu2ss_udc *, int); 50 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *); 51 52 /*===========================================================================*/ 53 /* Macro */ 54 #define _nbu2ss_zero_len_pkt(udc, epnum) \ 55 _nbu2ss_ep_in_end(udc, epnum, 0, 0) 56 57 /*===========================================================================*/ 58 /* Global */ 59 struct nbu2ss_udc udc_controller; 60 61 /*-------------------------------------------------------------------------*/ 62 /* Read */ 63 static inline u32 _nbu2ss_readl(void *address) 64 { 65 return __raw_readl(address); 66 } 67 68 /*-------------------------------------------------------------------------*/ 69 /* Write */ 70 static inline void _nbu2ss_writel(void *address, u32 udata) 71 { 72 __raw_writel(udata, address); 73 } 74 75 /*-------------------------------------------------------------------------*/ 76 /* Set Bit */ 77 static inline void _nbu2ss_bitset(void *address, u32 udata) 78 { 79 u32 reg_dt = __raw_readl(address) | (udata); 80 81 __raw_writel(reg_dt, address); 82 } 83 84 /*-------------------------------------------------------------------------*/ 85 /* Clear Bit */ 86 static inline void _nbu2ss_bitclr(void *address, u32 udata) 87 { 88 u32 reg_dt = __raw_readl(address) & ~(udata); 89 90 __raw_writel(reg_dt, address); 91 } 92 93 #ifdef UDC_DEBUG_DUMP 94 /*-------------------------------------------------------------------------*/ 95 static void _nbu2ss_dump_register(struct nbu2ss_udc *udc) 96 { 97 int i; 98 u32 reg_data; 99 100 pr_info("=== %s()\n", __func__); 101 102 if (!udc) { 103 pr_err("%s udc == NULL\n", __func__); 104 return; 105 } 106 107 spin_unlock(&udc->lock); 108 109 dev_dbg(&udc->dev, "\n-USB REG-\n"); 110 for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) { 111 reg_data = _nbu2ss_readl( 112 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i)); 113 dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data); 114 115 reg_data = _nbu2ss_readl( 116 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 4)); 117 dev_dbg(&udc->dev, " %08x", (int)reg_data); 118 119 reg_data = _nbu2ss_readl( 120 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 8)); 121 dev_dbg(&udc->dev, " %08x", (int)reg_data); 122 123 reg_data = _nbu2ss_readl( 124 (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 12)); 125 dev_dbg(&udc->dev, " %08x\n", (int)reg_data); 126 } 127 128 spin_lock(&udc->lock); 129 } 130 #endif /* UDC_DEBUG_DUMP */ 131 132 /*-------------------------------------------------------------------------*/ 133 /* Endpoint 0 Callback (Complete) */ 134 static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req) 135 { 136 u8 recipient; 137 u16 selector; 138 u32 test_mode; 139 struct usb_ctrlrequest *p_ctrl; 140 struct nbu2ss_udc *udc; 141 142 if ((!_ep) || (!_req)) 143 return; 144 145 udc = (struct nbu2ss_udc *)_req->context; 146 p_ctrl = &udc->ctrl; 147 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 148 if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) { 149 /*-------------------------------------------------*/ 150 /* SET_FEATURE */ 151 recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK); 152 selector = p_ctrl->wValue; 153 if ((recipient == USB_RECIP_DEVICE) && 154 (selector == USB_DEVICE_TEST_MODE)) { 155 test_mode = (u32)(p_ctrl->wIndex >> 8); 156 _nbu2ss_set_test_mode(udc, test_mode); 157 } 158 } 159 } 160 } 161 162 /*-------------------------------------------------------------------------*/ 163 /* Initialization usb_request */ 164 static void _nbu2ss_create_ep0_packet( 165 struct nbu2ss_udc *udc, 166 void *p_buf, 167 unsigned length 168 ) 169 { 170 udc->ep0_req.req.buf = p_buf; 171 udc->ep0_req.req.length = length; 172 udc->ep0_req.req.dma = 0; 173 udc->ep0_req.req.zero = TRUE; 174 udc->ep0_req.req.complete = _nbu2ss_ep0_complete; 175 udc->ep0_req.req.status = -EINPROGRESS; 176 udc->ep0_req.req.context = udc; 177 udc->ep0_req.req.actual = 0; 178 } 179 180 /*-------------------------------------------------------------------------*/ 181 /* Acquisition of the first address of RAM(FIFO) */ 182 static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc) 183 { 184 u32 num, buf_type; 185 u32 data, last_ram_adr, use_ram_size; 186 187 struct ep_regs *p_ep_regs; 188 189 last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2; 190 use_ram_size = 0; 191 192 for (num = 0; num < NUM_ENDPOINTS - 1; num++) { 193 p_ep_regs = &udc->p_regs->EP_REGS[num]; 194 data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS); 195 buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPN_BUF_TYPE; 196 if (buf_type == 0) { 197 /* Single Buffer */ 198 use_ram_size += (data & EPN_MPKT) / sizeof(u32); 199 } else { 200 /* Double Buffer */ 201 use_ram_size += ((data & EPN_MPKT) / sizeof(u32)) * 2; 202 } 203 204 if ((data >> 16) > last_ram_adr) 205 last_ram_adr = data >> 16; 206 } 207 208 return last_ram_adr + use_ram_size; 209 } 210 211 /*-------------------------------------------------------------------------*/ 212 /* Construction of Endpoint */ 213 static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 214 { 215 u32 num; 216 u32 data; 217 u32 begin_adrs; 218 219 if (ep->epnum == 0) 220 return -EINVAL; 221 222 num = ep->epnum - 1; 223 224 /*-------------------------------------------------------------*/ 225 /* RAM Transfer Address */ 226 begin_adrs = _nbu2ss_get_begin_ram_address(udc); 227 data = (begin_adrs << 16) | ep->ep.maxpacket; 228 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data); 229 230 /*-------------------------------------------------------------*/ 231 /* Interrupt Enable */ 232 data = 1 << (ep->epnum + 8); 233 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data); 234 235 /*-------------------------------------------------------------*/ 236 /* Endpoint Type(Mode) */ 237 /* Bulk, Interrupt, ISO */ 238 switch (ep->ep_type) { 239 case USB_ENDPOINT_XFER_BULK: 240 data = EPN_BULK; 241 break; 242 243 case USB_ENDPOINT_XFER_INT: 244 data = EPN_BUF_SINGLE | EPN_INTERRUPT; 245 break; 246 247 case USB_ENDPOINT_XFER_ISOC: 248 data = EPN_ISO; 249 break; 250 251 default: 252 data = 0; 253 break; 254 } 255 256 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 257 _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum | ep->direct)); 258 259 if (ep->direct == USB_DIR_OUT) { 260 /*---------------------------------------------------------*/ 261 /* OUT */ 262 data = EPN_EN | EPN_BCLR | EPN_DIR0; 263 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 264 265 data = EPN_ONAK | EPN_OSTL_EN | EPN_OSTL; 266 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 267 268 data = EPN_OUT_EN | EPN_OUT_END_EN; 269 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 270 } else { 271 /*---------------------------------------------------------*/ 272 /* IN */ 273 data = EPN_EN | EPN_BCLR | EPN_AUTO; 274 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 275 276 data = EPN_ISTL; 277 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 278 279 data = EPN_IN_EN | EPN_IN_END_EN; 280 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 281 } 282 283 return 0; 284 } 285 286 /*-------------------------------------------------------------------------*/ 287 /* Release of Endpoint */ 288 static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 289 { 290 u32 num; 291 u32 data; 292 293 if ((ep->epnum == 0) || (udc->vbus_active == 0)) 294 return -EINVAL; 295 296 num = ep->epnum - 1; 297 298 /*-------------------------------------------------------------*/ 299 /* RAM Transfer Address */ 300 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0); 301 302 /*-------------------------------------------------------------*/ 303 /* Interrupt Disable */ 304 data = 1 << (ep->epnum + 8); 305 _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data); 306 307 if (ep->direct == USB_DIR_OUT) { 308 /*---------------------------------------------------------*/ 309 /* OUT */ 310 data = EPN_ONAK | EPN_BCLR; 311 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 312 313 data = EPN_EN | EPN_DIR0; 314 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 315 316 data = EPN_OUT_EN | EPN_OUT_END_EN; 317 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 318 } else { 319 /*---------------------------------------------------------*/ 320 /* IN */ 321 data = EPN_BCLR; 322 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 323 324 data = EPN_EN | EPN_AUTO; 325 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 326 327 data = EPN_IN_EN | EPN_IN_END_EN; 328 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); 329 } 330 331 return 0; 332 } 333 334 /*-------------------------------------------------------------------------*/ 335 /* DMA setting (without Endpoint 0) */ 336 static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 337 { 338 u32 num; 339 u32 data; 340 341 data = _nbu2ss_readl(&udc->p_regs->USBSSCONF); 342 if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0)) 343 return; /* Not Support DMA */ 344 345 num = ep->epnum - 1; 346 347 if (ep->direct == USB_DIR_OUT) { 348 /*---------------------------------------------------------*/ 349 /* OUT */ 350 data = ep->ep.maxpacket; 351 _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data); 352 353 /*---------------------------------------------------------*/ 354 /* Transfer Direct */ 355 data = DCR1_EPN_DIR0; 356 _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data); 357 358 /*---------------------------------------------------------*/ 359 /* DMA Mode etc. */ 360 data = EPN_STOP_MODE | EPN_STOP_SET | EPN_DMAMODE0; 361 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data); 362 } else { 363 /*---------------------------------------------------------*/ 364 /* IN */ 365 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPN_AUTO); 366 367 /*---------------------------------------------------------*/ 368 /* DMA Mode etc. */ 369 data = EPN_BURST_SET | EPN_DMAMODE0; 370 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data); 371 } 372 } 373 374 /*-------------------------------------------------------------------------*/ 375 /* DMA setting release */ 376 static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 377 { 378 u32 num; 379 u32 data; 380 struct fc_regs *preg = udc->p_regs; 381 382 if (udc->vbus_active == 0) 383 return; /* VBUS OFF */ 384 385 data = _nbu2ss_readl(&preg->USBSSCONF); 386 if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0)) 387 return; /* Not Support DMA */ 388 389 num = ep->epnum - 1; 390 391 _nbu2ss_ep_dma_abort(udc, ep); 392 393 if (ep->direct == USB_DIR_OUT) { 394 /*---------------------------------------------------------*/ 395 /* OUT */ 396 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0); 397 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_DIR0); 398 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); 399 } else { 400 /*---------------------------------------------------------*/ 401 /* IN */ 402 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); 403 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); 404 } 405 } 406 407 /*-------------------------------------------------------------------------*/ 408 /* Abort DMA */ 409 static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 410 { 411 struct fc_regs *preg = udc->p_regs; 412 413 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPN_REQEN); 414 mdelay(DMA_DISABLE_TIME); /* DCR1_EPN_REQEN Clear */ 415 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPN_DMA_EN); 416 } 417 418 /*-------------------------------------------------------------------------*/ 419 /* Start IN Transfer */ 420 static void _nbu2ss_ep_in_end( 421 struct nbu2ss_udc *udc, 422 u32 epnum, 423 u32 data32, 424 u32 length 425 ) 426 { 427 u32 data; 428 u32 num; 429 struct fc_regs *preg = udc->p_regs; 430 431 if (length >= sizeof(u32)) 432 return; 433 434 if (epnum == 0) { 435 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO); 436 437 /* Writing of 1-4 bytes */ 438 if (length) 439 _nbu2ss_writel(&preg->EP0_WRITE, data32); 440 441 data = ((length << 5) & EP0_DW) | EP0_DEND; 442 _nbu2ss_writel(&preg->EP0_CONTROL, data); 443 444 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO); 445 } else { 446 num = epnum - 1; 447 448 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); 449 450 /* Writing of 1-4 bytes */ 451 if (length) 452 _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32); 453 454 data = (((length) << 5) & EPN_DW) | EPN_DEND; 455 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data); 456 457 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); 458 } 459 } 460 461 #ifdef USE_DMA 462 /*-------------------------------------------------------------------------*/ 463 static void _nbu2ss_dma_map_single( 464 struct nbu2ss_udc *udc, 465 struct nbu2ss_ep *ep, 466 struct nbu2ss_req *req, 467 u8 direct 468 ) 469 { 470 if (req->req.dma == DMA_ADDR_INVALID) { 471 if (req->unaligned) { 472 req->req.dma = ep->phys_buf; 473 } else { 474 req->req.dma = dma_map_single( 475 udc->gadget.dev.parent, 476 req->req.buf, 477 req->req.length, 478 (direct == USB_DIR_IN) 479 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 480 } 481 req->mapped = 1; 482 } else { 483 if (!req->unaligned) 484 dma_sync_single_for_device( 485 udc->gadget.dev.parent, 486 req->req.dma, 487 req->req.length, 488 (direct == USB_DIR_IN) 489 ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 490 491 req->mapped = 0; 492 } 493 } 494 495 /*-------------------------------------------------------------------------*/ 496 static void _nbu2ss_dma_unmap_single( 497 struct nbu2ss_udc *udc, 498 struct nbu2ss_ep *ep, 499 struct nbu2ss_req *req, 500 u8 direct 501 ) 502 { 503 u8 data[4]; 504 u8 *p; 505 u32 count = 0; 506 507 if (direct == USB_DIR_OUT) { 508 count = req->req.actual % 4; 509 if (count) { 510 p = req->req.buf; 511 p += (req->req.actual - count); 512 memcpy(data, p, count); 513 } 514 } 515 516 if (req->mapped) { 517 if (req->unaligned) { 518 if (direct == USB_DIR_OUT) 519 memcpy(req->req.buf, ep->virt_buf, 520 req->req.actual & 0xfffffffc); 521 } else { 522 dma_unmap_single(udc->gadget.dev.parent, 523 req->req.dma, req->req.length, 524 (direct == USB_DIR_IN) 525 ? DMA_TO_DEVICE 526 : DMA_FROM_DEVICE); 527 } 528 req->req.dma = DMA_ADDR_INVALID; 529 req->mapped = 0; 530 } else { 531 if (!req->unaligned) 532 dma_sync_single_for_cpu(udc->gadget.dev.parent, 533 req->req.dma, req->req.length, 534 (direct == USB_DIR_IN) 535 ? DMA_TO_DEVICE 536 : DMA_FROM_DEVICE); 537 } 538 539 if (count) { 540 p = req->req.buf; 541 p += (req->req.actual - count); 542 memcpy(p, data, count); 543 } 544 } 545 #endif 546 547 /*-------------------------------------------------------------------------*/ 548 /* Endpoint 0 OUT Transfer (PIO) */ 549 static int ep0_out_pio(struct nbu2ss_udc *udc, u8 *buf, u32 length) 550 { 551 u32 i; 552 u32 numreads = length / sizeof(u32); 553 union usb_reg_access *buf32 = (union usb_reg_access *)buf; 554 555 if (!numreads) 556 return 0; 557 558 /* PIO Read */ 559 for (i = 0; i < numreads; i++) { 560 buf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ); 561 buf32++; 562 } 563 564 return numreads * sizeof(u32); 565 } 566 567 /*-------------------------------------------------------------------------*/ 568 /* Endpoint 0 OUT Transfer (PIO, OverBytes) */ 569 static int ep0_out_overbytes(struct nbu2ss_udc *udc, u8 *p_buf, u32 length) 570 { 571 u32 i; 572 u32 i_read_size = 0; 573 union usb_reg_access temp_32; 574 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; 575 576 if ((length > 0) && (length < sizeof(u32))) { 577 temp_32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ); 578 for (i = 0 ; i < length ; i++) 579 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i]; 580 i_read_size += length; 581 } 582 583 return i_read_size; 584 } 585 586 /*-------------------------------------------------------------------------*/ 587 /* Endpoint 0 IN Transfer (PIO) */ 588 static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *p_buf, u32 length) 589 { 590 u32 i; 591 u32 i_max_length = EP0_PACKETSIZE; 592 u32 i_word_length = 0; 593 u32 i_write_length = 0; 594 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; 595 596 /*------------------------------------------------------------*/ 597 /* Transfer Length */ 598 if (i_max_length < length) 599 i_word_length = i_max_length / sizeof(u32); 600 else 601 i_word_length = length / sizeof(u32); 602 603 /*------------------------------------------------------------*/ 604 /* PIO */ 605 for (i = 0; i < i_word_length; i++) { 606 _nbu2ss_writel(&udc->p_regs->EP0_WRITE, p_buf_32->dw); 607 p_buf_32++; 608 i_write_length += sizeof(u32); 609 } 610 611 return i_write_length; 612 } 613 614 /*-------------------------------------------------------------------------*/ 615 /* Endpoint 0 IN Transfer (PIO, OverBytes) */ 616 static int ep0_in_overbytes(struct nbu2ss_udc *udc, 617 u8 *p_buf, 618 u32 i_remain_size) 619 { 620 u32 i; 621 union usb_reg_access temp_32; 622 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; 623 624 if ((i_remain_size > 0) && (i_remain_size < sizeof(u32))) { 625 for (i = 0 ; i < i_remain_size ; i++) 626 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i]; 627 _nbu2ss_ep_in_end(udc, 0, temp_32.dw, i_remain_size); 628 629 return i_remain_size; 630 } 631 632 return 0; 633 } 634 635 /*-------------------------------------------------------------------------*/ 636 /* Transfer NULL Packet (Epndoint 0) */ 637 static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag) 638 { 639 u32 data; 640 641 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 642 data &= ~(u32)EP0_INAK; 643 644 if (pid_flag) 645 data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND); 646 else 647 data |= (EP0_INAK_EN | EP0_DEND); 648 649 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); 650 651 return 0; 652 } 653 654 /*-------------------------------------------------------------------------*/ 655 /* Receive NULL Packet (Endpoint 0) */ 656 static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag) 657 { 658 u32 data; 659 660 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 661 data &= ~(u32)EP0_ONAK; 662 663 if (pid_flag) 664 data |= EP0_PIDCLR; 665 666 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); 667 668 return 0; 669 } 670 671 /*-------------------------------------------------------------------------*/ 672 static int _nbu2ss_ep0_in_transfer( 673 struct nbu2ss_udc *udc, 674 struct nbu2ss_req *req 675 ) 676 { 677 u8 *p_buffer; /* IN Data Buffer */ 678 u32 data; 679 u32 i_remain_size = 0; 680 int result = 0; 681 682 /*-------------------------------------------------------------*/ 683 /* End confirmation */ 684 if (req->req.actual == req->req.length) { 685 if ((req->req.actual % EP0_PACKETSIZE) == 0) { 686 if (req->zero) { 687 req->zero = false; 688 EP0_send_NULL(udc, FALSE); 689 return 1; 690 } 691 } 692 693 return 0; /* Transfer End */ 694 } 695 696 /*-------------------------------------------------------------*/ 697 /* NAK release */ 698 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 699 data |= EP0_INAK_EN; 700 data &= ~(u32)EP0_INAK; 701 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); 702 703 i_remain_size = req->req.length - req->req.actual; 704 p_buffer = (u8 *)req->req.buf; 705 p_buffer += req->req.actual; 706 707 /*-------------------------------------------------------------*/ 708 /* Data transfer */ 709 result = EP0_in_PIO(udc, p_buffer, i_remain_size); 710 711 req->div_len = result; 712 i_remain_size -= result; 713 714 if (i_remain_size == 0) { 715 EP0_send_NULL(udc, FALSE); 716 return result; 717 } 718 719 if ((i_remain_size < sizeof(u32)) && (result != EP0_PACKETSIZE)) { 720 p_buffer += result; 721 result += ep0_in_overbytes(udc, p_buffer, i_remain_size); 722 req->div_len = result; 723 } 724 725 return result; 726 } 727 728 /*-------------------------------------------------------------------------*/ 729 static int _nbu2ss_ep0_out_transfer( 730 struct nbu2ss_udc *udc, 731 struct nbu2ss_req *req 732 ) 733 { 734 u8 *p_buffer; 735 u32 i_remain_size; 736 u32 i_recv_length; 737 int result = 0; 738 int f_rcv_zero; 739 740 /*-------------------------------------------------------------*/ 741 /* Receive data confirmation */ 742 i_recv_length = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA; 743 if (i_recv_length != 0) { 744 f_rcv_zero = 0; 745 746 i_remain_size = req->req.length - req->req.actual; 747 p_buffer = (u8 *)req->req.buf; 748 p_buffer += req->req.actual; 749 750 result = ep0_out_pio(udc, p_buffer 751 , min(i_remain_size, i_recv_length)); 752 if (result < 0) 753 return result; 754 755 req->req.actual += result; 756 i_recv_length -= result; 757 758 if ((i_recv_length > 0) && (i_recv_length < sizeof(u32))) { 759 p_buffer += result; 760 i_remain_size -= result; 761 762 result = ep0_out_overbytes(udc, p_buffer 763 , min(i_remain_size, i_recv_length)); 764 req->req.actual += result; 765 } 766 } else { 767 f_rcv_zero = 1; 768 } 769 770 /*-------------------------------------------------------------*/ 771 /* End confirmation */ 772 if (req->req.actual == req->req.length) { 773 if ((req->req.actual % EP0_PACKETSIZE) == 0) { 774 if (req->zero) { 775 req->zero = false; 776 EP0_receive_NULL(udc, FALSE); 777 return 1; 778 } 779 } 780 781 return 0; /* Transfer End */ 782 } 783 784 if ((req->req.actual % EP0_PACKETSIZE) != 0) 785 return 0; /* Short Packet Transfer End */ 786 787 if (req->req.actual > req->req.length) { 788 dev_err(udc->dev, " *** Overrun Error\n"); 789 return -EOVERFLOW; 790 } 791 792 if (f_rcv_zero != 0) { 793 i_remain_size = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); 794 if (i_remain_size & EP0_ONAK) { 795 /*---------------------------------------------------*/ 796 /* NACK release */ 797 _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK); 798 } 799 result = 1; 800 } 801 802 return result; 803 } 804 805 /*-------------------------------------------------------------------------*/ 806 static int _nbu2ss_out_dma( 807 struct nbu2ss_udc *udc, 808 struct nbu2ss_req *req, 809 u32 num, 810 u32 length 811 ) 812 { 813 dma_addr_t p_buffer; 814 u32 mpkt; 815 u32 lmpkt; 816 u32 dmacnt; 817 u32 burst = 1; 818 u32 data; 819 int result = -EINVAL; 820 struct fc_regs *preg = udc->p_regs; 821 822 if (req->dma_flag) 823 return 1; /* DMA is forwarded */ 824 825 req->dma_flag = TRUE; 826 p_buffer = req->req.dma; 827 p_buffer += req->req.actual; 828 829 /* DMA Address */ 830 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer); 831 832 /* Number of transfer packets */ 833 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT; 834 dmacnt = length / mpkt; 835 lmpkt = (length % mpkt) & ~(u32)0x03; 836 837 if (dmacnt > DMA_MAX_COUNT) { 838 dmacnt = DMA_MAX_COUNT; 839 lmpkt = 0; 840 } else if (lmpkt != 0) { 841 if (dmacnt == 0) 842 burst = 0; /* Burst OFF */ 843 dmacnt++; 844 } 845 846 data = mpkt | (lmpkt << 16); 847 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data); 848 849 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_DIR0 | DCR1_EPN_REQEN; 850 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data); 851 852 if (burst == 0) { 853 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0); 854 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET); 855 } else { 856 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT 857 , (dmacnt << 16)); 858 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET); 859 } 860 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN); 861 862 result = length & ~(u32)0x03; 863 req->div_len = result; 864 865 return result; 866 } 867 868 /*-------------------------------------------------------------------------*/ 869 static int _nbu2ss_epn_out_pio( 870 struct nbu2ss_udc *udc, 871 struct nbu2ss_ep *ep, 872 struct nbu2ss_req *req, 873 u32 length 874 ) 875 { 876 u8 *p_buffer; 877 u32 i; 878 u32 data; 879 u32 i_word_length; 880 union usb_reg_access temp_32; 881 union usb_reg_access *p_buf_32; 882 int result = 0; 883 struct fc_regs *preg = udc->p_regs; 884 885 if (req->dma_flag) 886 return 1; /* DMA is forwarded */ 887 888 if (length == 0) 889 return 0; 890 891 p_buffer = (u8 *)req->req.buf; 892 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual); 893 894 i_word_length = length / sizeof(u32); 895 if (i_word_length > 0) { 896 /*---------------------------------------------------------*/ 897 /* Copy of every four bytes */ 898 for (i = 0; i < i_word_length; i++) { 899 p_buf_32->dw = 900 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ); 901 p_buf_32++; 902 } 903 result = i_word_length * sizeof(u32); 904 } 905 906 data = length - result; 907 if (data > 0) { 908 /*---------------------------------------------------------*/ 909 /* Copy of fraction byte */ 910 temp_32.dw = 911 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ); 912 for (i = 0 ; i < data ; i++) 913 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i]; 914 result += data; 915 } 916 917 req->req.actual += result; 918 919 if ((req->req.actual == req->req.length) || 920 ((req->req.actual % ep->ep.maxpacket) != 0)) { 921 result = 0; 922 } 923 924 return result; 925 } 926 927 /*-------------------------------------------------------------------------*/ 928 static int _nbu2ss_epn_out_data( 929 struct nbu2ss_udc *udc, 930 struct nbu2ss_ep *ep, 931 struct nbu2ss_req *req, 932 u32 data_size 933 ) 934 { 935 u32 num; 936 u32 i_buf_size; 937 int nret = 1; 938 939 if (ep->epnum == 0) 940 return -EINVAL; 941 942 num = ep->epnum - 1; 943 944 i_buf_size = min((req->req.length - req->req.actual), data_size); 945 946 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) && 947 (i_buf_size >= sizeof(u32))) { 948 nret = _nbu2ss_out_dma(udc, req, num, i_buf_size); 949 } else { 950 i_buf_size = min_t(u32, i_buf_size, ep->ep.maxpacket); 951 nret = _nbu2ss_epn_out_pio(udc, ep, req, i_buf_size); 952 } 953 954 return nret; 955 } 956 957 /*-------------------------------------------------------------------------*/ 958 static int _nbu2ss_epn_out_transfer( 959 struct nbu2ss_udc *udc, 960 struct nbu2ss_ep *ep, 961 struct nbu2ss_req *req 962 ) 963 { 964 u32 num; 965 u32 i_recv_length; 966 int result = 1; 967 struct fc_regs *preg = udc->p_regs; 968 969 if (ep->epnum == 0) 970 return -EINVAL; 971 972 num = ep->epnum - 1; 973 974 /*-------------------------------------------------------------*/ 975 /* Receive Length */ 976 i_recv_length 977 = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPN_LDATA; 978 979 if (i_recv_length != 0) { 980 result = _nbu2ss_epn_out_data(udc, ep, req, i_recv_length); 981 if (i_recv_length < ep->ep.maxpacket) { 982 if (i_recv_length == result) { 983 req->req.actual += result; 984 result = 0; 985 } 986 } 987 } else { 988 if ((req->req.actual == req->req.length) || 989 ((req->req.actual % ep->ep.maxpacket) != 0)) { 990 result = 0; 991 } 992 } 993 994 if (result == 0) { 995 if ((req->req.actual % ep->ep.maxpacket) == 0) { 996 if (req->zero) { 997 req->zero = false; 998 return 1; 999 } 1000 } 1001 } 1002 1003 if (req->req.actual > req->req.length) { 1004 dev_err(udc->dev, " Overrun Error\n"); 1005 dev_err(udc->dev, " actual = %d, length = %d\n", 1006 req->req.actual, req->req.length); 1007 result = -EOVERFLOW; 1008 } 1009 1010 return result; 1011 } 1012 1013 /*-------------------------------------------------------------------------*/ 1014 static int _nbu2ss_in_dma( 1015 struct nbu2ss_udc *udc, 1016 struct nbu2ss_ep *ep, 1017 struct nbu2ss_req *req, 1018 u32 num, 1019 u32 length 1020 ) 1021 { 1022 dma_addr_t p_buffer; 1023 u32 mpkt; /* MaxPacketSize */ 1024 u32 lmpkt; /* Last Packet Data Size */ 1025 u32 dmacnt; /* IN Data Size */ 1026 u32 i_write_length; 1027 u32 data; 1028 int result = -EINVAL; 1029 struct fc_regs *preg = udc->p_regs; 1030 1031 if (req->dma_flag) 1032 return 1; /* DMA is forwarded */ 1033 1034 #ifdef USE_DMA 1035 if (req->req.actual == 0) 1036 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN); 1037 #endif 1038 req->dma_flag = TRUE; 1039 1040 /* MAX Packet Size */ 1041 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT; 1042 1043 if ((DMA_MAX_COUNT * mpkt) < length) 1044 i_write_length = DMA_MAX_COUNT * mpkt; 1045 else 1046 i_write_length = length; 1047 1048 /*------------------------------------------------------------*/ 1049 /* Number of transmission packets */ 1050 if (mpkt < i_write_length) { 1051 dmacnt = i_write_length / mpkt; 1052 lmpkt = (i_write_length % mpkt) & ~(u32)0x3; 1053 if (lmpkt != 0) 1054 dmacnt++; 1055 else 1056 lmpkt = mpkt & ~(u32)0x3; 1057 1058 } else { 1059 dmacnt = 1; 1060 lmpkt = i_write_length & ~(u32)0x3; 1061 } 1062 1063 /* Packet setting */ 1064 data = mpkt | (lmpkt << 16); 1065 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data); 1066 1067 /* Address setting */ 1068 p_buffer = req->req.dma; 1069 p_buffer += req->req.actual; 1070 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer); 1071 1072 /* Packet and DMA setting */ 1073 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_REQEN; 1074 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data); 1075 1076 /* Packet setting of EPC */ 1077 data = dmacnt << 16; 1078 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data); 1079 1080 /*DMA setting of EPC */ 1081 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN); 1082 1083 result = i_write_length & ~(u32)0x3; 1084 req->div_len = result; 1085 1086 return result; 1087 } 1088 1089 /*-------------------------------------------------------------------------*/ 1090 static int _nbu2ss_epn_in_pio( 1091 struct nbu2ss_udc *udc, 1092 struct nbu2ss_ep *ep, 1093 struct nbu2ss_req *req, 1094 u32 length 1095 ) 1096 { 1097 u8 *p_buffer; 1098 u32 i; 1099 u32 data; 1100 u32 i_word_length; 1101 union usb_reg_access temp_32; 1102 union usb_reg_access *p_buf_32 = NULL; 1103 int result = 0; 1104 struct fc_regs *preg = udc->p_regs; 1105 1106 if (req->dma_flag) 1107 return 1; /* DMA is forwarded */ 1108 1109 if (length > 0) { 1110 p_buffer = (u8 *)req->req.buf; 1111 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual); 1112 1113 i_word_length = length / sizeof(u32); 1114 if (i_word_length > 0) { 1115 for (i = 0; i < i_word_length; i++) { 1116 _nbu2ss_writel( 1117 &preg->EP_REGS[ep->epnum - 1].EP_WRITE 1118 , p_buf_32->dw 1119 ); 1120 1121 p_buf_32++; 1122 } 1123 result = i_word_length * sizeof(u32); 1124 } 1125 } 1126 1127 if (result != ep->ep.maxpacket) { 1128 data = length - result; 1129 temp_32.dw = 0; 1130 for (i = 0 ; i < data ; i++) 1131 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i]; 1132 1133 _nbu2ss_ep_in_end(udc, ep->epnum, temp_32.dw, data); 1134 result += data; 1135 } 1136 1137 req->div_len = result; 1138 1139 return result; 1140 } 1141 1142 /*-------------------------------------------------------------------------*/ 1143 static int _nbu2ss_epn_in_data( 1144 struct nbu2ss_udc *udc, 1145 struct nbu2ss_ep *ep, 1146 struct nbu2ss_req *req, 1147 u32 data_size 1148 ) 1149 { 1150 u32 num; 1151 int nret = 1; 1152 1153 if (ep->epnum == 0) 1154 return -EINVAL; 1155 1156 num = ep->epnum - 1; 1157 1158 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) && 1159 (data_size >= sizeof(u32))) { 1160 nret = _nbu2ss_in_dma(udc, ep, req, num, data_size); 1161 } else { 1162 data_size = min_t(u32, data_size, ep->ep.maxpacket); 1163 nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size); 1164 } 1165 1166 return nret; 1167 } 1168 1169 /*-------------------------------------------------------------------------*/ 1170 static int _nbu2ss_epn_in_transfer( 1171 struct nbu2ss_udc *udc, 1172 struct nbu2ss_ep *ep, 1173 struct nbu2ss_req *req 1174 ) 1175 { 1176 u32 num; 1177 u32 i_buf_size; 1178 int result = 0; 1179 u32 status; 1180 1181 if (ep->epnum == 0) 1182 return -EINVAL; 1183 1184 num = ep->epnum - 1; 1185 1186 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS); 1187 1188 /*-------------------------------------------------------------*/ 1189 /* State confirmation of FIFO */ 1190 if (req->req.actual == 0) { 1191 if ((status & EPN_IN_EMPTY) == 0) 1192 return 1; /* Not Empty */ 1193 1194 } else { 1195 if ((status & EPN_IN_FULL) != 0) 1196 return 1; /* Not Empty */ 1197 } 1198 1199 /*-------------------------------------------------------------*/ 1200 /* Start transfer */ 1201 i_buf_size = req->req.length - req->req.actual; 1202 if (i_buf_size > 0) 1203 result = _nbu2ss_epn_in_data(udc, ep, req, i_buf_size); 1204 else if (req->req.length == 0) 1205 _nbu2ss_zero_len_pkt(udc, ep->epnum); 1206 1207 return result; 1208 } 1209 1210 /*-------------------------------------------------------------------------*/ 1211 static int _nbu2ss_start_transfer( 1212 struct nbu2ss_udc *udc, 1213 struct nbu2ss_ep *ep, 1214 struct nbu2ss_req *req, 1215 bool bflag) 1216 { 1217 int nret = -EINVAL; 1218 1219 req->dma_flag = FALSE; 1220 req->div_len = 0; 1221 1222 if (req->req.length == 0) { 1223 req->zero = false; 1224 } else { 1225 if ((req->req.length % ep->ep.maxpacket) == 0) 1226 req->zero = req->req.zero; 1227 else 1228 req->zero = false; 1229 } 1230 1231 if (ep->epnum == 0) { 1232 /* EP0 */ 1233 switch (udc->ep0state) { 1234 case EP0_IN_DATA_PHASE: 1235 nret = _nbu2ss_ep0_in_transfer(udc, req); 1236 break; 1237 1238 case EP0_OUT_DATA_PHASE: 1239 nret = _nbu2ss_ep0_out_transfer(udc, req); 1240 break; 1241 1242 case EP0_IN_STATUS_PHASE: 1243 nret = EP0_send_NULL(udc, TRUE); 1244 break; 1245 1246 default: 1247 break; 1248 } 1249 1250 } else { 1251 /* EPN */ 1252 if (ep->direct == USB_DIR_OUT) { 1253 /* OUT */ 1254 if (!bflag) 1255 nret = _nbu2ss_epn_out_transfer(udc, ep, req); 1256 } else { 1257 /* IN */ 1258 nret = _nbu2ss_epn_in_transfer(udc, ep, req); 1259 } 1260 } 1261 1262 return nret; 1263 } 1264 1265 /*-------------------------------------------------------------------------*/ 1266 static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep) 1267 { 1268 u32 length; 1269 bool bflag = FALSE; 1270 struct nbu2ss_req *req; 1271 1272 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1273 if (!req) 1274 return; 1275 1276 if (ep->epnum > 0) { 1277 length = _nbu2ss_readl( 1278 &ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT); 1279 1280 length &= EPN_LDATA; 1281 if (length < ep->ep.maxpacket) 1282 bflag = TRUE; 1283 } 1284 1285 _nbu2ss_start_transfer(ep->udc, ep, req, bflag); 1286 } 1287 1288 /*-------------------------------------------------------------------------*/ 1289 /* Endpoint Toggle Reset */ 1290 static void _nbu2ss_endpoint_toggle_reset( 1291 struct nbu2ss_udc *udc, 1292 u8 ep_adrs) 1293 { 1294 u8 num; 1295 u32 data; 1296 1297 if ((ep_adrs == 0) || (ep_adrs == 0x80)) 1298 return; 1299 1300 num = (ep_adrs & 0x7F) - 1; 1301 1302 if (ep_adrs & USB_DIR_IN) 1303 data = EPN_IPIDCLR; 1304 else 1305 data = EPN_BCLR | EPN_OPIDCLR; 1306 1307 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); 1308 } 1309 1310 /*-------------------------------------------------------------------------*/ 1311 /* Endpoint STALL set */ 1312 static void _nbu2ss_set_endpoint_stall( 1313 struct nbu2ss_udc *udc, 1314 u8 ep_adrs, 1315 bool bstall) 1316 { 1317 u8 num, epnum; 1318 u32 data; 1319 struct nbu2ss_ep *ep; 1320 struct fc_regs *preg = udc->p_regs; 1321 1322 if ((ep_adrs == 0) || (ep_adrs == 0x80)) { 1323 if (bstall) { 1324 /* Set STALL */ 1325 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL); 1326 } else { 1327 /* Clear STALL */ 1328 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL); 1329 } 1330 } else { 1331 epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK; 1332 num = epnum - 1; 1333 ep = &udc->ep[epnum]; 1334 1335 if (bstall) { 1336 /* Set STALL */ 1337 ep->halted = TRUE; 1338 1339 if (ep_adrs & USB_DIR_IN) 1340 data = EPN_BCLR | EPN_ISTL; 1341 else 1342 data = EPN_OSTL_EN | EPN_OSTL; 1343 1344 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data); 1345 } else { 1346 /* Clear STALL */ 1347 ep->stalled = FALSE; 1348 if (ep_adrs & USB_DIR_IN) { 1349 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL 1350 , EPN_ISTL); 1351 } else { 1352 data = 1353 _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL); 1354 1355 data &= ~EPN_OSTL; 1356 data |= EPN_OSTL_EN; 1357 1358 _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL 1359 , data); 1360 } 1361 1362 ep->stalled = FALSE; 1363 if (ep->halted) { 1364 ep->halted = FALSE; 1365 _nbu2ss_restert_transfer(ep); 1366 } 1367 } 1368 } 1369 } 1370 1371 /*-------------------------------------------------------------------------*/ 1372 /* Device Descriptor */ 1373 static struct usb_device_descriptor device_desc = { 1374 .bLength = sizeof(device_desc), 1375 .bDescriptorType = USB_DT_DEVICE, 1376 .bcdUSB = cpu_to_le16(0x0200), 1377 .bDeviceClass = USB_CLASS_VENDOR_SPEC, 1378 .bDeviceSubClass = 0x00, 1379 .bDeviceProtocol = 0x00, 1380 .bMaxPacketSize0 = 64, 1381 .idVendor = cpu_to_le16(0x0409), 1382 .idProduct = cpu_to_le16(0xfff0), 1383 .bcdDevice = 0xffff, 1384 .iManufacturer = 0x00, 1385 .iProduct = 0x00, 1386 .iSerialNumber = 0x00, 1387 .bNumConfigurations = 0x01, 1388 }; 1389 1390 /*-------------------------------------------------------------------------*/ 1391 static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode) 1392 { 1393 u32 data; 1394 1395 if (mode > MAX_TEST_MODE_NUM) 1396 return; 1397 1398 dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode); 1399 1400 data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL); 1401 data &= ~TEST_FORCE_ENABLE; 1402 data |= mode << TEST_MODE_SHIFT; 1403 1404 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data); 1405 _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN); 1406 } 1407 1408 /*-------------------------------------------------------------------------*/ 1409 static int _nbu2ss_set_feature_device( 1410 struct nbu2ss_udc *udc, 1411 u16 selector, 1412 u16 wIndex 1413 ) 1414 { 1415 int result = -EOPNOTSUPP; 1416 1417 switch (selector) { 1418 case USB_DEVICE_REMOTE_WAKEUP: 1419 if (wIndex == 0x0000) { 1420 udc->remote_wakeup = U2F_ENABLE; 1421 result = 0; 1422 } 1423 break; 1424 1425 case USB_DEVICE_TEST_MODE: 1426 wIndex >>= 8; 1427 if (wIndex <= MAX_TEST_MODE_NUM) 1428 result = 0; 1429 break; 1430 1431 default: 1432 break; 1433 } 1434 1435 return result; 1436 } 1437 1438 /*-------------------------------------------------------------------------*/ 1439 static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs) 1440 { 1441 u8 epnum; 1442 u32 data = 0, bit_data; 1443 struct fc_regs *preg = udc->p_regs; 1444 1445 epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK; 1446 if (epnum == 0) { 1447 data = _nbu2ss_readl(&preg->EP0_CONTROL); 1448 bit_data = EP0_STL; 1449 1450 } else { 1451 data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL); 1452 if ((data & EPN_EN) == 0) 1453 return -1; 1454 1455 if (ep_adrs & USB_ENDPOINT_DIR_MASK) 1456 bit_data = EPN_ISTL; 1457 else 1458 bit_data = EPN_OSTL; 1459 } 1460 1461 if ((data & bit_data) == 0) 1462 return 0; 1463 return 1; 1464 } 1465 1466 /*-------------------------------------------------------------------------*/ 1467 static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset) 1468 { 1469 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK); 1470 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN); 1471 u16 selector = udc->ctrl.wValue; 1472 u16 wIndex = udc->ctrl.wIndex; 1473 u8 ep_adrs; 1474 int result = -EOPNOTSUPP; 1475 1476 if ((udc->ctrl.wLength != 0x0000) || 1477 (direction != USB_DIR_OUT)) { 1478 return -EINVAL; 1479 } 1480 1481 switch (recipient) { 1482 case USB_RECIP_DEVICE: 1483 if (bset) 1484 result = 1485 _nbu2ss_set_feature_device(udc, selector, wIndex); 1486 break; 1487 1488 case USB_RECIP_ENDPOINT: 1489 if (0x0000 == (wIndex & 0xFF70)) { 1490 if (selector == USB_ENDPOINT_HALT) { 1491 ep_adrs = wIndex & 0xFF; 1492 if (!bset) { 1493 _nbu2ss_endpoint_toggle_reset( 1494 udc, ep_adrs); 1495 } 1496 1497 _nbu2ss_set_endpoint_stall( 1498 udc, ep_adrs, bset); 1499 1500 result = 0; 1501 } 1502 } 1503 break; 1504 1505 default: 1506 break; 1507 } 1508 1509 if (result >= 0) 1510 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0); 1511 1512 return result; 1513 } 1514 1515 /*-------------------------------------------------------------------------*/ 1516 static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc) 1517 { 1518 u32 data; 1519 enum usb_device_speed speed = USB_SPEED_FULL; 1520 1521 data = _nbu2ss_readl(&udc->p_regs->USB_STATUS); 1522 if (data & HIGH_SPEED) 1523 speed = USB_SPEED_HIGH; 1524 1525 return speed; 1526 } 1527 1528 /*-------------------------------------------------------------------------*/ 1529 static void _nbu2ss_epn_set_stall( 1530 struct nbu2ss_udc *udc, 1531 struct nbu2ss_ep *ep 1532 ) 1533 { 1534 u8 ep_adrs; 1535 u32 regdata; 1536 int limit_cnt = 0; 1537 1538 struct fc_regs *preg = udc->p_regs; 1539 1540 if (ep->direct == USB_DIR_IN) { 1541 for (limit_cnt = 0 1542 ; limit_cnt < IN_DATA_EMPTY_COUNT 1543 ; limit_cnt++) { 1544 regdata = _nbu2ss_readl( 1545 &preg->EP_REGS[ep->epnum - 1].EP_STATUS); 1546 1547 if ((regdata & EPN_IN_DATA) == 0) 1548 break; 1549 1550 mdelay(1); 1551 } 1552 } 1553 1554 ep_adrs = ep->epnum | ep->direct; 1555 _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1); 1556 } 1557 1558 /*-------------------------------------------------------------------------*/ 1559 static int std_req_get_status(struct nbu2ss_udc *udc) 1560 { 1561 u32 length; 1562 u16 status_data = 0; 1563 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK); 1564 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN); 1565 u8 ep_adrs; 1566 int result = -EINVAL; 1567 1568 if ((udc->ctrl.wValue != 0x0000) || (direction != USB_DIR_IN)) 1569 return result; 1570 1571 length = min_t(u16, udc->ctrl.wLength, sizeof(status_data)); 1572 1573 switch (recipient) { 1574 case USB_RECIP_DEVICE: 1575 if (udc->ctrl.wIndex == 0x0000) { 1576 if (udc->gadget.is_selfpowered) 1577 status_data |= (1 << USB_DEVICE_SELF_POWERED); 1578 1579 if (udc->remote_wakeup) 1580 status_data |= (1 << USB_DEVICE_REMOTE_WAKEUP); 1581 1582 result = 0; 1583 } 1584 break; 1585 1586 case USB_RECIP_ENDPOINT: 1587 if (0x0000 == (udc->ctrl.wIndex & 0xFF70)) { 1588 ep_adrs = (u8)(udc->ctrl.wIndex & 0xFF); 1589 result = _nbu2ss_get_ep_stall(udc, ep_adrs); 1590 1591 if (result > 0) 1592 status_data |= (1 << USB_ENDPOINT_HALT); 1593 } 1594 break; 1595 1596 default: 1597 break; 1598 } 1599 1600 if (result >= 0) { 1601 memcpy(udc->ep0_buf, &status_data, length); 1602 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length); 1603 _nbu2ss_ep0_in_transfer(udc, &udc->ep0_req); 1604 1605 } else { 1606 dev_err(udc->dev, " Error GET_STATUS\n"); 1607 } 1608 1609 return result; 1610 } 1611 1612 /*-------------------------------------------------------------------------*/ 1613 static int std_req_clear_feature(struct nbu2ss_udc *udc) 1614 { 1615 return _nbu2ss_req_feature(udc, FALSE); 1616 } 1617 1618 /*-------------------------------------------------------------------------*/ 1619 static int std_req_set_feature(struct nbu2ss_udc *udc) 1620 { 1621 return _nbu2ss_req_feature(udc, TRUE); 1622 } 1623 1624 /*-------------------------------------------------------------------------*/ 1625 static int std_req_set_address(struct nbu2ss_udc *udc) 1626 { 1627 int result = 0; 1628 u32 wValue = udc->ctrl.wValue; 1629 1630 if ((udc->ctrl.bRequestType != 0x00) || 1631 (udc->ctrl.wIndex != 0x0000) || 1632 (udc->ctrl.wLength != 0x0000)) { 1633 return -EINVAL; 1634 } 1635 1636 if (wValue != (wValue & 0x007F)) 1637 return -EINVAL; 1638 1639 wValue <<= USB_ADRS_SHIFT; 1640 1641 _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue); 1642 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0); 1643 1644 return result; 1645 } 1646 1647 /*-------------------------------------------------------------------------*/ 1648 static int std_req_set_configuration(struct nbu2ss_udc *udc) 1649 { 1650 u32 config_value = (u32)(udc->ctrl.wValue & 0x00ff); 1651 1652 if ((udc->ctrl.wIndex != 0x0000) || 1653 (udc->ctrl.wLength != 0x0000) || 1654 (udc->ctrl.bRequestType != 0x00)) { 1655 return -EINVAL; 1656 } 1657 1658 udc->curr_config = config_value; 1659 1660 if (config_value > 0) { 1661 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF); 1662 udc->devstate = USB_STATE_CONFIGURED; 1663 1664 } else { 1665 _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF); 1666 udc->devstate = USB_STATE_ADDRESS; 1667 } 1668 1669 return 0; 1670 } 1671 1672 /*-------------------------------------------------------------------------*/ 1673 static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata) 1674 { 1675 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0); 1676 pdata++; 1677 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1); 1678 } 1679 1680 /*-------------------------------------------------------------------------*/ 1681 static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc) 1682 { 1683 bool bcall_back = TRUE; 1684 int nret = -EINVAL; 1685 struct usb_ctrlrequest *p_ctrl; 1686 1687 p_ctrl = &udc->ctrl; 1688 _nbu2ss_read_request_data(udc, (u32 *)p_ctrl); 1689 1690 /* ep0 state control */ 1691 if (p_ctrl->wLength == 0) { 1692 udc->ep0state = EP0_IN_STATUS_PHASE; 1693 1694 } else { 1695 if (p_ctrl->bRequestType & USB_DIR_IN) 1696 udc->ep0state = EP0_IN_DATA_PHASE; 1697 else 1698 udc->ep0state = EP0_OUT_DATA_PHASE; 1699 } 1700 1701 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 1702 switch (p_ctrl->bRequest) { 1703 case USB_REQ_GET_STATUS: 1704 nret = std_req_get_status(udc); 1705 bcall_back = FALSE; 1706 break; 1707 1708 case USB_REQ_CLEAR_FEATURE: 1709 nret = std_req_clear_feature(udc); 1710 bcall_back = FALSE; 1711 break; 1712 1713 case USB_REQ_SET_FEATURE: 1714 nret = std_req_set_feature(udc); 1715 bcall_back = FALSE; 1716 break; 1717 1718 case USB_REQ_SET_ADDRESS: 1719 nret = std_req_set_address(udc); 1720 bcall_back = FALSE; 1721 break; 1722 1723 case USB_REQ_SET_CONFIGURATION: 1724 nret = std_req_set_configuration(udc); 1725 break; 1726 1727 default: 1728 break; 1729 } 1730 } 1731 1732 if (!bcall_back) { 1733 if (udc->ep0state == EP0_IN_STATUS_PHASE) { 1734 if (nret >= 0) { 1735 /*--------------------------------------*/ 1736 /* Status Stage */ 1737 nret = EP0_send_NULL(udc, TRUE); 1738 } 1739 } 1740 1741 } else { 1742 spin_unlock(&udc->lock); 1743 nret = udc->driver->setup(&udc->gadget, &udc->ctrl); 1744 spin_lock(&udc->lock); 1745 } 1746 1747 if (nret < 0) 1748 udc->ep0state = EP0_IDLE; 1749 1750 return nret; 1751 } 1752 1753 /*-------------------------------------------------------------------------*/ 1754 static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc) 1755 { 1756 int nret; 1757 struct nbu2ss_req *req; 1758 struct nbu2ss_ep *ep = &udc->ep[0]; 1759 1760 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1761 if (!req) 1762 req = &udc->ep0_req; 1763 1764 req->req.actual += req->div_len; 1765 req->div_len = 0; 1766 1767 nret = _nbu2ss_ep0_in_transfer(udc, req); 1768 if (nret == 0) { 1769 udc->ep0state = EP0_OUT_STATUS_PAHSE; 1770 EP0_receive_NULL(udc, TRUE); 1771 } 1772 1773 return 0; 1774 } 1775 1776 /*-------------------------------------------------------------------------*/ 1777 static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc) 1778 { 1779 int nret; 1780 struct nbu2ss_req *req; 1781 struct nbu2ss_ep *ep = &udc->ep[0]; 1782 1783 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1784 if (!req) 1785 req = &udc->ep0_req; 1786 1787 nret = _nbu2ss_ep0_out_transfer(udc, req); 1788 if (nret == 0) { 1789 udc->ep0state = EP0_IN_STATUS_PHASE; 1790 EP0_send_NULL(udc, TRUE); 1791 1792 } else if (nret < 0) { 1793 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR); 1794 req->req.status = nret; 1795 } 1796 1797 return 0; 1798 } 1799 1800 /*-------------------------------------------------------------------------*/ 1801 static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc) 1802 { 1803 struct nbu2ss_req *req; 1804 struct nbu2ss_ep *ep = &udc->ep[0]; 1805 1806 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 1807 if (!req) { 1808 req = &udc->ep0_req; 1809 if (req->req.complete) 1810 req->req.complete(&ep->ep, &req->req); 1811 1812 } else { 1813 if (req->req.complete) 1814 _nbu2ss_ep_done(ep, req, 0); 1815 } 1816 1817 udc->ep0state = EP0_IDLE; 1818 1819 return 0; 1820 } 1821 1822 /*-------------------------------------------------------------------------*/ 1823 static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc) 1824 { 1825 int i; 1826 u32 status; 1827 u32 intr; 1828 int nret = -1; 1829 1830 status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS); 1831 intr = status & EP0_STATUS_RW_BIT; 1832 _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~intr); 1833 1834 status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT 1835 | STG_END_INT | EP0_OUT_NULL_INT); 1836 1837 if (status == 0) { 1838 dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__); 1839 dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr); 1840 return; 1841 } 1842 1843 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1844 udc->gadget.speed = _nbu2ss_get_speed(udc); 1845 1846 for (i = 0; i < EP0_END_XFER; i++) { 1847 switch (udc->ep0state) { 1848 case EP0_IDLE: 1849 if (status & SETUP_INT) { 1850 status = 0; 1851 nret = _nbu2ss_decode_request(udc); 1852 } 1853 break; 1854 1855 case EP0_IN_DATA_PHASE: 1856 if (status & EP0_IN_INT) { 1857 status &= ~EP0_IN_INT; 1858 nret = _nbu2ss_ep0_in_data_stage(udc); 1859 } 1860 break; 1861 1862 case EP0_OUT_DATA_PHASE: 1863 if (status & EP0_OUT_INT) { 1864 status &= ~EP0_OUT_INT; 1865 nret = _nbu2ss_ep0_out_data_stage(udc); 1866 } 1867 break; 1868 1869 case EP0_IN_STATUS_PHASE: 1870 if ((status & STG_END_INT) || (status & SETUP_INT)) { 1871 status &= ~(STG_END_INT | EP0_IN_INT); 1872 nret = _nbu2ss_ep0_status_stage(udc); 1873 } 1874 break; 1875 1876 case EP0_OUT_STATUS_PAHSE: 1877 if ((status & STG_END_INT) || (status & SETUP_INT) || 1878 (status & EP0_OUT_NULL_INT)) { 1879 status &= ~(STG_END_INT 1880 | EP0_OUT_INT 1881 | EP0_OUT_NULL_INT); 1882 1883 nret = _nbu2ss_ep0_status_stage(udc); 1884 } 1885 1886 break; 1887 1888 default: 1889 status = 0; 1890 break; 1891 } 1892 1893 if (status == 0) 1894 break; 1895 } 1896 1897 if (nret < 0) { 1898 /* Send Stall */ 1899 _nbu2ss_set_endpoint_stall(udc, 0, TRUE); 1900 } 1901 } 1902 1903 /*-------------------------------------------------------------------------*/ 1904 static void _nbu2ss_ep_done( 1905 struct nbu2ss_ep *ep, 1906 struct nbu2ss_req *req, 1907 int status) 1908 { 1909 struct nbu2ss_udc *udc = ep->udc; 1910 1911 list_del_init(&req->queue); 1912 1913 if (status == -ECONNRESET) 1914 _nbu2ss_fifo_flush(udc, ep); 1915 1916 if (likely(req->req.status == -EINPROGRESS)) 1917 req->req.status = status; 1918 1919 if (ep->stalled) { 1920 _nbu2ss_epn_set_stall(udc, ep); 1921 } else { 1922 if (!list_empty(&ep->queue)) 1923 _nbu2ss_restert_transfer(ep); 1924 } 1925 1926 #ifdef USE_DMA 1927 if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) && 1928 (req->req.dma != 0)) 1929 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT); 1930 #endif 1931 1932 spin_unlock(&udc->lock); 1933 req->req.complete(&ep->ep, &req->req); 1934 spin_lock(&udc->lock); 1935 } 1936 1937 /*-------------------------------------------------------------------------*/ 1938 static inline void _nbu2ss_epn_in_int( 1939 struct nbu2ss_udc *udc, 1940 struct nbu2ss_ep *ep, 1941 struct nbu2ss_req *req) 1942 { 1943 int result = 0; 1944 u32 status; 1945 1946 struct fc_regs *preg = udc->p_regs; 1947 1948 if (req->dma_flag) 1949 return; /* DMA is forwarded */ 1950 1951 req->req.actual += req->div_len; 1952 req->div_len = 0; 1953 1954 if (req->req.actual != req->req.length) { 1955 /*---------------------------------------------------------*/ 1956 /* remainder of data */ 1957 result = _nbu2ss_epn_in_transfer(udc, ep, req); 1958 1959 } else { 1960 if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) { 1961 status = 1962 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS); 1963 1964 if ((status & EPN_IN_FULL) == 0) { 1965 /*-----------------------------------------*/ 1966 /* 0 Length Packet */ 1967 req->zero = false; 1968 _nbu2ss_zero_len_pkt(udc, ep->epnum); 1969 } 1970 return; 1971 } 1972 } 1973 1974 if (result <= 0) { 1975 /*---------------------------------------------------------*/ 1976 /* Complete */ 1977 _nbu2ss_ep_done(ep, req, result); 1978 } 1979 } 1980 1981 /*-------------------------------------------------------------------------*/ 1982 static inline void _nbu2ss_epn_out_int( 1983 struct nbu2ss_udc *udc, 1984 struct nbu2ss_ep *ep, 1985 struct nbu2ss_req *req) 1986 { 1987 int result; 1988 1989 result = _nbu2ss_epn_out_transfer(udc, ep, req); 1990 if (result <= 0) 1991 _nbu2ss_ep_done(ep, req, result); 1992 } 1993 1994 /*-------------------------------------------------------------------------*/ 1995 static inline void _nbu2ss_epn_in_dma_int( 1996 struct nbu2ss_udc *udc, 1997 struct nbu2ss_ep *ep, 1998 struct nbu2ss_req *req) 1999 { 2000 u32 mpkt; 2001 u32 size; 2002 struct usb_request *preq; 2003 2004 preq = &req->req; 2005 2006 if (!req->dma_flag) 2007 return; 2008 2009 preq->actual += req->div_len; 2010 req->div_len = 0; 2011 req->dma_flag = FALSE; 2012 2013 #ifdef USE_DMA 2014 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN); 2015 #endif 2016 2017 if (preq->actual != preq->length) { 2018 _nbu2ss_epn_in_transfer(udc, ep, req); 2019 } else { 2020 mpkt = ep->ep.maxpacket; 2021 size = preq->actual % mpkt; 2022 if (size > 0) { 2023 if (((preq->actual & 0x03) == 0) && (size < mpkt)) 2024 _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0); 2025 } else { 2026 _nbu2ss_epn_in_int(udc, ep, req); 2027 } 2028 } 2029 } 2030 2031 /*-------------------------------------------------------------------------*/ 2032 static inline void _nbu2ss_epn_out_dma_int( 2033 struct nbu2ss_udc *udc, 2034 struct nbu2ss_ep *ep, 2035 struct nbu2ss_req *req) 2036 { 2037 int i; 2038 u32 num; 2039 u32 dmacnt, ep_dmacnt; 2040 u32 mpkt; 2041 struct fc_regs *preg = udc->p_regs; 2042 2043 num = ep->epnum - 1; 2044 2045 if (req->req.actual == req->req.length) { 2046 if ((req->req.length % ep->ep.maxpacket) && !req->zero) { 2047 req->div_len = 0; 2048 req->dma_flag = FALSE; 2049 _nbu2ss_ep_done(ep, req, 0); 2050 return; 2051 } 2052 } 2053 2054 ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) 2055 & EPN_DMACNT; 2056 ep_dmacnt >>= 16; 2057 2058 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) { 2059 dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1) 2060 & DCR1_EPN_DMACNT; 2061 dmacnt >>= 16; 2062 if (ep_dmacnt == dmacnt) 2063 break; 2064 } 2065 2066 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_REQEN); 2067 2068 if (dmacnt != 0) { 2069 mpkt = ep->ep.maxpacket; 2070 if ((req->div_len % mpkt) == 0) 2071 req->div_len -= mpkt * dmacnt; 2072 } 2073 2074 if ((req->req.actual % ep->ep.maxpacket) > 0) { 2075 if (req->req.actual == req->div_len) { 2076 req->div_len = 0; 2077 req->dma_flag = FALSE; 2078 _nbu2ss_ep_done(ep, req, 0); 2079 return; 2080 } 2081 } 2082 2083 req->req.actual += req->div_len; 2084 req->div_len = 0; 2085 req->dma_flag = FALSE; 2086 2087 _nbu2ss_epn_out_int(udc, ep, req); 2088 } 2089 2090 /*-------------------------------------------------------------------------*/ 2091 static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum) 2092 { 2093 u32 num; 2094 u32 status; 2095 2096 struct nbu2ss_req *req; 2097 struct nbu2ss_ep *ep = &udc->ep[epnum]; 2098 2099 num = epnum - 1; 2100 2101 /* Interrupt Status */ 2102 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS); 2103 2104 /* Interrupt Clear */ 2105 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~status); 2106 2107 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue); 2108 if (!req) { 2109 /* pr_warn("=== %s(%d) req == NULL\n", __func__, epnum); */ 2110 return; 2111 } 2112 2113 if (status & EPN_OUT_END_INT) { 2114 status &= ~EPN_OUT_INT; 2115 _nbu2ss_epn_out_dma_int(udc, ep, req); 2116 } 2117 2118 if (status & EPN_OUT_INT) 2119 _nbu2ss_epn_out_int(udc, ep, req); 2120 2121 if (status & EPN_IN_END_INT) { 2122 status &= ~EPN_IN_INT; 2123 _nbu2ss_epn_in_dma_int(udc, ep, req); 2124 } 2125 2126 if (status & EPN_IN_INT) 2127 _nbu2ss_epn_in_int(udc, ep, req); 2128 } 2129 2130 /*-------------------------------------------------------------------------*/ 2131 static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum) 2132 { 2133 if (epnum == 0) 2134 _nbu2ss_ep0_int(udc); 2135 else 2136 _nbu2ss_epn_int(udc, epnum); 2137 } 2138 2139 /*-------------------------------------------------------------------------*/ 2140 static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc) 2141 { 2142 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR)); 2143 _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT); 2144 } 2145 2146 /*-------------------------------------------------------------------------*/ 2147 static int _nbu2ss_nuke(struct nbu2ss_udc *udc, 2148 struct nbu2ss_ep *ep, 2149 int status) 2150 { 2151 struct nbu2ss_req *req; 2152 2153 /* Endpoint Disable */ 2154 _nbu2ss_epn_exit(udc, ep); 2155 2156 /* DMA Disable */ 2157 _nbu2ss_ep_dma_exit(udc, ep); 2158 2159 if (list_empty(&ep->queue)) 2160 return 0; 2161 2162 /* called with irqs blocked */ 2163 list_for_each_entry(req, &ep->queue, queue) { 2164 _nbu2ss_ep_done(ep, req, status); 2165 } 2166 2167 return 0; 2168 } 2169 2170 /*-------------------------------------------------------------------------*/ 2171 static void _nbu2ss_quiesce(struct nbu2ss_udc *udc) 2172 { 2173 struct nbu2ss_ep *ep; 2174 2175 udc->gadget.speed = USB_SPEED_UNKNOWN; 2176 2177 _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN); 2178 2179 /* Endpoint n */ 2180 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { 2181 _nbu2ss_nuke(udc, ep, -ESHUTDOWN); 2182 } 2183 } 2184 2185 /*-------------------------------------------------------------------------*/ 2186 static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on) 2187 { 2188 u32 reg_dt; 2189 2190 if (udc->vbus_active == 0) 2191 return -ESHUTDOWN; 2192 2193 if (is_on) { 2194 /* D+ Pullup */ 2195 if (udc->driver) { 2196 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) 2197 | PUE2) & ~(u32)CONNECTB; 2198 2199 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt); 2200 } 2201 2202 } else { 2203 /* D+ Pulldown */ 2204 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB) 2205 & ~(u32)PUE2; 2206 2207 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt); 2208 udc->gadget.speed = USB_SPEED_UNKNOWN; 2209 } 2210 2211 return 0; 2212 } 2213 2214 /*-------------------------------------------------------------------------*/ 2215 static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) 2216 { 2217 struct fc_regs *p = udc->p_regs; 2218 2219 if (udc->vbus_active == 0) 2220 return; 2221 2222 if (ep->epnum == 0) { 2223 /* EP0 */ 2224 _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR); 2225 2226 } else { 2227 /* EPN */ 2228 _nbu2ss_ep_dma_abort(udc, ep); 2229 _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPN_BCLR); 2230 } 2231 } 2232 2233 /*-------------------------------------------------------------------------*/ 2234 static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc) 2235 { 2236 int waitcnt = 0; 2237 2238 if (udc->udc_enabled) 2239 return 0; 2240 2241 /* Reset */ 2242 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST)); 2243 udelay(EPC_RST_DISABLE_TIME); /* 1us wait */ 2244 2245 _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD); 2246 mdelay(EPC_DIRPD_DISABLE_TIME); /* 1ms wait */ 2247 2248 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST); 2249 2250 _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE); 2251 2252 _nbu2ss_writel(&udc->p_regs->AHBMCTR, 2253 HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE); 2254 2255 while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) { 2256 waitcnt++; 2257 udelay(1); /* 1us wait */ 2258 if (waitcnt == EPC_PLL_LOCK_COUNT) { 2259 dev_err(udc->dev, "*** Reset Cancel failed\n"); 2260 return -EINVAL; 2261 } 2262 } 2263 2264 _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET); 2265 2266 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV)); 2267 2268 /* EP0 */ 2269 _nbu2ss_ep0_enable(udc); 2270 2271 /* USB Interrupt Enable */ 2272 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT); 2273 2274 udc->udc_enabled = TRUE; 2275 2276 return 0; 2277 } 2278 2279 /*-------------------------------------------------------------------------*/ 2280 static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc) 2281 { 2282 _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST); 2283 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST); 2284 } 2285 2286 /*-------------------------------------------------------------------------*/ 2287 static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc) 2288 { 2289 if (udc->udc_enabled) { 2290 udc->udc_enabled = FALSE; 2291 _nbu2ss_reset_controller(udc); 2292 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST)); 2293 } 2294 } 2295 2296 /*-------------------------------------------------------------------------*/ 2297 static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc) 2298 { 2299 int nret; 2300 u32 reg_dt; 2301 2302 /* chattering */ 2303 mdelay(VBUS_CHATTERING_MDELAY); /* wait (ms) */ 2304 2305 /* VBUS ON Check*/ 2306 reg_dt = gpio_get_value(VBUS_VALUE); 2307 if (reg_dt == 0) { 2308 udc->linux_suspended = 0; 2309 2310 _nbu2ss_reset_controller(udc); 2311 dev_info(udc->dev, " ----- VBUS OFF\n"); 2312 2313 if (udc->vbus_active == 1) { 2314 /* VBUS OFF */ 2315 udc->vbus_active = 0; 2316 if (udc->usb_suspended) { 2317 udc->usb_suspended = 0; 2318 /* _nbu2ss_reset_controller(udc); */ 2319 } 2320 udc->devstate = USB_STATE_NOTATTACHED; 2321 2322 _nbu2ss_quiesce(udc); 2323 if (udc->driver) { 2324 spin_unlock(&udc->lock); 2325 udc->driver->disconnect(&udc->gadget); 2326 spin_lock(&udc->lock); 2327 } 2328 2329 _nbu2ss_disable_controller(udc); 2330 } 2331 } else { 2332 mdelay(5); /* wait (5ms) */ 2333 reg_dt = gpio_get_value(VBUS_VALUE); 2334 if (reg_dt == 0) 2335 return; 2336 2337 dev_info(udc->dev, " ----- VBUS ON\n"); 2338 2339 if (udc->linux_suspended) 2340 return; 2341 2342 if (udc->vbus_active == 0) { 2343 /* VBUS ON */ 2344 udc->vbus_active = 1; 2345 udc->devstate = USB_STATE_POWERED; 2346 2347 nret = _nbu2ss_enable_controller(udc); 2348 if (nret < 0) { 2349 _nbu2ss_disable_controller(udc); 2350 udc->vbus_active = 0; 2351 return; 2352 } 2353 2354 _nbu2ss_pullup(udc, 1); 2355 2356 #ifdef UDC_DEBUG_DUMP 2357 _nbu2ss_dump_register(udc); 2358 #endif /* UDC_DEBUG_DUMP */ 2359 2360 } else { 2361 if (udc->devstate == USB_STATE_POWERED) 2362 _nbu2ss_pullup(udc, 1); 2363 } 2364 } 2365 } 2366 2367 /*-------------------------------------------------------------------------*/ 2368 static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc) 2369 { 2370 udc->devstate = USB_STATE_DEFAULT; 2371 udc->remote_wakeup = 0; 2372 2373 _nbu2ss_quiesce(udc); 2374 2375 udc->ep0state = EP0_IDLE; 2376 } 2377 2378 /*-------------------------------------------------------------------------*/ 2379 static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc) 2380 { 2381 if (udc->usb_suspended == 1) { 2382 udc->usb_suspended = 0; 2383 if (udc->driver && udc->driver->resume) { 2384 spin_unlock(&udc->lock); 2385 udc->driver->resume(&udc->gadget); 2386 spin_lock(&udc->lock); 2387 } 2388 } 2389 } 2390 2391 /*-------------------------------------------------------------------------*/ 2392 static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc) 2393 { 2394 u32 reg_dt; 2395 2396 if (udc->usb_suspended == 0) { 2397 reg_dt = gpio_get_value(VBUS_VALUE); 2398 2399 if (reg_dt == 0) 2400 return; 2401 2402 udc->usb_suspended = 1; 2403 if (udc->driver && udc->driver->suspend) { 2404 spin_unlock(&udc->lock); 2405 udc->driver->suspend(&udc->gadget); 2406 spin_lock(&udc->lock); 2407 } 2408 2409 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND); 2410 } 2411 } 2412 2413 /*-------------------------------------------------------------------------*/ 2414 /* VBUS (GPIO153) Interrupt */ 2415 static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc) 2416 { 2417 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc; 2418 2419 spin_lock(&udc->lock); 2420 _nbu2ss_check_vbus(udc); 2421 spin_unlock(&udc->lock); 2422 2423 return IRQ_HANDLED; 2424 } 2425 2426 /*-------------------------------------------------------------------------*/ 2427 /* Interrupt (udc) */ 2428 static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc) 2429 { 2430 u8 suspend_flag = 0; 2431 u32 status; 2432 u32 epnum, int_bit; 2433 2434 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc; 2435 struct fc_regs *preg = udc->p_regs; 2436 2437 if (gpio_get_value(VBUS_VALUE) == 0) { 2438 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW); 2439 _nbu2ss_writel(&preg->USB_INT_ENA, 0); 2440 return IRQ_HANDLED; 2441 } 2442 2443 spin_lock(&udc->lock); 2444 2445 for (;;) { 2446 if (gpio_get_value(VBUS_VALUE) == 0) { 2447 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW); 2448 _nbu2ss_writel(&preg->USB_INT_ENA, 0); 2449 status = 0; 2450 } else { 2451 status = _nbu2ss_readl(&preg->USB_INT_STA); 2452 } 2453 2454 if (status == 0) 2455 break; 2456 2457 _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW)); 2458 2459 if (status & USB_RST_INT) { 2460 /* USB Reset */ 2461 _nbu2ss_int_bus_reset(udc); 2462 } 2463 2464 if (status & RSUM_INT) { 2465 /* Resume */ 2466 _nbu2ss_int_usb_resume(udc); 2467 } 2468 2469 if (status & SPND_INT) { 2470 /* Suspend */ 2471 suspend_flag = 1; 2472 } 2473 2474 if (status & EPN_INT) { 2475 /* EP INT */ 2476 int_bit = status >> 8; 2477 2478 for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) { 2479 if (0x01 & int_bit) 2480 _nbu2ss_ep_int(udc, epnum); 2481 2482 int_bit >>= 1; 2483 2484 if (int_bit == 0) 2485 break; 2486 } 2487 } 2488 } 2489 2490 if (suspend_flag) 2491 _nbu2ss_int_usb_suspend(udc); 2492 2493 spin_unlock(&udc->lock); 2494 2495 return IRQ_HANDLED; 2496 } 2497 2498 /*-------------------------------------------------------------------------*/ 2499 /* usb_ep_ops */ 2500 static int nbu2ss_ep_enable( 2501 struct usb_ep *_ep, 2502 const struct usb_endpoint_descriptor *desc) 2503 { 2504 u8 ep_type; 2505 unsigned long flags; 2506 2507 struct nbu2ss_ep *ep; 2508 struct nbu2ss_udc *udc; 2509 2510 if ((!_ep) || (!desc)) { 2511 pr_err(" *** %s, bad param\n", __func__); 2512 return -EINVAL; 2513 } 2514 2515 ep = container_of(_ep, struct nbu2ss_ep, ep); 2516 if ((!ep) || (!ep->udc)) { 2517 pr_err(" *** %s, ep == NULL !!\n", __func__); 2518 return -EINVAL; 2519 } 2520 2521 ep_type = usb_endpoint_type(desc); 2522 if ((ep_type == USB_ENDPOINT_XFER_CONTROL) || 2523 (ep_type == USB_ENDPOINT_XFER_ISOC)) { 2524 pr_err(" *** %s, bat bmAttributes\n", __func__); 2525 return -EINVAL; 2526 } 2527 2528 udc = ep->udc; 2529 if (udc->vbus_active == 0) 2530 return -ESHUTDOWN; 2531 2532 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { 2533 dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__); 2534 return -ESHUTDOWN; 2535 } 2536 2537 spin_lock_irqsave(&udc->lock, flags); 2538 2539 ep->desc = desc; 2540 ep->epnum = usb_endpoint_num(desc); 2541 ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK; 2542 ep->ep_type = ep_type; 2543 ep->wedged = 0; 2544 ep->halted = FALSE; 2545 ep->stalled = FALSE; 2546 2547 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize); 2548 2549 /* DMA setting */ 2550 _nbu2ss_ep_dma_init(udc, ep); 2551 2552 /* Endpoint setting */ 2553 _nbu2ss_ep_init(udc, ep); 2554 2555 spin_unlock_irqrestore(&udc->lock, flags); 2556 2557 return 0; 2558 } 2559 2560 /*-------------------------------------------------------------------------*/ 2561 static int nbu2ss_ep_disable(struct usb_ep *_ep) 2562 { 2563 struct nbu2ss_ep *ep; 2564 struct nbu2ss_udc *udc; 2565 unsigned long flags; 2566 2567 if (!_ep) { 2568 pr_err(" *** %s, bad param\n", __func__); 2569 return -EINVAL; 2570 } 2571 2572 ep = container_of(_ep, struct nbu2ss_ep, ep); 2573 if ((!ep) || (!ep->udc)) { 2574 pr_err("udc: *** %s, ep == NULL !!\n", __func__); 2575 return -EINVAL; 2576 } 2577 2578 udc = ep->udc; 2579 if (udc->vbus_active == 0) 2580 return -ESHUTDOWN; 2581 2582 spin_lock_irqsave(&udc->lock, flags); 2583 _nbu2ss_nuke(udc, ep, -EINPROGRESS); /* dequeue request */ 2584 spin_unlock_irqrestore(&udc->lock, flags); 2585 2586 return 0; 2587 } 2588 2589 /*-------------------------------------------------------------------------*/ 2590 static struct usb_request *nbu2ss_ep_alloc_request( 2591 struct usb_ep *ep, 2592 gfp_t gfp_flags) 2593 { 2594 struct nbu2ss_req *req; 2595 2596 req = kzalloc(sizeof(*req), gfp_flags); 2597 if (!req) 2598 return NULL; 2599 2600 #ifdef USE_DMA 2601 req->req.dma = DMA_ADDR_INVALID; 2602 #endif 2603 INIT_LIST_HEAD(&req->queue); 2604 2605 return &req->req; 2606 } 2607 2608 /*-------------------------------------------------------------------------*/ 2609 static void nbu2ss_ep_free_request( 2610 struct usb_ep *_ep, 2611 struct usb_request *_req) 2612 { 2613 struct nbu2ss_req *req; 2614 2615 if (_req) { 2616 req = container_of(_req, struct nbu2ss_req, req); 2617 2618 kfree(req); 2619 } 2620 } 2621 2622 /*-------------------------------------------------------------------------*/ 2623 static int nbu2ss_ep_queue( 2624 struct usb_ep *_ep, 2625 struct usb_request *_req, 2626 gfp_t gfp_flags) 2627 { 2628 struct nbu2ss_req *req; 2629 struct nbu2ss_ep *ep; 2630 struct nbu2ss_udc *udc; 2631 unsigned long flags; 2632 bool bflag; 2633 int result = -EINVAL; 2634 2635 /* catch various bogus parameters */ 2636 if ((!_ep) || (!_req)) { 2637 if (!_ep) 2638 pr_err("udc: %s --- _ep == NULL\n", __func__); 2639 2640 if (!_req) 2641 pr_err("udc: %s --- _req == NULL\n", __func__); 2642 2643 return -EINVAL; 2644 } 2645 2646 req = container_of(_req, struct nbu2ss_req, req); 2647 if (unlikely(!_req->complete || 2648 !_req->buf || 2649 !list_empty(&req->queue))) { 2650 if (!_req->complete) 2651 pr_err("udc: %s --- !_req->complete\n", __func__); 2652 2653 if (!_req->buf) 2654 pr_err("udc:%s --- !_req->buf\n", __func__); 2655 2656 if (!list_empty(&req->queue)) 2657 pr_err("%s --- !list_empty(&req->queue)\n", __func__); 2658 2659 return -EINVAL; 2660 } 2661 2662 ep = container_of(_ep, struct nbu2ss_ep, ep); 2663 udc = ep->udc; 2664 2665 if (udc->vbus_active == 0) { 2666 dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n"); 2667 return -ESHUTDOWN; 2668 } 2669 2670 if (unlikely(!udc->driver)) { 2671 dev_err(udc->dev, "%s, bogus device state %p\n", __func__, 2672 udc->driver); 2673 return -ESHUTDOWN; 2674 } 2675 2676 spin_lock_irqsave(&udc->lock, flags); 2677 2678 #ifdef USE_DMA 2679 if ((uintptr_t)req->req.buf & 0x3) 2680 req->unaligned = TRUE; 2681 else 2682 req->unaligned = FALSE; 2683 2684 if (req->unaligned) { 2685 if (!ep->virt_buf) 2686 ep->virt_buf = dma_alloc_coherent( 2687 NULL, PAGE_SIZE, 2688 &ep->phys_buf, GFP_ATOMIC | GFP_DMA); 2689 if (ep->epnum > 0) { 2690 if (ep->direct == USB_DIR_IN) 2691 memcpy(ep->virt_buf, req->req.buf, 2692 req->req.length); 2693 } 2694 } 2695 2696 if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) && 2697 (req->req.dma != 0)) 2698 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT); 2699 #endif 2700 2701 _req->status = -EINPROGRESS; 2702 _req->actual = 0; 2703 2704 bflag = list_empty(&ep->queue); 2705 list_add_tail(&req->queue, &ep->queue); 2706 2707 if (bflag && !ep->stalled) { 2708 result = _nbu2ss_start_transfer(udc, ep, req, FALSE); 2709 if (result < 0) { 2710 dev_err(udc->dev, " *** %s, result = %d\n", __func__, 2711 result); 2712 list_del(&req->queue); 2713 } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) { 2714 #ifdef USE_DMA 2715 if (req->req.length < 4 && 2716 req->req.length == req->req.actual) 2717 #else 2718 if (req->req.length == req->req.actual) 2719 #endif 2720 _nbu2ss_ep_done(ep, req, result); 2721 } 2722 } 2723 2724 spin_unlock_irqrestore(&udc->lock, flags); 2725 2726 return 0; 2727 } 2728 2729 /*-------------------------------------------------------------------------*/ 2730 static int nbu2ss_ep_dequeue( 2731 struct usb_ep *_ep, 2732 struct usb_request *_req) 2733 { 2734 struct nbu2ss_req *req; 2735 struct nbu2ss_ep *ep; 2736 struct nbu2ss_udc *udc; 2737 unsigned long flags; 2738 2739 /* catch various bogus parameters */ 2740 if ((!_ep) || (!_req)) { 2741 /* pr_err("%s, bad param(1)\n", __func__); */ 2742 return -EINVAL; 2743 } 2744 2745 ep = container_of(_ep, struct nbu2ss_ep, ep); 2746 if (!ep) { 2747 pr_err("%s, ep == NULL !!\n", __func__); 2748 return -EINVAL; 2749 } 2750 2751 udc = ep->udc; 2752 if (!udc) 2753 return -EINVAL; 2754 2755 spin_lock_irqsave(&udc->lock, flags); 2756 2757 /* make sure it's actually queued on this endpoint */ 2758 list_for_each_entry(req, &ep->queue, queue) { 2759 if (&req->req == _req) 2760 break; 2761 } 2762 if (&req->req != _req) { 2763 spin_unlock_irqrestore(&udc->lock, flags); 2764 pr_debug("%s no queue(EINVAL)\n", __func__); 2765 return -EINVAL; 2766 } 2767 2768 _nbu2ss_ep_done(ep, req, -ECONNRESET); 2769 2770 spin_unlock_irqrestore(&udc->lock, flags); 2771 2772 return 0; 2773 } 2774 2775 /*-------------------------------------------------------------------------*/ 2776 static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value) 2777 { 2778 u8 ep_adrs; 2779 unsigned long flags; 2780 2781 struct nbu2ss_ep *ep; 2782 struct nbu2ss_udc *udc; 2783 2784 if (!_ep) { 2785 pr_err("%s, bad param\n", __func__); 2786 return -EINVAL; 2787 } 2788 2789 ep = container_of(_ep, struct nbu2ss_ep, ep); 2790 if (!ep) { 2791 pr_err("%s, bad ep\n", __func__); 2792 return -EINVAL; 2793 } 2794 2795 udc = ep->udc; 2796 if (!udc) { 2797 dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__); 2798 return -EINVAL; 2799 } 2800 2801 spin_lock_irqsave(&udc->lock, flags); 2802 2803 ep_adrs = ep->epnum | ep->direct; 2804 if (value == 0) { 2805 _nbu2ss_set_endpoint_stall(udc, ep_adrs, value); 2806 ep->stalled = FALSE; 2807 } else { 2808 if (list_empty(&ep->queue)) 2809 _nbu2ss_epn_set_stall(udc, ep); 2810 else 2811 ep->stalled = TRUE; 2812 } 2813 2814 if (value == 0) 2815 ep->wedged = 0; 2816 2817 spin_unlock_irqrestore(&udc->lock, flags); 2818 2819 return 0; 2820 } 2821 2822 static int nbu2ss_ep_set_wedge(struct usb_ep *_ep) 2823 { 2824 return nbu2ss_ep_set_halt(_ep, 1); 2825 } 2826 2827 /*-------------------------------------------------------------------------*/ 2828 static int nbu2ss_ep_fifo_status(struct usb_ep *_ep) 2829 { 2830 u32 data; 2831 struct nbu2ss_ep *ep; 2832 struct nbu2ss_udc *udc; 2833 unsigned long flags; 2834 struct fc_regs *preg; 2835 2836 if (!_ep) { 2837 pr_err("%s, bad param\n", __func__); 2838 return -EINVAL; 2839 } 2840 2841 ep = container_of(_ep, struct nbu2ss_ep, ep); 2842 if (!ep) { 2843 pr_err("%s, bad ep\n", __func__); 2844 return -EINVAL; 2845 } 2846 2847 udc = ep->udc; 2848 if (!udc) { 2849 dev_err(ep->udc->dev, "%s, bad udc\n", __func__); 2850 return -EINVAL; 2851 } 2852 2853 preg = udc->p_regs; 2854 2855 data = gpio_get_value(VBUS_VALUE); 2856 if (data == 0) 2857 return -EINVAL; 2858 2859 spin_lock_irqsave(&udc->lock, flags); 2860 2861 if (ep->epnum == 0) { 2862 data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA; 2863 2864 } else { 2865 data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT) 2866 & EPN_LDATA; 2867 } 2868 2869 spin_unlock_irqrestore(&udc->lock, flags); 2870 2871 return 0; 2872 } 2873 2874 /*-------------------------------------------------------------------------*/ 2875 static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep) 2876 { 2877 u32 data; 2878 struct nbu2ss_ep *ep; 2879 struct nbu2ss_udc *udc; 2880 unsigned long flags; 2881 2882 if (!_ep) { 2883 pr_err("udc: %s, bad param\n", __func__); 2884 return; 2885 } 2886 2887 ep = container_of(_ep, struct nbu2ss_ep, ep); 2888 if (!ep) { 2889 pr_err("udc: %s, bad ep\n", __func__); 2890 return; 2891 } 2892 2893 udc = ep->udc; 2894 if (!udc) { 2895 dev_err(ep->udc->dev, "%s, bad udc\n", __func__); 2896 return; 2897 } 2898 2899 data = gpio_get_value(VBUS_VALUE); 2900 if (data == 0) 2901 return; 2902 2903 spin_lock_irqsave(&udc->lock, flags); 2904 _nbu2ss_fifo_flush(udc, ep); 2905 spin_unlock_irqrestore(&udc->lock, flags); 2906 } 2907 2908 /*-------------------------------------------------------------------------*/ 2909 static const struct usb_ep_ops nbu2ss_ep_ops = { 2910 .enable = nbu2ss_ep_enable, 2911 .disable = nbu2ss_ep_disable, 2912 2913 .alloc_request = nbu2ss_ep_alloc_request, 2914 .free_request = nbu2ss_ep_free_request, 2915 2916 .queue = nbu2ss_ep_queue, 2917 .dequeue = nbu2ss_ep_dequeue, 2918 2919 .set_halt = nbu2ss_ep_set_halt, 2920 .set_wedge = nbu2ss_ep_set_wedge, 2921 2922 .fifo_status = nbu2ss_ep_fifo_status, 2923 .fifo_flush = nbu2ss_ep_fifo_flush, 2924 }; 2925 2926 /*-------------------------------------------------------------------------*/ 2927 /* usb_gadget_ops */ 2928 2929 /*-------------------------------------------------------------------------*/ 2930 static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget) 2931 { 2932 u32 data; 2933 struct nbu2ss_udc *udc; 2934 2935 if (!pgadget) { 2936 pr_err("udc: %s, bad param\n", __func__); 2937 return -EINVAL; 2938 } 2939 2940 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2941 data = gpio_get_value(VBUS_VALUE); 2942 if (data == 0) 2943 return -EINVAL; 2944 2945 return _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME; 2946 } 2947 2948 /*-------------------------------------------------------------------------*/ 2949 static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget) 2950 { 2951 int i; 2952 u32 data; 2953 2954 struct nbu2ss_udc *udc; 2955 2956 if (!pgadget) { 2957 pr_err("%s, bad param\n", __func__); 2958 return -EINVAL; 2959 } 2960 2961 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 2962 if (!udc) { 2963 dev_err(&pgadget->dev, "%s, udc == NULL\n", __func__); 2964 return -EINVAL; 2965 } 2966 2967 data = gpio_get_value(VBUS_VALUE); 2968 if (data == 0) { 2969 dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data); 2970 return -EINVAL; 2971 } 2972 2973 _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME); 2974 2975 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) { 2976 data = _nbu2ss_readl(&udc->p_regs->EPCTR); 2977 2978 if (data & PLL_LOCK) 2979 break; 2980 } 2981 2982 _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME); 2983 2984 return 0; 2985 } 2986 2987 /*-------------------------------------------------------------------------*/ 2988 static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget, 2989 int is_selfpowered) 2990 { 2991 struct nbu2ss_udc *udc; 2992 unsigned long flags; 2993 2994 if (!pgadget) { 2995 pr_err("%s, bad param\n", __func__); 2996 return -EINVAL; 2997 } 2998 2999 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 3000 3001 spin_lock_irqsave(&udc->lock, flags); 3002 pgadget->is_selfpowered = (is_selfpowered != 0); 3003 spin_unlock_irqrestore(&udc->lock, flags); 3004 3005 return 0; 3006 } 3007 3008 /*-------------------------------------------------------------------------*/ 3009 static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active) 3010 { 3011 return 0; 3012 } 3013 3014 /*-------------------------------------------------------------------------*/ 3015 static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned int mA) 3016 { 3017 struct nbu2ss_udc *udc; 3018 unsigned long flags; 3019 3020 if (!pgadget) { 3021 pr_err("%s, bad param\n", __func__); 3022 return -EINVAL; 3023 } 3024 3025 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 3026 3027 spin_lock_irqsave(&udc->lock, flags); 3028 udc->mA = mA; 3029 spin_unlock_irqrestore(&udc->lock, flags); 3030 3031 return 0; 3032 } 3033 3034 /*-------------------------------------------------------------------------*/ 3035 static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on) 3036 { 3037 struct nbu2ss_udc *udc; 3038 unsigned long flags; 3039 3040 if (!pgadget) { 3041 pr_err("%s, bad param\n", __func__); 3042 return -EINVAL; 3043 } 3044 3045 udc = container_of(pgadget, struct nbu2ss_udc, gadget); 3046 3047 if (!udc->driver) { 3048 pr_warn("%s, Not Regist Driver\n", __func__); 3049 return -EINVAL; 3050 } 3051 3052 if (udc->vbus_active == 0) 3053 return -ESHUTDOWN; 3054 3055 spin_lock_irqsave(&udc->lock, flags); 3056 _nbu2ss_pullup(udc, is_on); 3057 spin_unlock_irqrestore(&udc->lock, flags); 3058 3059 return 0; 3060 } 3061 3062 /*-------------------------------------------------------------------------*/ 3063 static int nbu2ss_gad_ioctl( 3064 struct usb_gadget *pgadget, 3065 unsigned int code, 3066 unsigned long param) 3067 { 3068 return 0; 3069 } 3070 3071 static const struct usb_gadget_ops nbu2ss_gadget_ops = { 3072 .get_frame = nbu2ss_gad_get_frame, 3073 .wakeup = nbu2ss_gad_wakeup, 3074 .set_selfpowered = nbu2ss_gad_set_selfpowered, 3075 .vbus_session = nbu2ss_gad_vbus_session, 3076 .vbus_draw = nbu2ss_gad_vbus_draw, 3077 .pullup = nbu2ss_gad_pullup, 3078 .ioctl = nbu2ss_gad_ioctl, 3079 }; 3080 3081 static const struct { 3082 const char *name; 3083 const struct usb_ep_caps caps; 3084 } ep_info[NUM_ENDPOINTS] = { 3085 #define EP_INFO(_name, _caps) \ 3086 { \ 3087 .name = _name, \ 3088 .caps = _caps, \ 3089 } 3090 3091 EP_INFO("ep0", 3092 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)), 3093 EP_INFO("ep1-bulk", 3094 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 3095 EP_INFO("ep2-bulk", 3096 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 3097 EP_INFO("ep3in-int", 3098 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)), 3099 EP_INFO("ep4-iso", 3100 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 3101 EP_INFO("ep5-iso", 3102 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 3103 EP_INFO("ep6-bulk", 3104 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 3105 EP_INFO("ep7-bulk", 3106 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 3107 EP_INFO("ep8in-int", 3108 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)), 3109 EP_INFO("ep9-iso", 3110 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 3111 EP_INFO("epa-iso", 3112 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)), 3113 EP_INFO("epb-bulk", 3114 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 3115 EP_INFO("epc-bulk", 3116 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)), 3117 EP_INFO("epdin-int", 3118 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)), 3119 3120 #undef EP_INFO 3121 }; 3122 3123 /*-------------------------------------------------------------------------*/ 3124 static void nbu2ss_drv_ep_init(struct nbu2ss_udc *udc) 3125 { 3126 int i; 3127 3128 INIT_LIST_HEAD(&udc->gadget.ep_list); 3129 udc->gadget.ep0 = &udc->ep[0].ep; 3130 3131 for (i = 0; i < NUM_ENDPOINTS; i++) { 3132 struct nbu2ss_ep *ep = &udc->ep[i]; 3133 3134 ep->udc = udc; 3135 ep->desc = NULL; 3136 3137 ep->ep.driver_data = NULL; 3138 ep->ep.name = ep_info[i].name; 3139 ep->ep.caps = ep_info[i].caps; 3140 ep->ep.ops = &nbu2ss_ep_ops; 3141 3142 usb_ep_set_maxpacket_limit(&ep->ep, 3143 i == 0 ? EP0_PACKETSIZE 3144 : EP_PACKETSIZE); 3145 3146 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 3147 INIT_LIST_HEAD(&ep->queue); 3148 } 3149 3150 list_del_init(&udc->ep[0].ep.ep_list); 3151 } 3152 3153 /*-------------------------------------------------------------------------*/ 3154 /* platform_driver */ 3155 static int nbu2ss_drv_contest_init( 3156 struct platform_device *pdev, 3157 struct nbu2ss_udc *udc) 3158 { 3159 spin_lock_init(&udc->lock); 3160 udc->dev = &pdev->dev; 3161 3162 udc->gadget.is_selfpowered = 1; 3163 udc->devstate = USB_STATE_NOTATTACHED; 3164 udc->pdev = pdev; 3165 udc->mA = 0; 3166 3167 udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 3168 3169 /* init Endpoint */ 3170 nbu2ss_drv_ep_init(udc); 3171 3172 /* init Gadget */ 3173 udc->gadget.ops = &nbu2ss_gadget_ops; 3174 udc->gadget.ep0 = &udc->ep[0].ep; 3175 udc->gadget.speed = USB_SPEED_UNKNOWN; 3176 udc->gadget.name = driver_name; 3177 /* udc->gadget.is_dualspeed = 1; */ 3178 3179 device_initialize(&udc->gadget.dev); 3180 3181 dev_set_name(&udc->gadget.dev, "gadget"); 3182 udc->gadget.dev.parent = &pdev->dev; 3183 udc->gadget.dev.dma_mask = pdev->dev.dma_mask; 3184 3185 return 0; 3186 } 3187 3188 /* 3189 * probe - binds to the platform device 3190 */ 3191 static int nbu2ss_drv_probe(struct platform_device *pdev) 3192 { 3193 int status = -ENODEV; 3194 struct nbu2ss_udc *udc; 3195 struct resource *r; 3196 int irq; 3197 void __iomem *mmio_base; 3198 3199 udc = &udc_controller; 3200 memset(udc, 0, sizeof(struct nbu2ss_udc)); 3201 3202 platform_set_drvdata(pdev, udc); 3203 3204 /* require I/O memory and IRQ to be provided as resources */ 3205 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3206 mmio_base = devm_ioremap_resource(&pdev->dev, r); 3207 if (IS_ERR(mmio_base)) 3208 return PTR_ERR(mmio_base); 3209 3210 irq = platform_get_irq(pdev, 0); 3211 if (irq < 0) { 3212 dev_err(&pdev->dev, "failed to get IRQ\n"); 3213 return irq; 3214 } 3215 status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq, 3216 0, driver_name, udc); 3217 3218 /* IO Memory */ 3219 udc->p_regs = (struct fc_regs *)mmio_base; 3220 3221 /* USB Function Controller Interrupt */ 3222 if (status != 0) { 3223 dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n"); 3224 return status; 3225 } 3226 3227 /* Driver Initialization */ 3228 status = nbu2ss_drv_contest_init(pdev, udc); 3229 if (status < 0) { 3230 /* Error */ 3231 return status; 3232 } 3233 3234 /* VBUS Interrupt */ 3235 irq_set_irq_type(INT_VBUS, IRQ_TYPE_EDGE_BOTH); 3236 status = request_irq(INT_VBUS, 3237 _nbu2ss_vbus_irq, IRQF_SHARED, driver_name, udc); 3238 3239 if (status != 0) { 3240 dev_err(udc->dev, "request_irq(INT_VBUS) failed\n"); 3241 return status; 3242 } 3243 3244 return status; 3245 } 3246 3247 /*-------------------------------------------------------------------------*/ 3248 static void nbu2ss_drv_shutdown(struct platform_device *pdev) 3249 { 3250 struct nbu2ss_udc *udc; 3251 3252 udc = platform_get_drvdata(pdev); 3253 if (!udc) 3254 return; 3255 3256 _nbu2ss_disable_controller(udc); 3257 } 3258 3259 /*-------------------------------------------------------------------------*/ 3260 static int nbu2ss_drv_remove(struct platform_device *pdev) 3261 { 3262 struct nbu2ss_udc *udc; 3263 struct nbu2ss_ep *ep; 3264 int i; 3265 3266 udc = &udc_controller; 3267 3268 for (i = 0; i < NUM_ENDPOINTS; i++) { 3269 ep = &udc->ep[i]; 3270 if (ep->virt_buf) 3271 dma_free_coherent(NULL, PAGE_SIZE, (void *)ep->virt_buf, 3272 ep->phys_buf); 3273 } 3274 3275 /* Interrupt Handler - Release */ 3276 free_irq(INT_VBUS, udc); 3277 3278 return 0; 3279 } 3280 3281 /*-------------------------------------------------------------------------*/ 3282 static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state) 3283 { 3284 struct nbu2ss_udc *udc; 3285 3286 udc = platform_get_drvdata(pdev); 3287 if (!udc) 3288 return 0; 3289 3290 if (udc->vbus_active) { 3291 udc->vbus_active = 0; 3292 udc->devstate = USB_STATE_NOTATTACHED; 3293 udc->linux_suspended = 1; 3294 3295 if (udc->usb_suspended) { 3296 udc->usb_suspended = 0; 3297 _nbu2ss_reset_controller(udc); 3298 } 3299 3300 _nbu2ss_quiesce(udc); 3301 } 3302 _nbu2ss_disable_controller(udc); 3303 3304 return 0; 3305 } 3306 3307 /*-------------------------------------------------------------------------*/ 3308 static int nbu2ss_drv_resume(struct platform_device *pdev) 3309 { 3310 u32 data; 3311 struct nbu2ss_udc *udc; 3312 3313 udc = platform_get_drvdata(pdev); 3314 if (!udc) 3315 return 0; 3316 3317 data = gpio_get_value(VBUS_VALUE); 3318 if (data) { 3319 udc->vbus_active = 1; 3320 udc->devstate = USB_STATE_POWERED; 3321 _nbu2ss_enable_controller(udc); 3322 _nbu2ss_pullup(udc, 1); 3323 } 3324 3325 udc->linux_suspended = 0; 3326 3327 return 0; 3328 } 3329 3330 static struct platform_driver udc_driver = { 3331 .probe = nbu2ss_drv_probe, 3332 .shutdown = nbu2ss_drv_shutdown, 3333 .remove = nbu2ss_drv_remove, 3334 .suspend = nbu2ss_drv_suspend, 3335 .resume = nbu2ss_drv_resume, 3336 .driver = { 3337 .name = driver_name, 3338 }, 3339 }; 3340 3341 module_platform_driver(udc_driver); 3342 3343 MODULE_DESCRIPTION(DRIVER_DESC); 3344 MODULE_AUTHOR("Renesas Electronics Corporation"); 3345 MODULE_LICENSE("GPL"); 3346