1 /* 2 * Sonics Silicon Backplane 3 * Bus scanning 4 * 5 * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de> 6 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de> 7 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net> 8 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org> 9 * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 * Copyright (C) 2006 Broadcom Corporation. 11 * 12 * Licensed under the GNU/GPL. See COPYING for details. 13 */ 14 15 #include <linux/ssb/ssb.h> 16 #include <linux/ssb/ssb_regs.h> 17 #include <linux/pci.h> 18 #include <linux/io.h> 19 20 #include <pcmcia/cs_types.h> 21 #include <pcmcia/cs.h> 22 #include <pcmcia/cistpl.h> 23 #include <pcmcia/ds.h> 24 25 #include "ssb_private.h" 26 27 28 const char *ssb_core_name(u16 coreid) 29 { 30 switch (coreid) { 31 case SSB_DEV_CHIPCOMMON: 32 return "ChipCommon"; 33 case SSB_DEV_ILINE20: 34 return "ILine 20"; 35 case SSB_DEV_SDRAM: 36 return "SDRAM"; 37 case SSB_DEV_PCI: 38 return "PCI"; 39 case SSB_DEV_MIPS: 40 return "MIPS"; 41 case SSB_DEV_ETHERNET: 42 return "Fast Ethernet"; 43 case SSB_DEV_V90: 44 return "V90"; 45 case SSB_DEV_USB11_HOSTDEV: 46 return "USB 1.1 Hostdev"; 47 case SSB_DEV_ADSL: 48 return "ADSL"; 49 case SSB_DEV_ILINE100: 50 return "ILine 100"; 51 case SSB_DEV_IPSEC: 52 return "IPSEC"; 53 case SSB_DEV_PCMCIA: 54 return "PCMCIA"; 55 case SSB_DEV_INTERNAL_MEM: 56 return "Internal Memory"; 57 case SSB_DEV_MEMC_SDRAM: 58 return "MEMC SDRAM"; 59 case SSB_DEV_EXTIF: 60 return "EXTIF"; 61 case SSB_DEV_80211: 62 return "IEEE 802.11"; 63 case SSB_DEV_MIPS_3302: 64 return "MIPS 3302"; 65 case SSB_DEV_USB11_HOST: 66 return "USB 1.1 Host"; 67 case SSB_DEV_USB11_DEV: 68 return "USB 1.1 Device"; 69 case SSB_DEV_USB20_HOST: 70 return "USB 2.0 Host"; 71 case SSB_DEV_USB20_DEV: 72 return "USB 2.0 Device"; 73 case SSB_DEV_SDIO_HOST: 74 return "SDIO Host"; 75 case SSB_DEV_ROBOSWITCH: 76 return "Roboswitch"; 77 case SSB_DEV_PARA_ATA: 78 return "PATA"; 79 case SSB_DEV_SATA_XORDMA: 80 return "SATA XOR-DMA"; 81 case SSB_DEV_ETHERNET_GBIT: 82 return "GBit Ethernet"; 83 case SSB_DEV_PCIE: 84 return "PCI-E"; 85 case SSB_DEV_MIMO_PHY: 86 return "MIMO PHY"; 87 case SSB_DEV_SRAM_CTRLR: 88 return "SRAM Controller"; 89 case SSB_DEV_MINI_MACPHY: 90 return "Mini MACPHY"; 91 case SSB_DEV_ARM_1176: 92 return "ARM 1176"; 93 case SSB_DEV_ARM_7TDMI: 94 return "ARM 7TDMI"; 95 } 96 return "UNKNOWN"; 97 } 98 99 static u16 pcidev_to_chipid(struct pci_dev *pci_dev) 100 { 101 u16 chipid_fallback = 0; 102 103 switch (pci_dev->device) { 104 case 0x4301: 105 chipid_fallback = 0x4301; 106 break; 107 case 0x4305 ... 0x4307: 108 chipid_fallback = 0x4307; 109 break; 110 case 0x4403: 111 chipid_fallback = 0x4402; 112 break; 113 case 0x4610 ... 0x4615: 114 chipid_fallback = 0x4610; 115 break; 116 case 0x4710 ... 0x4715: 117 chipid_fallback = 0x4710; 118 break; 119 case 0x4320 ... 0x4325: 120 chipid_fallback = 0x4309; 121 break; 122 case PCI_DEVICE_ID_BCM4401: 123 case PCI_DEVICE_ID_BCM4401B0: 124 case PCI_DEVICE_ID_BCM4401B1: 125 chipid_fallback = 0x4401; 126 break; 127 default: 128 ssb_printk(KERN_ERR PFX 129 "PCI-ID not in fallback list\n"); 130 } 131 132 return chipid_fallback; 133 } 134 135 static u8 chipid_to_nrcores(u16 chipid) 136 { 137 switch (chipid) { 138 case 0x5365: 139 return 7; 140 case 0x4306: 141 return 6; 142 case 0x4310: 143 return 8; 144 case 0x4307: 145 case 0x4301: 146 return 5; 147 case 0x4401: 148 case 0x4402: 149 return 3; 150 case 0x4710: 151 case 0x4610: 152 case 0x4704: 153 return 9; 154 default: 155 ssb_printk(KERN_ERR PFX 156 "CHIPID not in nrcores fallback list\n"); 157 } 158 159 return 1; 160 } 161 162 static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx, 163 u16 offset) 164 { 165 u32 lo, hi; 166 167 switch (bus->bustype) { 168 case SSB_BUSTYPE_SSB: 169 offset += current_coreidx * SSB_CORE_SIZE; 170 break; 171 case SSB_BUSTYPE_PCI: 172 break; 173 case SSB_BUSTYPE_PCMCIA: 174 if (offset >= 0x800) { 175 ssb_pcmcia_switch_segment(bus, 1); 176 offset -= 0x800; 177 } else 178 ssb_pcmcia_switch_segment(bus, 0); 179 lo = readw(bus->mmio + offset); 180 hi = readw(bus->mmio + offset + 2); 181 return lo | (hi << 16); 182 case SSB_BUSTYPE_SDIO: 183 offset += current_coreidx * SSB_CORE_SIZE; 184 return ssb_sdio_scan_read32(bus, offset); 185 } 186 return readl(bus->mmio + offset); 187 } 188 189 static int scan_switchcore(struct ssb_bus *bus, u8 coreidx) 190 { 191 switch (bus->bustype) { 192 case SSB_BUSTYPE_SSB: 193 break; 194 case SSB_BUSTYPE_PCI: 195 return ssb_pci_switch_coreidx(bus, coreidx); 196 case SSB_BUSTYPE_PCMCIA: 197 return ssb_pcmcia_switch_coreidx(bus, coreidx); 198 case SSB_BUSTYPE_SDIO: 199 return ssb_sdio_scan_switch_coreidx(bus, coreidx); 200 } 201 return 0; 202 } 203 204 void ssb_iounmap(struct ssb_bus *bus) 205 { 206 switch (bus->bustype) { 207 case SSB_BUSTYPE_SSB: 208 case SSB_BUSTYPE_PCMCIA: 209 iounmap(bus->mmio); 210 break; 211 case SSB_BUSTYPE_PCI: 212 #ifdef CONFIG_SSB_PCIHOST 213 pci_iounmap(bus->host_pci, bus->mmio); 214 #else 215 SSB_BUG_ON(1); /* Can't reach this code. */ 216 #endif 217 break; 218 case SSB_BUSTYPE_SDIO: 219 break; 220 } 221 bus->mmio = NULL; 222 bus->mapped_device = NULL; 223 } 224 225 static void __iomem *ssb_ioremap(struct ssb_bus *bus, 226 unsigned long baseaddr) 227 { 228 void __iomem *mmio = NULL; 229 230 switch (bus->bustype) { 231 case SSB_BUSTYPE_SSB: 232 /* Only map the first core for now. */ 233 /* fallthrough... */ 234 case SSB_BUSTYPE_PCMCIA: 235 mmio = ioremap(baseaddr, SSB_CORE_SIZE); 236 break; 237 case SSB_BUSTYPE_PCI: 238 #ifdef CONFIG_SSB_PCIHOST 239 mmio = pci_iomap(bus->host_pci, 0, ~0UL); 240 #else 241 SSB_BUG_ON(1); /* Can't reach this code. */ 242 #endif 243 break; 244 case SSB_BUSTYPE_SDIO: 245 /* Nothing to ioremap in the SDIO case, just fake it */ 246 mmio = (void __iomem *)baseaddr; 247 break; 248 } 249 250 return mmio; 251 } 252 253 static int we_support_multiple_80211_cores(struct ssb_bus *bus) 254 { 255 /* More than one 802.11 core is only supported by special chips. 256 * There are chips with two 802.11 cores, but with dangling 257 * pins on the second core. Be careful and reject them here. 258 */ 259 260 #ifdef CONFIG_SSB_PCIHOST 261 if (bus->bustype == SSB_BUSTYPE_PCI) { 262 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM && 263 bus->host_pci->device == 0x4324) 264 return 1; 265 } 266 #endif /* CONFIG_SSB_PCIHOST */ 267 return 0; 268 } 269 270 int ssb_bus_scan(struct ssb_bus *bus, 271 unsigned long baseaddr) 272 { 273 int err = -ENOMEM; 274 void __iomem *mmio; 275 u32 idhi, cc, rev, tmp; 276 int dev_i, i; 277 struct ssb_device *dev; 278 int nr_80211_cores = 0; 279 280 mmio = ssb_ioremap(bus, baseaddr); 281 if (!mmio) 282 goto out; 283 bus->mmio = mmio; 284 285 err = scan_switchcore(bus, 0); /* Switch to first core */ 286 if (err) 287 goto err_unmap; 288 289 idhi = scan_read32(bus, 0, SSB_IDHIGH); 290 cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT; 291 rev = (idhi & SSB_IDHIGH_RCLO); 292 rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT; 293 294 bus->nr_devices = 0; 295 if (cc == SSB_DEV_CHIPCOMMON) { 296 tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID); 297 298 bus->chip_id = (tmp & SSB_CHIPCO_IDMASK); 299 bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >> 300 SSB_CHIPCO_REVSHIFT; 301 bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >> 302 SSB_CHIPCO_PACKSHIFT; 303 if (rev >= 4) { 304 bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >> 305 SSB_CHIPCO_NRCORESSHIFT; 306 } 307 tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP); 308 bus->chipco.capabilities = tmp; 309 } else { 310 if (bus->bustype == SSB_BUSTYPE_PCI) { 311 bus->chip_id = pcidev_to_chipid(bus->host_pci); 312 pci_read_config_word(bus->host_pci, PCI_REVISION_ID, 313 &bus->chip_rev); 314 bus->chip_package = 0; 315 } else { 316 bus->chip_id = 0x4710; 317 bus->chip_rev = 0; 318 bus->chip_package = 0; 319 } 320 } 321 if (!bus->nr_devices) 322 bus->nr_devices = chipid_to_nrcores(bus->chip_id); 323 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) { 324 ssb_printk(KERN_ERR PFX 325 "More than %d ssb cores found (%d)\n", 326 SSB_MAX_NR_CORES, bus->nr_devices); 327 goto err_unmap; 328 } 329 if (bus->bustype == SSB_BUSTYPE_SSB) { 330 /* Now that we know the number of cores, 331 * remap the whole IO space for all cores. 332 */ 333 err = -ENOMEM; 334 iounmap(mmio); 335 mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices); 336 if (!mmio) 337 goto out; 338 bus->mmio = mmio; 339 } 340 341 /* Fetch basic information about each core/device */ 342 for (i = 0, dev_i = 0; i < bus->nr_devices; i++) { 343 err = scan_switchcore(bus, i); 344 if (err) 345 goto err_unmap; 346 dev = &(bus->devices[dev_i]); 347 348 idhi = scan_read32(bus, i, SSB_IDHIGH); 349 dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT; 350 dev->id.revision = (idhi & SSB_IDHIGH_RCLO); 351 dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT; 352 dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT; 353 dev->core_index = i; 354 dev->bus = bus; 355 dev->ops = bus->ops; 356 357 ssb_dprintk(KERN_INFO PFX 358 "Core %d found: %s " 359 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n", 360 i, ssb_core_name(dev->id.coreid), 361 dev->id.coreid, dev->id.revision, dev->id.vendor); 362 363 switch (dev->id.coreid) { 364 case SSB_DEV_80211: 365 nr_80211_cores++; 366 if (nr_80211_cores > 1) { 367 if (!we_support_multiple_80211_cores(bus)) { 368 ssb_dprintk(KERN_INFO PFX "Ignoring additional " 369 "802.11 core\n"); 370 continue; 371 } 372 } 373 break; 374 case SSB_DEV_EXTIF: 375 #ifdef CONFIG_SSB_DRIVER_EXTIF 376 if (bus->extif.dev) { 377 ssb_printk(KERN_WARNING PFX 378 "WARNING: Multiple EXTIFs found\n"); 379 break; 380 } 381 bus->extif.dev = dev; 382 #endif /* CONFIG_SSB_DRIVER_EXTIF */ 383 break; 384 case SSB_DEV_CHIPCOMMON: 385 if (bus->chipco.dev) { 386 ssb_printk(KERN_WARNING PFX 387 "WARNING: Multiple ChipCommon found\n"); 388 break; 389 } 390 bus->chipco.dev = dev; 391 break; 392 case SSB_DEV_MIPS: 393 case SSB_DEV_MIPS_3302: 394 #ifdef CONFIG_SSB_DRIVER_MIPS 395 if (bus->mipscore.dev) { 396 ssb_printk(KERN_WARNING PFX 397 "WARNING: Multiple MIPS cores found\n"); 398 break; 399 } 400 bus->mipscore.dev = dev; 401 #endif /* CONFIG_SSB_DRIVER_MIPS */ 402 break; 403 case SSB_DEV_PCI: 404 case SSB_DEV_PCIE: 405 #ifdef CONFIG_SSB_DRIVER_PCICORE 406 if (bus->bustype == SSB_BUSTYPE_PCI) { 407 /* Ignore PCI cores on PCI-E cards. 408 * Ignore PCI-E cores on PCI cards. */ 409 if (dev->id.coreid == SSB_DEV_PCI) { 410 if (bus->host_pci->is_pcie) 411 continue; 412 } else { 413 if (!bus->host_pci->is_pcie) 414 continue; 415 } 416 } 417 if (bus->pcicore.dev) { 418 ssb_printk(KERN_WARNING PFX 419 "WARNING: Multiple PCI(E) cores found\n"); 420 break; 421 } 422 bus->pcicore.dev = dev; 423 #endif /* CONFIG_SSB_DRIVER_PCICORE */ 424 break; 425 default: 426 break; 427 } 428 429 dev_i++; 430 } 431 bus->nr_devices = dev_i; 432 433 err = 0; 434 out: 435 return err; 436 err_unmap: 437 ssb_iounmap(bus); 438 goto out; 439 } 440