1 /* 2 * Sonics Silicon Backplane 3 * Subsystem core 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include "ssb_private.h" 12 13 #include <linux/delay.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/ssb/ssb.h> 18 #include <linux/ssb/ssb_regs.h> 19 #include <linux/ssb/ssb_driver_gige.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/pci.h> 22 #include <linux/mmc/sdio_func.h> 23 #include <linux/slab.h> 24 25 #include <pcmcia/cistpl.h> 26 #include <pcmcia/ds.h> 27 28 29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver"); 30 MODULE_LICENSE("GPL"); 31 32 33 /* Temporary list of yet-to-be-attached buses */ 34 static LIST_HEAD(attach_queue); 35 /* List if running buses */ 36 static LIST_HEAD(buses); 37 /* Software ID counter */ 38 static unsigned int next_busnumber; 39 /* buses_mutes locks the two buslists and the next_busnumber. 40 * Don't lock this directly, but use ssb_buses_[un]lock() below. */ 41 static DEFINE_MUTEX(buses_mutex); 42 43 /* There are differences in the codeflow, if the bus is 44 * initialized from early boot, as various needed services 45 * are not available early. This is a mechanism to delay 46 * these initializations to after early boot has finished. 47 * It's also used to avoid mutex locking, as that's not 48 * available and needed early. */ 49 static bool ssb_is_early_boot = 1; 50 51 static void ssb_buses_lock(void); 52 static void ssb_buses_unlock(void); 53 54 55 #ifdef CONFIG_SSB_PCIHOST 56 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev) 57 { 58 struct ssb_bus *bus; 59 60 ssb_buses_lock(); 61 list_for_each_entry(bus, &buses, list) { 62 if (bus->bustype == SSB_BUSTYPE_PCI && 63 bus->host_pci == pdev) 64 goto found; 65 } 66 bus = NULL; 67 found: 68 ssb_buses_unlock(); 69 70 return bus; 71 } 72 #endif /* CONFIG_SSB_PCIHOST */ 73 74 #ifdef CONFIG_SSB_PCMCIAHOST 75 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev) 76 { 77 struct ssb_bus *bus; 78 79 ssb_buses_lock(); 80 list_for_each_entry(bus, &buses, list) { 81 if (bus->bustype == SSB_BUSTYPE_PCMCIA && 82 bus->host_pcmcia == pdev) 83 goto found; 84 } 85 bus = NULL; 86 found: 87 ssb_buses_unlock(); 88 89 return bus; 90 } 91 #endif /* CONFIG_SSB_PCMCIAHOST */ 92 93 #ifdef CONFIG_SSB_SDIOHOST 94 struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func) 95 { 96 struct ssb_bus *bus; 97 98 ssb_buses_lock(); 99 list_for_each_entry(bus, &buses, list) { 100 if (bus->bustype == SSB_BUSTYPE_SDIO && 101 bus->host_sdio == func) 102 goto found; 103 } 104 bus = NULL; 105 found: 106 ssb_buses_unlock(); 107 108 return bus; 109 } 110 #endif /* CONFIG_SSB_SDIOHOST */ 111 112 int ssb_for_each_bus_call(unsigned long data, 113 int (*func)(struct ssb_bus *bus, unsigned long data)) 114 { 115 struct ssb_bus *bus; 116 int res; 117 118 ssb_buses_lock(); 119 list_for_each_entry(bus, &buses, list) { 120 res = func(bus, data); 121 if (res >= 0) { 122 ssb_buses_unlock(); 123 return res; 124 } 125 } 126 ssb_buses_unlock(); 127 128 return -ENODEV; 129 } 130 131 static struct ssb_device *ssb_device_get(struct ssb_device *dev) 132 { 133 if (dev) 134 get_device(dev->dev); 135 return dev; 136 } 137 138 static void ssb_device_put(struct ssb_device *dev) 139 { 140 if (dev) 141 put_device(dev->dev); 142 } 143 144 static int ssb_device_resume(struct device *dev) 145 { 146 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 147 struct ssb_driver *ssb_drv; 148 int err = 0; 149 150 if (dev->driver) { 151 ssb_drv = drv_to_ssb_drv(dev->driver); 152 if (ssb_drv && ssb_drv->resume) 153 err = ssb_drv->resume(ssb_dev); 154 if (err) 155 goto out; 156 } 157 out: 158 return err; 159 } 160 161 static int ssb_device_suspend(struct device *dev, pm_message_t state) 162 { 163 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 164 struct ssb_driver *ssb_drv; 165 int err = 0; 166 167 if (dev->driver) { 168 ssb_drv = drv_to_ssb_drv(dev->driver); 169 if (ssb_drv && ssb_drv->suspend) 170 err = ssb_drv->suspend(ssb_dev, state); 171 if (err) 172 goto out; 173 } 174 out: 175 return err; 176 } 177 178 int ssb_bus_resume(struct ssb_bus *bus) 179 { 180 int err; 181 182 /* Reset HW state information in memory, so that HW is 183 * completely reinitialized. */ 184 bus->mapped_device = NULL; 185 #ifdef CONFIG_SSB_DRIVER_PCICORE 186 bus->pcicore.setup_done = 0; 187 #endif 188 189 err = ssb_bus_powerup(bus, 0); 190 if (err) 191 return err; 192 err = ssb_pcmcia_hardware_setup(bus); 193 if (err) { 194 ssb_bus_may_powerdown(bus); 195 return err; 196 } 197 ssb_chipco_resume(&bus->chipco); 198 ssb_bus_may_powerdown(bus); 199 200 return 0; 201 } 202 EXPORT_SYMBOL(ssb_bus_resume); 203 204 int ssb_bus_suspend(struct ssb_bus *bus) 205 { 206 ssb_chipco_suspend(&bus->chipco); 207 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 208 209 return 0; 210 } 211 EXPORT_SYMBOL(ssb_bus_suspend); 212 213 #ifdef CONFIG_SSB_SPROM 214 /** ssb_devices_freeze - Freeze all devices on the bus. 215 * 216 * After freezing no device driver will be handling a device 217 * on this bus anymore. ssb_devices_thaw() must be called after 218 * a successful freeze to reactivate the devices. 219 * 220 * @bus: The bus. 221 * @ctx: Context structure. Pass this to ssb_devices_thaw(). 222 */ 223 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx) 224 { 225 struct ssb_device *sdev; 226 struct ssb_driver *sdrv; 227 unsigned int i; 228 229 memset(ctx, 0, sizeof(*ctx)); 230 ctx->bus = bus; 231 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen)); 232 233 for (i = 0; i < bus->nr_devices; i++) { 234 sdev = ssb_device_get(&bus->devices[i]); 235 236 if (!sdev->dev || !sdev->dev->driver || 237 !device_is_registered(sdev->dev)) { 238 ssb_device_put(sdev); 239 continue; 240 } 241 sdrv = drv_to_ssb_drv(sdev->dev->driver); 242 if (SSB_WARN_ON(!sdrv->remove)) 243 continue; 244 sdrv->remove(sdev); 245 ctx->device_frozen[i] = 1; 246 } 247 248 return 0; 249 } 250 251 /** ssb_devices_thaw - Unfreeze all devices on the bus. 252 * 253 * This will re-attach the device drivers and re-init the devices. 254 * 255 * @ctx: The context structure from ssb_devices_freeze() 256 */ 257 int ssb_devices_thaw(struct ssb_freeze_context *ctx) 258 { 259 struct ssb_bus *bus = ctx->bus; 260 struct ssb_device *sdev; 261 struct ssb_driver *sdrv; 262 unsigned int i; 263 int err, result = 0; 264 265 for (i = 0; i < bus->nr_devices; i++) { 266 if (!ctx->device_frozen[i]) 267 continue; 268 sdev = &bus->devices[i]; 269 270 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver)) 271 continue; 272 sdrv = drv_to_ssb_drv(sdev->dev->driver); 273 if (SSB_WARN_ON(!sdrv || !sdrv->probe)) 274 continue; 275 276 err = sdrv->probe(sdev, &sdev->id); 277 if (err) { 278 ssb_err("Failed to thaw device %s\n", 279 dev_name(sdev->dev)); 280 result = err; 281 } 282 ssb_device_put(sdev); 283 } 284 285 return result; 286 } 287 #endif /* CONFIG_SSB_SPROM */ 288 289 static void ssb_device_shutdown(struct device *dev) 290 { 291 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 292 struct ssb_driver *ssb_drv; 293 294 if (!dev->driver) 295 return; 296 ssb_drv = drv_to_ssb_drv(dev->driver); 297 if (ssb_drv && ssb_drv->shutdown) 298 ssb_drv->shutdown(ssb_dev); 299 } 300 301 static int ssb_device_remove(struct device *dev) 302 { 303 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 304 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 305 306 if (ssb_drv && ssb_drv->remove) 307 ssb_drv->remove(ssb_dev); 308 ssb_device_put(ssb_dev); 309 310 return 0; 311 } 312 313 static int ssb_device_probe(struct device *dev) 314 { 315 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 316 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 317 int err = 0; 318 319 ssb_device_get(ssb_dev); 320 if (ssb_drv && ssb_drv->probe) 321 err = ssb_drv->probe(ssb_dev, &ssb_dev->id); 322 if (err) 323 ssb_device_put(ssb_dev); 324 325 return err; 326 } 327 328 static int ssb_match_devid(const struct ssb_device_id *tabid, 329 const struct ssb_device_id *devid) 330 { 331 if ((tabid->vendor != devid->vendor) && 332 tabid->vendor != SSB_ANY_VENDOR) 333 return 0; 334 if ((tabid->coreid != devid->coreid) && 335 tabid->coreid != SSB_ANY_ID) 336 return 0; 337 if ((tabid->revision != devid->revision) && 338 tabid->revision != SSB_ANY_REV) 339 return 0; 340 return 1; 341 } 342 343 static int ssb_bus_match(struct device *dev, struct device_driver *drv) 344 { 345 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 346 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv); 347 const struct ssb_device_id *id; 348 349 for (id = ssb_drv->id_table; 350 id->vendor || id->coreid || id->revision; 351 id++) { 352 if (ssb_match_devid(id, &ssb_dev->id)) 353 return 1; /* found */ 354 } 355 356 return 0; 357 } 358 359 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env) 360 { 361 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 362 363 if (!dev) 364 return -ENODEV; 365 366 return add_uevent_var(env, 367 "MODALIAS=ssb:v%04Xid%04Xrev%02X", 368 ssb_dev->id.vendor, ssb_dev->id.coreid, 369 ssb_dev->id.revision); 370 } 371 372 #define ssb_config_attr(attrib, field, format_string) \ 373 static ssize_t \ 374 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \ 375 { \ 376 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \ 377 } \ 378 static DEVICE_ATTR_RO(attrib); 379 380 ssb_config_attr(core_num, core_index, "%u\n") 381 ssb_config_attr(coreid, id.coreid, "0x%04x\n") 382 ssb_config_attr(vendor, id.vendor, "0x%04x\n") 383 ssb_config_attr(revision, id.revision, "%u\n") 384 ssb_config_attr(irq, irq, "%u\n") 385 static ssize_t 386 name_show(struct device *dev, struct device_attribute *attr, char *buf) 387 { 388 return sprintf(buf, "%s\n", 389 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid)); 390 } 391 static DEVICE_ATTR_RO(name); 392 393 static struct attribute *ssb_device_attrs[] = { 394 &dev_attr_name.attr, 395 &dev_attr_core_num.attr, 396 &dev_attr_coreid.attr, 397 &dev_attr_vendor.attr, 398 &dev_attr_revision.attr, 399 &dev_attr_irq.attr, 400 NULL, 401 }; 402 ATTRIBUTE_GROUPS(ssb_device); 403 404 static struct bus_type ssb_bustype = { 405 .name = "ssb", 406 .match = ssb_bus_match, 407 .probe = ssb_device_probe, 408 .remove = ssb_device_remove, 409 .shutdown = ssb_device_shutdown, 410 .suspend = ssb_device_suspend, 411 .resume = ssb_device_resume, 412 .uevent = ssb_device_uevent, 413 .dev_groups = ssb_device_groups, 414 }; 415 416 static void ssb_buses_lock(void) 417 { 418 /* See the comment at the ssb_is_early_boot definition */ 419 if (!ssb_is_early_boot) 420 mutex_lock(&buses_mutex); 421 } 422 423 static void ssb_buses_unlock(void) 424 { 425 /* See the comment at the ssb_is_early_boot definition */ 426 if (!ssb_is_early_boot) 427 mutex_unlock(&buses_mutex); 428 } 429 430 static void ssb_devices_unregister(struct ssb_bus *bus) 431 { 432 struct ssb_device *sdev; 433 int i; 434 435 for (i = bus->nr_devices - 1; i >= 0; i--) { 436 sdev = &(bus->devices[i]); 437 if (sdev->dev) 438 device_unregister(sdev->dev); 439 } 440 441 #ifdef CONFIG_SSB_EMBEDDED 442 if (bus->bustype == SSB_BUSTYPE_SSB) 443 platform_device_unregister(bus->watchdog); 444 #endif 445 } 446 447 void ssb_bus_unregister(struct ssb_bus *bus) 448 { 449 int err; 450 451 err = ssb_gpio_unregister(bus); 452 if (err == -EBUSY) 453 ssb_dbg("Some GPIOs are still in use\n"); 454 else if (err) 455 ssb_dbg("Can not unregister GPIO driver: %i\n", err); 456 457 ssb_buses_lock(); 458 ssb_devices_unregister(bus); 459 list_del(&bus->list); 460 ssb_buses_unlock(); 461 462 ssb_pcmcia_exit(bus); 463 ssb_pci_exit(bus); 464 ssb_iounmap(bus); 465 } 466 EXPORT_SYMBOL(ssb_bus_unregister); 467 468 static void ssb_release_dev(struct device *dev) 469 { 470 struct __ssb_dev_wrapper *devwrap; 471 472 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev); 473 kfree(devwrap); 474 } 475 476 static int ssb_devices_register(struct ssb_bus *bus) 477 { 478 struct ssb_device *sdev; 479 struct device *dev; 480 struct __ssb_dev_wrapper *devwrap; 481 int i, err = 0; 482 int dev_idx = 0; 483 484 for (i = 0; i < bus->nr_devices; i++) { 485 sdev = &(bus->devices[i]); 486 487 /* We don't register SSB-system devices to the kernel, 488 * as the drivers for them are built into SSB. */ 489 switch (sdev->id.coreid) { 490 case SSB_DEV_CHIPCOMMON: 491 case SSB_DEV_PCI: 492 case SSB_DEV_PCIE: 493 case SSB_DEV_PCMCIA: 494 case SSB_DEV_MIPS: 495 case SSB_DEV_MIPS_3302: 496 case SSB_DEV_EXTIF: 497 continue; 498 } 499 500 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL); 501 if (!devwrap) { 502 ssb_err("Could not allocate device\n"); 503 err = -ENOMEM; 504 goto error; 505 } 506 dev = &devwrap->dev; 507 devwrap->sdev = sdev; 508 509 dev->release = ssb_release_dev; 510 dev->bus = &ssb_bustype; 511 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx); 512 513 switch (bus->bustype) { 514 case SSB_BUSTYPE_PCI: 515 #ifdef CONFIG_SSB_PCIHOST 516 sdev->irq = bus->host_pci->irq; 517 dev->parent = &bus->host_pci->dev; 518 sdev->dma_dev = dev->parent; 519 #endif 520 break; 521 case SSB_BUSTYPE_PCMCIA: 522 #ifdef CONFIG_SSB_PCMCIAHOST 523 sdev->irq = bus->host_pcmcia->irq; 524 dev->parent = &bus->host_pcmcia->dev; 525 #endif 526 break; 527 case SSB_BUSTYPE_SDIO: 528 #ifdef CONFIG_SSB_SDIOHOST 529 dev->parent = &bus->host_sdio->dev; 530 #endif 531 break; 532 case SSB_BUSTYPE_SSB: 533 dev->dma_mask = &dev->coherent_dma_mask; 534 sdev->dma_dev = dev; 535 break; 536 } 537 538 sdev->dev = dev; 539 err = device_register(dev); 540 if (err) { 541 ssb_err("Could not register %s\n", dev_name(dev)); 542 /* Set dev to NULL to not unregister 543 * dev on error unwinding. */ 544 sdev->dev = NULL; 545 kfree(devwrap); 546 goto error; 547 } 548 dev_idx++; 549 } 550 551 #ifdef CONFIG_SSB_DRIVER_MIPS 552 if (bus->mipscore.pflash.present) { 553 err = platform_device_register(&ssb_pflash_dev); 554 if (err) 555 pr_err("Error registering parallel flash\n"); 556 } 557 #endif 558 559 #ifdef CONFIG_SSB_SFLASH 560 if (bus->mipscore.sflash.present) { 561 err = platform_device_register(&ssb_sflash_dev); 562 if (err) 563 pr_err("Error registering serial flash\n"); 564 } 565 #endif 566 567 return 0; 568 error: 569 /* Unwind the already registered devices. */ 570 ssb_devices_unregister(bus); 571 return err; 572 } 573 574 /* Needs ssb_buses_lock() */ 575 static int ssb_attach_queued_buses(void) 576 { 577 struct ssb_bus *bus, *n; 578 int err = 0; 579 int drop_them_all = 0; 580 581 list_for_each_entry_safe(bus, n, &attach_queue, list) { 582 if (drop_them_all) { 583 list_del(&bus->list); 584 continue; 585 } 586 /* Can't init the PCIcore in ssb_bus_register(), as that 587 * is too early in boot for embedded systems 588 * (no udelay() available). So do it here in attach stage. 589 */ 590 err = ssb_bus_powerup(bus, 0); 591 if (err) 592 goto error; 593 ssb_pcicore_init(&bus->pcicore); 594 if (bus->bustype == SSB_BUSTYPE_SSB) 595 ssb_watchdog_register(bus); 596 ssb_bus_may_powerdown(bus); 597 598 err = ssb_devices_register(bus); 599 error: 600 if (err) { 601 drop_them_all = 1; 602 list_del(&bus->list); 603 continue; 604 } 605 list_move_tail(&bus->list, &buses); 606 } 607 608 return err; 609 } 610 611 static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset) 612 { 613 struct ssb_bus *bus = dev->bus; 614 615 offset += dev->core_index * SSB_CORE_SIZE; 616 return readb(bus->mmio + offset); 617 } 618 619 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset) 620 { 621 struct ssb_bus *bus = dev->bus; 622 623 offset += dev->core_index * SSB_CORE_SIZE; 624 return readw(bus->mmio + offset); 625 } 626 627 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset) 628 { 629 struct ssb_bus *bus = dev->bus; 630 631 offset += dev->core_index * SSB_CORE_SIZE; 632 return readl(bus->mmio + offset); 633 } 634 635 #ifdef CONFIG_SSB_BLOCKIO 636 static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer, 637 size_t count, u16 offset, u8 reg_width) 638 { 639 struct ssb_bus *bus = dev->bus; 640 void __iomem *addr; 641 642 offset += dev->core_index * SSB_CORE_SIZE; 643 addr = bus->mmio + offset; 644 645 switch (reg_width) { 646 case sizeof(u8): { 647 u8 *buf = buffer; 648 649 while (count) { 650 *buf = __raw_readb(addr); 651 buf++; 652 count--; 653 } 654 break; 655 } 656 case sizeof(u16): { 657 __le16 *buf = buffer; 658 659 SSB_WARN_ON(count & 1); 660 while (count) { 661 *buf = (__force __le16)__raw_readw(addr); 662 buf++; 663 count -= 2; 664 } 665 break; 666 } 667 case sizeof(u32): { 668 __le32 *buf = buffer; 669 670 SSB_WARN_ON(count & 3); 671 while (count) { 672 *buf = (__force __le32)__raw_readl(addr); 673 buf++; 674 count -= 4; 675 } 676 break; 677 } 678 default: 679 SSB_WARN_ON(1); 680 } 681 } 682 #endif /* CONFIG_SSB_BLOCKIO */ 683 684 static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value) 685 { 686 struct ssb_bus *bus = dev->bus; 687 688 offset += dev->core_index * SSB_CORE_SIZE; 689 writeb(value, bus->mmio + offset); 690 } 691 692 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value) 693 { 694 struct ssb_bus *bus = dev->bus; 695 696 offset += dev->core_index * SSB_CORE_SIZE; 697 writew(value, bus->mmio + offset); 698 } 699 700 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value) 701 { 702 struct ssb_bus *bus = dev->bus; 703 704 offset += dev->core_index * SSB_CORE_SIZE; 705 writel(value, bus->mmio + offset); 706 } 707 708 #ifdef CONFIG_SSB_BLOCKIO 709 static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer, 710 size_t count, u16 offset, u8 reg_width) 711 { 712 struct ssb_bus *bus = dev->bus; 713 void __iomem *addr; 714 715 offset += dev->core_index * SSB_CORE_SIZE; 716 addr = bus->mmio + offset; 717 718 switch (reg_width) { 719 case sizeof(u8): { 720 const u8 *buf = buffer; 721 722 while (count) { 723 __raw_writeb(*buf, addr); 724 buf++; 725 count--; 726 } 727 break; 728 } 729 case sizeof(u16): { 730 const __le16 *buf = buffer; 731 732 SSB_WARN_ON(count & 1); 733 while (count) { 734 __raw_writew((__force u16)(*buf), addr); 735 buf++; 736 count -= 2; 737 } 738 break; 739 } 740 case sizeof(u32): { 741 const __le32 *buf = buffer; 742 743 SSB_WARN_ON(count & 3); 744 while (count) { 745 __raw_writel((__force u32)(*buf), addr); 746 buf++; 747 count -= 4; 748 } 749 break; 750 } 751 default: 752 SSB_WARN_ON(1); 753 } 754 } 755 #endif /* CONFIG_SSB_BLOCKIO */ 756 757 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */ 758 static const struct ssb_bus_ops ssb_ssb_ops = { 759 .read8 = ssb_ssb_read8, 760 .read16 = ssb_ssb_read16, 761 .read32 = ssb_ssb_read32, 762 .write8 = ssb_ssb_write8, 763 .write16 = ssb_ssb_write16, 764 .write32 = ssb_ssb_write32, 765 #ifdef CONFIG_SSB_BLOCKIO 766 .block_read = ssb_ssb_block_read, 767 .block_write = ssb_ssb_block_write, 768 #endif 769 }; 770 771 static int ssb_fetch_invariants(struct ssb_bus *bus, 772 ssb_invariants_func_t get_invariants) 773 { 774 struct ssb_init_invariants iv; 775 int err; 776 777 memset(&iv, 0, sizeof(iv)); 778 err = get_invariants(bus, &iv); 779 if (err) 780 goto out; 781 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo)); 782 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom)); 783 bus->has_cardbus_slot = iv.has_cardbus_slot; 784 out: 785 return err; 786 } 787 788 static int ssb_bus_register(struct ssb_bus *bus, 789 ssb_invariants_func_t get_invariants, 790 unsigned long baseaddr) 791 { 792 int err; 793 794 spin_lock_init(&bus->bar_lock); 795 INIT_LIST_HEAD(&bus->list); 796 #ifdef CONFIG_SSB_EMBEDDED 797 spin_lock_init(&bus->gpio_lock); 798 #endif 799 800 /* Powerup the bus */ 801 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 802 if (err) 803 goto out; 804 805 /* Init SDIO-host device (if any), before the scan */ 806 err = ssb_sdio_init(bus); 807 if (err) 808 goto err_disable_xtal; 809 810 ssb_buses_lock(); 811 bus->busnumber = next_busnumber; 812 /* Scan for devices (cores) */ 813 err = ssb_bus_scan(bus, baseaddr); 814 if (err) 815 goto err_sdio_exit; 816 817 /* Init PCI-host device (if any) */ 818 err = ssb_pci_init(bus); 819 if (err) 820 goto err_unmap; 821 /* Init PCMCIA-host device (if any) */ 822 err = ssb_pcmcia_init(bus); 823 if (err) 824 goto err_pci_exit; 825 826 /* Initialize basic system devices (if available) */ 827 err = ssb_bus_powerup(bus, 0); 828 if (err) 829 goto err_pcmcia_exit; 830 ssb_chipcommon_init(&bus->chipco); 831 ssb_extif_init(&bus->extif); 832 ssb_mipscore_init(&bus->mipscore); 833 err = ssb_gpio_init(bus); 834 if (err == -ENOTSUPP) 835 ssb_dbg("GPIO driver not activated\n"); 836 else if (err) 837 ssb_dbg("Error registering GPIO driver: %i\n", err); 838 err = ssb_fetch_invariants(bus, get_invariants); 839 if (err) { 840 ssb_bus_may_powerdown(bus); 841 goto err_pcmcia_exit; 842 } 843 ssb_bus_may_powerdown(bus); 844 845 /* Queue it for attach. 846 * See the comment at the ssb_is_early_boot definition. */ 847 list_add_tail(&bus->list, &attach_queue); 848 if (!ssb_is_early_boot) { 849 /* This is not early boot, so we must attach the bus now */ 850 err = ssb_attach_queued_buses(); 851 if (err) 852 goto err_dequeue; 853 } 854 next_busnumber++; 855 ssb_buses_unlock(); 856 857 out: 858 return err; 859 860 err_dequeue: 861 list_del(&bus->list); 862 err_pcmcia_exit: 863 ssb_pcmcia_exit(bus); 864 err_pci_exit: 865 ssb_pci_exit(bus); 866 err_unmap: 867 ssb_iounmap(bus); 868 err_sdio_exit: 869 ssb_sdio_exit(bus); 870 err_disable_xtal: 871 ssb_buses_unlock(); 872 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 873 return err; 874 } 875 876 #ifdef CONFIG_SSB_PCIHOST 877 int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci) 878 { 879 int err; 880 881 bus->bustype = SSB_BUSTYPE_PCI; 882 bus->host_pci = host_pci; 883 bus->ops = &ssb_pci_ops; 884 885 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0); 886 if (!err) { 887 ssb_info("Sonics Silicon Backplane found on PCI device %s\n", 888 dev_name(&host_pci->dev)); 889 } else { 890 ssb_err("Failed to register PCI version of SSB with error %d\n", 891 err); 892 } 893 894 return err; 895 } 896 EXPORT_SYMBOL(ssb_bus_pcibus_register); 897 #endif /* CONFIG_SSB_PCIHOST */ 898 899 #ifdef CONFIG_SSB_PCMCIAHOST 900 int ssb_bus_pcmciabus_register(struct ssb_bus *bus, 901 struct pcmcia_device *pcmcia_dev, 902 unsigned long baseaddr) 903 { 904 int err; 905 906 bus->bustype = SSB_BUSTYPE_PCMCIA; 907 bus->host_pcmcia = pcmcia_dev; 908 bus->ops = &ssb_pcmcia_ops; 909 910 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr); 911 if (!err) { 912 ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n", 913 pcmcia_dev->devname); 914 } 915 916 return err; 917 } 918 EXPORT_SYMBOL(ssb_bus_pcmciabus_register); 919 #endif /* CONFIG_SSB_PCMCIAHOST */ 920 921 #ifdef CONFIG_SSB_SDIOHOST 922 int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func, 923 unsigned int quirks) 924 { 925 int err; 926 927 bus->bustype = SSB_BUSTYPE_SDIO; 928 bus->host_sdio = func; 929 bus->ops = &ssb_sdio_ops; 930 bus->quirks = quirks; 931 932 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0); 933 if (!err) { 934 ssb_info("Sonics Silicon Backplane found on SDIO device %s\n", 935 sdio_func_id(func)); 936 } 937 938 return err; 939 } 940 EXPORT_SYMBOL(ssb_bus_sdiobus_register); 941 #endif /* CONFIG_SSB_PCMCIAHOST */ 942 943 int ssb_bus_ssbbus_register(struct ssb_bus *bus, unsigned long baseaddr, 944 ssb_invariants_func_t get_invariants) 945 { 946 int err; 947 948 bus->bustype = SSB_BUSTYPE_SSB; 949 bus->ops = &ssb_ssb_ops; 950 951 err = ssb_bus_register(bus, get_invariants, baseaddr); 952 if (!err) { 953 ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n", 954 baseaddr); 955 } 956 957 return err; 958 } 959 960 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner) 961 { 962 drv->drv.name = drv->name; 963 drv->drv.bus = &ssb_bustype; 964 drv->drv.owner = owner; 965 966 return driver_register(&drv->drv); 967 } 968 EXPORT_SYMBOL(__ssb_driver_register); 969 970 void ssb_driver_unregister(struct ssb_driver *drv) 971 { 972 driver_unregister(&drv->drv); 973 } 974 EXPORT_SYMBOL(ssb_driver_unregister); 975 976 void ssb_set_devtypedata(struct ssb_device *dev, void *data) 977 { 978 struct ssb_bus *bus = dev->bus; 979 struct ssb_device *ent; 980 int i; 981 982 for (i = 0; i < bus->nr_devices; i++) { 983 ent = &(bus->devices[i]); 984 if (ent->id.vendor != dev->id.vendor) 985 continue; 986 if (ent->id.coreid != dev->id.coreid) 987 continue; 988 989 ent->devtypedata = data; 990 } 991 } 992 EXPORT_SYMBOL(ssb_set_devtypedata); 993 994 static u32 clkfactor_f6_resolve(u32 v) 995 { 996 /* map the magic values */ 997 switch (v) { 998 case SSB_CHIPCO_CLK_F6_2: 999 return 2; 1000 case SSB_CHIPCO_CLK_F6_3: 1001 return 3; 1002 case SSB_CHIPCO_CLK_F6_4: 1003 return 4; 1004 case SSB_CHIPCO_CLK_F6_5: 1005 return 5; 1006 case SSB_CHIPCO_CLK_F6_6: 1007 return 6; 1008 case SSB_CHIPCO_CLK_F6_7: 1009 return 7; 1010 } 1011 return 0; 1012 } 1013 1014 /* Calculate the speed the backplane would run at a given set of clockcontrol values */ 1015 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) 1016 { 1017 u32 n1, n2, clock, m1, m2, m3, mc; 1018 1019 n1 = (n & SSB_CHIPCO_CLK_N1); 1020 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT); 1021 1022 switch (plltype) { 1023 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ 1024 if (m & SSB_CHIPCO_CLK_T6_MMASK) 1025 return SSB_CHIPCO_CLK_T6_M1; 1026 return SSB_CHIPCO_CLK_T6_M0; 1027 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 1028 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1029 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 1030 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1031 n1 = clkfactor_f6_resolve(n1); 1032 n2 += SSB_CHIPCO_CLK_F5_BIAS; 1033 break; 1034 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ 1035 n1 += SSB_CHIPCO_CLK_T2_BIAS; 1036 n2 += SSB_CHIPCO_CLK_T2_BIAS; 1037 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7))); 1038 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23))); 1039 break; 1040 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ 1041 return 100000000; 1042 default: 1043 SSB_WARN_ON(1); 1044 } 1045 1046 switch (plltype) { 1047 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1048 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1049 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2; 1050 break; 1051 default: 1052 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2; 1053 } 1054 if (!clock) 1055 return 0; 1056 1057 m1 = (m & SSB_CHIPCO_CLK_M1); 1058 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); 1059 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT); 1060 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT); 1061 1062 switch (plltype) { 1063 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 1064 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1065 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 1066 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1067 m1 = clkfactor_f6_resolve(m1); 1068 if ((plltype == SSB_PLLTYPE_1) || 1069 (plltype == SSB_PLLTYPE_3)) 1070 m2 += SSB_CHIPCO_CLK_F5_BIAS; 1071 else 1072 m2 = clkfactor_f6_resolve(m2); 1073 m3 = clkfactor_f6_resolve(m3); 1074 1075 switch (mc) { 1076 case SSB_CHIPCO_CLK_MC_BYPASS: 1077 return clock; 1078 case SSB_CHIPCO_CLK_MC_M1: 1079 return (clock / m1); 1080 case SSB_CHIPCO_CLK_MC_M1M2: 1081 return (clock / (m1 * m2)); 1082 case SSB_CHIPCO_CLK_MC_M1M2M3: 1083 return (clock / (m1 * m2 * m3)); 1084 case SSB_CHIPCO_CLK_MC_M1M3: 1085 return (clock / (m1 * m3)); 1086 } 1087 return 0; 1088 case SSB_PLLTYPE_2: 1089 m1 += SSB_CHIPCO_CLK_T2_BIAS; 1090 m2 += SSB_CHIPCO_CLK_T2M2_BIAS; 1091 m3 += SSB_CHIPCO_CLK_T2_BIAS; 1092 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7))); 1093 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10))); 1094 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7))); 1095 1096 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP)) 1097 clock /= m1; 1098 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP)) 1099 clock /= m2; 1100 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP)) 1101 clock /= m3; 1102 return clock; 1103 default: 1104 SSB_WARN_ON(1); 1105 } 1106 return 0; 1107 } 1108 1109 /* Get the current speed the backplane is running at */ 1110 u32 ssb_clockspeed(struct ssb_bus *bus) 1111 { 1112 u32 rate; 1113 u32 plltype; 1114 u32 clkctl_n, clkctl_m; 1115 1116 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU) 1117 return ssb_pmu_get_controlclock(&bus->chipco); 1118 1119 if (ssb_extif_available(&bus->extif)) 1120 ssb_extif_get_clockcontrol(&bus->extif, &plltype, 1121 &clkctl_n, &clkctl_m); 1122 else if (bus->chipco.dev) 1123 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype, 1124 &clkctl_n, &clkctl_m); 1125 else 1126 return 0; 1127 1128 if (bus->chip_id == 0x5365) { 1129 rate = 100000000; 1130 } else { 1131 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); 1132 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ 1133 rate /= 2; 1134 } 1135 1136 return rate; 1137 } 1138 EXPORT_SYMBOL(ssb_clockspeed); 1139 1140 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev) 1141 { 1142 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; 1143 1144 /* The REJECT bit seems to be different for Backplane rev 2.3 */ 1145 switch (rev) { 1146 case SSB_IDLOW_SSBREV_22: 1147 case SSB_IDLOW_SSBREV_24: 1148 case SSB_IDLOW_SSBREV_26: 1149 return SSB_TMSLOW_REJECT; 1150 case SSB_IDLOW_SSBREV_23: 1151 return SSB_TMSLOW_REJECT_23; 1152 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ 1153 case SSB_IDLOW_SSBREV_27: /* same here */ 1154 return SSB_TMSLOW_REJECT; /* this is a guess */ 1155 default: 1156 WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); 1157 } 1158 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23); 1159 } 1160 1161 int ssb_device_is_enabled(struct ssb_device *dev) 1162 { 1163 u32 val; 1164 u32 reject; 1165 1166 reject = ssb_tmslow_reject_bitmask(dev); 1167 val = ssb_read32(dev, SSB_TMSLOW); 1168 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject; 1169 1170 return (val == SSB_TMSLOW_CLOCK); 1171 } 1172 EXPORT_SYMBOL(ssb_device_is_enabled); 1173 1174 static void ssb_flush_tmslow(struct ssb_device *dev) 1175 { 1176 /* Make _really_ sure the device has finished the TMSLOW 1177 * register write transaction, as we risk running into 1178 * a machine check exception otherwise. 1179 * Do this by reading the register back to commit the 1180 * PCI write and delay an additional usec for the device 1181 * to react to the change. */ 1182 ssb_read32(dev, SSB_TMSLOW); 1183 udelay(1); 1184 } 1185 1186 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags) 1187 { 1188 u32 val; 1189 1190 ssb_device_disable(dev, core_specific_flags); 1191 ssb_write32(dev, SSB_TMSLOW, 1192 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK | 1193 SSB_TMSLOW_FGC | core_specific_flags); 1194 ssb_flush_tmslow(dev); 1195 1196 /* Clear SERR if set. This is a hw bug workaround. */ 1197 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR) 1198 ssb_write32(dev, SSB_TMSHIGH, 0); 1199 1200 val = ssb_read32(dev, SSB_IMSTATE); 1201 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { 1202 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); 1203 ssb_write32(dev, SSB_IMSTATE, val); 1204 } 1205 1206 ssb_write32(dev, SSB_TMSLOW, 1207 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC | 1208 core_specific_flags); 1209 ssb_flush_tmslow(dev); 1210 1211 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK | 1212 core_specific_flags); 1213 ssb_flush_tmslow(dev); 1214 } 1215 EXPORT_SYMBOL(ssb_device_enable); 1216 1217 /* Wait for bitmask in a register to get set or cleared. 1218 * timeout is in units of ten-microseconds */ 1219 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask, 1220 int timeout, int set) 1221 { 1222 int i; 1223 u32 val; 1224 1225 for (i = 0; i < timeout; i++) { 1226 val = ssb_read32(dev, reg); 1227 if (set) { 1228 if ((val & bitmask) == bitmask) 1229 return 0; 1230 } else { 1231 if (!(val & bitmask)) 1232 return 0; 1233 } 1234 udelay(10); 1235 } 1236 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on " 1237 "register %04X to %s.\n", 1238 bitmask, reg, (set ? "set" : "clear")); 1239 1240 return -ETIMEDOUT; 1241 } 1242 1243 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) 1244 { 1245 u32 reject, val; 1246 1247 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) 1248 return; 1249 1250 reject = ssb_tmslow_reject_bitmask(dev); 1251 1252 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) { 1253 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); 1254 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1); 1255 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); 1256 1257 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1258 val = ssb_read32(dev, SSB_IMSTATE); 1259 val |= SSB_IMSTATE_REJECT; 1260 ssb_write32(dev, SSB_IMSTATE, val); 1261 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000, 1262 0); 1263 } 1264 1265 ssb_write32(dev, SSB_TMSLOW, 1266 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | 1267 reject | SSB_TMSLOW_RESET | 1268 core_specific_flags); 1269 ssb_flush_tmslow(dev); 1270 1271 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1272 val = ssb_read32(dev, SSB_IMSTATE); 1273 val &= ~SSB_IMSTATE_REJECT; 1274 ssb_write32(dev, SSB_IMSTATE, val); 1275 } 1276 } 1277 1278 ssb_write32(dev, SSB_TMSLOW, 1279 reject | SSB_TMSLOW_RESET | 1280 core_specific_flags); 1281 ssb_flush_tmslow(dev); 1282 } 1283 EXPORT_SYMBOL(ssb_device_disable); 1284 1285 /* Some chipsets need routing known for PCIe and 64-bit DMA */ 1286 static bool ssb_dma_translation_special_bit(struct ssb_device *dev) 1287 { 1288 u16 chip_id = dev->bus->chip_id; 1289 1290 if (dev->id.coreid == SSB_DEV_80211) { 1291 return (chip_id == 0x4322 || chip_id == 43221 || 1292 chip_id == 43231 || chip_id == 43222); 1293 } 1294 1295 return 0; 1296 } 1297 1298 u32 ssb_dma_translation(struct ssb_device *dev) 1299 { 1300 switch (dev->bus->bustype) { 1301 case SSB_BUSTYPE_SSB: 1302 return 0; 1303 case SSB_BUSTYPE_PCI: 1304 if (pci_is_pcie(dev->bus->host_pci) && 1305 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) { 1306 return SSB_PCIE_DMA_H32; 1307 } else { 1308 if (ssb_dma_translation_special_bit(dev)) 1309 return SSB_PCIE_DMA_H32; 1310 else 1311 return SSB_PCI_DMA; 1312 } 1313 default: 1314 __ssb_dma_not_implemented(dev); 1315 } 1316 return 0; 1317 } 1318 EXPORT_SYMBOL(ssb_dma_translation); 1319 1320 int ssb_bus_may_powerdown(struct ssb_bus *bus) 1321 { 1322 struct ssb_chipcommon *cc; 1323 int err = 0; 1324 1325 /* On buses where more than one core may be working 1326 * at a time, we must not powerdown stuff if there are 1327 * still cores that may want to run. */ 1328 if (bus->bustype == SSB_BUSTYPE_SSB) 1329 goto out; 1330 1331 cc = &bus->chipco; 1332 1333 if (!cc->dev) 1334 goto out; 1335 if (cc->dev->id.revision < 5) 1336 goto out; 1337 1338 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); 1339 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 1340 if (err) 1341 goto error; 1342 out: 1343 #ifdef CONFIG_SSB_DEBUG 1344 bus->powered_up = 0; 1345 #endif 1346 return err; 1347 error: 1348 ssb_err("Bus powerdown failed\n"); 1349 goto out; 1350 } 1351 EXPORT_SYMBOL(ssb_bus_may_powerdown); 1352 1353 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) 1354 { 1355 int err; 1356 enum ssb_clkmode mode; 1357 1358 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 1359 if (err) 1360 goto error; 1361 1362 #ifdef CONFIG_SSB_DEBUG 1363 bus->powered_up = 1; 1364 #endif 1365 1366 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; 1367 ssb_chipco_set_clockmode(&bus->chipco, mode); 1368 1369 return 0; 1370 error: 1371 ssb_err("Bus powerup failed\n"); 1372 return err; 1373 } 1374 EXPORT_SYMBOL(ssb_bus_powerup); 1375 1376 static void ssb_broadcast_value(struct ssb_device *dev, 1377 u32 address, u32 data) 1378 { 1379 #ifdef CONFIG_SSB_DRIVER_PCICORE 1380 /* This is used for both, PCI and ChipCommon core, so be careful. */ 1381 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); 1382 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); 1383 #endif 1384 1385 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address); 1386 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */ 1387 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data); 1388 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */ 1389 } 1390 1391 void ssb_commit_settings(struct ssb_bus *bus) 1392 { 1393 struct ssb_device *dev; 1394 1395 #ifdef CONFIG_SSB_DRIVER_PCICORE 1396 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; 1397 #else 1398 dev = bus->chipco.dev; 1399 #endif 1400 if (WARN_ON(!dev)) 1401 return; 1402 /* This forces an update of the cached registers. */ 1403 ssb_broadcast_value(dev, 0xFD8, 0); 1404 } 1405 EXPORT_SYMBOL(ssb_commit_settings); 1406 1407 u32 ssb_admatch_base(u32 adm) 1408 { 1409 u32 base = 0; 1410 1411 switch (adm & SSB_ADM_TYPE) { 1412 case SSB_ADM_TYPE0: 1413 base = (adm & SSB_ADM_BASE0); 1414 break; 1415 case SSB_ADM_TYPE1: 1416 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1417 base = (adm & SSB_ADM_BASE1); 1418 break; 1419 case SSB_ADM_TYPE2: 1420 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1421 base = (adm & SSB_ADM_BASE2); 1422 break; 1423 default: 1424 SSB_WARN_ON(1); 1425 } 1426 1427 return base; 1428 } 1429 EXPORT_SYMBOL(ssb_admatch_base); 1430 1431 u32 ssb_admatch_size(u32 adm) 1432 { 1433 u32 size = 0; 1434 1435 switch (adm & SSB_ADM_TYPE) { 1436 case SSB_ADM_TYPE0: 1437 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT); 1438 break; 1439 case SSB_ADM_TYPE1: 1440 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1441 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT); 1442 break; 1443 case SSB_ADM_TYPE2: 1444 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1445 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT); 1446 break; 1447 default: 1448 SSB_WARN_ON(1); 1449 } 1450 size = (1 << (size + 1)); 1451 1452 return size; 1453 } 1454 EXPORT_SYMBOL(ssb_admatch_size); 1455 1456 static int __init ssb_modinit(void) 1457 { 1458 int err; 1459 1460 /* See the comment at the ssb_is_early_boot definition */ 1461 ssb_is_early_boot = 0; 1462 err = bus_register(&ssb_bustype); 1463 if (err) 1464 return err; 1465 1466 /* Maybe we already registered some buses at early boot. 1467 * Check for this and attach them 1468 */ 1469 ssb_buses_lock(); 1470 err = ssb_attach_queued_buses(); 1471 ssb_buses_unlock(); 1472 if (err) { 1473 bus_unregister(&ssb_bustype); 1474 goto out; 1475 } 1476 1477 err = b43_pci_ssb_bridge_init(); 1478 if (err) { 1479 ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n"); 1480 /* don't fail SSB init because of this */ 1481 err = 0; 1482 } 1483 err = ssb_gige_init(); 1484 if (err) { 1485 ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n"); 1486 /* don't fail SSB init because of this */ 1487 err = 0; 1488 } 1489 out: 1490 return err; 1491 } 1492 /* ssb must be initialized after PCI but before the ssb drivers. 1493 * That means we must use some initcall between subsys_initcall 1494 * and device_initcall. */ 1495 fs_initcall(ssb_modinit); 1496 1497 static void __exit ssb_modexit(void) 1498 { 1499 ssb_gige_exit(); 1500 b43_pci_ssb_bridge_exit(); 1501 bus_unregister(&ssb_bustype); 1502 } 1503 module_exit(ssb_modexit) 1504