1 /* 2 * Sonics Silicon Backplane 3 * Subsystem core 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include "ssb_private.h" 12 13 #include <linux/delay.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/ssb/ssb.h> 18 #include <linux/ssb/ssb_regs.h> 19 #include <linux/ssb/ssb_driver_gige.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/pci.h> 22 #include <linux/mmc/sdio_func.h> 23 #include <linux/slab.h> 24 25 #include <pcmcia/cistpl.h> 26 #include <pcmcia/ds.h> 27 28 29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver"); 30 MODULE_LICENSE("GPL"); 31 32 33 /* Temporary list of yet-to-be-attached buses */ 34 static LIST_HEAD(attach_queue); 35 /* List if running buses */ 36 static LIST_HEAD(buses); 37 /* Software ID counter */ 38 static unsigned int next_busnumber; 39 /* buses_mutes locks the two buslists and the next_busnumber. 40 * Don't lock this directly, but use ssb_buses_[un]lock() below. */ 41 static DEFINE_MUTEX(buses_mutex); 42 43 /* There are differences in the codeflow, if the bus is 44 * initialized from early boot, as various needed services 45 * are not available early. This is a mechanism to delay 46 * these initializations to after early boot has finished. 47 * It's also used to avoid mutex locking, as that's not 48 * available and needed early. */ 49 static bool ssb_is_early_boot = 1; 50 51 static void ssb_buses_lock(void); 52 static void ssb_buses_unlock(void); 53 54 55 #ifdef CONFIG_SSB_PCIHOST 56 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev) 57 { 58 struct ssb_bus *bus; 59 60 ssb_buses_lock(); 61 list_for_each_entry(bus, &buses, list) { 62 if (bus->bustype == SSB_BUSTYPE_PCI && 63 bus->host_pci == pdev) 64 goto found; 65 } 66 bus = NULL; 67 found: 68 ssb_buses_unlock(); 69 70 return bus; 71 } 72 #endif /* CONFIG_SSB_PCIHOST */ 73 74 #ifdef CONFIG_SSB_PCMCIAHOST 75 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev) 76 { 77 struct ssb_bus *bus; 78 79 ssb_buses_lock(); 80 list_for_each_entry(bus, &buses, list) { 81 if (bus->bustype == SSB_BUSTYPE_PCMCIA && 82 bus->host_pcmcia == pdev) 83 goto found; 84 } 85 bus = NULL; 86 found: 87 ssb_buses_unlock(); 88 89 return bus; 90 } 91 #endif /* CONFIG_SSB_PCMCIAHOST */ 92 93 #ifdef CONFIG_SSB_SDIOHOST 94 struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func) 95 { 96 struct ssb_bus *bus; 97 98 ssb_buses_lock(); 99 list_for_each_entry(bus, &buses, list) { 100 if (bus->bustype == SSB_BUSTYPE_SDIO && 101 bus->host_sdio == func) 102 goto found; 103 } 104 bus = NULL; 105 found: 106 ssb_buses_unlock(); 107 108 return bus; 109 } 110 #endif /* CONFIG_SSB_SDIOHOST */ 111 112 int ssb_for_each_bus_call(unsigned long data, 113 int (*func)(struct ssb_bus *bus, unsigned long data)) 114 { 115 struct ssb_bus *bus; 116 int res; 117 118 ssb_buses_lock(); 119 list_for_each_entry(bus, &buses, list) { 120 res = func(bus, data); 121 if (res >= 0) { 122 ssb_buses_unlock(); 123 return res; 124 } 125 } 126 ssb_buses_unlock(); 127 128 return -ENODEV; 129 } 130 131 static struct ssb_device *ssb_device_get(struct ssb_device *dev) 132 { 133 if (dev) 134 get_device(dev->dev); 135 return dev; 136 } 137 138 static void ssb_device_put(struct ssb_device *dev) 139 { 140 if (dev) 141 put_device(dev->dev); 142 } 143 144 static int ssb_device_resume(struct device *dev) 145 { 146 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 147 struct ssb_driver *ssb_drv; 148 int err = 0; 149 150 if (dev->driver) { 151 ssb_drv = drv_to_ssb_drv(dev->driver); 152 if (ssb_drv && ssb_drv->resume) 153 err = ssb_drv->resume(ssb_dev); 154 if (err) 155 goto out; 156 } 157 out: 158 return err; 159 } 160 161 static int ssb_device_suspend(struct device *dev, pm_message_t state) 162 { 163 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 164 struct ssb_driver *ssb_drv; 165 int err = 0; 166 167 if (dev->driver) { 168 ssb_drv = drv_to_ssb_drv(dev->driver); 169 if (ssb_drv && ssb_drv->suspend) 170 err = ssb_drv->suspend(ssb_dev, state); 171 if (err) 172 goto out; 173 } 174 out: 175 return err; 176 } 177 178 int ssb_bus_resume(struct ssb_bus *bus) 179 { 180 int err; 181 182 /* Reset HW state information in memory, so that HW is 183 * completely reinitialized. */ 184 bus->mapped_device = NULL; 185 #ifdef CONFIG_SSB_DRIVER_PCICORE 186 bus->pcicore.setup_done = 0; 187 #endif 188 189 err = ssb_bus_powerup(bus, 0); 190 if (err) 191 return err; 192 err = ssb_pcmcia_hardware_setup(bus); 193 if (err) { 194 ssb_bus_may_powerdown(bus); 195 return err; 196 } 197 ssb_chipco_resume(&bus->chipco); 198 ssb_bus_may_powerdown(bus); 199 200 return 0; 201 } 202 EXPORT_SYMBOL(ssb_bus_resume); 203 204 int ssb_bus_suspend(struct ssb_bus *bus) 205 { 206 ssb_chipco_suspend(&bus->chipco); 207 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 208 209 return 0; 210 } 211 EXPORT_SYMBOL(ssb_bus_suspend); 212 213 #ifdef CONFIG_SSB_SPROM 214 /** ssb_devices_freeze - Freeze all devices on the bus. 215 * 216 * After freezing no device driver will be handling a device 217 * on this bus anymore. ssb_devices_thaw() must be called after 218 * a successful freeze to reactivate the devices. 219 * 220 * @bus: The bus. 221 * @ctx: Context structure. Pass this to ssb_devices_thaw(). 222 */ 223 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx) 224 { 225 struct ssb_device *sdev; 226 struct ssb_driver *sdrv; 227 unsigned int i; 228 229 memset(ctx, 0, sizeof(*ctx)); 230 ctx->bus = bus; 231 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen)); 232 233 for (i = 0; i < bus->nr_devices; i++) { 234 sdev = ssb_device_get(&bus->devices[i]); 235 236 if (!sdev->dev || !sdev->dev->driver || 237 !device_is_registered(sdev->dev)) { 238 ssb_device_put(sdev); 239 continue; 240 } 241 sdrv = drv_to_ssb_drv(sdev->dev->driver); 242 if (SSB_WARN_ON(!sdrv->remove)) 243 continue; 244 sdrv->remove(sdev); 245 ctx->device_frozen[i] = 1; 246 } 247 248 return 0; 249 } 250 251 /** ssb_devices_thaw - Unfreeze all devices on the bus. 252 * 253 * This will re-attach the device drivers and re-init the devices. 254 * 255 * @ctx: The context structure from ssb_devices_freeze() 256 */ 257 int ssb_devices_thaw(struct ssb_freeze_context *ctx) 258 { 259 struct ssb_bus *bus = ctx->bus; 260 struct ssb_device *sdev; 261 struct ssb_driver *sdrv; 262 unsigned int i; 263 int err, result = 0; 264 265 for (i = 0; i < bus->nr_devices; i++) { 266 if (!ctx->device_frozen[i]) 267 continue; 268 sdev = &bus->devices[i]; 269 270 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver)) 271 continue; 272 sdrv = drv_to_ssb_drv(sdev->dev->driver); 273 if (SSB_WARN_ON(!sdrv || !sdrv->probe)) 274 continue; 275 276 err = sdrv->probe(sdev, &sdev->id); 277 if (err) { 278 ssb_err("Failed to thaw device %s\n", 279 dev_name(sdev->dev)); 280 result = err; 281 } 282 ssb_device_put(sdev); 283 } 284 285 return result; 286 } 287 #endif /* CONFIG_SSB_SPROM */ 288 289 static void ssb_device_shutdown(struct device *dev) 290 { 291 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 292 struct ssb_driver *ssb_drv; 293 294 if (!dev->driver) 295 return; 296 ssb_drv = drv_to_ssb_drv(dev->driver); 297 if (ssb_drv && ssb_drv->shutdown) 298 ssb_drv->shutdown(ssb_dev); 299 } 300 301 static int ssb_device_remove(struct device *dev) 302 { 303 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 304 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 305 306 if (ssb_drv && ssb_drv->remove) 307 ssb_drv->remove(ssb_dev); 308 ssb_device_put(ssb_dev); 309 310 return 0; 311 } 312 313 static int ssb_device_probe(struct device *dev) 314 { 315 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 316 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 317 int err = 0; 318 319 ssb_device_get(ssb_dev); 320 if (ssb_drv && ssb_drv->probe) 321 err = ssb_drv->probe(ssb_dev, &ssb_dev->id); 322 if (err) 323 ssb_device_put(ssb_dev); 324 325 return err; 326 } 327 328 static int ssb_match_devid(const struct ssb_device_id *tabid, 329 const struct ssb_device_id *devid) 330 { 331 if ((tabid->vendor != devid->vendor) && 332 tabid->vendor != SSB_ANY_VENDOR) 333 return 0; 334 if ((tabid->coreid != devid->coreid) && 335 tabid->coreid != SSB_ANY_ID) 336 return 0; 337 if ((tabid->revision != devid->revision) && 338 tabid->revision != SSB_ANY_REV) 339 return 0; 340 return 1; 341 } 342 343 static int ssb_bus_match(struct device *dev, struct device_driver *drv) 344 { 345 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 346 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv); 347 const struct ssb_device_id *id; 348 349 for (id = ssb_drv->id_table; 350 id->vendor || id->coreid || id->revision; 351 id++) { 352 if (ssb_match_devid(id, &ssb_dev->id)) 353 return 1; /* found */ 354 } 355 356 return 0; 357 } 358 359 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env) 360 { 361 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 362 363 if (!dev) 364 return -ENODEV; 365 366 return add_uevent_var(env, 367 "MODALIAS=ssb:v%04Xid%04Xrev%02X", 368 ssb_dev->id.vendor, ssb_dev->id.coreid, 369 ssb_dev->id.revision); 370 } 371 372 #define ssb_config_attr(attrib, field, format_string) \ 373 static ssize_t \ 374 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \ 375 { \ 376 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \ 377 } 378 379 ssb_config_attr(core_num, core_index, "%u\n") 380 ssb_config_attr(coreid, id.coreid, "0x%04x\n") 381 ssb_config_attr(vendor, id.vendor, "0x%04x\n") 382 ssb_config_attr(revision, id.revision, "%u\n") 383 ssb_config_attr(irq, irq, "%u\n") 384 static ssize_t 385 name_show(struct device *dev, struct device_attribute *attr, char *buf) 386 { 387 return sprintf(buf, "%s\n", 388 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid)); 389 } 390 391 static struct device_attribute ssb_device_attrs[] = { 392 __ATTR_RO(name), 393 __ATTR_RO(core_num), 394 __ATTR_RO(coreid), 395 __ATTR_RO(vendor), 396 __ATTR_RO(revision), 397 __ATTR_RO(irq), 398 __ATTR_NULL, 399 }; 400 401 static struct bus_type ssb_bustype = { 402 .name = "ssb", 403 .match = ssb_bus_match, 404 .probe = ssb_device_probe, 405 .remove = ssb_device_remove, 406 .shutdown = ssb_device_shutdown, 407 .suspend = ssb_device_suspend, 408 .resume = ssb_device_resume, 409 .uevent = ssb_device_uevent, 410 .dev_attrs = ssb_device_attrs, 411 }; 412 413 static void ssb_buses_lock(void) 414 { 415 /* See the comment at the ssb_is_early_boot definition */ 416 if (!ssb_is_early_boot) 417 mutex_lock(&buses_mutex); 418 } 419 420 static void ssb_buses_unlock(void) 421 { 422 /* See the comment at the ssb_is_early_boot definition */ 423 if (!ssb_is_early_boot) 424 mutex_unlock(&buses_mutex); 425 } 426 427 static void ssb_devices_unregister(struct ssb_bus *bus) 428 { 429 struct ssb_device *sdev; 430 int i; 431 432 for (i = bus->nr_devices - 1; i >= 0; i--) { 433 sdev = &(bus->devices[i]); 434 if (sdev->dev) 435 device_unregister(sdev->dev); 436 } 437 438 #ifdef CONFIG_SSB_EMBEDDED 439 if (bus->bustype == SSB_BUSTYPE_SSB) 440 platform_device_unregister(bus->watchdog); 441 #endif 442 } 443 444 void ssb_bus_unregister(struct ssb_bus *bus) 445 { 446 int err; 447 448 err = ssb_gpio_unregister(bus); 449 if (err == -EBUSY) 450 ssb_dbg("Some GPIOs are still in use\n"); 451 else if (err) 452 ssb_dbg("Can not unregister GPIO driver: %i\n", err); 453 454 ssb_buses_lock(); 455 ssb_devices_unregister(bus); 456 list_del(&bus->list); 457 ssb_buses_unlock(); 458 459 ssb_pcmcia_exit(bus); 460 ssb_pci_exit(bus); 461 ssb_iounmap(bus); 462 } 463 EXPORT_SYMBOL(ssb_bus_unregister); 464 465 static void ssb_release_dev(struct device *dev) 466 { 467 struct __ssb_dev_wrapper *devwrap; 468 469 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev); 470 kfree(devwrap); 471 } 472 473 static int ssb_devices_register(struct ssb_bus *bus) 474 { 475 struct ssb_device *sdev; 476 struct device *dev; 477 struct __ssb_dev_wrapper *devwrap; 478 int i, err = 0; 479 int dev_idx = 0; 480 481 for (i = 0; i < bus->nr_devices; i++) { 482 sdev = &(bus->devices[i]); 483 484 /* We don't register SSB-system devices to the kernel, 485 * as the drivers for them are built into SSB. */ 486 switch (sdev->id.coreid) { 487 case SSB_DEV_CHIPCOMMON: 488 case SSB_DEV_PCI: 489 case SSB_DEV_PCIE: 490 case SSB_DEV_PCMCIA: 491 case SSB_DEV_MIPS: 492 case SSB_DEV_MIPS_3302: 493 case SSB_DEV_EXTIF: 494 continue; 495 } 496 497 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL); 498 if (!devwrap) { 499 ssb_err("Could not allocate device\n"); 500 err = -ENOMEM; 501 goto error; 502 } 503 dev = &devwrap->dev; 504 devwrap->sdev = sdev; 505 506 dev->release = ssb_release_dev; 507 dev->bus = &ssb_bustype; 508 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx); 509 510 switch (bus->bustype) { 511 case SSB_BUSTYPE_PCI: 512 #ifdef CONFIG_SSB_PCIHOST 513 sdev->irq = bus->host_pci->irq; 514 dev->parent = &bus->host_pci->dev; 515 sdev->dma_dev = dev->parent; 516 #endif 517 break; 518 case SSB_BUSTYPE_PCMCIA: 519 #ifdef CONFIG_SSB_PCMCIAHOST 520 sdev->irq = bus->host_pcmcia->irq; 521 dev->parent = &bus->host_pcmcia->dev; 522 #endif 523 break; 524 case SSB_BUSTYPE_SDIO: 525 #ifdef CONFIG_SSB_SDIOHOST 526 dev->parent = &bus->host_sdio->dev; 527 #endif 528 break; 529 case SSB_BUSTYPE_SSB: 530 dev->dma_mask = &dev->coherent_dma_mask; 531 sdev->dma_dev = dev; 532 break; 533 } 534 535 sdev->dev = dev; 536 err = device_register(dev); 537 if (err) { 538 ssb_err("Could not register %s\n", dev_name(dev)); 539 /* Set dev to NULL to not unregister 540 * dev on error unwinding. */ 541 sdev->dev = NULL; 542 kfree(devwrap); 543 goto error; 544 } 545 dev_idx++; 546 } 547 548 #ifdef CONFIG_SSB_DRIVER_MIPS 549 if (bus->mipscore.pflash.present) { 550 err = platform_device_register(&ssb_pflash_dev); 551 if (err) 552 pr_err("Error registering parallel flash\n"); 553 } 554 #endif 555 556 #ifdef CONFIG_SSB_SFLASH 557 if (bus->mipscore.sflash.present) { 558 err = platform_device_register(&ssb_sflash_dev); 559 if (err) 560 pr_err("Error registering serial flash\n"); 561 } 562 #endif 563 564 return 0; 565 error: 566 /* Unwind the already registered devices. */ 567 ssb_devices_unregister(bus); 568 return err; 569 } 570 571 /* Needs ssb_buses_lock() */ 572 static int ssb_attach_queued_buses(void) 573 { 574 struct ssb_bus *bus, *n; 575 int err = 0; 576 int drop_them_all = 0; 577 578 list_for_each_entry_safe(bus, n, &attach_queue, list) { 579 if (drop_them_all) { 580 list_del(&bus->list); 581 continue; 582 } 583 /* Can't init the PCIcore in ssb_bus_register(), as that 584 * is too early in boot for embedded systems 585 * (no udelay() available). So do it here in attach stage. 586 */ 587 err = ssb_bus_powerup(bus, 0); 588 if (err) 589 goto error; 590 ssb_pcicore_init(&bus->pcicore); 591 if (bus->bustype == SSB_BUSTYPE_SSB) 592 ssb_watchdog_register(bus); 593 ssb_bus_may_powerdown(bus); 594 595 err = ssb_devices_register(bus); 596 error: 597 if (err) { 598 drop_them_all = 1; 599 list_del(&bus->list); 600 continue; 601 } 602 list_move_tail(&bus->list, &buses); 603 } 604 605 return err; 606 } 607 608 static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset) 609 { 610 struct ssb_bus *bus = dev->bus; 611 612 offset += dev->core_index * SSB_CORE_SIZE; 613 return readb(bus->mmio + offset); 614 } 615 616 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset) 617 { 618 struct ssb_bus *bus = dev->bus; 619 620 offset += dev->core_index * SSB_CORE_SIZE; 621 return readw(bus->mmio + offset); 622 } 623 624 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset) 625 { 626 struct ssb_bus *bus = dev->bus; 627 628 offset += dev->core_index * SSB_CORE_SIZE; 629 return readl(bus->mmio + offset); 630 } 631 632 #ifdef CONFIG_SSB_BLOCKIO 633 static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer, 634 size_t count, u16 offset, u8 reg_width) 635 { 636 struct ssb_bus *bus = dev->bus; 637 void __iomem *addr; 638 639 offset += dev->core_index * SSB_CORE_SIZE; 640 addr = bus->mmio + offset; 641 642 switch (reg_width) { 643 case sizeof(u8): { 644 u8 *buf = buffer; 645 646 while (count) { 647 *buf = __raw_readb(addr); 648 buf++; 649 count--; 650 } 651 break; 652 } 653 case sizeof(u16): { 654 __le16 *buf = buffer; 655 656 SSB_WARN_ON(count & 1); 657 while (count) { 658 *buf = (__force __le16)__raw_readw(addr); 659 buf++; 660 count -= 2; 661 } 662 break; 663 } 664 case sizeof(u32): { 665 __le32 *buf = buffer; 666 667 SSB_WARN_ON(count & 3); 668 while (count) { 669 *buf = (__force __le32)__raw_readl(addr); 670 buf++; 671 count -= 4; 672 } 673 break; 674 } 675 default: 676 SSB_WARN_ON(1); 677 } 678 } 679 #endif /* CONFIG_SSB_BLOCKIO */ 680 681 static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value) 682 { 683 struct ssb_bus *bus = dev->bus; 684 685 offset += dev->core_index * SSB_CORE_SIZE; 686 writeb(value, bus->mmio + offset); 687 } 688 689 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value) 690 { 691 struct ssb_bus *bus = dev->bus; 692 693 offset += dev->core_index * SSB_CORE_SIZE; 694 writew(value, bus->mmio + offset); 695 } 696 697 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value) 698 { 699 struct ssb_bus *bus = dev->bus; 700 701 offset += dev->core_index * SSB_CORE_SIZE; 702 writel(value, bus->mmio + offset); 703 } 704 705 #ifdef CONFIG_SSB_BLOCKIO 706 static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer, 707 size_t count, u16 offset, u8 reg_width) 708 { 709 struct ssb_bus *bus = dev->bus; 710 void __iomem *addr; 711 712 offset += dev->core_index * SSB_CORE_SIZE; 713 addr = bus->mmio + offset; 714 715 switch (reg_width) { 716 case sizeof(u8): { 717 const u8 *buf = buffer; 718 719 while (count) { 720 __raw_writeb(*buf, addr); 721 buf++; 722 count--; 723 } 724 break; 725 } 726 case sizeof(u16): { 727 const __le16 *buf = buffer; 728 729 SSB_WARN_ON(count & 1); 730 while (count) { 731 __raw_writew((__force u16)(*buf), addr); 732 buf++; 733 count -= 2; 734 } 735 break; 736 } 737 case sizeof(u32): { 738 const __le32 *buf = buffer; 739 740 SSB_WARN_ON(count & 3); 741 while (count) { 742 __raw_writel((__force u32)(*buf), addr); 743 buf++; 744 count -= 4; 745 } 746 break; 747 } 748 default: 749 SSB_WARN_ON(1); 750 } 751 } 752 #endif /* CONFIG_SSB_BLOCKIO */ 753 754 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */ 755 static const struct ssb_bus_ops ssb_ssb_ops = { 756 .read8 = ssb_ssb_read8, 757 .read16 = ssb_ssb_read16, 758 .read32 = ssb_ssb_read32, 759 .write8 = ssb_ssb_write8, 760 .write16 = ssb_ssb_write16, 761 .write32 = ssb_ssb_write32, 762 #ifdef CONFIG_SSB_BLOCKIO 763 .block_read = ssb_ssb_block_read, 764 .block_write = ssb_ssb_block_write, 765 #endif 766 }; 767 768 static int ssb_fetch_invariants(struct ssb_bus *bus, 769 ssb_invariants_func_t get_invariants) 770 { 771 struct ssb_init_invariants iv; 772 int err; 773 774 memset(&iv, 0, sizeof(iv)); 775 err = get_invariants(bus, &iv); 776 if (err) 777 goto out; 778 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo)); 779 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom)); 780 bus->has_cardbus_slot = iv.has_cardbus_slot; 781 out: 782 return err; 783 } 784 785 static int ssb_bus_register(struct ssb_bus *bus, 786 ssb_invariants_func_t get_invariants, 787 unsigned long baseaddr) 788 { 789 int err; 790 791 spin_lock_init(&bus->bar_lock); 792 INIT_LIST_HEAD(&bus->list); 793 #ifdef CONFIG_SSB_EMBEDDED 794 spin_lock_init(&bus->gpio_lock); 795 #endif 796 797 /* Powerup the bus */ 798 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 799 if (err) 800 goto out; 801 802 /* Init SDIO-host device (if any), before the scan */ 803 err = ssb_sdio_init(bus); 804 if (err) 805 goto err_disable_xtal; 806 807 ssb_buses_lock(); 808 bus->busnumber = next_busnumber; 809 /* Scan for devices (cores) */ 810 err = ssb_bus_scan(bus, baseaddr); 811 if (err) 812 goto err_sdio_exit; 813 814 /* Init PCI-host device (if any) */ 815 err = ssb_pci_init(bus); 816 if (err) 817 goto err_unmap; 818 /* Init PCMCIA-host device (if any) */ 819 err = ssb_pcmcia_init(bus); 820 if (err) 821 goto err_pci_exit; 822 823 /* Initialize basic system devices (if available) */ 824 err = ssb_bus_powerup(bus, 0); 825 if (err) 826 goto err_pcmcia_exit; 827 ssb_chipcommon_init(&bus->chipco); 828 ssb_extif_init(&bus->extif); 829 ssb_mipscore_init(&bus->mipscore); 830 err = ssb_gpio_init(bus); 831 if (err == -ENOTSUPP) 832 ssb_dbg("GPIO driver not activated\n"); 833 else if (err) 834 ssb_dbg("Error registering GPIO driver: %i\n", err); 835 err = ssb_fetch_invariants(bus, get_invariants); 836 if (err) { 837 ssb_bus_may_powerdown(bus); 838 goto err_pcmcia_exit; 839 } 840 ssb_bus_may_powerdown(bus); 841 842 /* Queue it for attach. 843 * See the comment at the ssb_is_early_boot definition. */ 844 list_add_tail(&bus->list, &attach_queue); 845 if (!ssb_is_early_boot) { 846 /* This is not early boot, so we must attach the bus now */ 847 err = ssb_attach_queued_buses(); 848 if (err) 849 goto err_dequeue; 850 } 851 next_busnumber++; 852 ssb_buses_unlock(); 853 854 out: 855 return err; 856 857 err_dequeue: 858 list_del(&bus->list); 859 err_pcmcia_exit: 860 ssb_pcmcia_exit(bus); 861 err_pci_exit: 862 ssb_pci_exit(bus); 863 err_unmap: 864 ssb_iounmap(bus); 865 err_sdio_exit: 866 ssb_sdio_exit(bus); 867 err_disable_xtal: 868 ssb_buses_unlock(); 869 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 870 return err; 871 } 872 873 #ifdef CONFIG_SSB_PCIHOST 874 int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci) 875 { 876 int err; 877 878 bus->bustype = SSB_BUSTYPE_PCI; 879 bus->host_pci = host_pci; 880 bus->ops = &ssb_pci_ops; 881 882 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0); 883 if (!err) { 884 ssb_info("Sonics Silicon Backplane found on PCI device %s\n", 885 dev_name(&host_pci->dev)); 886 } else { 887 ssb_err("Failed to register PCI version of SSB with error %d\n", 888 err); 889 } 890 891 return err; 892 } 893 EXPORT_SYMBOL(ssb_bus_pcibus_register); 894 #endif /* CONFIG_SSB_PCIHOST */ 895 896 #ifdef CONFIG_SSB_PCMCIAHOST 897 int ssb_bus_pcmciabus_register(struct ssb_bus *bus, 898 struct pcmcia_device *pcmcia_dev, 899 unsigned long baseaddr) 900 { 901 int err; 902 903 bus->bustype = SSB_BUSTYPE_PCMCIA; 904 bus->host_pcmcia = pcmcia_dev; 905 bus->ops = &ssb_pcmcia_ops; 906 907 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr); 908 if (!err) { 909 ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n", 910 pcmcia_dev->devname); 911 } 912 913 return err; 914 } 915 EXPORT_SYMBOL(ssb_bus_pcmciabus_register); 916 #endif /* CONFIG_SSB_PCMCIAHOST */ 917 918 #ifdef CONFIG_SSB_SDIOHOST 919 int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func, 920 unsigned int quirks) 921 { 922 int err; 923 924 bus->bustype = SSB_BUSTYPE_SDIO; 925 bus->host_sdio = func; 926 bus->ops = &ssb_sdio_ops; 927 bus->quirks = quirks; 928 929 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0); 930 if (!err) { 931 ssb_info("Sonics Silicon Backplane found on SDIO device %s\n", 932 sdio_func_id(func)); 933 } 934 935 return err; 936 } 937 EXPORT_SYMBOL(ssb_bus_sdiobus_register); 938 #endif /* CONFIG_SSB_PCMCIAHOST */ 939 940 int ssb_bus_ssbbus_register(struct ssb_bus *bus, unsigned long baseaddr, 941 ssb_invariants_func_t get_invariants) 942 { 943 int err; 944 945 bus->bustype = SSB_BUSTYPE_SSB; 946 bus->ops = &ssb_ssb_ops; 947 948 err = ssb_bus_register(bus, get_invariants, baseaddr); 949 if (!err) { 950 ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n", 951 baseaddr); 952 } 953 954 return err; 955 } 956 957 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner) 958 { 959 drv->drv.name = drv->name; 960 drv->drv.bus = &ssb_bustype; 961 drv->drv.owner = owner; 962 963 return driver_register(&drv->drv); 964 } 965 EXPORT_SYMBOL(__ssb_driver_register); 966 967 void ssb_driver_unregister(struct ssb_driver *drv) 968 { 969 driver_unregister(&drv->drv); 970 } 971 EXPORT_SYMBOL(ssb_driver_unregister); 972 973 void ssb_set_devtypedata(struct ssb_device *dev, void *data) 974 { 975 struct ssb_bus *bus = dev->bus; 976 struct ssb_device *ent; 977 int i; 978 979 for (i = 0; i < bus->nr_devices; i++) { 980 ent = &(bus->devices[i]); 981 if (ent->id.vendor != dev->id.vendor) 982 continue; 983 if (ent->id.coreid != dev->id.coreid) 984 continue; 985 986 ent->devtypedata = data; 987 } 988 } 989 EXPORT_SYMBOL(ssb_set_devtypedata); 990 991 static u32 clkfactor_f6_resolve(u32 v) 992 { 993 /* map the magic values */ 994 switch (v) { 995 case SSB_CHIPCO_CLK_F6_2: 996 return 2; 997 case SSB_CHIPCO_CLK_F6_3: 998 return 3; 999 case SSB_CHIPCO_CLK_F6_4: 1000 return 4; 1001 case SSB_CHIPCO_CLK_F6_5: 1002 return 5; 1003 case SSB_CHIPCO_CLK_F6_6: 1004 return 6; 1005 case SSB_CHIPCO_CLK_F6_7: 1006 return 7; 1007 } 1008 return 0; 1009 } 1010 1011 /* Calculate the speed the backplane would run at a given set of clockcontrol values */ 1012 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) 1013 { 1014 u32 n1, n2, clock, m1, m2, m3, mc; 1015 1016 n1 = (n & SSB_CHIPCO_CLK_N1); 1017 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT); 1018 1019 switch (plltype) { 1020 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ 1021 if (m & SSB_CHIPCO_CLK_T6_MMASK) 1022 return SSB_CHIPCO_CLK_T6_M1; 1023 return SSB_CHIPCO_CLK_T6_M0; 1024 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 1025 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1026 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 1027 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1028 n1 = clkfactor_f6_resolve(n1); 1029 n2 += SSB_CHIPCO_CLK_F5_BIAS; 1030 break; 1031 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ 1032 n1 += SSB_CHIPCO_CLK_T2_BIAS; 1033 n2 += SSB_CHIPCO_CLK_T2_BIAS; 1034 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7))); 1035 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23))); 1036 break; 1037 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ 1038 return 100000000; 1039 default: 1040 SSB_WARN_ON(1); 1041 } 1042 1043 switch (plltype) { 1044 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1045 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1046 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2; 1047 break; 1048 default: 1049 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2; 1050 } 1051 if (!clock) 1052 return 0; 1053 1054 m1 = (m & SSB_CHIPCO_CLK_M1); 1055 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); 1056 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT); 1057 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT); 1058 1059 switch (plltype) { 1060 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 1061 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1062 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 1063 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1064 m1 = clkfactor_f6_resolve(m1); 1065 if ((plltype == SSB_PLLTYPE_1) || 1066 (plltype == SSB_PLLTYPE_3)) 1067 m2 += SSB_CHIPCO_CLK_F5_BIAS; 1068 else 1069 m2 = clkfactor_f6_resolve(m2); 1070 m3 = clkfactor_f6_resolve(m3); 1071 1072 switch (mc) { 1073 case SSB_CHIPCO_CLK_MC_BYPASS: 1074 return clock; 1075 case SSB_CHIPCO_CLK_MC_M1: 1076 return (clock / m1); 1077 case SSB_CHIPCO_CLK_MC_M1M2: 1078 return (clock / (m1 * m2)); 1079 case SSB_CHIPCO_CLK_MC_M1M2M3: 1080 return (clock / (m1 * m2 * m3)); 1081 case SSB_CHIPCO_CLK_MC_M1M3: 1082 return (clock / (m1 * m3)); 1083 } 1084 return 0; 1085 case SSB_PLLTYPE_2: 1086 m1 += SSB_CHIPCO_CLK_T2_BIAS; 1087 m2 += SSB_CHIPCO_CLK_T2M2_BIAS; 1088 m3 += SSB_CHIPCO_CLK_T2_BIAS; 1089 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7))); 1090 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10))); 1091 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7))); 1092 1093 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP)) 1094 clock /= m1; 1095 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP)) 1096 clock /= m2; 1097 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP)) 1098 clock /= m3; 1099 return clock; 1100 default: 1101 SSB_WARN_ON(1); 1102 } 1103 return 0; 1104 } 1105 1106 /* Get the current speed the backplane is running at */ 1107 u32 ssb_clockspeed(struct ssb_bus *bus) 1108 { 1109 u32 rate; 1110 u32 plltype; 1111 u32 clkctl_n, clkctl_m; 1112 1113 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU) 1114 return ssb_pmu_get_controlclock(&bus->chipco); 1115 1116 if (ssb_extif_available(&bus->extif)) 1117 ssb_extif_get_clockcontrol(&bus->extif, &plltype, 1118 &clkctl_n, &clkctl_m); 1119 else if (bus->chipco.dev) 1120 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype, 1121 &clkctl_n, &clkctl_m); 1122 else 1123 return 0; 1124 1125 if (bus->chip_id == 0x5365) { 1126 rate = 100000000; 1127 } else { 1128 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); 1129 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ 1130 rate /= 2; 1131 } 1132 1133 return rate; 1134 } 1135 EXPORT_SYMBOL(ssb_clockspeed); 1136 1137 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev) 1138 { 1139 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; 1140 1141 /* The REJECT bit seems to be different for Backplane rev 2.3 */ 1142 switch (rev) { 1143 case SSB_IDLOW_SSBREV_22: 1144 case SSB_IDLOW_SSBREV_24: 1145 case SSB_IDLOW_SSBREV_26: 1146 return SSB_TMSLOW_REJECT; 1147 case SSB_IDLOW_SSBREV_23: 1148 return SSB_TMSLOW_REJECT_23; 1149 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ 1150 case SSB_IDLOW_SSBREV_27: /* same here */ 1151 return SSB_TMSLOW_REJECT; /* this is a guess */ 1152 default: 1153 WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); 1154 } 1155 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23); 1156 } 1157 1158 int ssb_device_is_enabled(struct ssb_device *dev) 1159 { 1160 u32 val; 1161 u32 reject; 1162 1163 reject = ssb_tmslow_reject_bitmask(dev); 1164 val = ssb_read32(dev, SSB_TMSLOW); 1165 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject; 1166 1167 return (val == SSB_TMSLOW_CLOCK); 1168 } 1169 EXPORT_SYMBOL(ssb_device_is_enabled); 1170 1171 static void ssb_flush_tmslow(struct ssb_device *dev) 1172 { 1173 /* Make _really_ sure the device has finished the TMSLOW 1174 * register write transaction, as we risk running into 1175 * a machine check exception otherwise. 1176 * Do this by reading the register back to commit the 1177 * PCI write and delay an additional usec for the device 1178 * to react to the change. */ 1179 ssb_read32(dev, SSB_TMSLOW); 1180 udelay(1); 1181 } 1182 1183 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags) 1184 { 1185 u32 val; 1186 1187 ssb_device_disable(dev, core_specific_flags); 1188 ssb_write32(dev, SSB_TMSLOW, 1189 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK | 1190 SSB_TMSLOW_FGC | core_specific_flags); 1191 ssb_flush_tmslow(dev); 1192 1193 /* Clear SERR if set. This is a hw bug workaround. */ 1194 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR) 1195 ssb_write32(dev, SSB_TMSHIGH, 0); 1196 1197 val = ssb_read32(dev, SSB_IMSTATE); 1198 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { 1199 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); 1200 ssb_write32(dev, SSB_IMSTATE, val); 1201 } 1202 1203 ssb_write32(dev, SSB_TMSLOW, 1204 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC | 1205 core_specific_flags); 1206 ssb_flush_tmslow(dev); 1207 1208 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK | 1209 core_specific_flags); 1210 ssb_flush_tmslow(dev); 1211 } 1212 EXPORT_SYMBOL(ssb_device_enable); 1213 1214 /* Wait for bitmask in a register to get set or cleared. 1215 * timeout is in units of ten-microseconds */ 1216 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask, 1217 int timeout, int set) 1218 { 1219 int i; 1220 u32 val; 1221 1222 for (i = 0; i < timeout; i++) { 1223 val = ssb_read32(dev, reg); 1224 if (set) { 1225 if ((val & bitmask) == bitmask) 1226 return 0; 1227 } else { 1228 if (!(val & bitmask)) 1229 return 0; 1230 } 1231 udelay(10); 1232 } 1233 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on " 1234 "register %04X to %s.\n", 1235 bitmask, reg, (set ? "set" : "clear")); 1236 1237 return -ETIMEDOUT; 1238 } 1239 1240 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) 1241 { 1242 u32 reject, val; 1243 1244 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) 1245 return; 1246 1247 reject = ssb_tmslow_reject_bitmask(dev); 1248 1249 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) { 1250 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); 1251 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1); 1252 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); 1253 1254 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1255 val = ssb_read32(dev, SSB_IMSTATE); 1256 val |= SSB_IMSTATE_REJECT; 1257 ssb_write32(dev, SSB_IMSTATE, val); 1258 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000, 1259 0); 1260 } 1261 1262 ssb_write32(dev, SSB_TMSLOW, 1263 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | 1264 reject | SSB_TMSLOW_RESET | 1265 core_specific_flags); 1266 ssb_flush_tmslow(dev); 1267 1268 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1269 val = ssb_read32(dev, SSB_IMSTATE); 1270 val &= ~SSB_IMSTATE_REJECT; 1271 ssb_write32(dev, SSB_IMSTATE, val); 1272 } 1273 } 1274 1275 ssb_write32(dev, SSB_TMSLOW, 1276 reject | SSB_TMSLOW_RESET | 1277 core_specific_flags); 1278 ssb_flush_tmslow(dev); 1279 } 1280 EXPORT_SYMBOL(ssb_device_disable); 1281 1282 /* Some chipsets need routing known for PCIe and 64-bit DMA */ 1283 static bool ssb_dma_translation_special_bit(struct ssb_device *dev) 1284 { 1285 u16 chip_id = dev->bus->chip_id; 1286 1287 if (dev->id.coreid == SSB_DEV_80211) { 1288 return (chip_id == 0x4322 || chip_id == 43221 || 1289 chip_id == 43231 || chip_id == 43222); 1290 } 1291 1292 return 0; 1293 } 1294 1295 u32 ssb_dma_translation(struct ssb_device *dev) 1296 { 1297 switch (dev->bus->bustype) { 1298 case SSB_BUSTYPE_SSB: 1299 return 0; 1300 case SSB_BUSTYPE_PCI: 1301 if (pci_is_pcie(dev->bus->host_pci) && 1302 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) { 1303 return SSB_PCIE_DMA_H32; 1304 } else { 1305 if (ssb_dma_translation_special_bit(dev)) 1306 return SSB_PCIE_DMA_H32; 1307 else 1308 return SSB_PCI_DMA; 1309 } 1310 default: 1311 __ssb_dma_not_implemented(dev); 1312 } 1313 return 0; 1314 } 1315 EXPORT_SYMBOL(ssb_dma_translation); 1316 1317 int ssb_bus_may_powerdown(struct ssb_bus *bus) 1318 { 1319 struct ssb_chipcommon *cc; 1320 int err = 0; 1321 1322 /* On buses where more than one core may be working 1323 * at a time, we must not powerdown stuff if there are 1324 * still cores that may want to run. */ 1325 if (bus->bustype == SSB_BUSTYPE_SSB) 1326 goto out; 1327 1328 cc = &bus->chipco; 1329 1330 if (!cc->dev) 1331 goto out; 1332 if (cc->dev->id.revision < 5) 1333 goto out; 1334 1335 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); 1336 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 1337 if (err) 1338 goto error; 1339 out: 1340 #ifdef CONFIG_SSB_DEBUG 1341 bus->powered_up = 0; 1342 #endif 1343 return err; 1344 error: 1345 ssb_err("Bus powerdown failed\n"); 1346 goto out; 1347 } 1348 EXPORT_SYMBOL(ssb_bus_may_powerdown); 1349 1350 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) 1351 { 1352 int err; 1353 enum ssb_clkmode mode; 1354 1355 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 1356 if (err) 1357 goto error; 1358 1359 #ifdef CONFIG_SSB_DEBUG 1360 bus->powered_up = 1; 1361 #endif 1362 1363 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; 1364 ssb_chipco_set_clockmode(&bus->chipco, mode); 1365 1366 return 0; 1367 error: 1368 ssb_err("Bus powerup failed\n"); 1369 return err; 1370 } 1371 EXPORT_SYMBOL(ssb_bus_powerup); 1372 1373 static void ssb_broadcast_value(struct ssb_device *dev, 1374 u32 address, u32 data) 1375 { 1376 #ifdef CONFIG_SSB_DRIVER_PCICORE 1377 /* This is used for both, PCI and ChipCommon core, so be careful. */ 1378 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); 1379 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); 1380 #endif 1381 1382 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address); 1383 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */ 1384 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data); 1385 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */ 1386 } 1387 1388 void ssb_commit_settings(struct ssb_bus *bus) 1389 { 1390 struct ssb_device *dev; 1391 1392 #ifdef CONFIG_SSB_DRIVER_PCICORE 1393 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; 1394 #else 1395 dev = bus->chipco.dev; 1396 #endif 1397 if (WARN_ON(!dev)) 1398 return; 1399 /* This forces an update of the cached registers. */ 1400 ssb_broadcast_value(dev, 0xFD8, 0); 1401 } 1402 EXPORT_SYMBOL(ssb_commit_settings); 1403 1404 u32 ssb_admatch_base(u32 adm) 1405 { 1406 u32 base = 0; 1407 1408 switch (adm & SSB_ADM_TYPE) { 1409 case SSB_ADM_TYPE0: 1410 base = (adm & SSB_ADM_BASE0); 1411 break; 1412 case SSB_ADM_TYPE1: 1413 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1414 base = (adm & SSB_ADM_BASE1); 1415 break; 1416 case SSB_ADM_TYPE2: 1417 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1418 base = (adm & SSB_ADM_BASE2); 1419 break; 1420 default: 1421 SSB_WARN_ON(1); 1422 } 1423 1424 return base; 1425 } 1426 EXPORT_SYMBOL(ssb_admatch_base); 1427 1428 u32 ssb_admatch_size(u32 adm) 1429 { 1430 u32 size = 0; 1431 1432 switch (adm & SSB_ADM_TYPE) { 1433 case SSB_ADM_TYPE0: 1434 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT); 1435 break; 1436 case SSB_ADM_TYPE1: 1437 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1438 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT); 1439 break; 1440 case SSB_ADM_TYPE2: 1441 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1442 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT); 1443 break; 1444 default: 1445 SSB_WARN_ON(1); 1446 } 1447 size = (1 << (size + 1)); 1448 1449 return size; 1450 } 1451 EXPORT_SYMBOL(ssb_admatch_size); 1452 1453 static int __init ssb_modinit(void) 1454 { 1455 int err; 1456 1457 /* See the comment at the ssb_is_early_boot definition */ 1458 ssb_is_early_boot = 0; 1459 err = bus_register(&ssb_bustype); 1460 if (err) 1461 return err; 1462 1463 /* Maybe we already registered some buses at early boot. 1464 * Check for this and attach them 1465 */ 1466 ssb_buses_lock(); 1467 err = ssb_attach_queued_buses(); 1468 ssb_buses_unlock(); 1469 if (err) { 1470 bus_unregister(&ssb_bustype); 1471 goto out; 1472 } 1473 1474 err = b43_pci_ssb_bridge_init(); 1475 if (err) { 1476 ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n"); 1477 /* don't fail SSB init because of this */ 1478 err = 0; 1479 } 1480 err = ssb_gige_init(); 1481 if (err) { 1482 ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n"); 1483 /* don't fail SSB init because of this */ 1484 err = 0; 1485 } 1486 out: 1487 return err; 1488 } 1489 /* ssb must be initialized after PCI but before the ssb drivers. 1490 * That means we must use some initcall between subsys_initcall 1491 * and device_initcall. */ 1492 fs_initcall(ssb_modinit); 1493 1494 static void __exit ssb_modexit(void) 1495 { 1496 ssb_gige_exit(); 1497 b43_pci_ssb_bridge_exit(); 1498 bus_unregister(&ssb_bustype); 1499 } 1500 module_exit(ssb_modexit) 1501