1 /* 2 * Sonics Silicon Backplane 3 * Subsystem core 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include "ssb_private.h" 12 13 #include <linux/delay.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/ssb/ssb.h> 18 #include <linux/ssb/ssb_regs.h> 19 #include <linux/ssb/ssb_driver_gige.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/pci.h> 22 #include <linux/mmc/sdio_func.h> 23 #include <linux/slab.h> 24 25 #include <pcmcia/cistpl.h> 26 #include <pcmcia/ds.h> 27 28 29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver"); 30 MODULE_LICENSE("GPL"); 31 32 33 /* Temporary list of yet-to-be-attached buses */ 34 static LIST_HEAD(attach_queue); 35 /* List if running buses */ 36 static LIST_HEAD(buses); 37 /* Software ID counter */ 38 static unsigned int next_busnumber; 39 /* buses_mutes locks the two buslists and the next_busnumber. 40 * Don't lock this directly, but use ssb_buses_[un]lock() below. */ 41 static DEFINE_MUTEX(buses_mutex); 42 43 /* There are differences in the codeflow, if the bus is 44 * initialized from early boot, as various needed services 45 * are not available early. This is a mechanism to delay 46 * these initializations to after early boot has finished. 47 * It's also used to avoid mutex locking, as that's not 48 * available and needed early. */ 49 static bool ssb_is_early_boot = 1; 50 51 static void ssb_buses_lock(void); 52 static void ssb_buses_unlock(void); 53 54 55 #ifdef CONFIG_SSB_PCIHOST 56 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev) 57 { 58 struct ssb_bus *bus; 59 60 ssb_buses_lock(); 61 list_for_each_entry(bus, &buses, list) { 62 if (bus->bustype == SSB_BUSTYPE_PCI && 63 bus->host_pci == pdev) 64 goto found; 65 } 66 bus = NULL; 67 found: 68 ssb_buses_unlock(); 69 70 return bus; 71 } 72 #endif /* CONFIG_SSB_PCIHOST */ 73 74 #ifdef CONFIG_SSB_PCMCIAHOST 75 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev) 76 { 77 struct ssb_bus *bus; 78 79 ssb_buses_lock(); 80 list_for_each_entry(bus, &buses, list) { 81 if (bus->bustype == SSB_BUSTYPE_PCMCIA && 82 bus->host_pcmcia == pdev) 83 goto found; 84 } 85 bus = NULL; 86 found: 87 ssb_buses_unlock(); 88 89 return bus; 90 } 91 #endif /* CONFIG_SSB_PCMCIAHOST */ 92 93 #ifdef CONFIG_SSB_SDIOHOST 94 struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func) 95 { 96 struct ssb_bus *bus; 97 98 ssb_buses_lock(); 99 list_for_each_entry(bus, &buses, list) { 100 if (bus->bustype == SSB_BUSTYPE_SDIO && 101 bus->host_sdio == func) 102 goto found; 103 } 104 bus = NULL; 105 found: 106 ssb_buses_unlock(); 107 108 return bus; 109 } 110 #endif /* CONFIG_SSB_SDIOHOST */ 111 112 int ssb_for_each_bus_call(unsigned long data, 113 int (*func)(struct ssb_bus *bus, unsigned long data)) 114 { 115 struct ssb_bus *bus; 116 int res; 117 118 ssb_buses_lock(); 119 list_for_each_entry(bus, &buses, list) { 120 res = func(bus, data); 121 if (res >= 0) { 122 ssb_buses_unlock(); 123 return res; 124 } 125 } 126 ssb_buses_unlock(); 127 128 return -ENODEV; 129 } 130 131 static struct ssb_device *ssb_device_get(struct ssb_device *dev) 132 { 133 if (dev) 134 get_device(dev->dev); 135 return dev; 136 } 137 138 static void ssb_device_put(struct ssb_device *dev) 139 { 140 if (dev) 141 put_device(dev->dev); 142 } 143 144 static int ssb_device_resume(struct device *dev) 145 { 146 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 147 struct ssb_driver *ssb_drv; 148 int err = 0; 149 150 if (dev->driver) { 151 ssb_drv = drv_to_ssb_drv(dev->driver); 152 if (ssb_drv && ssb_drv->resume) 153 err = ssb_drv->resume(ssb_dev); 154 if (err) 155 goto out; 156 } 157 out: 158 return err; 159 } 160 161 static int ssb_device_suspend(struct device *dev, pm_message_t state) 162 { 163 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 164 struct ssb_driver *ssb_drv; 165 int err = 0; 166 167 if (dev->driver) { 168 ssb_drv = drv_to_ssb_drv(dev->driver); 169 if (ssb_drv && ssb_drv->suspend) 170 err = ssb_drv->suspend(ssb_dev, state); 171 if (err) 172 goto out; 173 } 174 out: 175 return err; 176 } 177 178 int ssb_bus_resume(struct ssb_bus *bus) 179 { 180 int err; 181 182 /* Reset HW state information in memory, so that HW is 183 * completely reinitialized. */ 184 bus->mapped_device = NULL; 185 #ifdef CONFIG_SSB_DRIVER_PCICORE 186 bus->pcicore.setup_done = 0; 187 #endif 188 189 err = ssb_bus_powerup(bus, 0); 190 if (err) 191 return err; 192 err = ssb_pcmcia_hardware_setup(bus); 193 if (err) { 194 ssb_bus_may_powerdown(bus); 195 return err; 196 } 197 ssb_chipco_resume(&bus->chipco); 198 ssb_bus_may_powerdown(bus); 199 200 return 0; 201 } 202 EXPORT_SYMBOL(ssb_bus_resume); 203 204 int ssb_bus_suspend(struct ssb_bus *bus) 205 { 206 ssb_chipco_suspend(&bus->chipco); 207 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 208 209 return 0; 210 } 211 EXPORT_SYMBOL(ssb_bus_suspend); 212 213 #ifdef CONFIG_SSB_SPROM 214 /** ssb_devices_freeze - Freeze all devices on the bus. 215 * 216 * After freezing no device driver will be handling a device 217 * on this bus anymore. ssb_devices_thaw() must be called after 218 * a successful freeze to reactivate the devices. 219 * 220 * @bus: The bus. 221 * @ctx: Context structure. Pass this to ssb_devices_thaw(). 222 */ 223 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx) 224 { 225 struct ssb_device *sdev; 226 struct ssb_driver *sdrv; 227 unsigned int i; 228 229 memset(ctx, 0, sizeof(*ctx)); 230 ctx->bus = bus; 231 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen)); 232 233 for (i = 0; i < bus->nr_devices; i++) { 234 sdev = ssb_device_get(&bus->devices[i]); 235 236 if (!sdev->dev || !sdev->dev->driver || 237 !device_is_registered(sdev->dev)) { 238 ssb_device_put(sdev); 239 continue; 240 } 241 sdrv = drv_to_ssb_drv(sdev->dev->driver); 242 if (SSB_WARN_ON(!sdrv->remove)) 243 continue; 244 sdrv->remove(sdev); 245 ctx->device_frozen[i] = 1; 246 } 247 248 return 0; 249 } 250 251 /** ssb_devices_thaw - Unfreeze all devices on the bus. 252 * 253 * This will re-attach the device drivers and re-init the devices. 254 * 255 * @ctx: The context structure from ssb_devices_freeze() 256 */ 257 int ssb_devices_thaw(struct ssb_freeze_context *ctx) 258 { 259 struct ssb_bus *bus = ctx->bus; 260 struct ssb_device *sdev; 261 struct ssb_driver *sdrv; 262 unsigned int i; 263 int err, result = 0; 264 265 for (i = 0; i < bus->nr_devices; i++) { 266 if (!ctx->device_frozen[i]) 267 continue; 268 sdev = &bus->devices[i]; 269 270 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver)) 271 continue; 272 sdrv = drv_to_ssb_drv(sdev->dev->driver); 273 if (SSB_WARN_ON(!sdrv || !sdrv->probe)) 274 continue; 275 276 err = sdrv->probe(sdev, &sdev->id); 277 if (err) { 278 ssb_err("Failed to thaw device %s\n", 279 dev_name(sdev->dev)); 280 result = err; 281 } 282 ssb_device_put(sdev); 283 } 284 285 return result; 286 } 287 #endif /* CONFIG_SSB_SPROM */ 288 289 static void ssb_device_shutdown(struct device *dev) 290 { 291 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 292 struct ssb_driver *ssb_drv; 293 294 if (!dev->driver) 295 return; 296 ssb_drv = drv_to_ssb_drv(dev->driver); 297 if (ssb_drv && ssb_drv->shutdown) 298 ssb_drv->shutdown(ssb_dev); 299 } 300 301 static int ssb_device_remove(struct device *dev) 302 { 303 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 304 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 305 306 if (ssb_drv && ssb_drv->remove) 307 ssb_drv->remove(ssb_dev); 308 ssb_device_put(ssb_dev); 309 310 return 0; 311 } 312 313 static int ssb_device_probe(struct device *dev) 314 { 315 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 316 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 317 int err = 0; 318 319 ssb_device_get(ssb_dev); 320 if (ssb_drv && ssb_drv->probe) 321 err = ssb_drv->probe(ssb_dev, &ssb_dev->id); 322 if (err) 323 ssb_device_put(ssb_dev); 324 325 return err; 326 } 327 328 static int ssb_match_devid(const struct ssb_device_id *tabid, 329 const struct ssb_device_id *devid) 330 { 331 if ((tabid->vendor != devid->vendor) && 332 tabid->vendor != SSB_ANY_VENDOR) 333 return 0; 334 if ((tabid->coreid != devid->coreid) && 335 tabid->coreid != SSB_ANY_ID) 336 return 0; 337 if ((tabid->revision != devid->revision) && 338 tabid->revision != SSB_ANY_REV) 339 return 0; 340 return 1; 341 } 342 343 static int ssb_bus_match(struct device *dev, struct device_driver *drv) 344 { 345 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 346 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv); 347 const struct ssb_device_id *id; 348 349 for (id = ssb_drv->id_table; 350 id->vendor || id->coreid || id->revision; 351 id++) { 352 if (ssb_match_devid(id, &ssb_dev->id)) 353 return 1; /* found */ 354 } 355 356 return 0; 357 } 358 359 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env) 360 { 361 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 362 363 if (!dev) 364 return -ENODEV; 365 366 return add_uevent_var(env, 367 "MODALIAS=ssb:v%04Xid%04Xrev%02X", 368 ssb_dev->id.vendor, ssb_dev->id.coreid, 369 ssb_dev->id.revision); 370 } 371 372 #define ssb_config_attr(attrib, field, format_string) \ 373 static ssize_t \ 374 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \ 375 { \ 376 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \ 377 } \ 378 static DEVICE_ATTR_RO(attrib); 379 380 ssb_config_attr(core_num, core_index, "%u\n") 381 ssb_config_attr(coreid, id.coreid, "0x%04x\n") 382 ssb_config_attr(vendor, id.vendor, "0x%04x\n") 383 ssb_config_attr(revision, id.revision, "%u\n") 384 ssb_config_attr(irq, irq, "%u\n") 385 static ssize_t 386 name_show(struct device *dev, struct device_attribute *attr, char *buf) 387 { 388 return sprintf(buf, "%s\n", 389 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid)); 390 } 391 static DEVICE_ATTR_RO(name); 392 393 static struct attribute *ssb_device_attrs[] = { 394 &dev_attr_name.attr, 395 &dev_attr_core_num.attr, 396 &dev_attr_coreid.attr, 397 &dev_attr_vendor.attr, 398 &dev_attr_revision.attr, 399 &dev_attr_irq.attr, 400 NULL, 401 }; 402 ATTRIBUTE_GROUPS(ssb_device); 403 404 static struct bus_type ssb_bustype = { 405 .name = "ssb", 406 .match = ssb_bus_match, 407 .probe = ssb_device_probe, 408 .remove = ssb_device_remove, 409 .shutdown = ssb_device_shutdown, 410 .suspend = ssb_device_suspend, 411 .resume = ssb_device_resume, 412 .uevent = ssb_device_uevent, 413 .dev_groups = ssb_device_groups, 414 }; 415 416 static void ssb_buses_lock(void) 417 { 418 /* See the comment at the ssb_is_early_boot definition */ 419 if (!ssb_is_early_boot) 420 mutex_lock(&buses_mutex); 421 } 422 423 static void ssb_buses_unlock(void) 424 { 425 /* See the comment at the ssb_is_early_boot definition */ 426 if (!ssb_is_early_boot) 427 mutex_unlock(&buses_mutex); 428 } 429 430 static void ssb_devices_unregister(struct ssb_bus *bus) 431 { 432 struct ssb_device *sdev; 433 int i; 434 435 for (i = bus->nr_devices - 1; i >= 0; i--) { 436 sdev = &(bus->devices[i]); 437 if (sdev->dev) 438 device_unregister(sdev->dev); 439 } 440 441 #ifdef CONFIG_SSB_EMBEDDED 442 if (bus->bustype == SSB_BUSTYPE_SSB) 443 platform_device_unregister(bus->watchdog); 444 #endif 445 } 446 447 void ssb_bus_unregister(struct ssb_bus *bus) 448 { 449 int err; 450 451 err = ssb_gpio_unregister(bus); 452 if (err == -EBUSY) 453 ssb_dbg("Some GPIOs are still in use\n"); 454 else if (err) 455 ssb_dbg("Can not unregister GPIO driver: %i\n", err); 456 457 ssb_buses_lock(); 458 ssb_devices_unregister(bus); 459 list_del(&bus->list); 460 ssb_buses_unlock(); 461 462 ssb_pcmcia_exit(bus); 463 ssb_pci_exit(bus); 464 ssb_iounmap(bus); 465 } 466 EXPORT_SYMBOL(ssb_bus_unregister); 467 468 static void ssb_release_dev(struct device *dev) 469 { 470 struct __ssb_dev_wrapper *devwrap; 471 472 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev); 473 kfree(devwrap); 474 } 475 476 static int ssb_devices_register(struct ssb_bus *bus) 477 { 478 struct ssb_device *sdev; 479 struct device *dev; 480 struct __ssb_dev_wrapper *devwrap; 481 int i, err = 0; 482 int dev_idx = 0; 483 484 for (i = 0; i < bus->nr_devices; i++) { 485 sdev = &(bus->devices[i]); 486 487 /* We don't register SSB-system devices to the kernel, 488 * as the drivers for them are built into SSB. */ 489 switch (sdev->id.coreid) { 490 case SSB_DEV_CHIPCOMMON: 491 case SSB_DEV_PCI: 492 case SSB_DEV_PCIE: 493 case SSB_DEV_PCMCIA: 494 case SSB_DEV_MIPS: 495 case SSB_DEV_MIPS_3302: 496 case SSB_DEV_EXTIF: 497 continue; 498 } 499 500 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL); 501 if (!devwrap) { 502 ssb_err("Could not allocate device\n"); 503 err = -ENOMEM; 504 goto error; 505 } 506 dev = &devwrap->dev; 507 devwrap->sdev = sdev; 508 509 dev->release = ssb_release_dev; 510 dev->bus = &ssb_bustype; 511 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx); 512 513 switch (bus->bustype) { 514 case SSB_BUSTYPE_PCI: 515 #ifdef CONFIG_SSB_PCIHOST 516 sdev->irq = bus->host_pci->irq; 517 dev->parent = &bus->host_pci->dev; 518 sdev->dma_dev = dev->parent; 519 #endif 520 break; 521 case SSB_BUSTYPE_PCMCIA: 522 #ifdef CONFIG_SSB_PCMCIAHOST 523 sdev->irq = bus->host_pcmcia->irq; 524 dev->parent = &bus->host_pcmcia->dev; 525 #endif 526 break; 527 case SSB_BUSTYPE_SDIO: 528 #ifdef CONFIG_SSB_SDIOHOST 529 dev->parent = &bus->host_sdio->dev; 530 #endif 531 break; 532 case SSB_BUSTYPE_SSB: 533 dev->dma_mask = &dev->coherent_dma_mask; 534 sdev->dma_dev = dev; 535 break; 536 } 537 538 sdev->dev = dev; 539 err = device_register(dev); 540 if (err) { 541 ssb_err("Could not register %s\n", dev_name(dev)); 542 /* Set dev to NULL to not unregister 543 * dev on error unwinding. */ 544 sdev->dev = NULL; 545 kfree(devwrap); 546 goto error; 547 } 548 dev_idx++; 549 } 550 551 #ifdef CONFIG_SSB_DRIVER_MIPS 552 if (bus->mipscore.pflash.present) { 553 err = platform_device_register(&ssb_pflash_dev); 554 if (err) 555 pr_err("Error registering parallel flash\n"); 556 } 557 #endif 558 559 #ifdef CONFIG_SSB_SFLASH 560 if (bus->mipscore.sflash.present) { 561 err = platform_device_register(&ssb_sflash_dev); 562 if (err) 563 pr_err("Error registering serial flash\n"); 564 } 565 #endif 566 567 return 0; 568 error: 569 /* Unwind the already registered devices. */ 570 ssb_devices_unregister(bus); 571 return err; 572 } 573 574 /* Needs ssb_buses_lock() */ 575 static int ssb_attach_queued_buses(void) 576 { 577 struct ssb_bus *bus, *n; 578 int err = 0; 579 int drop_them_all = 0; 580 581 list_for_each_entry_safe(bus, n, &attach_queue, list) { 582 if (drop_them_all) { 583 list_del(&bus->list); 584 continue; 585 } 586 /* Can't init the PCIcore in ssb_bus_register(), as that 587 * is too early in boot for embedded systems 588 * (no udelay() available). So do it here in attach stage. 589 */ 590 err = ssb_bus_powerup(bus, 0); 591 if (err) 592 goto error; 593 ssb_pcicore_init(&bus->pcicore); 594 if (bus->bustype == SSB_BUSTYPE_SSB) 595 ssb_watchdog_register(bus); 596 597 err = ssb_gpio_init(bus); 598 if (err == -ENOTSUPP) 599 ssb_dbg("GPIO driver not activated\n"); 600 else if (err) 601 ssb_dbg("Error registering GPIO driver: %i\n", err); 602 603 ssb_bus_may_powerdown(bus); 604 605 err = ssb_devices_register(bus); 606 error: 607 if (err) { 608 drop_them_all = 1; 609 list_del(&bus->list); 610 continue; 611 } 612 list_move_tail(&bus->list, &buses); 613 } 614 615 return err; 616 } 617 618 static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset) 619 { 620 struct ssb_bus *bus = dev->bus; 621 622 offset += dev->core_index * SSB_CORE_SIZE; 623 return readb(bus->mmio + offset); 624 } 625 626 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset) 627 { 628 struct ssb_bus *bus = dev->bus; 629 630 offset += dev->core_index * SSB_CORE_SIZE; 631 return readw(bus->mmio + offset); 632 } 633 634 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset) 635 { 636 struct ssb_bus *bus = dev->bus; 637 638 offset += dev->core_index * SSB_CORE_SIZE; 639 return readl(bus->mmio + offset); 640 } 641 642 #ifdef CONFIG_SSB_BLOCKIO 643 static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer, 644 size_t count, u16 offset, u8 reg_width) 645 { 646 struct ssb_bus *bus = dev->bus; 647 void __iomem *addr; 648 649 offset += dev->core_index * SSB_CORE_SIZE; 650 addr = bus->mmio + offset; 651 652 switch (reg_width) { 653 case sizeof(u8): { 654 u8 *buf = buffer; 655 656 while (count) { 657 *buf = __raw_readb(addr); 658 buf++; 659 count--; 660 } 661 break; 662 } 663 case sizeof(u16): { 664 __le16 *buf = buffer; 665 666 SSB_WARN_ON(count & 1); 667 while (count) { 668 *buf = (__force __le16)__raw_readw(addr); 669 buf++; 670 count -= 2; 671 } 672 break; 673 } 674 case sizeof(u32): { 675 __le32 *buf = buffer; 676 677 SSB_WARN_ON(count & 3); 678 while (count) { 679 *buf = (__force __le32)__raw_readl(addr); 680 buf++; 681 count -= 4; 682 } 683 break; 684 } 685 default: 686 SSB_WARN_ON(1); 687 } 688 } 689 #endif /* CONFIG_SSB_BLOCKIO */ 690 691 static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value) 692 { 693 struct ssb_bus *bus = dev->bus; 694 695 offset += dev->core_index * SSB_CORE_SIZE; 696 writeb(value, bus->mmio + offset); 697 } 698 699 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value) 700 { 701 struct ssb_bus *bus = dev->bus; 702 703 offset += dev->core_index * SSB_CORE_SIZE; 704 writew(value, bus->mmio + offset); 705 } 706 707 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value) 708 { 709 struct ssb_bus *bus = dev->bus; 710 711 offset += dev->core_index * SSB_CORE_SIZE; 712 writel(value, bus->mmio + offset); 713 } 714 715 #ifdef CONFIG_SSB_BLOCKIO 716 static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer, 717 size_t count, u16 offset, u8 reg_width) 718 { 719 struct ssb_bus *bus = dev->bus; 720 void __iomem *addr; 721 722 offset += dev->core_index * SSB_CORE_SIZE; 723 addr = bus->mmio + offset; 724 725 switch (reg_width) { 726 case sizeof(u8): { 727 const u8 *buf = buffer; 728 729 while (count) { 730 __raw_writeb(*buf, addr); 731 buf++; 732 count--; 733 } 734 break; 735 } 736 case sizeof(u16): { 737 const __le16 *buf = buffer; 738 739 SSB_WARN_ON(count & 1); 740 while (count) { 741 __raw_writew((__force u16)(*buf), addr); 742 buf++; 743 count -= 2; 744 } 745 break; 746 } 747 case sizeof(u32): { 748 const __le32 *buf = buffer; 749 750 SSB_WARN_ON(count & 3); 751 while (count) { 752 __raw_writel((__force u32)(*buf), addr); 753 buf++; 754 count -= 4; 755 } 756 break; 757 } 758 default: 759 SSB_WARN_ON(1); 760 } 761 } 762 #endif /* CONFIG_SSB_BLOCKIO */ 763 764 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */ 765 static const struct ssb_bus_ops ssb_ssb_ops = { 766 .read8 = ssb_ssb_read8, 767 .read16 = ssb_ssb_read16, 768 .read32 = ssb_ssb_read32, 769 .write8 = ssb_ssb_write8, 770 .write16 = ssb_ssb_write16, 771 .write32 = ssb_ssb_write32, 772 #ifdef CONFIG_SSB_BLOCKIO 773 .block_read = ssb_ssb_block_read, 774 .block_write = ssb_ssb_block_write, 775 #endif 776 }; 777 778 static int ssb_fetch_invariants(struct ssb_bus *bus, 779 ssb_invariants_func_t get_invariants) 780 { 781 struct ssb_init_invariants iv; 782 int err; 783 784 memset(&iv, 0, sizeof(iv)); 785 err = get_invariants(bus, &iv); 786 if (err) 787 goto out; 788 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo)); 789 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom)); 790 bus->has_cardbus_slot = iv.has_cardbus_slot; 791 out: 792 return err; 793 } 794 795 static int ssb_bus_register(struct ssb_bus *bus, 796 ssb_invariants_func_t get_invariants, 797 unsigned long baseaddr) 798 { 799 int err; 800 801 spin_lock_init(&bus->bar_lock); 802 INIT_LIST_HEAD(&bus->list); 803 #ifdef CONFIG_SSB_EMBEDDED 804 spin_lock_init(&bus->gpio_lock); 805 #endif 806 807 /* Powerup the bus */ 808 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 809 if (err) 810 goto out; 811 812 /* Init SDIO-host device (if any), before the scan */ 813 err = ssb_sdio_init(bus); 814 if (err) 815 goto err_disable_xtal; 816 817 ssb_buses_lock(); 818 bus->busnumber = next_busnumber; 819 /* Scan for devices (cores) */ 820 err = ssb_bus_scan(bus, baseaddr); 821 if (err) 822 goto err_sdio_exit; 823 824 /* Init PCI-host device (if any) */ 825 err = ssb_pci_init(bus); 826 if (err) 827 goto err_unmap; 828 /* Init PCMCIA-host device (if any) */ 829 err = ssb_pcmcia_init(bus); 830 if (err) 831 goto err_pci_exit; 832 833 /* Initialize basic system devices (if available) */ 834 err = ssb_bus_powerup(bus, 0); 835 if (err) 836 goto err_pcmcia_exit; 837 ssb_chipcommon_init(&bus->chipco); 838 ssb_extif_init(&bus->extif); 839 ssb_mipscore_init(&bus->mipscore); 840 err = ssb_fetch_invariants(bus, get_invariants); 841 if (err) { 842 ssb_bus_may_powerdown(bus); 843 goto err_pcmcia_exit; 844 } 845 ssb_bus_may_powerdown(bus); 846 847 /* Queue it for attach. 848 * See the comment at the ssb_is_early_boot definition. */ 849 list_add_tail(&bus->list, &attach_queue); 850 if (!ssb_is_early_boot) { 851 /* This is not early boot, so we must attach the bus now */ 852 err = ssb_attach_queued_buses(); 853 if (err) 854 goto err_dequeue; 855 } 856 next_busnumber++; 857 ssb_buses_unlock(); 858 859 out: 860 return err; 861 862 err_dequeue: 863 list_del(&bus->list); 864 err_pcmcia_exit: 865 ssb_pcmcia_exit(bus); 866 err_pci_exit: 867 ssb_pci_exit(bus); 868 err_unmap: 869 ssb_iounmap(bus); 870 err_sdio_exit: 871 ssb_sdio_exit(bus); 872 err_disable_xtal: 873 ssb_buses_unlock(); 874 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 875 return err; 876 } 877 878 #ifdef CONFIG_SSB_PCIHOST 879 int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci) 880 { 881 int err; 882 883 bus->bustype = SSB_BUSTYPE_PCI; 884 bus->host_pci = host_pci; 885 bus->ops = &ssb_pci_ops; 886 887 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0); 888 if (!err) { 889 ssb_info("Sonics Silicon Backplane found on PCI device %s\n", 890 dev_name(&host_pci->dev)); 891 } else { 892 ssb_err("Failed to register PCI version of SSB with error %d\n", 893 err); 894 } 895 896 return err; 897 } 898 EXPORT_SYMBOL(ssb_bus_pcibus_register); 899 #endif /* CONFIG_SSB_PCIHOST */ 900 901 #ifdef CONFIG_SSB_PCMCIAHOST 902 int ssb_bus_pcmciabus_register(struct ssb_bus *bus, 903 struct pcmcia_device *pcmcia_dev, 904 unsigned long baseaddr) 905 { 906 int err; 907 908 bus->bustype = SSB_BUSTYPE_PCMCIA; 909 bus->host_pcmcia = pcmcia_dev; 910 bus->ops = &ssb_pcmcia_ops; 911 912 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr); 913 if (!err) { 914 ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n", 915 pcmcia_dev->devname); 916 } 917 918 return err; 919 } 920 EXPORT_SYMBOL(ssb_bus_pcmciabus_register); 921 #endif /* CONFIG_SSB_PCMCIAHOST */ 922 923 #ifdef CONFIG_SSB_SDIOHOST 924 int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func, 925 unsigned int quirks) 926 { 927 int err; 928 929 bus->bustype = SSB_BUSTYPE_SDIO; 930 bus->host_sdio = func; 931 bus->ops = &ssb_sdio_ops; 932 bus->quirks = quirks; 933 934 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0); 935 if (!err) { 936 ssb_info("Sonics Silicon Backplane found on SDIO device %s\n", 937 sdio_func_id(func)); 938 } 939 940 return err; 941 } 942 EXPORT_SYMBOL(ssb_bus_sdiobus_register); 943 #endif /* CONFIG_SSB_PCMCIAHOST */ 944 945 int ssb_bus_ssbbus_register(struct ssb_bus *bus, unsigned long baseaddr, 946 ssb_invariants_func_t get_invariants) 947 { 948 int err; 949 950 bus->bustype = SSB_BUSTYPE_SSB; 951 bus->ops = &ssb_ssb_ops; 952 953 err = ssb_bus_register(bus, get_invariants, baseaddr); 954 if (!err) { 955 ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n", 956 baseaddr); 957 } 958 959 return err; 960 } 961 962 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner) 963 { 964 drv->drv.name = drv->name; 965 drv->drv.bus = &ssb_bustype; 966 drv->drv.owner = owner; 967 968 return driver_register(&drv->drv); 969 } 970 EXPORT_SYMBOL(__ssb_driver_register); 971 972 void ssb_driver_unregister(struct ssb_driver *drv) 973 { 974 driver_unregister(&drv->drv); 975 } 976 EXPORT_SYMBOL(ssb_driver_unregister); 977 978 void ssb_set_devtypedata(struct ssb_device *dev, void *data) 979 { 980 struct ssb_bus *bus = dev->bus; 981 struct ssb_device *ent; 982 int i; 983 984 for (i = 0; i < bus->nr_devices; i++) { 985 ent = &(bus->devices[i]); 986 if (ent->id.vendor != dev->id.vendor) 987 continue; 988 if (ent->id.coreid != dev->id.coreid) 989 continue; 990 991 ent->devtypedata = data; 992 } 993 } 994 EXPORT_SYMBOL(ssb_set_devtypedata); 995 996 static u32 clkfactor_f6_resolve(u32 v) 997 { 998 /* map the magic values */ 999 switch (v) { 1000 case SSB_CHIPCO_CLK_F6_2: 1001 return 2; 1002 case SSB_CHIPCO_CLK_F6_3: 1003 return 3; 1004 case SSB_CHIPCO_CLK_F6_4: 1005 return 4; 1006 case SSB_CHIPCO_CLK_F6_5: 1007 return 5; 1008 case SSB_CHIPCO_CLK_F6_6: 1009 return 6; 1010 case SSB_CHIPCO_CLK_F6_7: 1011 return 7; 1012 } 1013 return 0; 1014 } 1015 1016 /* Calculate the speed the backplane would run at a given set of clockcontrol values */ 1017 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) 1018 { 1019 u32 n1, n2, clock, m1, m2, m3, mc; 1020 1021 n1 = (n & SSB_CHIPCO_CLK_N1); 1022 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT); 1023 1024 switch (plltype) { 1025 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ 1026 if (m & SSB_CHIPCO_CLK_T6_MMASK) 1027 return SSB_CHIPCO_CLK_T6_M1; 1028 return SSB_CHIPCO_CLK_T6_M0; 1029 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 1030 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1031 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 1032 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1033 n1 = clkfactor_f6_resolve(n1); 1034 n2 += SSB_CHIPCO_CLK_F5_BIAS; 1035 break; 1036 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ 1037 n1 += SSB_CHIPCO_CLK_T2_BIAS; 1038 n2 += SSB_CHIPCO_CLK_T2_BIAS; 1039 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7))); 1040 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23))); 1041 break; 1042 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ 1043 return 100000000; 1044 default: 1045 SSB_WARN_ON(1); 1046 } 1047 1048 switch (plltype) { 1049 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1050 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1051 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2; 1052 break; 1053 default: 1054 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2; 1055 } 1056 if (!clock) 1057 return 0; 1058 1059 m1 = (m & SSB_CHIPCO_CLK_M1); 1060 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); 1061 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT); 1062 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT); 1063 1064 switch (plltype) { 1065 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 1066 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1067 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 1068 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1069 m1 = clkfactor_f6_resolve(m1); 1070 if ((plltype == SSB_PLLTYPE_1) || 1071 (plltype == SSB_PLLTYPE_3)) 1072 m2 += SSB_CHIPCO_CLK_F5_BIAS; 1073 else 1074 m2 = clkfactor_f6_resolve(m2); 1075 m3 = clkfactor_f6_resolve(m3); 1076 1077 switch (mc) { 1078 case SSB_CHIPCO_CLK_MC_BYPASS: 1079 return clock; 1080 case SSB_CHIPCO_CLK_MC_M1: 1081 return (clock / m1); 1082 case SSB_CHIPCO_CLK_MC_M1M2: 1083 return (clock / (m1 * m2)); 1084 case SSB_CHIPCO_CLK_MC_M1M2M3: 1085 return (clock / (m1 * m2 * m3)); 1086 case SSB_CHIPCO_CLK_MC_M1M3: 1087 return (clock / (m1 * m3)); 1088 } 1089 return 0; 1090 case SSB_PLLTYPE_2: 1091 m1 += SSB_CHIPCO_CLK_T2_BIAS; 1092 m2 += SSB_CHIPCO_CLK_T2M2_BIAS; 1093 m3 += SSB_CHIPCO_CLK_T2_BIAS; 1094 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7))); 1095 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10))); 1096 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7))); 1097 1098 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP)) 1099 clock /= m1; 1100 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP)) 1101 clock /= m2; 1102 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP)) 1103 clock /= m3; 1104 return clock; 1105 default: 1106 SSB_WARN_ON(1); 1107 } 1108 return 0; 1109 } 1110 1111 /* Get the current speed the backplane is running at */ 1112 u32 ssb_clockspeed(struct ssb_bus *bus) 1113 { 1114 u32 rate; 1115 u32 plltype; 1116 u32 clkctl_n, clkctl_m; 1117 1118 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU) 1119 return ssb_pmu_get_controlclock(&bus->chipco); 1120 1121 if (ssb_extif_available(&bus->extif)) 1122 ssb_extif_get_clockcontrol(&bus->extif, &plltype, 1123 &clkctl_n, &clkctl_m); 1124 else if (bus->chipco.dev) 1125 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype, 1126 &clkctl_n, &clkctl_m); 1127 else 1128 return 0; 1129 1130 if (bus->chip_id == 0x5365) { 1131 rate = 100000000; 1132 } else { 1133 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); 1134 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ 1135 rate /= 2; 1136 } 1137 1138 return rate; 1139 } 1140 EXPORT_SYMBOL(ssb_clockspeed); 1141 1142 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev) 1143 { 1144 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; 1145 1146 /* The REJECT bit seems to be different for Backplane rev 2.3 */ 1147 switch (rev) { 1148 case SSB_IDLOW_SSBREV_22: 1149 case SSB_IDLOW_SSBREV_24: 1150 case SSB_IDLOW_SSBREV_26: 1151 return SSB_TMSLOW_REJECT; 1152 case SSB_IDLOW_SSBREV_23: 1153 return SSB_TMSLOW_REJECT_23; 1154 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ 1155 case SSB_IDLOW_SSBREV_27: /* same here */ 1156 return SSB_TMSLOW_REJECT; /* this is a guess */ 1157 default: 1158 WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); 1159 } 1160 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23); 1161 } 1162 1163 int ssb_device_is_enabled(struct ssb_device *dev) 1164 { 1165 u32 val; 1166 u32 reject; 1167 1168 reject = ssb_tmslow_reject_bitmask(dev); 1169 val = ssb_read32(dev, SSB_TMSLOW); 1170 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject; 1171 1172 return (val == SSB_TMSLOW_CLOCK); 1173 } 1174 EXPORT_SYMBOL(ssb_device_is_enabled); 1175 1176 static void ssb_flush_tmslow(struct ssb_device *dev) 1177 { 1178 /* Make _really_ sure the device has finished the TMSLOW 1179 * register write transaction, as we risk running into 1180 * a machine check exception otherwise. 1181 * Do this by reading the register back to commit the 1182 * PCI write and delay an additional usec for the device 1183 * to react to the change. */ 1184 ssb_read32(dev, SSB_TMSLOW); 1185 udelay(1); 1186 } 1187 1188 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags) 1189 { 1190 u32 val; 1191 1192 ssb_device_disable(dev, core_specific_flags); 1193 ssb_write32(dev, SSB_TMSLOW, 1194 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK | 1195 SSB_TMSLOW_FGC | core_specific_flags); 1196 ssb_flush_tmslow(dev); 1197 1198 /* Clear SERR if set. This is a hw bug workaround. */ 1199 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR) 1200 ssb_write32(dev, SSB_TMSHIGH, 0); 1201 1202 val = ssb_read32(dev, SSB_IMSTATE); 1203 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { 1204 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); 1205 ssb_write32(dev, SSB_IMSTATE, val); 1206 } 1207 1208 ssb_write32(dev, SSB_TMSLOW, 1209 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC | 1210 core_specific_flags); 1211 ssb_flush_tmslow(dev); 1212 1213 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK | 1214 core_specific_flags); 1215 ssb_flush_tmslow(dev); 1216 } 1217 EXPORT_SYMBOL(ssb_device_enable); 1218 1219 /* Wait for bitmask in a register to get set or cleared. 1220 * timeout is in units of ten-microseconds */ 1221 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask, 1222 int timeout, int set) 1223 { 1224 int i; 1225 u32 val; 1226 1227 for (i = 0; i < timeout; i++) { 1228 val = ssb_read32(dev, reg); 1229 if (set) { 1230 if ((val & bitmask) == bitmask) 1231 return 0; 1232 } else { 1233 if (!(val & bitmask)) 1234 return 0; 1235 } 1236 udelay(10); 1237 } 1238 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on " 1239 "register %04X to %s.\n", 1240 bitmask, reg, (set ? "set" : "clear")); 1241 1242 return -ETIMEDOUT; 1243 } 1244 1245 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) 1246 { 1247 u32 reject, val; 1248 1249 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) 1250 return; 1251 1252 reject = ssb_tmslow_reject_bitmask(dev); 1253 1254 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) { 1255 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); 1256 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1); 1257 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); 1258 1259 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1260 val = ssb_read32(dev, SSB_IMSTATE); 1261 val |= SSB_IMSTATE_REJECT; 1262 ssb_write32(dev, SSB_IMSTATE, val); 1263 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000, 1264 0); 1265 } 1266 1267 ssb_write32(dev, SSB_TMSLOW, 1268 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | 1269 reject | SSB_TMSLOW_RESET | 1270 core_specific_flags); 1271 ssb_flush_tmslow(dev); 1272 1273 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1274 val = ssb_read32(dev, SSB_IMSTATE); 1275 val &= ~SSB_IMSTATE_REJECT; 1276 ssb_write32(dev, SSB_IMSTATE, val); 1277 } 1278 } 1279 1280 ssb_write32(dev, SSB_TMSLOW, 1281 reject | SSB_TMSLOW_RESET | 1282 core_specific_flags); 1283 ssb_flush_tmslow(dev); 1284 } 1285 EXPORT_SYMBOL(ssb_device_disable); 1286 1287 /* Some chipsets need routing known for PCIe and 64-bit DMA */ 1288 static bool ssb_dma_translation_special_bit(struct ssb_device *dev) 1289 { 1290 u16 chip_id = dev->bus->chip_id; 1291 1292 if (dev->id.coreid == SSB_DEV_80211) { 1293 return (chip_id == 0x4322 || chip_id == 43221 || 1294 chip_id == 43231 || chip_id == 43222); 1295 } 1296 1297 return 0; 1298 } 1299 1300 u32 ssb_dma_translation(struct ssb_device *dev) 1301 { 1302 switch (dev->bus->bustype) { 1303 case SSB_BUSTYPE_SSB: 1304 return 0; 1305 case SSB_BUSTYPE_PCI: 1306 if (pci_is_pcie(dev->bus->host_pci) && 1307 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) { 1308 return SSB_PCIE_DMA_H32; 1309 } else { 1310 if (ssb_dma_translation_special_bit(dev)) 1311 return SSB_PCIE_DMA_H32; 1312 else 1313 return SSB_PCI_DMA; 1314 } 1315 default: 1316 __ssb_dma_not_implemented(dev); 1317 } 1318 return 0; 1319 } 1320 EXPORT_SYMBOL(ssb_dma_translation); 1321 1322 int ssb_bus_may_powerdown(struct ssb_bus *bus) 1323 { 1324 struct ssb_chipcommon *cc; 1325 int err = 0; 1326 1327 /* On buses where more than one core may be working 1328 * at a time, we must not powerdown stuff if there are 1329 * still cores that may want to run. */ 1330 if (bus->bustype == SSB_BUSTYPE_SSB) 1331 goto out; 1332 1333 cc = &bus->chipco; 1334 1335 if (!cc->dev) 1336 goto out; 1337 if (cc->dev->id.revision < 5) 1338 goto out; 1339 1340 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); 1341 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 1342 if (err) 1343 goto error; 1344 out: 1345 #ifdef CONFIG_SSB_DEBUG 1346 bus->powered_up = 0; 1347 #endif 1348 return err; 1349 error: 1350 ssb_err("Bus powerdown failed\n"); 1351 goto out; 1352 } 1353 EXPORT_SYMBOL(ssb_bus_may_powerdown); 1354 1355 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) 1356 { 1357 int err; 1358 enum ssb_clkmode mode; 1359 1360 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 1361 if (err) 1362 goto error; 1363 1364 #ifdef CONFIG_SSB_DEBUG 1365 bus->powered_up = 1; 1366 #endif 1367 1368 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; 1369 ssb_chipco_set_clockmode(&bus->chipco, mode); 1370 1371 return 0; 1372 error: 1373 ssb_err("Bus powerup failed\n"); 1374 return err; 1375 } 1376 EXPORT_SYMBOL(ssb_bus_powerup); 1377 1378 static void ssb_broadcast_value(struct ssb_device *dev, 1379 u32 address, u32 data) 1380 { 1381 #ifdef CONFIG_SSB_DRIVER_PCICORE 1382 /* This is used for both, PCI and ChipCommon core, so be careful. */ 1383 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); 1384 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); 1385 #endif 1386 1387 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address); 1388 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */ 1389 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data); 1390 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */ 1391 } 1392 1393 void ssb_commit_settings(struct ssb_bus *bus) 1394 { 1395 struct ssb_device *dev; 1396 1397 #ifdef CONFIG_SSB_DRIVER_PCICORE 1398 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; 1399 #else 1400 dev = bus->chipco.dev; 1401 #endif 1402 if (WARN_ON(!dev)) 1403 return; 1404 /* This forces an update of the cached registers. */ 1405 ssb_broadcast_value(dev, 0xFD8, 0); 1406 } 1407 EXPORT_SYMBOL(ssb_commit_settings); 1408 1409 u32 ssb_admatch_base(u32 adm) 1410 { 1411 u32 base = 0; 1412 1413 switch (adm & SSB_ADM_TYPE) { 1414 case SSB_ADM_TYPE0: 1415 base = (adm & SSB_ADM_BASE0); 1416 break; 1417 case SSB_ADM_TYPE1: 1418 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1419 base = (adm & SSB_ADM_BASE1); 1420 break; 1421 case SSB_ADM_TYPE2: 1422 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1423 base = (adm & SSB_ADM_BASE2); 1424 break; 1425 default: 1426 SSB_WARN_ON(1); 1427 } 1428 1429 return base; 1430 } 1431 EXPORT_SYMBOL(ssb_admatch_base); 1432 1433 u32 ssb_admatch_size(u32 adm) 1434 { 1435 u32 size = 0; 1436 1437 switch (adm & SSB_ADM_TYPE) { 1438 case SSB_ADM_TYPE0: 1439 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT); 1440 break; 1441 case SSB_ADM_TYPE1: 1442 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1443 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT); 1444 break; 1445 case SSB_ADM_TYPE2: 1446 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1447 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT); 1448 break; 1449 default: 1450 SSB_WARN_ON(1); 1451 } 1452 size = (1 << (size + 1)); 1453 1454 return size; 1455 } 1456 EXPORT_SYMBOL(ssb_admatch_size); 1457 1458 static int __init ssb_modinit(void) 1459 { 1460 int err; 1461 1462 /* See the comment at the ssb_is_early_boot definition */ 1463 ssb_is_early_boot = 0; 1464 err = bus_register(&ssb_bustype); 1465 if (err) 1466 return err; 1467 1468 /* Maybe we already registered some buses at early boot. 1469 * Check for this and attach them 1470 */ 1471 ssb_buses_lock(); 1472 err = ssb_attach_queued_buses(); 1473 ssb_buses_unlock(); 1474 if (err) { 1475 bus_unregister(&ssb_bustype); 1476 goto out; 1477 } 1478 1479 err = b43_pci_ssb_bridge_init(); 1480 if (err) { 1481 ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n"); 1482 /* don't fail SSB init because of this */ 1483 err = 0; 1484 } 1485 err = ssb_gige_init(); 1486 if (err) { 1487 ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n"); 1488 /* don't fail SSB init because of this */ 1489 err = 0; 1490 } 1491 out: 1492 return err; 1493 } 1494 /* ssb must be initialized after PCI but before the ssb drivers. 1495 * That means we must use some initcall between subsys_initcall 1496 * and device_initcall. */ 1497 fs_initcall(ssb_modinit); 1498 1499 static void __exit ssb_modexit(void) 1500 { 1501 ssb_gige_exit(); 1502 b43_pci_ssb_bridge_exit(); 1503 bus_unregister(&ssb_bustype); 1504 } 1505 module_exit(ssb_modexit) 1506