1 /* 2 * Sonics Silicon Backplane 3 * Subsystem core 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include "ssb_private.h" 12 13 #include <linux/delay.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/ssb/ssb.h> 18 #include <linux/ssb/ssb_regs.h> 19 #include <linux/ssb/ssb_driver_gige.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/pci.h> 22 #include <linux/mmc/sdio_func.h> 23 #include <linux/slab.h> 24 25 #include <pcmcia/cistpl.h> 26 #include <pcmcia/ds.h> 27 28 29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver"); 30 MODULE_LICENSE("GPL"); 31 32 33 /* Temporary list of yet-to-be-attached buses */ 34 static LIST_HEAD(attach_queue); 35 /* List if running buses */ 36 static LIST_HEAD(buses); 37 /* Software ID counter */ 38 static unsigned int next_busnumber; 39 /* buses_mutes locks the two buslists and the next_busnumber. 40 * Don't lock this directly, but use ssb_buses_[un]lock() below. */ 41 static DEFINE_MUTEX(buses_mutex); 42 43 /* There are differences in the codeflow, if the bus is 44 * initialized from early boot, as various needed services 45 * are not available early. This is a mechanism to delay 46 * these initializations to after early boot has finished. 47 * It's also used to avoid mutex locking, as that's not 48 * available and needed early. */ 49 static bool ssb_is_early_boot = 1; 50 51 static void ssb_buses_lock(void); 52 static void ssb_buses_unlock(void); 53 54 55 #ifdef CONFIG_SSB_PCIHOST 56 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev) 57 { 58 struct ssb_bus *bus; 59 60 ssb_buses_lock(); 61 list_for_each_entry(bus, &buses, list) { 62 if (bus->bustype == SSB_BUSTYPE_PCI && 63 bus->host_pci == pdev) 64 goto found; 65 } 66 bus = NULL; 67 found: 68 ssb_buses_unlock(); 69 70 return bus; 71 } 72 #endif /* CONFIG_SSB_PCIHOST */ 73 74 #ifdef CONFIG_SSB_PCMCIAHOST 75 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev) 76 { 77 struct ssb_bus *bus; 78 79 ssb_buses_lock(); 80 list_for_each_entry(bus, &buses, list) { 81 if (bus->bustype == SSB_BUSTYPE_PCMCIA && 82 bus->host_pcmcia == pdev) 83 goto found; 84 } 85 bus = NULL; 86 found: 87 ssb_buses_unlock(); 88 89 return bus; 90 } 91 #endif /* CONFIG_SSB_PCMCIAHOST */ 92 93 #ifdef CONFIG_SSB_SDIOHOST 94 struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func) 95 { 96 struct ssb_bus *bus; 97 98 ssb_buses_lock(); 99 list_for_each_entry(bus, &buses, list) { 100 if (bus->bustype == SSB_BUSTYPE_SDIO && 101 bus->host_sdio == func) 102 goto found; 103 } 104 bus = NULL; 105 found: 106 ssb_buses_unlock(); 107 108 return bus; 109 } 110 #endif /* CONFIG_SSB_SDIOHOST */ 111 112 int ssb_for_each_bus_call(unsigned long data, 113 int (*func)(struct ssb_bus *bus, unsigned long data)) 114 { 115 struct ssb_bus *bus; 116 int res; 117 118 ssb_buses_lock(); 119 list_for_each_entry(bus, &buses, list) { 120 res = func(bus, data); 121 if (res >= 0) { 122 ssb_buses_unlock(); 123 return res; 124 } 125 } 126 ssb_buses_unlock(); 127 128 return -ENODEV; 129 } 130 131 static struct ssb_device *ssb_device_get(struct ssb_device *dev) 132 { 133 if (dev) 134 get_device(dev->dev); 135 return dev; 136 } 137 138 static void ssb_device_put(struct ssb_device *dev) 139 { 140 if (dev) 141 put_device(dev->dev); 142 } 143 144 static int ssb_device_resume(struct device *dev) 145 { 146 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 147 struct ssb_driver *ssb_drv; 148 int err = 0; 149 150 if (dev->driver) { 151 ssb_drv = drv_to_ssb_drv(dev->driver); 152 if (ssb_drv && ssb_drv->resume) 153 err = ssb_drv->resume(ssb_dev); 154 if (err) 155 goto out; 156 } 157 out: 158 return err; 159 } 160 161 static int ssb_device_suspend(struct device *dev, pm_message_t state) 162 { 163 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 164 struct ssb_driver *ssb_drv; 165 int err = 0; 166 167 if (dev->driver) { 168 ssb_drv = drv_to_ssb_drv(dev->driver); 169 if (ssb_drv && ssb_drv->suspend) 170 err = ssb_drv->suspend(ssb_dev, state); 171 if (err) 172 goto out; 173 } 174 out: 175 return err; 176 } 177 178 int ssb_bus_resume(struct ssb_bus *bus) 179 { 180 int err; 181 182 /* Reset HW state information in memory, so that HW is 183 * completely reinitialized. */ 184 bus->mapped_device = NULL; 185 #ifdef CONFIG_SSB_DRIVER_PCICORE 186 bus->pcicore.setup_done = 0; 187 #endif 188 189 err = ssb_bus_powerup(bus, 0); 190 if (err) 191 return err; 192 err = ssb_pcmcia_hardware_setup(bus); 193 if (err) { 194 ssb_bus_may_powerdown(bus); 195 return err; 196 } 197 ssb_chipco_resume(&bus->chipco); 198 ssb_bus_may_powerdown(bus); 199 200 return 0; 201 } 202 EXPORT_SYMBOL(ssb_bus_resume); 203 204 int ssb_bus_suspend(struct ssb_bus *bus) 205 { 206 ssb_chipco_suspend(&bus->chipco); 207 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 208 209 return 0; 210 } 211 EXPORT_SYMBOL(ssb_bus_suspend); 212 213 #ifdef CONFIG_SSB_SPROM 214 /** ssb_devices_freeze - Freeze all devices on the bus. 215 * 216 * After freezing no device driver will be handling a device 217 * on this bus anymore. ssb_devices_thaw() must be called after 218 * a successful freeze to reactivate the devices. 219 * 220 * @bus: The bus. 221 * @ctx: Context structure. Pass this to ssb_devices_thaw(). 222 */ 223 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx) 224 { 225 struct ssb_device *sdev; 226 struct ssb_driver *sdrv; 227 unsigned int i; 228 229 memset(ctx, 0, sizeof(*ctx)); 230 ctx->bus = bus; 231 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen)); 232 233 for (i = 0; i < bus->nr_devices; i++) { 234 sdev = ssb_device_get(&bus->devices[i]); 235 236 if (!sdev->dev || !sdev->dev->driver || 237 !device_is_registered(sdev->dev)) { 238 ssb_device_put(sdev); 239 continue; 240 } 241 sdrv = drv_to_ssb_drv(sdev->dev->driver); 242 if (SSB_WARN_ON(!sdrv->remove)) 243 continue; 244 sdrv->remove(sdev); 245 ctx->device_frozen[i] = 1; 246 } 247 248 return 0; 249 } 250 251 /** ssb_devices_thaw - Unfreeze all devices on the bus. 252 * 253 * This will re-attach the device drivers and re-init the devices. 254 * 255 * @ctx: The context structure from ssb_devices_freeze() 256 */ 257 int ssb_devices_thaw(struct ssb_freeze_context *ctx) 258 { 259 struct ssb_bus *bus = ctx->bus; 260 struct ssb_device *sdev; 261 struct ssb_driver *sdrv; 262 unsigned int i; 263 int err, result = 0; 264 265 for (i = 0; i < bus->nr_devices; i++) { 266 if (!ctx->device_frozen[i]) 267 continue; 268 sdev = &bus->devices[i]; 269 270 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver)) 271 continue; 272 sdrv = drv_to_ssb_drv(sdev->dev->driver); 273 if (SSB_WARN_ON(!sdrv || !sdrv->probe)) 274 continue; 275 276 err = sdrv->probe(sdev, &sdev->id); 277 if (err) { 278 ssb_err("Failed to thaw device %s\n", 279 dev_name(sdev->dev)); 280 result = err; 281 } 282 ssb_device_put(sdev); 283 } 284 285 return result; 286 } 287 #endif /* CONFIG_SSB_SPROM */ 288 289 static void ssb_device_shutdown(struct device *dev) 290 { 291 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 292 struct ssb_driver *ssb_drv; 293 294 if (!dev->driver) 295 return; 296 ssb_drv = drv_to_ssb_drv(dev->driver); 297 if (ssb_drv && ssb_drv->shutdown) 298 ssb_drv->shutdown(ssb_dev); 299 } 300 301 static int ssb_device_remove(struct device *dev) 302 { 303 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 304 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 305 306 if (ssb_drv && ssb_drv->remove) 307 ssb_drv->remove(ssb_dev); 308 ssb_device_put(ssb_dev); 309 310 return 0; 311 } 312 313 static int ssb_device_probe(struct device *dev) 314 { 315 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 316 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 317 int err = 0; 318 319 ssb_device_get(ssb_dev); 320 if (ssb_drv && ssb_drv->probe) 321 err = ssb_drv->probe(ssb_dev, &ssb_dev->id); 322 if (err) 323 ssb_device_put(ssb_dev); 324 325 return err; 326 } 327 328 static int ssb_match_devid(const struct ssb_device_id *tabid, 329 const struct ssb_device_id *devid) 330 { 331 if ((tabid->vendor != devid->vendor) && 332 tabid->vendor != SSB_ANY_VENDOR) 333 return 0; 334 if ((tabid->coreid != devid->coreid) && 335 tabid->coreid != SSB_ANY_ID) 336 return 0; 337 if ((tabid->revision != devid->revision) && 338 tabid->revision != SSB_ANY_REV) 339 return 0; 340 return 1; 341 } 342 343 static int ssb_bus_match(struct device *dev, struct device_driver *drv) 344 { 345 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 346 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv); 347 const struct ssb_device_id *id; 348 349 for (id = ssb_drv->id_table; 350 id->vendor || id->coreid || id->revision; 351 id++) { 352 if (ssb_match_devid(id, &ssb_dev->id)) 353 return 1; /* found */ 354 } 355 356 return 0; 357 } 358 359 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env) 360 { 361 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 362 363 if (!dev) 364 return -ENODEV; 365 366 return add_uevent_var(env, 367 "MODALIAS=ssb:v%04Xid%04Xrev%02X", 368 ssb_dev->id.vendor, ssb_dev->id.coreid, 369 ssb_dev->id.revision); 370 } 371 372 #define ssb_config_attr(attrib, field, format_string) \ 373 static ssize_t \ 374 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \ 375 { \ 376 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \ 377 } 378 379 ssb_config_attr(core_num, core_index, "%u\n") 380 ssb_config_attr(coreid, id.coreid, "0x%04x\n") 381 ssb_config_attr(vendor, id.vendor, "0x%04x\n") 382 ssb_config_attr(revision, id.revision, "%u\n") 383 ssb_config_attr(irq, irq, "%u\n") 384 static ssize_t 385 name_show(struct device *dev, struct device_attribute *attr, char *buf) 386 { 387 return sprintf(buf, "%s\n", 388 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid)); 389 } 390 391 static struct device_attribute ssb_device_attrs[] = { 392 __ATTR_RO(name), 393 __ATTR_RO(core_num), 394 __ATTR_RO(coreid), 395 __ATTR_RO(vendor), 396 __ATTR_RO(revision), 397 __ATTR_RO(irq), 398 __ATTR_NULL, 399 }; 400 401 static struct bus_type ssb_bustype = { 402 .name = "ssb", 403 .match = ssb_bus_match, 404 .probe = ssb_device_probe, 405 .remove = ssb_device_remove, 406 .shutdown = ssb_device_shutdown, 407 .suspend = ssb_device_suspend, 408 .resume = ssb_device_resume, 409 .uevent = ssb_device_uevent, 410 .dev_attrs = ssb_device_attrs, 411 }; 412 413 static void ssb_buses_lock(void) 414 { 415 /* See the comment at the ssb_is_early_boot definition */ 416 if (!ssb_is_early_boot) 417 mutex_lock(&buses_mutex); 418 } 419 420 static void ssb_buses_unlock(void) 421 { 422 /* See the comment at the ssb_is_early_boot definition */ 423 if (!ssb_is_early_boot) 424 mutex_unlock(&buses_mutex); 425 } 426 427 static void ssb_devices_unregister(struct ssb_bus *bus) 428 { 429 struct ssb_device *sdev; 430 int i; 431 432 for (i = bus->nr_devices - 1; i >= 0; i--) { 433 sdev = &(bus->devices[i]); 434 if (sdev->dev) 435 device_unregister(sdev->dev); 436 } 437 438 #ifdef CONFIG_SSB_EMBEDDED 439 if (bus->bustype == SSB_BUSTYPE_SSB) 440 platform_device_unregister(bus->watchdog); 441 #endif 442 } 443 444 void ssb_bus_unregister(struct ssb_bus *bus) 445 { 446 int err; 447 448 err = ssb_gpio_unregister(bus); 449 if (err == -EBUSY) 450 ssb_dbg("Some GPIOs are still in use\n"); 451 else if (err) 452 ssb_dbg("Can not unregister GPIO driver: %i\n", err); 453 454 ssb_buses_lock(); 455 ssb_devices_unregister(bus); 456 list_del(&bus->list); 457 ssb_buses_unlock(); 458 459 ssb_pcmcia_exit(bus); 460 ssb_pci_exit(bus); 461 ssb_iounmap(bus); 462 } 463 EXPORT_SYMBOL(ssb_bus_unregister); 464 465 static void ssb_release_dev(struct device *dev) 466 { 467 struct __ssb_dev_wrapper *devwrap; 468 469 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev); 470 kfree(devwrap); 471 } 472 473 static int ssb_devices_register(struct ssb_bus *bus) 474 { 475 struct ssb_device *sdev; 476 struct device *dev; 477 struct __ssb_dev_wrapper *devwrap; 478 int i, err = 0; 479 int dev_idx = 0; 480 481 for (i = 0; i < bus->nr_devices; i++) { 482 sdev = &(bus->devices[i]); 483 484 /* We don't register SSB-system devices to the kernel, 485 * as the drivers for them are built into SSB. */ 486 switch (sdev->id.coreid) { 487 case SSB_DEV_CHIPCOMMON: 488 case SSB_DEV_PCI: 489 case SSB_DEV_PCIE: 490 case SSB_DEV_PCMCIA: 491 case SSB_DEV_MIPS: 492 case SSB_DEV_MIPS_3302: 493 case SSB_DEV_EXTIF: 494 continue; 495 } 496 497 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL); 498 if (!devwrap) { 499 ssb_err("Could not allocate device\n"); 500 err = -ENOMEM; 501 goto error; 502 } 503 dev = &devwrap->dev; 504 devwrap->sdev = sdev; 505 506 dev->release = ssb_release_dev; 507 dev->bus = &ssb_bustype; 508 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx); 509 510 switch (bus->bustype) { 511 case SSB_BUSTYPE_PCI: 512 #ifdef CONFIG_SSB_PCIHOST 513 sdev->irq = bus->host_pci->irq; 514 dev->parent = &bus->host_pci->dev; 515 sdev->dma_dev = dev->parent; 516 #endif 517 break; 518 case SSB_BUSTYPE_PCMCIA: 519 #ifdef CONFIG_SSB_PCMCIAHOST 520 sdev->irq = bus->host_pcmcia->irq; 521 dev->parent = &bus->host_pcmcia->dev; 522 #endif 523 break; 524 case SSB_BUSTYPE_SDIO: 525 #ifdef CONFIG_SSB_SDIOHOST 526 dev->parent = &bus->host_sdio->dev; 527 #endif 528 break; 529 case SSB_BUSTYPE_SSB: 530 dev->dma_mask = &dev->coherent_dma_mask; 531 sdev->dma_dev = dev; 532 break; 533 } 534 535 sdev->dev = dev; 536 err = device_register(dev); 537 if (err) { 538 ssb_err("Could not register %s\n", dev_name(dev)); 539 /* Set dev to NULL to not unregister 540 * dev on error unwinding. */ 541 sdev->dev = NULL; 542 kfree(devwrap); 543 goto error; 544 } 545 dev_idx++; 546 } 547 548 #ifdef CONFIG_SSB_DRIVER_MIPS 549 if (bus->mipscore.pflash.present) { 550 err = platform_device_register(&ssb_pflash_dev); 551 if (err) 552 pr_err("Error registering parallel flash\n"); 553 } 554 #endif 555 556 return 0; 557 error: 558 /* Unwind the already registered devices. */ 559 ssb_devices_unregister(bus); 560 return err; 561 } 562 563 /* Needs ssb_buses_lock() */ 564 static int ssb_attach_queued_buses(void) 565 { 566 struct ssb_bus *bus, *n; 567 int err = 0; 568 int drop_them_all = 0; 569 570 list_for_each_entry_safe(bus, n, &attach_queue, list) { 571 if (drop_them_all) { 572 list_del(&bus->list); 573 continue; 574 } 575 /* Can't init the PCIcore in ssb_bus_register(), as that 576 * is too early in boot for embedded systems 577 * (no udelay() available). So do it here in attach stage. 578 */ 579 err = ssb_bus_powerup(bus, 0); 580 if (err) 581 goto error; 582 ssb_pcicore_init(&bus->pcicore); 583 if (bus->bustype == SSB_BUSTYPE_SSB) 584 ssb_watchdog_register(bus); 585 ssb_bus_may_powerdown(bus); 586 587 err = ssb_devices_register(bus); 588 error: 589 if (err) { 590 drop_them_all = 1; 591 list_del(&bus->list); 592 continue; 593 } 594 list_move_tail(&bus->list, &buses); 595 } 596 597 return err; 598 } 599 600 static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset) 601 { 602 struct ssb_bus *bus = dev->bus; 603 604 offset += dev->core_index * SSB_CORE_SIZE; 605 return readb(bus->mmio + offset); 606 } 607 608 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset) 609 { 610 struct ssb_bus *bus = dev->bus; 611 612 offset += dev->core_index * SSB_CORE_SIZE; 613 return readw(bus->mmio + offset); 614 } 615 616 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset) 617 { 618 struct ssb_bus *bus = dev->bus; 619 620 offset += dev->core_index * SSB_CORE_SIZE; 621 return readl(bus->mmio + offset); 622 } 623 624 #ifdef CONFIG_SSB_BLOCKIO 625 static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer, 626 size_t count, u16 offset, u8 reg_width) 627 { 628 struct ssb_bus *bus = dev->bus; 629 void __iomem *addr; 630 631 offset += dev->core_index * SSB_CORE_SIZE; 632 addr = bus->mmio + offset; 633 634 switch (reg_width) { 635 case sizeof(u8): { 636 u8 *buf = buffer; 637 638 while (count) { 639 *buf = __raw_readb(addr); 640 buf++; 641 count--; 642 } 643 break; 644 } 645 case sizeof(u16): { 646 __le16 *buf = buffer; 647 648 SSB_WARN_ON(count & 1); 649 while (count) { 650 *buf = (__force __le16)__raw_readw(addr); 651 buf++; 652 count -= 2; 653 } 654 break; 655 } 656 case sizeof(u32): { 657 __le32 *buf = buffer; 658 659 SSB_WARN_ON(count & 3); 660 while (count) { 661 *buf = (__force __le32)__raw_readl(addr); 662 buf++; 663 count -= 4; 664 } 665 break; 666 } 667 default: 668 SSB_WARN_ON(1); 669 } 670 } 671 #endif /* CONFIG_SSB_BLOCKIO */ 672 673 static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value) 674 { 675 struct ssb_bus *bus = dev->bus; 676 677 offset += dev->core_index * SSB_CORE_SIZE; 678 writeb(value, bus->mmio + offset); 679 } 680 681 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value) 682 { 683 struct ssb_bus *bus = dev->bus; 684 685 offset += dev->core_index * SSB_CORE_SIZE; 686 writew(value, bus->mmio + offset); 687 } 688 689 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value) 690 { 691 struct ssb_bus *bus = dev->bus; 692 693 offset += dev->core_index * SSB_CORE_SIZE; 694 writel(value, bus->mmio + offset); 695 } 696 697 #ifdef CONFIG_SSB_BLOCKIO 698 static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer, 699 size_t count, u16 offset, u8 reg_width) 700 { 701 struct ssb_bus *bus = dev->bus; 702 void __iomem *addr; 703 704 offset += dev->core_index * SSB_CORE_SIZE; 705 addr = bus->mmio + offset; 706 707 switch (reg_width) { 708 case sizeof(u8): { 709 const u8 *buf = buffer; 710 711 while (count) { 712 __raw_writeb(*buf, addr); 713 buf++; 714 count--; 715 } 716 break; 717 } 718 case sizeof(u16): { 719 const __le16 *buf = buffer; 720 721 SSB_WARN_ON(count & 1); 722 while (count) { 723 __raw_writew((__force u16)(*buf), addr); 724 buf++; 725 count -= 2; 726 } 727 break; 728 } 729 case sizeof(u32): { 730 const __le32 *buf = buffer; 731 732 SSB_WARN_ON(count & 3); 733 while (count) { 734 __raw_writel((__force u32)(*buf), addr); 735 buf++; 736 count -= 4; 737 } 738 break; 739 } 740 default: 741 SSB_WARN_ON(1); 742 } 743 } 744 #endif /* CONFIG_SSB_BLOCKIO */ 745 746 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */ 747 static const struct ssb_bus_ops ssb_ssb_ops = { 748 .read8 = ssb_ssb_read8, 749 .read16 = ssb_ssb_read16, 750 .read32 = ssb_ssb_read32, 751 .write8 = ssb_ssb_write8, 752 .write16 = ssb_ssb_write16, 753 .write32 = ssb_ssb_write32, 754 #ifdef CONFIG_SSB_BLOCKIO 755 .block_read = ssb_ssb_block_read, 756 .block_write = ssb_ssb_block_write, 757 #endif 758 }; 759 760 static int ssb_fetch_invariants(struct ssb_bus *bus, 761 ssb_invariants_func_t get_invariants) 762 { 763 struct ssb_init_invariants iv; 764 int err; 765 766 memset(&iv, 0, sizeof(iv)); 767 err = get_invariants(bus, &iv); 768 if (err) 769 goto out; 770 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo)); 771 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom)); 772 bus->has_cardbus_slot = iv.has_cardbus_slot; 773 out: 774 return err; 775 } 776 777 static int ssb_bus_register(struct ssb_bus *bus, 778 ssb_invariants_func_t get_invariants, 779 unsigned long baseaddr) 780 { 781 int err; 782 783 spin_lock_init(&bus->bar_lock); 784 INIT_LIST_HEAD(&bus->list); 785 #ifdef CONFIG_SSB_EMBEDDED 786 spin_lock_init(&bus->gpio_lock); 787 #endif 788 789 /* Powerup the bus */ 790 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 791 if (err) 792 goto out; 793 794 /* Init SDIO-host device (if any), before the scan */ 795 err = ssb_sdio_init(bus); 796 if (err) 797 goto err_disable_xtal; 798 799 ssb_buses_lock(); 800 bus->busnumber = next_busnumber; 801 /* Scan for devices (cores) */ 802 err = ssb_bus_scan(bus, baseaddr); 803 if (err) 804 goto err_sdio_exit; 805 806 /* Init PCI-host device (if any) */ 807 err = ssb_pci_init(bus); 808 if (err) 809 goto err_unmap; 810 /* Init PCMCIA-host device (if any) */ 811 err = ssb_pcmcia_init(bus); 812 if (err) 813 goto err_pci_exit; 814 815 /* Initialize basic system devices (if available) */ 816 err = ssb_bus_powerup(bus, 0); 817 if (err) 818 goto err_pcmcia_exit; 819 ssb_chipcommon_init(&bus->chipco); 820 ssb_extif_init(&bus->extif); 821 ssb_mipscore_init(&bus->mipscore); 822 err = ssb_gpio_init(bus); 823 if (err == -ENOTSUPP) 824 ssb_dbg("GPIO driver not activated\n"); 825 else if (err) 826 ssb_dbg("Error registering GPIO driver: %i\n", err); 827 err = ssb_fetch_invariants(bus, get_invariants); 828 if (err) { 829 ssb_bus_may_powerdown(bus); 830 goto err_pcmcia_exit; 831 } 832 ssb_bus_may_powerdown(bus); 833 834 /* Queue it for attach. 835 * See the comment at the ssb_is_early_boot definition. */ 836 list_add_tail(&bus->list, &attach_queue); 837 if (!ssb_is_early_boot) { 838 /* This is not early boot, so we must attach the bus now */ 839 err = ssb_attach_queued_buses(); 840 if (err) 841 goto err_dequeue; 842 } 843 next_busnumber++; 844 ssb_buses_unlock(); 845 846 out: 847 return err; 848 849 err_dequeue: 850 list_del(&bus->list); 851 err_pcmcia_exit: 852 ssb_pcmcia_exit(bus); 853 err_pci_exit: 854 ssb_pci_exit(bus); 855 err_unmap: 856 ssb_iounmap(bus); 857 err_sdio_exit: 858 ssb_sdio_exit(bus); 859 err_disable_xtal: 860 ssb_buses_unlock(); 861 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 862 return err; 863 } 864 865 #ifdef CONFIG_SSB_PCIHOST 866 int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci) 867 { 868 int err; 869 870 bus->bustype = SSB_BUSTYPE_PCI; 871 bus->host_pci = host_pci; 872 bus->ops = &ssb_pci_ops; 873 874 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0); 875 if (!err) { 876 ssb_info("Sonics Silicon Backplane found on PCI device %s\n", 877 dev_name(&host_pci->dev)); 878 } else { 879 ssb_err("Failed to register PCI version of SSB with error %d\n", 880 err); 881 } 882 883 return err; 884 } 885 EXPORT_SYMBOL(ssb_bus_pcibus_register); 886 #endif /* CONFIG_SSB_PCIHOST */ 887 888 #ifdef CONFIG_SSB_PCMCIAHOST 889 int ssb_bus_pcmciabus_register(struct ssb_bus *bus, 890 struct pcmcia_device *pcmcia_dev, 891 unsigned long baseaddr) 892 { 893 int err; 894 895 bus->bustype = SSB_BUSTYPE_PCMCIA; 896 bus->host_pcmcia = pcmcia_dev; 897 bus->ops = &ssb_pcmcia_ops; 898 899 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr); 900 if (!err) { 901 ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n", 902 pcmcia_dev->devname); 903 } 904 905 return err; 906 } 907 EXPORT_SYMBOL(ssb_bus_pcmciabus_register); 908 #endif /* CONFIG_SSB_PCMCIAHOST */ 909 910 #ifdef CONFIG_SSB_SDIOHOST 911 int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func, 912 unsigned int quirks) 913 { 914 int err; 915 916 bus->bustype = SSB_BUSTYPE_SDIO; 917 bus->host_sdio = func; 918 bus->ops = &ssb_sdio_ops; 919 bus->quirks = quirks; 920 921 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0); 922 if (!err) { 923 ssb_info("Sonics Silicon Backplane found on SDIO device %s\n", 924 sdio_func_id(func)); 925 } 926 927 return err; 928 } 929 EXPORT_SYMBOL(ssb_bus_sdiobus_register); 930 #endif /* CONFIG_SSB_PCMCIAHOST */ 931 932 int ssb_bus_ssbbus_register(struct ssb_bus *bus, unsigned long baseaddr, 933 ssb_invariants_func_t get_invariants) 934 { 935 int err; 936 937 bus->bustype = SSB_BUSTYPE_SSB; 938 bus->ops = &ssb_ssb_ops; 939 940 err = ssb_bus_register(bus, get_invariants, baseaddr); 941 if (!err) { 942 ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n", 943 baseaddr); 944 } 945 946 return err; 947 } 948 949 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner) 950 { 951 drv->drv.name = drv->name; 952 drv->drv.bus = &ssb_bustype; 953 drv->drv.owner = owner; 954 955 return driver_register(&drv->drv); 956 } 957 EXPORT_SYMBOL(__ssb_driver_register); 958 959 void ssb_driver_unregister(struct ssb_driver *drv) 960 { 961 driver_unregister(&drv->drv); 962 } 963 EXPORT_SYMBOL(ssb_driver_unregister); 964 965 void ssb_set_devtypedata(struct ssb_device *dev, void *data) 966 { 967 struct ssb_bus *bus = dev->bus; 968 struct ssb_device *ent; 969 int i; 970 971 for (i = 0; i < bus->nr_devices; i++) { 972 ent = &(bus->devices[i]); 973 if (ent->id.vendor != dev->id.vendor) 974 continue; 975 if (ent->id.coreid != dev->id.coreid) 976 continue; 977 978 ent->devtypedata = data; 979 } 980 } 981 EXPORT_SYMBOL(ssb_set_devtypedata); 982 983 static u32 clkfactor_f6_resolve(u32 v) 984 { 985 /* map the magic values */ 986 switch (v) { 987 case SSB_CHIPCO_CLK_F6_2: 988 return 2; 989 case SSB_CHIPCO_CLK_F6_3: 990 return 3; 991 case SSB_CHIPCO_CLK_F6_4: 992 return 4; 993 case SSB_CHIPCO_CLK_F6_5: 994 return 5; 995 case SSB_CHIPCO_CLK_F6_6: 996 return 6; 997 case SSB_CHIPCO_CLK_F6_7: 998 return 7; 999 } 1000 return 0; 1001 } 1002 1003 /* Calculate the speed the backplane would run at a given set of clockcontrol values */ 1004 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) 1005 { 1006 u32 n1, n2, clock, m1, m2, m3, mc; 1007 1008 n1 = (n & SSB_CHIPCO_CLK_N1); 1009 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT); 1010 1011 switch (plltype) { 1012 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ 1013 if (m & SSB_CHIPCO_CLK_T6_MMASK) 1014 return SSB_CHIPCO_CLK_T6_M1; 1015 return SSB_CHIPCO_CLK_T6_M0; 1016 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 1017 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1018 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 1019 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1020 n1 = clkfactor_f6_resolve(n1); 1021 n2 += SSB_CHIPCO_CLK_F5_BIAS; 1022 break; 1023 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ 1024 n1 += SSB_CHIPCO_CLK_T2_BIAS; 1025 n2 += SSB_CHIPCO_CLK_T2_BIAS; 1026 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7))); 1027 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23))); 1028 break; 1029 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ 1030 return 100000000; 1031 default: 1032 SSB_WARN_ON(1); 1033 } 1034 1035 switch (plltype) { 1036 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1037 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1038 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2; 1039 break; 1040 default: 1041 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2; 1042 } 1043 if (!clock) 1044 return 0; 1045 1046 m1 = (m & SSB_CHIPCO_CLK_M1); 1047 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); 1048 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT); 1049 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT); 1050 1051 switch (plltype) { 1052 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 1053 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1054 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 1055 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1056 m1 = clkfactor_f6_resolve(m1); 1057 if ((plltype == SSB_PLLTYPE_1) || 1058 (plltype == SSB_PLLTYPE_3)) 1059 m2 += SSB_CHIPCO_CLK_F5_BIAS; 1060 else 1061 m2 = clkfactor_f6_resolve(m2); 1062 m3 = clkfactor_f6_resolve(m3); 1063 1064 switch (mc) { 1065 case SSB_CHIPCO_CLK_MC_BYPASS: 1066 return clock; 1067 case SSB_CHIPCO_CLK_MC_M1: 1068 return (clock / m1); 1069 case SSB_CHIPCO_CLK_MC_M1M2: 1070 return (clock / (m1 * m2)); 1071 case SSB_CHIPCO_CLK_MC_M1M2M3: 1072 return (clock / (m1 * m2 * m3)); 1073 case SSB_CHIPCO_CLK_MC_M1M3: 1074 return (clock / (m1 * m3)); 1075 } 1076 return 0; 1077 case SSB_PLLTYPE_2: 1078 m1 += SSB_CHIPCO_CLK_T2_BIAS; 1079 m2 += SSB_CHIPCO_CLK_T2M2_BIAS; 1080 m3 += SSB_CHIPCO_CLK_T2_BIAS; 1081 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7))); 1082 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10))); 1083 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7))); 1084 1085 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP)) 1086 clock /= m1; 1087 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP)) 1088 clock /= m2; 1089 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP)) 1090 clock /= m3; 1091 return clock; 1092 default: 1093 SSB_WARN_ON(1); 1094 } 1095 return 0; 1096 } 1097 1098 /* Get the current speed the backplane is running at */ 1099 u32 ssb_clockspeed(struct ssb_bus *bus) 1100 { 1101 u32 rate; 1102 u32 plltype; 1103 u32 clkctl_n, clkctl_m; 1104 1105 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU) 1106 return ssb_pmu_get_controlclock(&bus->chipco); 1107 1108 if (ssb_extif_available(&bus->extif)) 1109 ssb_extif_get_clockcontrol(&bus->extif, &plltype, 1110 &clkctl_n, &clkctl_m); 1111 else if (bus->chipco.dev) 1112 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype, 1113 &clkctl_n, &clkctl_m); 1114 else 1115 return 0; 1116 1117 if (bus->chip_id == 0x5365) { 1118 rate = 100000000; 1119 } else { 1120 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); 1121 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ 1122 rate /= 2; 1123 } 1124 1125 return rate; 1126 } 1127 EXPORT_SYMBOL(ssb_clockspeed); 1128 1129 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev) 1130 { 1131 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; 1132 1133 /* The REJECT bit seems to be different for Backplane rev 2.3 */ 1134 switch (rev) { 1135 case SSB_IDLOW_SSBREV_22: 1136 case SSB_IDLOW_SSBREV_24: 1137 case SSB_IDLOW_SSBREV_26: 1138 return SSB_TMSLOW_REJECT; 1139 case SSB_IDLOW_SSBREV_23: 1140 return SSB_TMSLOW_REJECT_23; 1141 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ 1142 case SSB_IDLOW_SSBREV_27: /* same here */ 1143 return SSB_TMSLOW_REJECT; /* this is a guess */ 1144 default: 1145 WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); 1146 } 1147 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23); 1148 } 1149 1150 int ssb_device_is_enabled(struct ssb_device *dev) 1151 { 1152 u32 val; 1153 u32 reject; 1154 1155 reject = ssb_tmslow_reject_bitmask(dev); 1156 val = ssb_read32(dev, SSB_TMSLOW); 1157 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject; 1158 1159 return (val == SSB_TMSLOW_CLOCK); 1160 } 1161 EXPORT_SYMBOL(ssb_device_is_enabled); 1162 1163 static void ssb_flush_tmslow(struct ssb_device *dev) 1164 { 1165 /* Make _really_ sure the device has finished the TMSLOW 1166 * register write transaction, as we risk running into 1167 * a machine check exception otherwise. 1168 * Do this by reading the register back to commit the 1169 * PCI write and delay an additional usec for the device 1170 * to react to the change. */ 1171 ssb_read32(dev, SSB_TMSLOW); 1172 udelay(1); 1173 } 1174 1175 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags) 1176 { 1177 u32 val; 1178 1179 ssb_device_disable(dev, core_specific_flags); 1180 ssb_write32(dev, SSB_TMSLOW, 1181 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK | 1182 SSB_TMSLOW_FGC | core_specific_flags); 1183 ssb_flush_tmslow(dev); 1184 1185 /* Clear SERR if set. This is a hw bug workaround. */ 1186 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR) 1187 ssb_write32(dev, SSB_TMSHIGH, 0); 1188 1189 val = ssb_read32(dev, SSB_IMSTATE); 1190 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { 1191 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); 1192 ssb_write32(dev, SSB_IMSTATE, val); 1193 } 1194 1195 ssb_write32(dev, SSB_TMSLOW, 1196 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC | 1197 core_specific_flags); 1198 ssb_flush_tmslow(dev); 1199 1200 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK | 1201 core_specific_flags); 1202 ssb_flush_tmslow(dev); 1203 } 1204 EXPORT_SYMBOL(ssb_device_enable); 1205 1206 /* Wait for bitmask in a register to get set or cleared. 1207 * timeout is in units of ten-microseconds */ 1208 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask, 1209 int timeout, int set) 1210 { 1211 int i; 1212 u32 val; 1213 1214 for (i = 0; i < timeout; i++) { 1215 val = ssb_read32(dev, reg); 1216 if (set) { 1217 if ((val & bitmask) == bitmask) 1218 return 0; 1219 } else { 1220 if (!(val & bitmask)) 1221 return 0; 1222 } 1223 udelay(10); 1224 } 1225 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on " 1226 "register %04X to %s.\n", 1227 bitmask, reg, (set ? "set" : "clear")); 1228 1229 return -ETIMEDOUT; 1230 } 1231 1232 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) 1233 { 1234 u32 reject, val; 1235 1236 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) 1237 return; 1238 1239 reject = ssb_tmslow_reject_bitmask(dev); 1240 1241 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) { 1242 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); 1243 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1); 1244 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); 1245 1246 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1247 val = ssb_read32(dev, SSB_IMSTATE); 1248 val |= SSB_IMSTATE_REJECT; 1249 ssb_write32(dev, SSB_IMSTATE, val); 1250 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000, 1251 0); 1252 } 1253 1254 ssb_write32(dev, SSB_TMSLOW, 1255 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | 1256 reject | SSB_TMSLOW_RESET | 1257 core_specific_flags); 1258 ssb_flush_tmslow(dev); 1259 1260 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1261 val = ssb_read32(dev, SSB_IMSTATE); 1262 val &= ~SSB_IMSTATE_REJECT; 1263 ssb_write32(dev, SSB_IMSTATE, val); 1264 } 1265 } 1266 1267 ssb_write32(dev, SSB_TMSLOW, 1268 reject | SSB_TMSLOW_RESET | 1269 core_specific_flags); 1270 ssb_flush_tmslow(dev); 1271 } 1272 EXPORT_SYMBOL(ssb_device_disable); 1273 1274 /* Some chipsets need routing known for PCIe and 64-bit DMA */ 1275 static bool ssb_dma_translation_special_bit(struct ssb_device *dev) 1276 { 1277 u16 chip_id = dev->bus->chip_id; 1278 1279 if (dev->id.coreid == SSB_DEV_80211) { 1280 return (chip_id == 0x4322 || chip_id == 43221 || 1281 chip_id == 43231 || chip_id == 43222); 1282 } 1283 1284 return 0; 1285 } 1286 1287 u32 ssb_dma_translation(struct ssb_device *dev) 1288 { 1289 switch (dev->bus->bustype) { 1290 case SSB_BUSTYPE_SSB: 1291 return 0; 1292 case SSB_BUSTYPE_PCI: 1293 if (pci_is_pcie(dev->bus->host_pci) && 1294 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) { 1295 return SSB_PCIE_DMA_H32; 1296 } else { 1297 if (ssb_dma_translation_special_bit(dev)) 1298 return SSB_PCIE_DMA_H32; 1299 else 1300 return SSB_PCI_DMA; 1301 } 1302 default: 1303 __ssb_dma_not_implemented(dev); 1304 } 1305 return 0; 1306 } 1307 EXPORT_SYMBOL(ssb_dma_translation); 1308 1309 int ssb_bus_may_powerdown(struct ssb_bus *bus) 1310 { 1311 struct ssb_chipcommon *cc; 1312 int err = 0; 1313 1314 /* On buses where more than one core may be working 1315 * at a time, we must not powerdown stuff if there are 1316 * still cores that may want to run. */ 1317 if (bus->bustype == SSB_BUSTYPE_SSB) 1318 goto out; 1319 1320 cc = &bus->chipco; 1321 1322 if (!cc->dev) 1323 goto out; 1324 if (cc->dev->id.revision < 5) 1325 goto out; 1326 1327 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); 1328 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 1329 if (err) 1330 goto error; 1331 out: 1332 #ifdef CONFIG_SSB_DEBUG 1333 bus->powered_up = 0; 1334 #endif 1335 return err; 1336 error: 1337 ssb_err("Bus powerdown failed\n"); 1338 goto out; 1339 } 1340 EXPORT_SYMBOL(ssb_bus_may_powerdown); 1341 1342 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) 1343 { 1344 int err; 1345 enum ssb_clkmode mode; 1346 1347 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 1348 if (err) 1349 goto error; 1350 1351 #ifdef CONFIG_SSB_DEBUG 1352 bus->powered_up = 1; 1353 #endif 1354 1355 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; 1356 ssb_chipco_set_clockmode(&bus->chipco, mode); 1357 1358 return 0; 1359 error: 1360 ssb_err("Bus powerup failed\n"); 1361 return err; 1362 } 1363 EXPORT_SYMBOL(ssb_bus_powerup); 1364 1365 static void ssb_broadcast_value(struct ssb_device *dev, 1366 u32 address, u32 data) 1367 { 1368 #ifdef CONFIG_SSB_DRIVER_PCICORE 1369 /* This is used for both, PCI and ChipCommon core, so be careful. */ 1370 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); 1371 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); 1372 #endif 1373 1374 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address); 1375 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */ 1376 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data); 1377 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */ 1378 } 1379 1380 void ssb_commit_settings(struct ssb_bus *bus) 1381 { 1382 struct ssb_device *dev; 1383 1384 #ifdef CONFIG_SSB_DRIVER_PCICORE 1385 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; 1386 #else 1387 dev = bus->chipco.dev; 1388 #endif 1389 if (WARN_ON(!dev)) 1390 return; 1391 /* This forces an update of the cached registers. */ 1392 ssb_broadcast_value(dev, 0xFD8, 0); 1393 } 1394 EXPORT_SYMBOL(ssb_commit_settings); 1395 1396 u32 ssb_admatch_base(u32 adm) 1397 { 1398 u32 base = 0; 1399 1400 switch (adm & SSB_ADM_TYPE) { 1401 case SSB_ADM_TYPE0: 1402 base = (adm & SSB_ADM_BASE0); 1403 break; 1404 case SSB_ADM_TYPE1: 1405 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1406 base = (adm & SSB_ADM_BASE1); 1407 break; 1408 case SSB_ADM_TYPE2: 1409 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1410 base = (adm & SSB_ADM_BASE2); 1411 break; 1412 default: 1413 SSB_WARN_ON(1); 1414 } 1415 1416 return base; 1417 } 1418 EXPORT_SYMBOL(ssb_admatch_base); 1419 1420 u32 ssb_admatch_size(u32 adm) 1421 { 1422 u32 size = 0; 1423 1424 switch (adm & SSB_ADM_TYPE) { 1425 case SSB_ADM_TYPE0: 1426 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT); 1427 break; 1428 case SSB_ADM_TYPE1: 1429 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1430 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT); 1431 break; 1432 case SSB_ADM_TYPE2: 1433 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1434 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT); 1435 break; 1436 default: 1437 SSB_WARN_ON(1); 1438 } 1439 size = (1 << (size + 1)); 1440 1441 return size; 1442 } 1443 EXPORT_SYMBOL(ssb_admatch_size); 1444 1445 static int __init ssb_modinit(void) 1446 { 1447 int err; 1448 1449 /* See the comment at the ssb_is_early_boot definition */ 1450 ssb_is_early_boot = 0; 1451 err = bus_register(&ssb_bustype); 1452 if (err) 1453 return err; 1454 1455 /* Maybe we already registered some buses at early boot. 1456 * Check for this and attach them 1457 */ 1458 ssb_buses_lock(); 1459 err = ssb_attach_queued_buses(); 1460 ssb_buses_unlock(); 1461 if (err) { 1462 bus_unregister(&ssb_bustype); 1463 goto out; 1464 } 1465 1466 err = b43_pci_ssb_bridge_init(); 1467 if (err) { 1468 ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n"); 1469 /* don't fail SSB init because of this */ 1470 err = 0; 1471 } 1472 err = ssb_gige_init(); 1473 if (err) { 1474 ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n"); 1475 /* don't fail SSB init because of this */ 1476 err = 0; 1477 } 1478 out: 1479 return err; 1480 } 1481 /* ssb must be initialized after PCI but before the ssb drivers. 1482 * That means we must use some initcall between subsys_initcall 1483 * and device_initcall. */ 1484 fs_initcall(ssb_modinit); 1485 1486 static void __exit ssb_modexit(void) 1487 { 1488 ssb_gige_exit(); 1489 b43_pci_ssb_bridge_exit(); 1490 bus_unregister(&ssb_bustype); 1491 } 1492 module_exit(ssb_modexit) 1493