1 /* 2 * Sonics Silicon Backplane 3 * Subsystem core 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include "ssb_private.h" 12 13 #include <linux/delay.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/ssb/ssb.h> 17 #include <linux/ssb/ssb_regs.h> 18 #include <linux/ssb/ssb_driver_gige.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/pci.h> 21 #include <linux/mmc/sdio_func.h> 22 #include <linux/slab.h> 23 24 #include <pcmcia/cistpl.h> 25 #include <pcmcia/ds.h> 26 27 28 MODULE_DESCRIPTION("Sonics Silicon Backplane driver"); 29 MODULE_LICENSE("GPL"); 30 31 32 /* Temporary list of yet-to-be-attached buses */ 33 static LIST_HEAD(attach_queue); 34 /* List if running buses */ 35 static LIST_HEAD(buses); 36 /* Software ID counter */ 37 static unsigned int next_busnumber; 38 /* buses_mutes locks the two buslists and the next_busnumber. 39 * Don't lock this directly, but use ssb_buses_[un]lock() below. */ 40 static DEFINE_MUTEX(buses_mutex); 41 42 /* There are differences in the codeflow, if the bus is 43 * initialized from early boot, as various needed services 44 * are not available early. This is a mechanism to delay 45 * these initializations to after early boot has finished. 46 * It's also used to avoid mutex locking, as that's not 47 * available and needed early. */ 48 static bool ssb_is_early_boot = 1; 49 50 static void ssb_buses_lock(void); 51 static void ssb_buses_unlock(void); 52 53 54 #ifdef CONFIG_SSB_PCIHOST 55 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev) 56 { 57 struct ssb_bus *bus; 58 59 ssb_buses_lock(); 60 list_for_each_entry(bus, &buses, list) { 61 if (bus->bustype == SSB_BUSTYPE_PCI && 62 bus->host_pci == pdev) 63 goto found; 64 } 65 bus = NULL; 66 found: 67 ssb_buses_unlock(); 68 69 return bus; 70 } 71 #endif /* CONFIG_SSB_PCIHOST */ 72 73 #ifdef CONFIG_SSB_PCMCIAHOST 74 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev) 75 { 76 struct ssb_bus *bus; 77 78 ssb_buses_lock(); 79 list_for_each_entry(bus, &buses, list) { 80 if (bus->bustype == SSB_BUSTYPE_PCMCIA && 81 bus->host_pcmcia == pdev) 82 goto found; 83 } 84 bus = NULL; 85 found: 86 ssb_buses_unlock(); 87 88 return bus; 89 } 90 #endif /* CONFIG_SSB_PCMCIAHOST */ 91 92 #ifdef CONFIG_SSB_SDIOHOST 93 struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func) 94 { 95 struct ssb_bus *bus; 96 97 ssb_buses_lock(); 98 list_for_each_entry(bus, &buses, list) { 99 if (bus->bustype == SSB_BUSTYPE_SDIO && 100 bus->host_sdio == func) 101 goto found; 102 } 103 bus = NULL; 104 found: 105 ssb_buses_unlock(); 106 107 return bus; 108 } 109 #endif /* CONFIG_SSB_SDIOHOST */ 110 111 int ssb_for_each_bus_call(unsigned long data, 112 int (*func)(struct ssb_bus *bus, unsigned long data)) 113 { 114 struct ssb_bus *bus; 115 int res; 116 117 ssb_buses_lock(); 118 list_for_each_entry(bus, &buses, list) { 119 res = func(bus, data); 120 if (res >= 0) { 121 ssb_buses_unlock(); 122 return res; 123 } 124 } 125 ssb_buses_unlock(); 126 127 return -ENODEV; 128 } 129 130 static struct ssb_device *ssb_device_get(struct ssb_device *dev) 131 { 132 if (dev) 133 get_device(dev->dev); 134 return dev; 135 } 136 137 static void ssb_device_put(struct ssb_device *dev) 138 { 139 if (dev) 140 put_device(dev->dev); 141 } 142 143 static int ssb_device_resume(struct device *dev) 144 { 145 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 146 struct ssb_driver *ssb_drv; 147 int err = 0; 148 149 if (dev->driver) { 150 ssb_drv = drv_to_ssb_drv(dev->driver); 151 if (ssb_drv && ssb_drv->resume) 152 err = ssb_drv->resume(ssb_dev); 153 if (err) 154 goto out; 155 } 156 out: 157 return err; 158 } 159 160 static int ssb_device_suspend(struct device *dev, pm_message_t state) 161 { 162 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 163 struct ssb_driver *ssb_drv; 164 int err = 0; 165 166 if (dev->driver) { 167 ssb_drv = drv_to_ssb_drv(dev->driver); 168 if (ssb_drv && ssb_drv->suspend) 169 err = ssb_drv->suspend(ssb_dev, state); 170 if (err) 171 goto out; 172 } 173 out: 174 return err; 175 } 176 177 int ssb_bus_resume(struct ssb_bus *bus) 178 { 179 int err; 180 181 /* Reset HW state information in memory, so that HW is 182 * completely reinitialized. */ 183 bus->mapped_device = NULL; 184 #ifdef CONFIG_SSB_DRIVER_PCICORE 185 bus->pcicore.setup_done = 0; 186 #endif 187 188 err = ssb_bus_powerup(bus, 0); 189 if (err) 190 return err; 191 err = ssb_pcmcia_hardware_setup(bus); 192 if (err) { 193 ssb_bus_may_powerdown(bus); 194 return err; 195 } 196 ssb_chipco_resume(&bus->chipco); 197 ssb_bus_may_powerdown(bus); 198 199 return 0; 200 } 201 EXPORT_SYMBOL(ssb_bus_resume); 202 203 int ssb_bus_suspend(struct ssb_bus *bus) 204 { 205 ssb_chipco_suspend(&bus->chipco); 206 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 207 208 return 0; 209 } 210 EXPORT_SYMBOL(ssb_bus_suspend); 211 212 #ifdef CONFIG_SSB_SPROM 213 /** ssb_devices_freeze - Freeze all devices on the bus. 214 * 215 * After freezing no device driver will be handling a device 216 * on this bus anymore. ssb_devices_thaw() must be called after 217 * a successful freeze to reactivate the devices. 218 * 219 * @bus: The bus. 220 * @ctx: Context structure. Pass this to ssb_devices_thaw(). 221 */ 222 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx) 223 { 224 struct ssb_device *sdev; 225 struct ssb_driver *sdrv; 226 unsigned int i; 227 228 memset(ctx, 0, sizeof(*ctx)); 229 ctx->bus = bus; 230 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen)); 231 232 for (i = 0; i < bus->nr_devices; i++) { 233 sdev = ssb_device_get(&bus->devices[i]); 234 235 if (!sdev->dev || !sdev->dev->driver || 236 !device_is_registered(sdev->dev)) { 237 ssb_device_put(sdev); 238 continue; 239 } 240 sdrv = drv_to_ssb_drv(sdev->dev->driver); 241 if (SSB_WARN_ON(!sdrv->remove)) 242 continue; 243 sdrv->remove(sdev); 244 ctx->device_frozen[i] = 1; 245 } 246 247 return 0; 248 } 249 250 /** ssb_devices_thaw - Unfreeze all devices on the bus. 251 * 252 * This will re-attach the device drivers and re-init the devices. 253 * 254 * @ctx: The context structure from ssb_devices_freeze() 255 */ 256 int ssb_devices_thaw(struct ssb_freeze_context *ctx) 257 { 258 struct ssb_bus *bus = ctx->bus; 259 struct ssb_device *sdev; 260 struct ssb_driver *sdrv; 261 unsigned int i; 262 int err, result = 0; 263 264 for (i = 0; i < bus->nr_devices; i++) { 265 if (!ctx->device_frozen[i]) 266 continue; 267 sdev = &bus->devices[i]; 268 269 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver)) 270 continue; 271 sdrv = drv_to_ssb_drv(sdev->dev->driver); 272 if (SSB_WARN_ON(!sdrv || !sdrv->probe)) 273 continue; 274 275 err = sdrv->probe(sdev, &sdev->id); 276 if (err) { 277 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n", 278 dev_name(sdev->dev)); 279 result = err; 280 } 281 ssb_device_put(sdev); 282 } 283 284 return result; 285 } 286 #endif /* CONFIG_SSB_SPROM */ 287 288 static void ssb_device_shutdown(struct device *dev) 289 { 290 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 291 struct ssb_driver *ssb_drv; 292 293 if (!dev->driver) 294 return; 295 ssb_drv = drv_to_ssb_drv(dev->driver); 296 if (ssb_drv && ssb_drv->shutdown) 297 ssb_drv->shutdown(ssb_dev); 298 } 299 300 static int ssb_device_remove(struct device *dev) 301 { 302 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 303 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 304 305 if (ssb_drv && ssb_drv->remove) 306 ssb_drv->remove(ssb_dev); 307 ssb_device_put(ssb_dev); 308 309 return 0; 310 } 311 312 static int ssb_device_probe(struct device *dev) 313 { 314 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 315 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 316 int err = 0; 317 318 ssb_device_get(ssb_dev); 319 if (ssb_drv && ssb_drv->probe) 320 err = ssb_drv->probe(ssb_dev, &ssb_dev->id); 321 if (err) 322 ssb_device_put(ssb_dev); 323 324 return err; 325 } 326 327 static int ssb_match_devid(const struct ssb_device_id *tabid, 328 const struct ssb_device_id *devid) 329 { 330 if ((tabid->vendor != devid->vendor) && 331 tabid->vendor != SSB_ANY_VENDOR) 332 return 0; 333 if ((tabid->coreid != devid->coreid) && 334 tabid->coreid != SSB_ANY_ID) 335 return 0; 336 if ((tabid->revision != devid->revision) && 337 tabid->revision != SSB_ANY_REV) 338 return 0; 339 return 1; 340 } 341 342 static int ssb_bus_match(struct device *dev, struct device_driver *drv) 343 { 344 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 345 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv); 346 const struct ssb_device_id *id; 347 348 for (id = ssb_drv->id_table; 349 id->vendor || id->coreid || id->revision; 350 id++) { 351 if (ssb_match_devid(id, &ssb_dev->id)) 352 return 1; /* found */ 353 } 354 355 return 0; 356 } 357 358 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env) 359 { 360 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 361 362 if (!dev) 363 return -ENODEV; 364 365 return add_uevent_var(env, 366 "MODALIAS=ssb:v%04Xid%04Xrev%02X", 367 ssb_dev->id.vendor, ssb_dev->id.coreid, 368 ssb_dev->id.revision); 369 } 370 371 #define ssb_config_attr(attrib, field, format_string) \ 372 static ssize_t \ 373 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \ 374 { \ 375 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \ 376 } 377 378 ssb_config_attr(core_num, core_index, "%u\n") 379 ssb_config_attr(coreid, id.coreid, "0x%04x\n") 380 ssb_config_attr(vendor, id.vendor, "0x%04x\n") 381 ssb_config_attr(revision, id.revision, "%u\n") 382 ssb_config_attr(irq, irq, "%u\n") 383 static ssize_t 384 name_show(struct device *dev, struct device_attribute *attr, char *buf) 385 { 386 return sprintf(buf, "%s\n", 387 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid)); 388 } 389 390 static struct device_attribute ssb_device_attrs[] = { 391 __ATTR_RO(name), 392 __ATTR_RO(core_num), 393 __ATTR_RO(coreid), 394 __ATTR_RO(vendor), 395 __ATTR_RO(revision), 396 __ATTR_RO(irq), 397 __ATTR_NULL, 398 }; 399 400 static struct bus_type ssb_bustype = { 401 .name = "ssb", 402 .match = ssb_bus_match, 403 .probe = ssb_device_probe, 404 .remove = ssb_device_remove, 405 .shutdown = ssb_device_shutdown, 406 .suspend = ssb_device_suspend, 407 .resume = ssb_device_resume, 408 .uevent = ssb_device_uevent, 409 .dev_attrs = ssb_device_attrs, 410 }; 411 412 static void ssb_buses_lock(void) 413 { 414 /* See the comment at the ssb_is_early_boot definition */ 415 if (!ssb_is_early_boot) 416 mutex_lock(&buses_mutex); 417 } 418 419 static void ssb_buses_unlock(void) 420 { 421 /* See the comment at the ssb_is_early_boot definition */ 422 if (!ssb_is_early_boot) 423 mutex_unlock(&buses_mutex); 424 } 425 426 static void ssb_devices_unregister(struct ssb_bus *bus) 427 { 428 struct ssb_device *sdev; 429 int i; 430 431 for (i = bus->nr_devices - 1; i >= 0; i--) { 432 sdev = &(bus->devices[i]); 433 if (sdev->dev) 434 device_unregister(sdev->dev); 435 } 436 } 437 438 void ssb_bus_unregister(struct ssb_bus *bus) 439 { 440 ssb_buses_lock(); 441 ssb_devices_unregister(bus); 442 list_del(&bus->list); 443 ssb_buses_unlock(); 444 445 ssb_pcmcia_exit(bus); 446 ssb_pci_exit(bus); 447 ssb_iounmap(bus); 448 } 449 EXPORT_SYMBOL(ssb_bus_unregister); 450 451 static void ssb_release_dev(struct device *dev) 452 { 453 struct __ssb_dev_wrapper *devwrap; 454 455 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev); 456 kfree(devwrap); 457 } 458 459 static int ssb_devices_register(struct ssb_bus *bus) 460 { 461 struct ssb_device *sdev; 462 struct device *dev; 463 struct __ssb_dev_wrapper *devwrap; 464 int i, err = 0; 465 int dev_idx = 0; 466 467 for (i = 0; i < bus->nr_devices; i++) { 468 sdev = &(bus->devices[i]); 469 470 /* We don't register SSB-system devices to the kernel, 471 * as the drivers for them are built into SSB. */ 472 switch (sdev->id.coreid) { 473 case SSB_DEV_CHIPCOMMON: 474 case SSB_DEV_PCI: 475 case SSB_DEV_PCIE: 476 case SSB_DEV_PCMCIA: 477 case SSB_DEV_MIPS: 478 case SSB_DEV_MIPS_3302: 479 case SSB_DEV_EXTIF: 480 continue; 481 } 482 483 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL); 484 if (!devwrap) { 485 ssb_printk(KERN_ERR PFX 486 "Could not allocate device\n"); 487 err = -ENOMEM; 488 goto error; 489 } 490 dev = &devwrap->dev; 491 devwrap->sdev = sdev; 492 493 dev->release = ssb_release_dev; 494 dev->bus = &ssb_bustype; 495 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx); 496 497 switch (bus->bustype) { 498 case SSB_BUSTYPE_PCI: 499 #ifdef CONFIG_SSB_PCIHOST 500 sdev->irq = bus->host_pci->irq; 501 dev->parent = &bus->host_pci->dev; 502 sdev->dma_dev = dev->parent; 503 #endif 504 break; 505 case SSB_BUSTYPE_PCMCIA: 506 #ifdef CONFIG_SSB_PCMCIAHOST 507 sdev->irq = bus->host_pcmcia->irq; 508 dev->parent = &bus->host_pcmcia->dev; 509 #endif 510 break; 511 case SSB_BUSTYPE_SDIO: 512 #ifdef CONFIG_SSB_SDIOHOST 513 dev->parent = &bus->host_sdio->dev; 514 #endif 515 break; 516 case SSB_BUSTYPE_SSB: 517 dev->dma_mask = &dev->coherent_dma_mask; 518 sdev->dma_dev = dev; 519 break; 520 } 521 522 sdev->dev = dev; 523 err = device_register(dev); 524 if (err) { 525 ssb_printk(KERN_ERR PFX 526 "Could not register %s\n", 527 dev_name(dev)); 528 /* Set dev to NULL to not unregister 529 * dev on error unwinding. */ 530 sdev->dev = NULL; 531 kfree(devwrap); 532 goto error; 533 } 534 dev_idx++; 535 } 536 537 return 0; 538 error: 539 /* Unwind the already registered devices. */ 540 ssb_devices_unregister(bus); 541 return err; 542 } 543 544 /* Needs ssb_buses_lock() */ 545 static int __devinit ssb_attach_queued_buses(void) 546 { 547 struct ssb_bus *bus, *n; 548 int err = 0; 549 int drop_them_all = 0; 550 551 list_for_each_entry_safe(bus, n, &attach_queue, list) { 552 if (drop_them_all) { 553 list_del(&bus->list); 554 continue; 555 } 556 /* Can't init the PCIcore in ssb_bus_register(), as that 557 * is too early in boot for embedded systems 558 * (no udelay() available). So do it here in attach stage. 559 */ 560 err = ssb_bus_powerup(bus, 0); 561 if (err) 562 goto error; 563 ssb_pcicore_init(&bus->pcicore); 564 ssb_bus_may_powerdown(bus); 565 566 err = ssb_devices_register(bus); 567 error: 568 if (err) { 569 drop_them_all = 1; 570 list_del(&bus->list); 571 continue; 572 } 573 list_move_tail(&bus->list, &buses); 574 } 575 576 return err; 577 } 578 579 static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset) 580 { 581 struct ssb_bus *bus = dev->bus; 582 583 offset += dev->core_index * SSB_CORE_SIZE; 584 return readb(bus->mmio + offset); 585 } 586 587 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset) 588 { 589 struct ssb_bus *bus = dev->bus; 590 591 offset += dev->core_index * SSB_CORE_SIZE; 592 return readw(bus->mmio + offset); 593 } 594 595 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset) 596 { 597 struct ssb_bus *bus = dev->bus; 598 599 offset += dev->core_index * SSB_CORE_SIZE; 600 return readl(bus->mmio + offset); 601 } 602 603 #ifdef CONFIG_SSB_BLOCKIO 604 static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer, 605 size_t count, u16 offset, u8 reg_width) 606 { 607 struct ssb_bus *bus = dev->bus; 608 void __iomem *addr; 609 610 offset += dev->core_index * SSB_CORE_SIZE; 611 addr = bus->mmio + offset; 612 613 switch (reg_width) { 614 case sizeof(u8): { 615 u8 *buf = buffer; 616 617 while (count) { 618 *buf = __raw_readb(addr); 619 buf++; 620 count--; 621 } 622 break; 623 } 624 case sizeof(u16): { 625 __le16 *buf = buffer; 626 627 SSB_WARN_ON(count & 1); 628 while (count) { 629 *buf = (__force __le16)__raw_readw(addr); 630 buf++; 631 count -= 2; 632 } 633 break; 634 } 635 case sizeof(u32): { 636 __le32 *buf = buffer; 637 638 SSB_WARN_ON(count & 3); 639 while (count) { 640 *buf = (__force __le32)__raw_readl(addr); 641 buf++; 642 count -= 4; 643 } 644 break; 645 } 646 default: 647 SSB_WARN_ON(1); 648 } 649 } 650 #endif /* CONFIG_SSB_BLOCKIO */ 651 652 static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value) 653 { 654 struct ssb_bus *bus = dev->bus; 655 656 offset += dev->core_index * SSB_CORE_SIZE; 657 writeb(value, bus->mmio + offset); 658 } 659 660 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value) 661 { 662 struct ssb_bus *bus = dev->bus; 663 664 offset += dev->core_index * SSB_CORE_SIZE; 665 writew(value, bus->mmio + offset); 666 } 667 668 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value) 669 { 670 struct ssb_bus *bus = dev->bus; 671 672 offset += dev->core_index * SSB_CORE_SIZE; 673 writel(value, bus->mmio + offset); 674 } 675 676 #ifdef CONFIG_SSB_BLOCKIO 677 static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer, 678 size_t count, u16 offset, u8 reg_width) 679 { 680 struct ssb_bus *bus = dev->bus; 681 void __iomem *addr; 682 683 offset += dev->core_index * SSB_CORE_SIZE; 684 addr = bus->mmio + offset; 685 686 switch (reg_width) { 687 case sizeof(u8): { 688 const u8 *buf = buffer; 689 690 while (count) { 691 __raw_writeb(*buf, addr); 692 buf++; 693 count--; 694 } 695 break; 696 } 697 case sizeof(u16): { 698 const __le16 *buf = buffer; 699 700 SSB_WARN_ON(count & 1); 701 while (count) { 702 __raw_writew((__force u16)(*buf), addr); 703 buf++; 704 count -= 2; 705 } 706 break; 707 } 708 case sizeof(u32): { 709 const __le32 *buf = buffer; 710 711 SSB_WARN_ON(count & 3); 712 while (count) { 713 __raw_writel((__force u32)(*buf), addr); 714 buf++; 715 count -= 4; 716 } 717 break; 718 } 719 default: 720 SSB_WARN_ON(1); 721 } 722 } 723 #endif /* CONFIG_SSB_BLOCKIO */ 724 725 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */ 726 static const struct ssb_bus_ops ssb_ssb_ops = { 727 .read8 = ssb_ssb_read8, 728 .read16 = ssb_ssb_read16, 729 .read32 = ssb_ssb_read32, 730 .write8 = ssb_ssb_write8, 731 .write16 = ssb_ssb_write16, 732 .write32 = ssb_ssb_write32, 733 #ifdef CONFIG_SSB_BLOCKIO 734 .block_read = ssb_ssb_block_read, 735 .block_write = ssb_ssb_block_write, 736 #endif 737 }; 738 739 static int ssb_fetch_invariants(struct ssb_bus *bus, 740 ssb_invariants_func_t get_invariants) 741 { 742 struct ssb_init_invariants iv; 743 int err; 744 745 memset(&iv, 0, sizeof(iv)); 746 err = get_invariants(bus, &iv); 747 if (err) 748 goto out; 749 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo)); 750 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom)); 751 bus->has_cardbus_slot = iv.has_cardbus_slot; 752 out: 753 return err; 754 } 755 756 static int __devinit ssb_bus_register(struct ssb_bus *bus, 757 ssb_invariants_func_t get_invariants, 758 unsigned long baseaddr) 759 { 760 int err; 761 762 spin_lock_init(&bus->bar_lock); 763 INIT_LIST_HEAD(&bus->list); 764 #ifdef CONFIG_SSB_EMBEDDED 765 spin_lock_init(&bus->gpio_lock); 766 #endif 767 768 /* Powerup the bus */ 769 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 770 if (err) 771 goto out; 772 773 /* Init SDIO-host device (if any), before the scan */ 774 err = ssb_sdio_init(bus); 775 if (err) 776 goto err_disable_xtal; 777 778 ssb_buses_lock(); 779 bus->busnumber = next_busnumber; 780 /* Scan for devices (cores) */ 781 err = ssb_bus_scan(bus, baseaddr); 782 if (err) 783 goto err_sdio_exit; 784 785 /* Init PCI-host device (if any) */ 786 err = ssb_pci_init(bus); 787 if (err) 788 goto err_unmap; 789 /* Init PCMCIA-host device (if any) */ 790 err = ssb_pcmcia_init(bus); 791 if (err) 792 goto err_pci_exit; 793 794 /* Initialize basic system devices (if available) */ 795 err = ssb_bus_powerup(bus, 0); 796 if (err) 797 goto err_pcmcia_exit; 798 ssb_chipcommon_init(&bus->chipco); 799 ssb_mipscore_init(&bus->mipscore); 800 err = ssb_fetch_invariants(bus, get_invariants); 801 if (err) { 802 ssb_bus_may_powerdown(bus); 803 goto err_pcmcia_exit; 804 } 805 ssb_bus_may_powerdown(bus); 806 807 /* Queue it for attach. 808 * See the comment at the ssb_is_early_boot definition. */ 809 list_add_tail(&bus->list, &attach_queue); 810 if (!ssb_is_early_boot) { 811 /* This is not early boot, so we must attach the bus now */ 812 err = ssb_attach_queued_buses(); 813 if (err) 814 goto err_dequeue; 815 } 816 next_busnumber++; 817 ssb_buses_unlock(); 818 819 out: 820 return err; 821 822 err_dequeue: 823 list_del(&bus->list); 824 err_pcmcia_exit: 825 ssb_pcmcia_exit(bus); 826 err_pci_exit: 827 ssb_pci_exit(bus); 828 err_unmap: 829 ssb_iounmap(bus); 830 err_sdio_exit: 831 ssb_sdio_exit(bus); 832 err_disable_xtal: 833 ssb_buses_unlock(); 834 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 835 return err; 836 } 837 838 #ifdef CONFIG_SSB_PCIHOST 839 int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus, 840 struct pci_dev *host_pci) 841 { 842 int err; 843 844 bus->bustype = SSB_BUSTYPE_PCI; 845 bus->host_pci = host_pci; 846 bus->ops = &ssb_pci_ops; 847 848 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0); 849 if (!err) { 850 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " 851 "PCI device %s\n", dev_name(&host_pci->dev)); 852 } else { 853 ssb_printk(KERN_ERR PFX "Failed to register PCI version" 854 " of SSB with error %d\n", err); 855 } 856 857 return err; 858 } 859 EXPORT_SYMBOL(ssb_bus_pcibus_register); 860 #endif /* CONFIG_SSB_PCIHOST */ 861 862 #ifdef CONFIG_SSB_PCMCIAHOST 863 int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus, 864 struct pcmcia_device *pcmcia_dev, 865 unsigned long baseaddr) 866 { 867 int err; 868 869 bus->bustype = SSB_BUSTYPE_PCMCIA; 870 bus->host_pcmcia = pcmcia_dev; 871 bus->ops = &ssb_pcmcia_ops; 872 873 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr); 874 if (!err) { 875 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " 876 "PCMCIA device %s\n", pcmcia_dev->devname); 877 } 878 879 return err; 880 } 881 EXPORT_SYMBOL(ssb_bus_pcmciabus_register); 882 #endif /* CONFIG_SSB_PCMCIAHOST */ 883 884 #ifdef CONFIG_SSB_SDIOHOST 885 int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus, 886 struct sdio_func *func, 887 unsigned int quirks) 888 { 889 int err; 890 891 bus->bustype = SSB_BUSTYPE_SDIO; 892 bus->host_sdio = func; 893 bus->ops = &ssb_sdio_ops; 894 bus->quirks = quirks; 895 896 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0); 897 if (!err) { 898 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " 899 "SDIO device %s\n", sdio_func_id(func)); 900 } 901 902 return err; 903 } 904 EXPORT_SYMBOL(ssb_bus_sdiobus_register); 905 #endif /* CONFIG_SSB_PCMCIAHOST */ 906 907 int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus, 908 unsigned long baseaddr, 909 ssb_invariants_func_t get_invariants) 910 { 911 int err; 912 913 bus->bustype = SSB_BUSTYPE_SSB; 914 bus->ops = &ssb_ssb_ops; 915 916 err = ssb_bus_register(bus, get_invariants, baseaddr); 917 if (!err) { 918 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at " 919 "address 0x%08lX\n", baseaddr); 920 } 921 922 return err; 923 } 924 925 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner) 926 { 927 drv->drv.name = drv->name; 928 drv->drv.bus = &ssb_bustype; 929 drv->drv.owner = owner; 930 931 return driver_register(&drv->drv); 932 } 933 EXPORT_SYMBOL(__ssb_driver_register); 934 935 void ssb_driver_unregister(struct ssb_driver *drv) 936 { 937 driver_unregister(&drv->drv); 938 } 939 EXPORT_SYMBOL(ssb_driver_unregister); 940 941 void ssb_set_devtypedata(struct ssb_device *dev, void *data) 942 { 943 struct ssb_bus *bus = dev->bus; 944 struct ssb_device *ent; 945 int i; 946 947 for (i = 0; i < bus->nr_devices; i++) { 948 ent = &(bus->devices[i]); 949 if (ent->id.vendor != dev->id.vendor) 950 continue; 951 if (ent->id.coreid != dev->id.coreid) 952 continue; 953 954 ent->devtypedata = data; 955 } 956 } 957 EXPORT_SYMBOL(ssb_set_devtypedata); 958 959 static u32 clkfactor_f6_resolve(u32 v) 960 { 961 /* map the magic values */ 962 switch (v) { 963 case SSB_CHIPCO_CLK_F6_2: 964 return 2; 965 case SSB_CHIPCO_CLK_F6_3: 966 return 3; 967 case SSB_CHIPCO_CLK_F6_4: 968 return 4; 969 case SSB_CHIPCO_CLK_F6_5: 970 return 5; 971 case SSB_CHIPCO_CLK_F6_6: 972 return 6; 973 case SSB_CHIPCO_CLK_F6_7: 974 return 7; 975 } 976 return 0; 977 } 978 979 /* Calculate the speed the backplane would run at a given set of clockcontrol values */ 980 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) 981 { 982 u32 n1, n2, clock, m1, m2, m3, mc; 983 984 n1 = (n & SSB_CHIPCO_CLK_N1); 985 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT); 986 987 switch (plltype) { 988 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ 989 if (m & SSB_CHIPCO_CLK_T6_MMASK) 990 return SSB_CHIPCO_CLK_T6_M1; 991 return SSB_CHIPCO_CLK_T6_M0; 992 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 993 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 994 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 995 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 996 n1 = clkfactor_f6_resolve(n1); 997 n2 += SSB_CHIPCO_CLK_F5_BIAS; 998 break; 999 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ 1000 n1 += SSB_CHIPCO_CLK_T2_BIAS; 1001 n2 += SSB_CHIPCO_CLK_T2_BIAS; 1002 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7))); 1003 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23))); 1004 break; 1005 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ 1006 return 100000000; 1007 default: 1008 SSB_WARN_ON(1); 1009 } 1010 1011 switch (plltype) { 1012 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1013 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1014 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2; 1015 break; 1016 default: 1017 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2; 1018 } 1019 if (!clock) 1020 return 0; 1021 1022 m1 = (m & SSB_CHIPCO_CLK_M1); 1023 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); 1024 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT); 1025 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT); 1026 1027 switch (plltype) { 1028 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 1029 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 1030 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 1031 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 1032 m1 = clkfactor_f6_resolve(m1); 1033 if ((plltype == SSB_PLLTYPE_1) || 1034 (plltype == SSB_PLLTYPE_3)) 1035 m2 += SSB_CHIPCO_CLK_F5_BIAS; 1036 else 1037 m2 = clkfactor_f6_resolve(m2); 1038 m3 = clkfactor_f6_resolve(m3); 1039 1040 switch (mc) { 1041 case SSB_CHIPCO_CLK_MC_BYPASS: 1042 return clock; 1043 case SSB_CHIPCO_CLK_MC_M1: 1044 return (clock / m1); 1045 case SSB_CHIPCO_CLK_MC_M1M2: 1046 return (clock / (m1 * m2)); 1047 case SSB_CHIPCO_CLK_MC_M1M2M3: 1048 return (clock / (m1 * m2 * m3)); 1049 case SSB_CHIPCO_CLK_MC_M1M3: 1050 return (clock / (m1 * m3)); 1051 } 1052 return 0; 1053 case SSB_PLLTYPE_2: 1054 m1 += SSB_CHIPCO_CLK_T2_BIAS; 1055 m2 += SSB_CHIPCO_CLK_T2M2_BIAS; 1056 m3 += SSB_CHIPCO_CLK_T2_BIAS; 1057 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7))); 1058 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10))); 1059 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7))); 1060 1061 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP)) 1062 clock /= m1; 1063 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP)) 1064 clock /= m2; 1065 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP)) 1066 clock /= m3; 1067 return clock; 1068 default: 1069 SSB_WARN_ON(1); 1070 } 1071 return 0; 1072 } 1073 1074 /* Get the current speed the backplane is running at */ 1075 u32 ssb_clockspeed(struct ssb_bus *bus) 1076 { 1077 u32 rate; 1078 u32 plltype; 1079 u32 clkctl_n, clkctl_m; 1080 1081 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU) 1082 return ssb_pmu_get_controlclock(&bus->chipco); 1083 1084 if (ssb_extif_available(&bus->extif)) 1085 ssb_extif_get_clockcontrol(&bus->extif, &plltype, 1086 &clkctl_n, &clkctl_m); 1087 else if (bus->chipco.dev) 1088 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype, 1089 &clkctl_n, &clkctl_m); 1090 else 1091 return 0; 1092 1093 if (bus->chip_id == 0x5365) { 1094 rate = 100000000; 1095 } else { 1096 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); 1097 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ 1098 rate /= 2; 1099 } 1100 1101 return rate; 1102 } 1103 EXPORT_SYMBOL(ssb_clockspeed); 1104 1105 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev) 1106 { 1107 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; 1108 1109 /* The REJECT bit seems to be different for Backplane rev 2.3 */ 1110 switch (rev) { 1111 case SSB_IDLOW_SSBREV_22: 1112 case SSB_IDLOW_SSBREV_24: 1113 case SSB_IDLOW_SSBREV_26: 1114 return SSB_TMSLOW_REJECT; 1115 case SSB_IDLOW_SSBREV_23: 1116 return SSB_TMSLOW_REJECT_23; 1117 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ 1118 case SSB_IDLOW_SSBREV_27: /* same here */ 1119 return SSB_TMSLOW_REJECT; /* this is a guess */ 1120 default: 1121 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); 1122 WARN_ON(1); 1123 } 1124 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23); 1125 } 1126 1127 int ssb_device_is_enabled(struct ssb_device *dev) 1128 { 1129 u32 val; 1130 u32 reject; 1131 1132 reject = ssb_tmslow_reject_bitmask(dev); 1133 val = ssb_read32(dev, SSB_TMSLOW); 1134 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject; 1135 1136 return (val == SSB_TMSLOW_CLOCK); 1137 } 1138 EXPORT_SYMBOL(ssb_device_is_enabled); 1139 1140 static void ssb_flush_tmslow(struct ssb_device *dev) 1141 { 1142 /* Make _really_ sure the device has finished the TMSLOW 1143 * register write transaction, as we risk running into 1144 * a machine check exception otherwise. 1145 * Do this by reading the register back to commit the 1146 * PCI write and delay an additional usec for the device 1147 * to react to the change. */ 1148 ssb_read32(dev, SSB_TMSLOW); 1149 udelay(1); 1150 } 1151 1152 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags) 1153 { 1154 u32 val; 1155 1156 ssb_device_disable(dev, core_specific_flags); 1157 ssb_write32(dev, SSB_TMSLOW, 1158 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK | 1159 SSB_TMSLOW_FGC | core_specific_flags); 1160 ssb_flush_tmslow(dev); 1161 1162 /* Clear SERR if set. This is a hw bug workaround. */ 1163 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR) 1164 ssb_write32(dev, SSB_TMSHIGH, 0); 1165 1166 val = ssb_read32(dev, SSB_IMSTATE); 1167 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { 1168 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); 1169 ssb_write32(dev, SSB_IMSTATE, val); 1170 } 1171 1172 ssb_write32(dev, SSB_TMSLOW, 1173 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC | 1174 core_specific_flags); 1175 ssb_flush_tmslow(dev); 1176 1177 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK | 1178 core_specific_flags); 1179 ssb_flush_tmslow(dev); 1180 } 1181 EXPORT_SYMBOL(ssb_device_enable); 1182 1183 /* Wait for bitmask in a register to get set or cleared. 1184 * timeout is in units of ten-microseconds */ 1185 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask, 1186 int timeout, int set) 1187 { 1188 int i; 1189 u32 val; 1190 1191 for (i = 0; i < timeout; i++) { 1192 val = ssb_read32(dev, reg); 1193 if (set) { 1194 if ((val & bitmask) == bitmask) 1195 return 0; 1196 } else { 1197 if (!(val & bitmask)) 1198 return 0; 1199 } 1200 udelay(10); 1201 } 1202 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on " 1203 "register %04X to %s.\n", 1204 bitmask, reg, (set ? "set" : "clear")); 1205 1206 return -ETIMEDOUT; 1207 } 1208 1209 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) 1210 { 1211 u32 reject, val; 1212 1213 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) 1214 return; 1215 1216 reject = ssb_tmslow_reject_bitmask(dev); 1217 1218 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) { 1219 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); 1220 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1); 1221 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); 1222 1223 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1224 val = ssb_read32(dev, SSB_IMSTATE); 1225 val |= SSB_IMSTATE_REJECT; 1226 ssb_write32(dev, SSB_IMSTATE, val); 1227 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000, 1228 0); 1229 } 1230 1231 ssb_write32(dev, SSB_TMSLOW, 1232 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | 1233 reject | SSB_TMSLOW_RESET | 1234 core_specific_flags); 1235 ssb_flush_tmslow(dev); 1236 1237 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1238 val = ssb_read32(dev, SSB_IMSTATE); 1239 val &= ~SSB_IMSTATE_REJECT; 1240 ssb_write32(dev, SSB_IMSTATE, val); 1241 } 1242 } 1243 1244 ssb_write32(dev, SSB_TMSLOW, 1245 reject | SSB_TMSLOW_RESET | 1246 core_specific_flags); 1247 ssb_flush_tmslow(dev); 1248 } 1249 EXPORT_SYMBOL(ssb_device_disable); 1250 1251 /* Some chipsets need routing known for PCIe and 64-bit DMA */ 1252 static bool ssb_dma_translation_special_bit(struct ssb_device *dev) 1253 { 1254 u16 chip_id = dev->bus->chip_id; 1255 1256 if (dev->id.coreid == SSB_DEV_80211) { 1257 return (chip_id == 0x4322 || chip_id == 43221 || 1258 chip_id == 43231 || chip_id == 43222); 1259 } 1260 1261 return 0; 1262 } 1263 1264 u32 ssb_dma_translation(struct ssb_device *dev) 1265 { 1266 switch (dev->bus->bustype) { 1267 case SSB_BUSTYPE_SSB: 1268 return 0; 1269 case SSB_BUSTYPE_PCI: 1270 if (pci_is_pcie(dev->bus->host_pci) && 1271 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) { 1272 return SSB_PCIE_DMA_H32; 1273 } else { 1274 if (ssb_dma_translation_special_bit(dev)) 1275 return SSB_PCIE_DMA_H32; 1276 else 1277 return SSB_PCI_DMA; 1278 } 1279 default: 1280 __ssb_dma_not_implemented(dev); 1281 } 1282 return 0; 1283 } 1284 EXPORT_SYMBOL(ssb_dma_translation); 1285 1286 int ssb_bus_may_powerdown(struct ssb_bus *bus) 1287 { 1288 struct ssb_chipcommon *cc; 1289 int err = 0; 1290 1291 /* On buses where more than one core may be working 1292 * at a time, we must not powerdown stuff if there are 1293 * still cores that may want to run. */ 1294 if (bus->bustype == SSB_BUSTYPE_SSB) 1295 goto out; 1296 1297 cc = &bus->chipco; 1298 1299 if (!cc->dev) 1300 goto out; 1301 if (cc->dev->id.revision < 5) 1302 goto out; 1303 1304 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); 1305 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 1306 if (err) 1307 goto error; 1308 out: 1309 #ifdef CONFIG_SSB_DEBUG 1310 bus->powered_up = 0; 1311 #endif 1312 return err; 1313 error: 1314 ssb_printk(KERN_ERR PFX "Bus powerdown failed\n"); 1315 goto out; 1316 } 1317 EXPORT_SYMBOL(ssb_bus_may_powerdown); 1318 1319 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) 1320 { 1321 int err; 1322 enum ssb_clkmode mode; 1323 1324 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 1325 if (err) 1326 goto error; 1327 1328 #ifdef CONFIG_SSB_DEBUG 1329 bus->powered_up = 1; 1330 #endif 1331 1332 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; 1333 ssb_chipco_set_clockmode(&bus->chipco, mode); 1334 1335 return 0; 1336 error: 1337 ssb_printk(KERN_ERR PFX "Bus powerup failed\n"); 1338 return err; 1339 } 1340 EXPORT_SYMBOL(ssb_bus_powerup); 1341 1342 static void ssb_broadcast_value(struct ssb_device *dev, 1343 u32 address, u32 data) 1344 { 1345 #ifdef CONFIG_SSB_DRIVER_PCICORE 1346 /* This is used for both, PCI and ChipCommon core, so be careful. */ 1347 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); 1348 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); 1349 #endif 1350 1351 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address); 1352 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */ 1353 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data); 1354 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */ 1355 } 1356 1357 void ssb_commit_settings(struct ssb_bus *bus) 1358 { 1359 struct ssb_device *dev; 1360 1361 #ifdef CONFIG_SSB_DRIVER_PCICORE 1362 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; 1363 #else 1364 dev = bus->chipco.dev; 1365 #endif 1366 if (WARN_ON(!dev)) 1367 return; 1368 /* This forces an update of the cached registers. */ 1369 ssb_broadcast_value(dev, 0xFD8, 0); 1370 } 1371 EXPORT_SYMBOL(ssb_commit_settings); 1372 1373 u32 ssb_admatch_base(u32 adm) 1374 { 1375 u32 base = 0; 1376 1377 switch (adm & SSB_ADM_TYPE) { 1378 case SSB_ADM_TYPE0: 1379 base = (adm & SSB_ADM_BASE0); 1380 break; 1381 case SSB_ADM_TYPE1: 1382 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1383 base = (adm & SSB_ADM_BASE1); 1384 break; 1385 case SSB_ADM_TYPE2: 1386 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1387 base = (adm & SSB_ADM_BASE2); 1388 break; 1389 default: 1390 SSB_WARN_ON(1); 1391 } 1392 1393 return base; 1394 } 1395 EXPORT_SYMBOL(ssb_admatch_base); 1396 1397 u32 ssb_admatch_size(u32 adm) 1398 { 1399 u32 size = 0; 1400 1401 switch (adm & SSB_ADM_TYPE) { 1402 case SSB_ADM_TYPE0: 1403 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT); 1404 break; 1405 case SSB_ADM_TYPE1: 1406 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1407 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT); 1408 break; 1409 case SSB_ADM_TYPE2: 1410 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1411 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT); 1412 break; 1413 default: 1414 SSB_WARN_ON(1); 1415 } 1416 size = (1 << (size + 1)); 1417 1418 return size; 1419 } 1420 EXPORT_SYMBOL(ssb_admatch_size); 1421 1422 static int __init ssb_modinit(void) 1423 { 1424 int err; 1425 1426 /* See the comment at the ssb_is_early_boot definition */ 1427 ssb_is_early_boot = 0; 1428 err = bus_register(&ssb_bustype); 1429 if (err) 1430 return err; 1431 1432 /* Maybe we already registered some buses at early boot. 1433 * Check for this and attach them 1434 */ 1435 ssb_buses_lock(); 1436 err = ssb_attach_queued_buses(); 1437 ssb_buses_unlock(); 1438 if (err) { 1439 bus_unregister(&ssb_bustype); 1440 goto out; 1441 } 1442 1443 err = b43_pci_ssb_bridge_init(); 1444 if (err) { 1445 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge " 1446 "initialization failed\n"); 1447 /* don't fail SSB init because of this */ 1448 err = 0; 1449 } 1450 err = ssb_gige_init(); 1451 if (err) { 1452 ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet " 1453 "driver initialization failed\n"); 1454 /* don't fail SSB init because of this */ 1455 err = 0; 1456 } 1457 out: 1458 return err; 1459 } 1460 /* ssb must be initialized after PCI but before the ssb drivers. 1461 * That means we must use some initcall between subsys_initcall 1462 * and device_initcall. */ 1463 fs_initcall(ssb_modinit); 1464 1465 static void __exit ssb_modexit(void) 1466 { 1467 ssb_gige_exit(); 1468 b43_pci_ssb_bridge_exit(); 1469 bus_unregister(&ssb_bustype); 1470 } 1471 module_exit(ssb_modexit) 1472