1 /* 2 * Sonics Silicon Backplane 3 * Subsystem core 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include "ssb_private.h" 12 13 #include <linux/delay.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/ssb/ssb.h> 18 #include <linux/ssb/ssb_regs.h> 19 #include <linux/ssb/ssb_driver_gige.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/pci.h> 22 #include <linux/mmc/sdio_func.h> 23 #include <linux/slab.h> 24 25 #include <pcmcia/cistpl.h> 26 #include <pcmcia/ds.h> 27 28 29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver"); 30 MODULE_LICENSE("GPL"); 31 32 33 /* Temporary list of yet-to-be-attached buses */ 34 static LIST_HEAD(attach_queue); 35 /* List if running buses */ 36 static LIST_HEAD(buses); 37 /* Software ID counter */ 38 static unsigned int next_busnumber; 39 /* buses_mutes locks the two buslists and the next_busnumber. 40 * Don't lock this directly, but use ssb_buses_[un]lock() below. */ 41 static DEFINE_MUTEX(buses_mutex); 42 43 /* There are differences in the codeflow, if the bus is 44 * initialized from early boot, as various needed services 45 * are not available early. This is a mechanism to delay 46 * these initializations to after early boot has finished. 47 * It's also used to avoid mutex locking, as that's not 48 * available and needed early. */ 49 static bool ssb_is_early_boot = 1; 50 51 static void ssb_buses_lock(void); 52 static void ssb_buses_unlock(void); 53 54 55 #ifdef CONFIG_SSB_PCIHOST 56 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev) 57 { 58 struct ssb_bus *bus; 59 60 ssb_buses_lock(); 61 list_for_each_entry(bus, &buses, list) { 62 if (bus->bustype == SSB_BUSTYPE_PCI && 63 bus->host_pci == pdev) 64 goto found; 65 } 66 bus = NULL; 67 found: 68 ssb_buses_unlock(); 69 70 return bus; 71 } 72 #endif /* CONFIG_SSB_PCIHOST */ 73 74 #ifdef CONFIG_SSB_PCMCIAHOST 75 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev) 76 { 77 struct ssb_bus *bus; 78 79 ssb_buses_lock(); 80 list_for_each_entry(bus, &buses, list) { 81 if (bus->bustype == SSB_BUSTYPE_PCMCIA && 82 bus->host_pcmcia == pdev) 83 goto found; 84 } 85 bus = NULL; 86 found: 87 ssb_buses_unlock(); 88 89 return bus; 90 } 91 #endif /* CONFIG_SSB_PCMCIAHOST */ 92 93 int ssb_for_each_bus_call(unsigned long data, 94 int (*func)(struct ssb_bus *bus, unsigned long data)) 95 { 96 struct ssb_bus *bus; 97 int res; 98 99 ssb_buses_lock(); 100 list_for_each_entry(bus, &buses, list) { 101 res = func(bus, data); 102 if (res >= 0) { 103 ssb_buses_unlock(); 104 return res; 105 } 106 } 107 ssb_buses_unlock(); 108 109 return -ENODEV; 110 } 111 112 static struct ssb_device *ssb_device_get(struct ssb_device *dev) 113 { 114 if (dev) 115 get_device(dev->dev); 116 return dev; 117 } 118 119 static void ssb_device_put(struct ssb_device *dev) 120 { 121 if (dev) 122 put_device(dev->dev); 123 } 124 125 static int ssb_device_resume(struct device *dev) 126 { 127 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 128 struct ssb_driver *ssb_drv; 129 int err = 0; 130 131 if (dev->driver) { 132 ssb_drv = drv_to_ssb_drv(dev->driver); 133 if (ssb_drv && ssb_drv->resume) 134 err = ssb_drv->resume(ssb_dev); 135 if (err) 136 goto out; 137 } 138 out: 139 return err; 140 } 141 142 static int ssb_device_suspend(struct device *dev, pm_message_t state) 143 { 144 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 145 struct ssb_driver *ssb_drv; 146 int err = 0; 147 148 if (dev->driver) { 149 ssb_drv = drv_to_ssb_drv(dev->driver); 150 if (ssb_drv && ssb_drv->suspend) 151 err = ssb_drv->suspend(ssb_dev, state); 152 if (err) 153 goto out; 154 } 155 out: 156 return err; 157 } 158 159 int ssb_bus_resume(struct ssb_bus *bus) 160 { 161 int err; 162 163 /* Reset HW state information in memory, so that HW is 164 * completely reinitialized. */ 165 bus->mapped_device = NULL; 166 #ifdef CONFIG_SSB_DRIVER_PCICORE 167 bus->pcicore.setup_done = 0; 168 #endif 169 170 err = ssb_bus_powerup(bus, 0); 171 if (err) 172 return err; 173 err = ssb_pcmcia_hardware_setup(bus); 174 if (err) { 175 ssb_bus_may_powerdown(bus); 176 return err; 177 } 178 ssb_chipco_resume(&bus->chipco); 179 ssb_bus_may_powerdown(bus); 180 181 return 0; 182 } 183 EXPORT_SYMBOL(ssb_bus_resume); 184 185 int ssb_bus_suspend(struct ssb_bus *bus) 186 { 187 ssb_chipco_suspend(&bus->chipco); 188 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 189 190 return 0; 191 } 192 EXPORT_SYMBOL(ssb_bus_suspend); 193 194 #ifdef CONFIG_SSB_SPROM 195 /** ssb_devices_freeze - Freeze all devices on the bus. 196 * 197 * After freezing no device driver will be handling a device 198 * on this bus anymore. ssb_devices_thaw() must be called after 199 * a successful freeze to reactivate the devices. 200 * 201 * @bus: The bus. 202 * @ctx: Context structure. Pass this to ssb_devices_thaw(). 203 */ 204 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx) 205 { 206 struct ssb_device *sdev; 207 struct ssb_driver *sdrv; 208 unsigned int i; 209 210 memset(ctx, 0, sizeof(*ctx)); 211 ctx->bus = bus; 212 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen)); 213 214 for (i = 0; i < bus->nr_devices; i++) { 215 sdev = ssb_device_get(&bus->devices[i]); 216 217 if (!sdev->dev || !sdev->dev->driver || 218 !device_is_registered(sdev->dev)) { 219 ssb_device_put(sdev); 220 continue; 221 } 222 sdrv = drv_to_ssb_drv(sdev->dev->driver); 223 if (SSB_WARN_ON(!sdrv->remove)) 224 continue; 225 sdrv->remove(sdev); 226 ctx->device_frozen[i] = 1; 227 } 228 229 return 0; 230 } 231 232 /** ssb_devices_thaw - Unfreeze all devices on the bus. 233 * 234 * This will re-attach the device drivers and re-init the devices. 235 * 236 * @ctx: The context structure from ssb_devices_freeze() 237 */ 238 int ssb_devices_thaw(struct ssb_freeze_context *ctx) 239 { 240 struct ssb_bus *bus = ctx->bus; 241 struct ssb_device *sdev; 242 struct ssb_driver *sdrv; 243 unsigned int i; 244 int err, result = 0; 245 246 for (i = 0; i < bus->nr_devices; i++) { 247 if (!ctx->device_frozen[i]) 248 continue; 249 sdev = &bus->devices[i]; 250 251 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver)) 252 continue; 253 sdrv = drv_to_ssb_drv(sdev->dev->driver); 254 if (SSB_WARN_ON(!sdrv || !sdrv->probe)) 255 continue; 256 257 err = sdrv->probe(sdev, &sdev->id); 258 if (err) { 259 ssb_err("Failed to thaw device %s\n", 260 dev_name(sdev->dev)); 261 result = err; 262 } 263 ssb_device_put(sdev); 264 } 265 266 return result; 267 } 268 #endif /* CONFIG_SSB_SPROM */ 269 270 static void ssb_device_shutdown(struct device *dev) 271 { 272 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 273 struct ssb_driver *ssb_drv; 274 275 if (!dev->driver) 276 return; 277 ssb_drv = drv_to_ssb_drv(dev->driver); 278 if (ssb_drv && ssb_drv->shutdown) 279 ssb_drv->shutdown(ssb_dev); 280 } 281 282 static int ssb_device_remove(struct device *dev) 283 { 284 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 285 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 286 287 if (ssb_drv && ssb_drv->remove) 288 ssb_drv->remove(ssb_dev); 289 ssb_device_put(ssb_dev); 290 291 return 0; 292 } 293 294 static int ssb_device_probe(struct device *dev) 295 { 296 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 297 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); 298 int err = 0; 299 300 ssb_device_get(ssb_dev); 301 if (ssb_drv && ssb_drv->probe) 302 err = ssb_drv->probe(ssb_dev, &ssb_dev->id); 303 if (err) 304 ssb_device_put(ssb_dev); 305 306 return err; 307 } 308 309 static int ssb_match_devid(const struct ssb_device_id *tabid, 310 const struct ssb_device_id *devid) 311 { 312 if ((tabid->vendor != devid->vendor) && 313 tabid->vendor != SSB_ANY_VENDOR) 314 return 0; 315 if ((tabid->coreid != devid->coreid) && 316 tabid->coreid != SSB_ANY_ID) 317 return 0; 318 if ((tabid->revision != devid->revision) && 319 tabid->revision != SSB_ANY_REV) 320 return 0; 321 return 1; 322 } 323 324 static int ssb_bus_match(struct device *dev, struct device_driver *drv) 325 { 326 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 327 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv); 328 const struct ssb_device_id *id; 329 330 for (id = ssb_drv->id_table; 331 id->vendor || id->coreid || id->revision; 332 id++) { 333 if (ssb_match_devid(id, &ssb_dev->id)) 334 return 1; /* found */ 335 } 336 337 return 0; 338 } 339 340 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env) 341 { 342 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); 343 344 if (!dev) 345 return -ENODEV; 346 347 return add_uevent_var(env, 348 "MODALIAS=ssb:v%04Xid%04Xrev%02X", 349 ssb_dev->id.vendor, ssb_dev->id.coreid, 350 ssb_dev->id.revision); 351 } 352 353 #define ssb_config_attr(attrib, field, format_string) \ 354 static ssize_t \ 355 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \ 356 { \ 357 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \ 358 } \ 359 static DEVICE_ATTR_RO(attrib); 360 361 ssb_config_attr(core_num, core_index, "%u\n") 362 ssb_config_attr(coreid, id.coreid, "0x%04x\n") 363 ssb_config_attr(vendor, id.vendor, "0x%04x\n") 364 ssb_config_attr(revision, id.revision, "%u\n") 365 ssb_config_attr(irq, irq, "%u\n") 366 static ssize_t 367 name_show(struct device *dev, struct device_attribute *attr, char *buf) 368 { 369 return sprintf(buf, "%s\n", 370 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid)); 371 } 372 static DEVICE_ATTR_RO(name); 373 374 static struct attribute *ssb_device_attrs[] = { 375 &dev_attr_name.attr, 376 &dev_attr_core_num.attr, 377 &dev_attr_coreid.attr, 378 &dev_attr_vendor.attr, 379 &dev_attr_revision.attr, 380 &dev_attr_irq.attr, 381 NULL, 382 }; 383 ATTRIBUTE_GROUPS(ssb_device); 384 385 static struct bus_type ssb_bustype = { 386 .name = "ssb", 387 .match = ssb_bus_match, 388 .probe = ssb_device_probe, 389 .remove = ssb_device_remove, 390 .shutdown = ssb_device_shutdown, 391 .suspend = ssb_device_suspend, 392 .resume = ssb_device_resume, 393 .uevent = ssb_device_uevent, 394 .dev_groups = ssb_device_groups, 395 }; 396 397 static void ssb_buses_lock(void) 398 { 399 /* See the comment at the ssb_is_early_boot definition */ 400 if (!ssb_is_early_boot) 401 mutex_lock(&buses_mutex); 402 } 403 404 static void ssb_buses_unlock(void) 405 { 406 /* See the comment at the ssb_is_early_boot definition */ 407 if (!ssb_is_early_boot) 408 mutex_unlock(&buses_mutex); 409 } 410 411 static void ssb_devices_unregister(struct ssb_bus *bus) 412 { 413 struct ssb_device *sdev; 414 int i; 415 416 for (i = bus->nr_devices - 1; i >= 0; i--) { 417 sdev = &(bus->devices[i]); 418 if (sdev->dev) 419 device_unregister(sdev->dev); 420 } 421 422 #ifdef CONFIG_SSB_EMBEDDED 423 if (bus->bustype == SSB_BUSTYPE_SSB) 424 platform_device_unregister(bus->watchdog); 425 #endif 426 } 427 428 void ssb_bus_unregister(struct ssb_bus *bus) 429 { 430 int err; 431 432 err = ssb_gpio_unregister(bus); 433 if (err == -EBUSY) 434 ssb_dbg("Some GPIOs are still in use\n"); 435 else if (err) 436 ssb_dbg("Can not unregister GPIO driver: %i\n", err); 437 438 ssb_buses_lock(); 439 ssb_devices_unregister(bus); 440 list_del(&bus->list); 441 ssb_buses_unlock(); 442 443 ssb_pcmcia_exit(bus); 444 ssb_pci_exit(bus); 445 ssb_iounmap(bus); 446 } 447 EXPORT_SYMBOL(ssb_bus_unregister); 448 449 static void ssb_release_dev(struct device *dev) 450 { 451 struct __ssb_dev_wrapper *devwrap; 452 453 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev); 454 kfree(devwrap); 455 } 456 457 static int ssb_devices_register(struct ssb_bus *bus) 458 { 459 struct ssb_device *sdev; 460 struct device *dev; 461 struct __ssb_dev_wrapper *devwrap; 462 int i, err = 0; 463 int dev_idx = 0; 464 465 for (i = 0; i < bus->nr_devices; i++) { 466 sdev = &(bus->devices[i]); 467 468 /* We don't register SSB-system devices to the kernel, 469 * as the drivers for them are built into SSB. */ 470 switch (sdev->id.coreid) { 471 case SSB_DEV_CHIPCOMMON: 472 case SSB_DEV_PCI: 473 case SSB_DEV_PCIE: 474 case SSB_DEV_PCMCIA: 475 case SSB_DEV_MIPS: 476 case SSB_DEV_MIPS_3302: 477 case SSB_DEV_EXTIF: 478 continue; 479 } 480 481 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL); 482 if (!devwrap) { 483 err = -ENOMEM; 484 goto error; 485 } 486 dev = &devwrap->dev; 487 devwrap->sdev = sdev; 488 489 dev->release = ssb_release_dev; 490 dev->bus = &ssb_bustype; 491 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx); 492 493 switch (bus->bustype) { 494 case SSB_BUSTYPE_PCI: 495 #ifdef CONFIG_SSB_PCIHOST 496 sdev->irq = bus->host_pci->irq; 497 dev->parent = &bus->host_pci->dev; 498 sdev->dma_dev = dev->parent; 499 #endif 500 break; 501 case SSB_BUSTYPE_PCMCIA: 502 #ifdef CONFIG_SSB_PCMCIAHOST 503 sdev->irq = bus->host_pcmcia->irq; 504 dev->parent = &bus->host_pcmcia->dev; 505 #endif 506 break; 507 case SSB_BUSTYPE_SDIO: 508 #ifdef CONFIG_SSB_SDIOHOST 509 dev->parent = &bus->host_sdio->dev; 510 #endif 511 break; 512 case SSB_BUSTYPE_SSB: 513 dev->dma_mask = &dev->coherent_dma_mask; 514 sdev->dma_dev = dev; 515 break; 516 } 517 518 sdev->dev = dev; 519 err = device_register(dev); 520 if (err) { 521 ssb_err("Could not register %s\n", dev_name(dev)); 522 /* Set dev to NULL to not unregister 523 * dev on error unwinding. */ 524 sdev->dev = NULL; 525 put_device(dev); 526 goto error; 527 } 528 dev_idx++; 529 } 530 531 #ifdef CONFIG_SSB_DRIVER_MIPS 532 if (bus->mipscore.pflash.present) { 533 err = platform_device_register(&ssb_pflash_dev); 534 if (err) 535 pr_err("Error registering parallel flash\n"); 536 } 537 #endif 538 539 #ifdef CONFIG_SSB_SFLASH 540 if (bus->mipscore.sflash.present) { 541 err = platform_device_register(&ssb_sflash_dev); 542 if (err) 543 pr_err("Error registering serial flash\n"); 544 } 545 #endif 546 547 return 0; 548 error: 549 /* Unwind the already registered devices. */ 550 ssb_devices_unregister(bus); 551 return err; 552 } 553 554 /* Needs ssb_buses_lock() */ 555 static int ssb_attach_queued_buses(void) 556 { 557 struct ssb_bus *bus, *n; 558 int err = 0; 559 int drop_them_all = 0; 560 561 list_for_each_entry_safe(bus, n, &attach_queue, list) { 562 if (drop_them_all) { 563 list_del(&bus->list); 564 continue; 565 } 566 /* Can't init the PCIcore in ssb_bus_register(), as that 567 * is too early in boot for embedded systems 568 * (no udelay() available). So do it here in attach stage. 569 */ 570 err = ssb_bus_powerup(bus, 0); 571 if (err) 572 goto error; 573 ssb_pcicore_init(&bus->pcicore); 574 if (bus->bustype == SSB_BUSTYPE_SSB) 575 ssb_watchdog_register(bus); 576 577 err = ssb_gpio_init(bus); 578 if (err == -ENOTSUPP) 579 ssb_dbg("GPIO driver not activated\n"); 580 else if (err) 581 ssb_dbg("Error registering GPIO driver: %i\n", err); 582 583 ssb_bus_may_powerdown(bus); 584 585 err = ssb_devices_register(bus); 586 error: 587 if (err) { 588 drop_them_all = 1; 589 list_del(&bus->list); 590 continue; 591 } 592 list_move_tail(&bus->list, &buses); 593 } 594 595 return err; 596 } 597 598 static int ssb_fetch_invariants(struct ssb_bus *bus, 599 ssb_invariants_func_t get_invariants) 600 { 601 struct ssb_init_invariants iv; 602 int err; 603 604 memset(&iv, 0, sizeof(iv)); 605 err = get_invariants(bus, &iv); 606 if (err) 607 goto out; 608 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo)); 609 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom)); 610 bus->has_cardbus_slot = iv.has_cardbus_slot; 611 out: 612 return err; 613 } 614 615 static int __maybe_unused 616 ssb_bus_register(struct ssb_bus *bus, 617 ssb_invariants_func_t get_invariants, 618 unsigned long baseaddr) 619 { 620 int err; 621 622 spin_lock_init(&bus->bar_lock); 623 INIT_LIST_HEAD(&bus->list); 624 #ifdef CONFIG_SSB_EMBEDDED 625 spin_lock_init(&bus->gpio_lock); 626 #endif 627 628 /* Powerup the bus */ 629 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 630 if (err) 631 goto out; 632 633 /* Init SDIO-host device (if any), before the scan */ 634 err = ssb_sdio_init(bus); 635 if (err) 636 goto err_disable_xtal; 637 638 ssb_buses_lock(); 639 bus->busnumber = next_busnumber; 640 /* Scan for devices (cores) */ 641 err = ssb_bus_scan(bus, baseaddr); 642 if (err) 643 goto err_sdio_exit; 644 645 /* Init PCI-host device (if any) */ 646 err = ssb_pci_init(bus); 647 if (err) 648 goto err_unmap; 649 /* Init PCMCIA-host device (if any) */ 650 err = ssb_pcmcia_init(bus); 651 if (err) 652 goto err_pci_exit; 653 654 /* Initialize basic system devices (if available) */ 655 err = ssb_bus_powerup(bus, 0); 656 if (err) 657 goto err_pcmcia_exit; 658 ssb_chipcommon_init(&bus->chipco); 659 ssb_extif_init(&bus->extif); 660 ssb_mipscore_init(&bus->mipscore); 661 err = ssb_fetch_invariants(bus, get_invariants); 662 if (err) { 663 ssb_bus_may_powerdown(bus); 664 goto err_pcmcia_exit; 665 } 666 ssb_bus_may_powerdown(bus); 667 668 /* Queue it for attach. 669 * See the comment at the ssb_is_early_boot definition. */ 670 list_add_tail(&bus->list, &attach_queue); 671 if (!ssb_is_early_boot) { 672 /* This is not early boot, so we must attach the bus now */ 673 err = ssb_attach_queued_buses(); 674 if (err) 675 goto err_dequeue; 676 } 677 next_busnumber++; 678 ssb_buses_unlock(); 679 680 out: 681 return err; 682 683 err_dequeue: 684 list_del(&bus->list); 685 err_pcmcia_exit: 686 ssb_pcmcia_exit(bus); 687 err_pci_exit: 688 ssb_pci_exit(bus); 689 err_unmap: 690 ssb_iounmap(bus); 691 err_sdio_exit: 692 ssb_sdio_exit(bus); 693 err_disable_xtal: 694 ssb_buses_unlock(); 695 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 696 return err; 697 } 698 699 #ifdef CONFIG_SSB_PCIHOST 700 int ssb_bus_pcibus_register(struct ssb_bus *bus, struct pci_dev *host_pci) 701 { 702 int err; 703 704 bus->bustype = SSB_BUSTYPE_PCI; 705 bus->host_pci = host_pci; 706 bus->ops = &ssb_pci_ops; 707 708 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0); 709 if (!err) { 710 ssb_info("Sonics Silicon Backplane found on PCI device %s\n", 711 dev_name(&host_pci->dev)); 712 } else { 713 ssb_err("Failed to register PCI version of SSB with error %d\n", 714 err); 715 } 716 717 return err; 718 } 719 #endif /* CONFIG_SSB_PCIHOST */ 720 721 #ifdef CONFIG_SSB_PCMCIAHOST 722 int ssb_bus_pcmciabus_register(struct ssb_bus *bus, 723 struct pcmcia_device *pcmcia_dev, 724 unsigned long baseaddr) 725 { 726 int err; 727 728 bus->bustype = SSB_BUSTYPE_PCMCIA; 729 bus->host_pcmcia = pcmcia_dev; 730 bus->ops = &ssb_pcmcia_ops; 731 732 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr); 733 if (!err) { 734 ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n", 735 pcmcia_dev->devname); 736 } 737 738 return err; 739 } 740 #endif /* CONFIG_SSB_PCMCIAHOST */ 741 742 #ifdef CONFIG_SSB_SDIOHOST 743 int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func, 744 unsigned int quirks) 745 { 746 int err; 747 748 bus->bustype = SSB_BUSTYPE_SDIO; 749 bus->host_sdio = func; 750 bus->ops = &ssb_sdio_ops; 751 bus->quirks = quirks; 752 753 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0); 754 if (!err) { 755 ssb_info("Sonics Silicon Backplane found on SDIO device %s\n", 756 sdio_func_id(func)); 757 } 758 759 return err; 760 } 761 EXPORT_SYMBOL(ssb_bus_sdiobus_register); 762 #endif /* CONFIG_SSB_PCMCIAHOST */ 763 764 #ifdef CONFIG_SSB_HOST_SOC 765 int ssb_bus_host_soc_register(struct ssb_bus *bus, unsigned long baseaddr) 766 { 767 int err; 768 769 bus->bustype = SSB_BUSTYPE_SSB; 770 bus->ops = &ssb_host_soc_ops; 771 772 err = ssb_bus_register(bus, ssb_host_soc_get_invariants, baseaddr); 773 if (!err) { 774 ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n", 775 baseaddr); 776 } 777 778 return err; 779 } 780 #endif 781 782 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner) 783 { 784 drv->drv.name = drv->name; 785 drv->drv.bus = &ssb_bustype; 786 drv->drv.owner = owner; 787 788 return driver_register(&drv->drv); 789 } 790 EXPORT_SYMBOL(__ssb_driver_register); 791 792 void ssb_driver_unregister(struct ssb_driver *drv) 793 { 794 driver_unregister(&drv->drv); 795 } 796 EXPORT_SYMBOL(ssb_driver_unregister); 797 798 void ssb_set_devtypedata(struct ssb_device *dev, void *data) 799 { 800 struct ssb_bus *bus = dev->bus; 801 struct ssb_device *ent; 802 int i; 803 804 for (i = 0; i < bus->nr_devices; i++) { 805 ent = &(bus->devices[i]); 806 if (ent->id.vendor != dev->id.vendor) 807 continue; 808 if (ent->id.coreid != dev->id.coreid) 809 continue; 810 811 ent->devtypedata = data; 812 } 813 } 814 EXPORT_SYMBOL(ssb_set_devtypedata); 815 816 static u32 clkfactor_f6_resolve(u32 v) 817 { 818 /* map the magic values */ 819 switch (v) { 820 case SSB_CHIPCO_CLK_F6_2: 821 return 2; 822 case SSB_CHIPCO_CLK_F6_3: 823 return 3; 824 case SSB_CHIPCO_CLK_F6_4: 825 return 4; 826 case SSB_CHIPCO_CLK_F6_5: 827 return 5; 828 case SSB_CHIPCO_CLK_F6_6: 829 return 6; 830 case SSB_CHIPCO_CLK_F6_7: 831 return 7; 832 } 833 return 0; 834 } 835 836 /* Calculate the speed the backplane would run at a given set of clockcontrol values */ 837 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) 838 { 839 u32 n1, n2, clock, m1, m2, m3, mc; 840 841 n1 = (n & SSB_CHIPCO_CLK_N1); 842 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT); 843 844 switch (plltype) { 845 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ 846 if (m & SSB_CHIPCO_CLK_T6_MMASK) 847 return SSB_CHIPCO_CLK_T6_M1; 848 return SSB_CHIPCO_CLK_T6_M0; 849 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 850 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 851 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 852 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 853 n1 = clkfactor_f6_resolve(n1); 854 n2 += SSB_CHIPCO_CLK_F5_BIAS; 855 break; 856 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ 857 n1 += SSB_CHIPCO_CLK_T2_BIAS; 858 n2 += SSB_CHIPCO_CLK_T2_BIAS; 859 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7))); 860 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23))); 861 break; 862 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ 863 return 100000000; 864 default: 865 SSB_WARN_ON(1); 866 } 867 868 switch (plltype) { 869 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 870 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 871 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2; 872 break; 873 default: 874 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2; 875 } 876 if (!clock) 877 return 0; 878 879 m1 = (m & SSB_CHIPCO_CLK_M1); 880 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); 881 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT); 882 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT); 883 884 switch (plltype) { 885 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ 886 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 887 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ 888 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ 889 m1 = clkfactor_f6_resolve(m1); 890 if ((plltype == SSB_PLLTYPE_1) || 891 (plltype == SSB_PLLTYPE_3)) 892 m2 += SSB_CHIPCO_CLK_F5_BIAS; 893 else 894 m2 = clkfactor_f6_resolve(m2); 895 m3 = clkfactor_f6_resolve(m3); 896 897 switch (mc) { 898 case SSB_CHIPCO_CLK_MC_BYPASS: 899 return clock; 900 case SSB_CHIPCO_CLK_MC_M1: 901 return (clock / m1); 902 case SSB_CHIPCO_CLK_MC_M1M2: 903 return (clock / (m1 * m2)); 904 case SSB_CHIPCO_CLK_MC_M1M2M3: 905 return (clock / (m1 * m2 * m3)); 906 case SSB_CHIPCO_CLK_MC_M1M3: 907 return (clock / (m1 * m3)); 908 } 909 return 0; 910 case SSB_PLLTYPE_2: 911 m1 += SSB_CHIPCO_CLK_T2_BIAS; 912 m2 += SSB_CHIPCO_CLK_T2M2_BIAS; 913 m3 += SSB_CHIPCO_CLK_T2_BIAS; 914 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7))); 915 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10))); 916 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7))); 917 918 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP)) 919 clock /= m1; 920 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP)) 921 clock /= m2; 922 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP)) 923 clock /= m3; 924 return clock; 925 default: 926 SSB_WARN_ON(1); 927 } 928 return 0; 929 } 930 931 /* Get the current speed the backplane is running at */ 932 u32 ssb_clockspeed(struct ssb_bus *bus) 933 { 934 u32 rate; 935 u32 plltype; 936 u32 clkctl_n, clkctl_m; 937 938 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU) 939 return ssb_pmu_get_controlclock(&bus->chipco); 940 941 if (ssb_extif_available(&bus->extif)) 942 ssb_extif_get_clockcontrol(&bus->extif, &plltype, 943 &clkctl_n, &clkctl_m); 944 else if (bus->chipco.dev) 945 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype, 946 &clkctl_n, &clkctl_m); 947 else 948 return 0; 949 950 if (bus->chip_id == 0x5365) { 951 rate = 100000000; 952 } else { 953 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); 954 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ 955 rate /= 2; 956 } 957 958 return rate; 959 } 960 EXPORT_SYMBOL(ssb_clockspeed); 961 962 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev) 963 { 964 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; 965 966 /* The REJECT bit seems to be different for Backplane rev 2.3 */ 967 switch (rev) { 968 case SSB_IDLOW_SSBREV_22: 969 case SSB_IDLOW_SSBREV_24: 970 case SSB_IDLOW_SSBREV_26: 971 return SSB_TMSLOW_REJECT; 972 case SSB_IDLOW_SSBREV_23: 973 return SSB_TMSLOW_REJECT_23; 974 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */ 975 case SSB_IDLOW_SSBREV_27: /* same here */ 976 return SSB_TMSLOW_REJECT; /* this is a guess */ 977 case SSB_IDLOW_SSBREV: 978 break; 979 default: 980 WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); 981 } 982 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23); 983 } 984 985 int ssb_device_is_enabled(struct ssb_device *dev) 986 { 987 u32 val; 988 u32 reject; 989 990 reject = ssb_tmslow_reject_bitmask(dev); 991 val = ssb_read32(dev, SSB_TMSLOW); 992 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject; 993 994 return (val == SSB_TMSLOW_CLOCK); 995 } 996 EXPORT_SYMBOL(ssb_device_is_enabled); 997 998 static void ssb_flush_tmslow(struct ssb_device *dev) 999 { 1000 /* Make _really_ sure the device has finished the TMSLOW 1001 * register write transaction, as we risk running into 1002 * a machine check exception otherwise. 1003 * Do this by reading the register back to commit the 1004 * PCI write and delay an additional usec for the device 1005 * to react to the change. */ 1006 ssb_read32(dev, SSB_TMSLOW); 1007 udelay(1); 1008 } 1009 1010 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags) 1011 { 1012 u32 val; 1013 1014 ssb_device_disable(dev, core_specific_flags); 1015 ssb_write32(dev, SSB_TMSLOW, 1016 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK | 1017 SSB_TMSLOW_FGC | core_specific_flags); 1018 ssb_flush_tmslow(dev); 1019 1020 /* Clear SERR if set. This is a hw bug workaround. */ 1021 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR) 1022 ssb_write32(dev, SSB_TMSHIGH, 0); 1023 1024 val = ssb_read32(dev, SSB_IMSTATE); 1025 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { 1026 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); 1027 ssb_write32(dev, SSB_IMSTATE, val); 1028 } 1029 1030 ssb_write32(dev, SSB_TMSLOW, 1031 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC | 1032 core_specific_flags); 1033 ssb_flush_tmslow(dev); 1034 1035 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK | 1036 core_specific_flags); 1037 ssb_flush_tmslow(dev); 1038 } 1039 EXPORT_SYMBOL(ssb_device_enable); 1040 1041 /* Wait for bitmask in a register to get set or cleared. 1042 * timeout is in units of ten-microseconds */ 1043 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask, 1044 int timeout, int set) 1045 { 1046 int i; 1047 u32 val; 1048 1049 for (i = 0; i < timeout; i++) { 1050 val = ssb_read32(dev, reg); 1051 if (set) { 1052 if ((val & bitmask) == bitmask) 1053 return 0; 1054 } else { 1055 if (!(val & bitmask)) 1056 return 0; 1057 } 1058 udelay(10); 1059 } 1060 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on " 1061 "register %04X to %s.\n", 1062 bitmask, reg, (set ? "set" : "clear")); 1063 1064 return -ETIMEDOUT; 1065 } 1066 1067 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) 1068 { 1069 u32 reject, val; 1070 1071 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) 1072 return; 1073 1074 reject = ssb_tmslow_reject_bitmask(dev); 1075 1076 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) { 1077 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); 1078 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1); 1079 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); 1080 1081 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1082 val = ssb_read32(dev, SSB_IMSTATE); 1083 val |= SSB_IMSTATE_REJECT; 1084 ssb_write32(dev, SSB_IMSTATE, val); 1085 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000, 1086 0); 1087 } 1088 1089 ssb_write32(dev, SSB_TMSLOW, 1090 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | 1091 reject | SSB_TMSLOW_RESET | 1092 core_specific_flags); 1093 ssb_flush_tmslow(dev); 1094 1095 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) { 1096 val = ssb_read32(dev, SSB_IMSTATE); 1097 val &= ~SSB_IMSTATE_REJECT; 1098 ssb_write32(dev, SSB_IMSTATE, val); 1099 } 1100 } 1101 1102 ssb_write32(dev, SSB_TMSLOW, 1103 reject | SSB_TMSLOW_RESET | 1104 core_specific_flags); 1105 ssb_flush_tmslow(dev); 1106 } 1107 EXPORT_SYMBOL(ssb_device_disable); 1108 1109 /* Some chipsets need routing known for PCIe and 64-bit DMA */ 1110 static bool ssb_dma_translation_special_bit(struct ssb_device *dev) 1111 { 1112 u16 chip_id = dev->bus->chip_id; 1113 1114 if (dev->id.coreid == SSB_DEV_80211) { 1115 return (chip_id == 0x4322 || chip_id == 43221 || 1116 chip_id == 43231 || chip_id == 43222); 1117 } 1118 1119 return false; 1120 } 1121 1122 u32 ssb_dma_translation(struct ssb_device *dev) 1123 { 1124 switch (dev->bus->bustype) { 1125 case SSB_BUSTYPE_SSB: 1126 return 0; 1127 case SSB_BUSTYPE_PCI: 1128 if (pci_is_pcie(dev->bus->host_pci) && 1129 ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) { 1130 return SSB_PCIE_DMA_H32; 1131 } else { 1132 if (ssb_dma_translation_special_bit(dev)) 1133 return SSB_PCIE_DMA_H32; 1134 else 1135 return SSB_PCI_DMA; 1136 } 1137 default: 1138 __ssb_dma_not_implemented(dev); 1139 } 1140 return 0; 1141 } 1142 EXPORT_SYMBOL(ssb_dma_translation); 1143 1144 int ssb_bus_may_powerdown(struct ssb_bus *bus) 1145 { 1146 struct ssb_chipcommon *cc; 1147 int err = 0; 1148 1149 /* On buses where more than one core may be working 1150 * at a time, we must not powerdown stuff if there are 1151 * still cores that may want to run. */ 1152 if (bus->bustype == SSB_BUSTYPE_SSB) 1153 goto out; 1154 1155 cc = &bus->chipco; 1156 1157 if (!cc->dev) 1158 goto out; 1159 if (cc->dev->id.revision < 5) 1160 goto out; 1161 1162 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); 1163 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); 1164 if (err) 1165 goto error; 1166 out: 1167 #ifdef CONFIG_SSB_DEBUG 1168 bus->powered_up = 0; 1169 #endif 1170 return err; 1171 error: 1172 ssb_err("Bus powerdown failed\n"); 1173 goto out; 1174 } 1175 EXPORT_SYMBOL(ssb_bus_may_powerdown); 1176 1177 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) 1178 { 1179 int err; 1180 enum ssb_clkmode mode; 1181 1182 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); 1183 if (err) 1184 goto error; 1185 1186 #ifdef CONFIG_SSB_DEBUG 1187 bus->powered_up = 1; 1188 #endif 1189 1190 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; 1191 ssb_chipco_set_clockmode(&bus->chipco, mode); 1192 1193 return 0; 1194 error: 1195 ssb_err("Bus powerup failed\n"); 1196 return err; 1197 } 1198 EXPORT_SYMBOL(ssb_bus_powerup); 1199 1200 static void ssb_broadcast_value(struct ssb_device *dev, 1201 u32 address, u32 data) 1202 { 1203 #ifdef CONFIG_SSB_DRIVER_PCICORE 1204 /* This is used for both, PCI and ChipCommon core, so be careful. */ 1205 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); 1206 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); 1207 #endif 1208 1209 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address); 1210 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */ 1211 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data); 1212 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */ 1213 } 1214 1215 void ssb_commit_settings(struct ssb_bus *bus) 1216 { 1217 struct ssb_device *dev; 1218 1219 #ifdef CONFIG_SSB_DRIVER_PCICORE 1220 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; 1221 #else 1222 dev = bus->chipco.dev; 1223 #endif 1224 if (WARN_ON(!dev)) 1225 return; 1226 /* This forces an update of the cached registers. */ 1227 ssb_broadcast_value(dev, 0xFD8, 0); 1228 } 1229 EXPORT_SYMBOL(ssb_commit_settings); 1230 1231 u32 ssb_admatch_base(u32 adm) 1232 { 1233 u32 base = 0; 1234 1235 switch (adm & SSB_ADM_TYPE) { 1236 case SSB_ADM_TYPE0: 1237 base = (adm & SSB_ADM_BASE0); 1238 break; 1239 case SSB_ADM_TYPE1: 1240 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1241 base = (adm & SSB_ADM_BASE1); 1242 break; 1243 case SSB_ADM_TYPE2: 1244 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1245 base = (adm & SSB_ADM_BASE2); 1246 break; 1247 default: 1248 SSB_WARN_ON(1); 1249 } 1250 1251 return base; 1252 } 1253 EXPORT_SYMBOL(ssb_admatch_base); 1254 1255 u32 ssb_admatch_size(u32 adm) 1256 { 1257 u32 size = 0; 1258 1259 switch (adm & SSB_ADM_TYPE) { 1260 case SSB_ADM_TYPE0: 1261 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT); 1262 break; 1263 case SSB_ADM_TYPE1: 1264 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1265 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT); 1266 break; 1267 case SSB_ADM_TYPE2: 1268 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ 1269 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT); 1270 break; 1271 default: 1272 SSB_WARN_ON(1); 1273 } 1274 size = (1 << (size + 1)); 1275 1276 return size; 1277 } 1278 EXPORT_SYMBOL(ssb_admatch_size); 1279 1280 static int __init ssb_modinit(void) 1281 { 1282 int err; 1283 1284 /* See the comment at the ssb_is_early_boot definition */ 1285 ssb_is_early_boot = 0; 1286 err = bus_register(&ssb_bustype); 1287 if (err) 1288 return err; 1289 1290 /* Maybe we already registered some buses at early boot. 1291 * Check for this and attach them 1292 */ 1293 ssb_buses_lock(); 1294 err = ssb_attach_queued_buses(); 1295 ssb_buses_unlock(); 1296 if (err) { 1297 bus_unregister(&ssb_bustype); 1298 goto out; 1299 } 1300 1301 err = b43_pci_ssb_bridge_init(); 1302 if (err) { 1303 ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n"); 1304 /* don't fail SSB init because of this */ 1305 err = 0; 1306 } 1307 err = ssb_host_pcmcia_init(); 1308 if (err) { 1309 ssb_err("PCMCIA host initialization failed\n"); 1310 /* don't fail SSB init because of this */ 1311 err = 0; 1312 } 1313 err = ssb_gige_init(); 1314 if (err) { 1315 ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n"); 1316 /* don't fail SSB init because of this */ 1317 err = 0; 1318 } 1319 out: 1320 return err; 1321 } 1322 /* ssb must be initialized after PCI but before the ssb drivers. 1323 * That means we must use some initcall between subsys_initcall 1324 * and device_initcall. */ 1325 fs_initcall(ssb_modinit); 1326 1327 static void __exit ssb_modexit(void) 1328 { 1329 ssb_gige_exit(); 1330 ssb_host_pcmcia_exit(); 1331 b43_pci_ssb_bridge_exit(); 1332 bus_unregister(&ssb_bustype); 1333 } 1334 module_exit(ssb_modexit) 1335