1 /* 2 * Sonics Silicon Backplane 3 * Broadcom PCI-core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include <linux/ssb/ssb.h> 12 #include <linux/pci.h> 13 #include <linux/delay.h> 14 #include <linux/ssb/ssb_embedded.h> 15 16 #include "ssb_private.h" 17 18 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address); 19 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data); 20 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address); 21 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, 22 u8 address, u16 data); 23 24 static void ssb_commit_settings(struct ssb_bus *bus); 25 26 static inline 27 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) 28 { 29 return ssb_read32(pc->dev, offset); 30 } 31 32 static inline 33 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value) 34 { 35 ssb_write32(pc->dev, offset, value); 36 } 37 38 static inline 39 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset) 40 { 41 return ssb_read16(pc->dev, offset); 42 } 43 44 static inline 45 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value) 46 { 47 ssb_write16(pc->dev, offset, value); 48 } 49 50 /************************************************** 51 * Code for hostmode operation. 52 **************************************************/ 53 54 #ifdef CONFIG_SSB_PCICORE_HOSTMODE 55 56 #include <asm/paccess.h> 57 /* Probe a 32bit value on the bus and catch bus exceptions. 58 * Returns nonzero on a bus exception. 59 * This is MIPS specific */ 60 #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) 61 62 /* Assume one-hot slot wiring */ 63 #define SSB_PCI_SLOT_MAX 16 64 65 /* Global lock is OK, as we won't have more than one extpci anyway. */ 66 static DEFINE_SPINLOCK(cfgspace_lock); 67 /* Core to access the external PCI config space. Can only have one. */ 68 static struct ssb_pcicore *extpci_core; 69 70 71 static u32 get_cfgspace_addr(struct ssb_pcicore *pc, 72 unsigned int bus, unsigned int dev, 73 unsigned int func, unsigned int off) 74 { 75 u32 addr = 0; 76 u32 tmp; 77 78 /* We do only have one cardbus device behind the bridge. */ 79 if (pc->cardbusmode && (dev >= 1)) 80 goto out; 81 82 if (bus == 0) { 83 /* Type 0 transaction */ 84 if (unlikely(dev >= SSB_PCI_SLOT_MAX)) 85 goto out; 86 /* Slide the window */ 87 tmp = SSB_PCICORE_SBTOPCI_CFG0; 88 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK); 89 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp); 90 /* Calculate the address */ 91 addr = SSB_PCI_CFG; 92 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK); 93 addr |= (func << 8); 94 addr |= (off & ~3); 95 } else { 96 /* Type 1 transaction */ 97 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, 98 SSB_PCICORE_SBTOPCI_CFG1); 99 /* Calculate the address */ 100 addr = SSB_PCI_CFG; 101 addr |= (bus << 16); 102 addr |= (dev << 11); 103 addr |= (func << 8); 104 addr |= (off & ~3); 105 } 106 out: 107 return addr; 108 } 109 110 static int ssb_extpci_read_config(struct ssb_pcicore *pc, 111 unsigned int bus, unsigned int dev, 112 unsigned int func, unsigned int off, 113 void *buf, int len) 114 { 115 int err = -EINVAL; 116 u32 addr, val; 117 void __iomem *mmio; 118 119 SSB_WARN_ON(!pc->hostmode); 120 if (unlikely(len != 1 && len != 2 && len != 4)) 121 goto out; 122 addr = get_cfgspace_addr(pc, bus, dev, func, off); 123 if (unlikely(!addr)) 124 goto out; 125 err = -ENOMEM; 126 mmio = ioremap_nocache(addr, len); 127 if (!mmio) 128 goto out; 129 130 if (mips_busprobe32(val, mmio)) { 131 val = 0xffffffff; 132 goto unmap; 133 } 134 135 val = readl(mmio); 136 val >>= (8 * (off & 3)); 137 138 switch (len) { 139 case 1: 140 *((u8 *)buf) = (u8)val; 141 break; 142 case 2: 143 *((u16 *)buf) = (u16)val; 144 break; 145 case 4: 146 *((u32 *)buf) = (u32)val; 147 break; 148 } 149 err = 0; 150 unmap: 151 iounmap(mmio); 152 out: 153 return err; 154 } 155 156 static int ssb_extpci_write_config(struct ssb_pcicore *pc, 157 unsigned int bus, unsigned int dev, 158 unsigned int func, unsigned int off, 159 const void *buf, int len) 160 { 161 int err = -EINVAL; 162 u32 addr, val = 0; 163 void __iomem *mmio; 164 165 SSB_WARN_ON(!pc->hostmode); 166 if (unlikely(len != 1 && len != 2 && len != 4)) 167 goto out; 168 addr = get_cfgspace_addr(pc, bus, dev, func, off); 169 if (unlikely(!addr)) 170 goto out; 171 err = -ENOMEM; 172 mmio = ioremap_nocache(addr, len); 173 if (!mmio) 174 goto out; 175 176 if (mips_busprobe32(val, mmio)) { 177 val = 0xffffffff; 178 goto unmap; 179 } 180 181 switch (len) { 182 case 1: 183 val = readl(mmio); 184 val &= ~(0xFF << (8 * (off & 3))); 185 val |= *((const u8 *)buf) << (8 * (off & 3)); 186 break; 187 case 2: 188 val = readl(mmio); 189 val &= ~(0xFFFF << (8 * (off & 3))); 190 val |= *((const u16 *)buf) << (8 * (off & 3)); 191 break; 192 case 4: 193 val = *((const u32 *)buf); 194 break; 195 } 196 writel(val, mmio); 197 198 err = 0; 199 unmap: 200 iounmap(mmio); 201 out: 202 return err; 203 } 204 205 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn, 206 int reg, int size, u32 *val) 207 { 208 unsigned long flags; 209 int err; 210 211 spin_lock_irqsave(&cfgspace_lock, flags); 212 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn), 213 PCI_FUNC(devfn), reg, val, size); 214 spin_unlock_irqrestore(&cfgspace_lock, flags); 215 216 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 217 } 218 219 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn, 220 int reg, int size, u32 val) 221 { 222 unsigned long flags; 223 int err; 224 225 spin_lock_irqsave(&cfgspace_lock, flags); 226 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn), 227 PCI_FUNC(devfn), reg, &val, size); 228 spin_unlock_irqrestore(&cfgspace_lock, flags); 229 230 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 231 } 232 233 static struct pci_ops ssb_pcicore_pciops = { 234 .read = ssb_pcicore_read_config, 235 .write = ssb_pcicore_write_config, 236 }; 237 238 static struct resource ssb_pcicore_mem_resource = { 239 .name = "SSB PCIcore external memory", 240 .start = SSB_PCI_DMA, 241 .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1, 242 .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED, 243 }; 244 245 static struct resource ssb_pcicore_io_resource = { 246 .name = "SSB PCIcore external I/O", 247 .start = 0x100, 248 .end = 0x7FF, 249 .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED, 250 }; 251 252 static struct pci_controller ssb_pcicore_controller = { 253 .pci_ops = &ssb_pcicore_pciops, 254 .io_resource = &ssb_pcicore_io_resource, 255 .mem_resource = &ssb_pcicore_mem_resource, 256 }; 257 258 /* This function is called when doing a pci_enable_device(). 259 * We must first check if the device is a device on the PCI-core bridge. */ 260 int ssb_pcicore_plat_dev_init(struct pci_dev *d) 261 { 262 if (d->bus->ops != &ssb_pcicore_pciops) { 263 /* This is not a device on the PCI-core bridge. */ 264 return -ENODEV; 265 } 266 267 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", 268 pci_name(d)); 269 270 /* Fix up interrupt lines */ 271 d->irq = ssb_mips_irq(extpci_core->dev) + 2; 272 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); 273 274 return 0; 275 } 276 277 /* Early PCI fixup for a device on the PCI-core bridge. */ 278 static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev) 279 { 280 u8 lat; 281 282 if (dev->bus->ops != &ssb_pcicore_pciops) { 283 /* This is not a device on the PCI-core bridge. */ 284 return; 285 } 286 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0) 287 return; 288 289 ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev)); 290 291 /* Enable PCI bridge bus mastering and memory space */ 292 pci_set_master(dev); 293 if (pcibios_enable_device(dev, ~0) < 0) { 294 ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n"); 295 return; 296 } 297 298 /* Enable PCI bridge BAR1 prefetch and burst */ 299 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3); 300 301 /* Make sure our latency is high enough to handle the devices behind us */ 302 lat = 168; 303 ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n", 304 pci_name(dev), lat); 305 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 306 } 307 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge); 308 309 /* PCI device IRQ mapping. */ 310 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 311 { 312 if (dev->bus->ops != &ssb_pcicore_pciops) { 313 /* This is not a device on the PCI-core bridge. */ 314 return -ENODEV; 315 } 316 return ssb_mips_irq(extpci_core->dev) + 2; 317 } 318 319 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) 320 { 321 u32 val; 322 323 if (WARN_ON(extpci_core)) 324 return; 325 extpci_core = pc; 326 327 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n"); 328 /* Reset devices on the external PCI bus */ 329 val = SSB_PCICORE_CTL_RST_OE; 330 val |= SSB_PCICORE_CTL_CLK_OE; 331 pcicore_write32(pc, SSB_PCICORE_CTL, val); 332 val |= SSB_PCICORE_CTL_CLK; /* Clock on */ 333 pcicore_write32(pc, SSB_PCICORE_CTL, val); 334 udelay(150); /* Assertion time demanded by the PCI standard */ 335 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */ 336 pcicore_write32(pc, SSB_PCICORE_CTL, val); 337 val = SSB_PCICORE_ARBCTL_INTERN; 338 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); 339 udelay(1); /* Assertion time demanded by the PCI standard */ 340 341 if (pc->dev->bus->has_cardbus_slot) { 342 ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n"); 343 pc->cardbusmode = 1; 344 /* GPIO 1 resets the bridge */ 345 ssb_gpio_out(pc->dev->bus, 1, 1); 346 ssb_gpio_outen(pc->dev->bus, 1, 1); 347 pcicore_write16(pc, SSB_PCICORE_SPROM(0), 348 pcicore_read16(pc, SSB_PCICORE_SPROM(0)) 349 | 0x0400); 350 } 351 352 /* 64MB I/O window */ 353 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0, 354 SSB_PCICORE_SBTOPCI_IO); 355 /* 64MB config space */ 356 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, 357 SSB_PCICORE_SBTOPCI_CFG0); 358 /* 1GB memory window */ 359 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, 360 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); 361 362 /* Enable PCI bridge BAR0 prefetch and burst */ 363 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 364 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); 365 /* Clear error conditions */ 366 val = 0; 367 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2); 368 369 /* Enable PCI interrupts */ 370 pcicore_write32(pc, SSB_PCICORE_IMASK, 371 SSB_PCICORE_IMASK_INTA); 372 373 /* Ok, ready to run, register it to the system. 374 * The following needs change, if we want to port hostmode 375 * to non-MIPS platform. */ 376 ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000); 377 set_io_port_base(ssb_pcicore_controller.io_map_base); 378 /* Give some time to the PCI controller to configure itself with the new 379 * values. Not waiting at this point causes crashes of the machine. */ 380 mdelay(10); 381 register_pci_controller(&ssb_pcicore_controller); 382 } 383 384 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc) 385 { 386 struct ssb_bus *bus = pc->dev->bus; 387 u16 chipid_top; 388 u32 tmp; 389 390 chipid_top = (bus->chip_id & 0xFF00); 391 if (chipid_top != 0x4700 && 392 chipid_top != 0x5300) 393 return 0; 394 395 if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI) 396 return 0; 397 398 /* The 200-pin BCM4712 package does not bond out PCI. Even when 399 * PCI is bonded out, some boards may leave the pins floating. */ 400 if (bus->chip_id == 0x4712) { 401 if (bus->chip_package == SSB_CHIPPACK_BCM4712S) 402 return 0; 403 if (bus->chip_package == SSB_CHIPPACK_BCM4712M) 404 return 0; 405 } 406 if (bus->chip_id == 0x5350) 407 return 0; 408 409 return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE))); 410 } 411 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ 412 413 /************************************************** 414 * Workarounds. 415 **************************************************/ 416 417 static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc) 418 { 419 u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0)); 420 if (((tmp & 0xF000) >> 12) != pc->dev->core_index) { 421 tmp &= ~0xF000; 422 tmp |= (pc->dev->core_index << 12); 423 pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp); 424 } 425 } 426 427 static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc) 428 { 429 return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80; 430 } 431 432 static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc) 433 { 434 const u8 serdes_pll_device = 0x1D; 435 const u8 serdes_rx_device = 0x1F; 436 u16 tmp; 437 438 ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */, 439 ssb_pcicore_polarity_workaround(pc)); 440 tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */); 441 if (tmp & 0x4000) 442 ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000); 443 } 444 445 static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc) 446 { 447 struct ssb_device *pdev = pc->dev; 448 struct ssb_bus *bus = pdev->bus; 449 u32 tmp; 450 451 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); 452 tmp |= SSB_PCICORE_SBTOPCI_PREF; 453 tmp |= SSB_PCICORE_SBTOPCI_BURST; 454 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); 455 456 if (pdev->id.revision < 5) { 457 tmp = ssb_read32(pdev, SSB_IMCFGLO); 458 tmp &= ~SSB_IMCFGLO_SERTO; 459 tmp |= 2; 460 tmp &= ~SSB_IMCFGLO_REQTO; 461 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT; 462 ssb_write32(pdev, SSB_IMCFGLO, tmp); 463 ssb_commit_settings(bus); 464 } else if (pdev->id.revision >= 11) { 465 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); 466 tmp |= SSB_PCICORE_SBTOPCI_MRM; 467 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); 468 } 469 } 470 471 static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc) 472 { 473 u32 tmp; 474 u8 rev = pc->dev->id.revision; 475 476 if (rev == 0 || rev == 1) { 477 /* TLP Workaround register. */ 478 tmp = ssb_pcie_read(pc, 0x4); 479 tmp |= 0x8; 480 ssb_pcie_write(pc, 0x4, tmp); 481 } 482 if (rev == 1) { 483 /* DLLP Link Control register. */ 484 tmp = ssb_pcie_read(pc, 0x100); 485 tmp |= 0x40; 486 ssb_pcie_write(pc, 0x100, tmp); 487 } 488 489 if (rev == 0) { 490 const u8 serdes_rx_device = 0x1F; 491 492 ssb_pcie_mdio_write(pc, serdes_rx_device, 493 2 /* Timer */, 0x8128); 494 ssb_pcie_mdio_write(pc, serdes_rx_device, 495 6 /* CDR */, 0x0100); 496 ssb_pcie_mdio_write(pc, serdes_rx_device, 497 7 /* CDR BW */, 0x1466); 498 } else if (rev == 3 || rev == 4 || rev == 5) { 499 /* TODO: DLLP Power Management Threshold */ 500 ssb_pcicore_serdes_workaround(pc); 501 /* TODO: ASPM */ 502 } else if (rev == 7) { 503 /* TODO: No PLL down */ 504 } 505 506 if (rev >= 6) { 507 /* Miscellaneous Configuration Fixup */ 508 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5)); 509 if (!(tmp & 0x8000)) 510 pcicore_write16(pc, SSB_PCICORE_SPROM(5), 511 tmp | 0x8000); 512 } 513 } 514 515 /************************************************** 516 * Generic and Clientmode operation code. 517 **************************************************/ 518 519 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) 520 { 521 /* Disable PCI interrupts. */ 522 ssb_write32(pc->dev, SSB_INTVEC, 0); 523 } 524 525 void ssb_pcicore_init(struct ssb_pcicore *pc) 526 { 527 struct ssb_device *dev = pc->dev; 528 529 if (!dev) 530 return; 531 if (!ssb_device_is_enabled(dev)) 532 ssb_device_enable(dev, 0); 533 534 ssb_pcicore_fix_sprom_core_index(pc); 535 536 #ifdef CONFIG_SSB_PCICORE_HOSTMODE 537 pc->hostmode = pcicore_is_in_hostmode(pc); 538 if (pc->hostmode) 539 ssb_pcicore_init_hostmode(pc); 540 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ 541 if (!pc->hostmode) 542 ssb_pcicore_init_clientmode(pc); 543 544 /* Additional always once-executed workarounds */ 545 ssb_pcicore_serdes_workaround(pc); 546 /* TODO: ASPM */ 547 /* TODO: Clock Request Update */ 548 } 549 550 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address) 551 { 552 pcicore_write32(pc, 0x130, address); 553 return pcicore_read32(pc, 0x134); 554 } 555 556 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data) 557 { 558 pcicore_write32(pc, 0x130, address); 559 pcicore_write32(pc, 0x134, data); 560 } 561 562 static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy) 563 { 564 const u16 mdio_control = 0x128; 565 const u16 mdio_data = 0x12C; 566 u32 v; 567 int i; 568 569 v = (1 << 30); /* Start of Transaction */ 570 v |= (1 << 28); /* Write Transaction */ 571 v |= (1 << 17); /* Turnaround */ 572 v |= (0x1F << 18); 573 v |= (phy << 4); 574 pcicore_write32(pc, mdio_data, v); 575 576 udelay(10); 577 for (i = 0; i < 200; i++) { 578 v = pcicore_read32(pc, mdio_control); 579 if (v & 0x100 /* Trans complete */) 580 break; 581 msleep(1); 582 } 583 } 584 585 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address) 586 { 587 const u16 mdio_control = 0x128; 588 const u16 mdio_data = 0x12C; 589 int max_retries = 10; 590 u16 ret = 0; 591 u32 v; 592 int i; 593 594 v = 0x80; /* Enable Preamble Sequence */ 595 v |= 0x2; /* MDIO Clock Divisor */ 596 pcicore_write32(pc, mdio_control, v); 597 598 if (pc->dev->id.revision >= 10) { 599 max_retries = 200; 600 ssb_pcie_mdio_set_phy(pc, device); 601 } 602 603 v = (1 << 30); /* Start of Transaction */ 604 v |= (1 << 29); /* Read Transaction */ 605 v |= (1 << 17); /* Turnaround */ 606 if (pc->dev->id.revision < 10) 607 v |= (u32)device << 22; 608 v |= (u32)address << 18; 609 pcicore_write32(pc, mdio_data, v); 610 /* Wait for the device to complete the transaction */ 611 udelay(10); 612 for (i = 0; i < max_retries; i++) { 613 v = pcicore_read32(pc, mdio_control); 614 if (v & 0x100 /* Trans complete */) { 615 udelay(10); 616 ret = pcicore_read32(pc, mdio_data); 617 break; 618 } 619 msleep(1); 620 } 621 pcicore_write32(pc, mdio_control, 0); 622 return ret; 623 } 624 625 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, 626 u8 address, u16 data) 627 { 628 const u16 mdio_control = 0x128; 629 const u16 mdio_data = 0x12C; 630 int max_retries = 10; 631 u32 v; 632 int i; 633 634 v = 0x80; /* Enable Preamble Sequence */ 635 v |= 0x2; /* MDIO Clock Divisor */ 636 pcicore_write32(pc, mdio_control, v); 637 638 if (pc->dev->id.revision >= 10) { 639 max_retries = 200; 640 ssb_pcie_mdio_set_phy(pc, device); 641 } 642 643 v = (1 << 30); /* Start of Transaction */ 644 v |= (1 << 28); /* Write Transaction */ 645 v |= (1 << 17); /* Turnaround */ 646 if (pc->dev->id.revision < 10) 647 v |= (u32)device << 22; 648 v |= (u32)address << 18; 649 v |= data; 650 pcicore_write32(pc, mdio_data, v); 651 /* Wait for the device to complete the transaction */ 652 udelay(10); 653 for (i = 0; i < max_retries; i++) { 654 v = pcicore_read32(pc, mdio_control); 655 if (v & 0x100 /* Trans complete */) 656 break; 657 msleep(1); 658 } 659 pcicore_write32(pc, mdio_control, 0); 660 } 661 662 static void ssb_broadcast_value(struct ssb_device *dev, 663 u32 address, u32 data) 664 { 665 /* This is used for both, PCI and ChipCommon core, so be careful. */ 666 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); 667 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); 668 669 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); 670 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ 671 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); 672 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ 673 } 674 675 static void ssb_commit_settings(struct ssb_bus *bus) 676 { 677 struct ssb_device *dev; 678 679 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; 680 if (WARN_ON(!dev)) 681 return; 682 /* This forces an update of the cached registers. */ 683 ssb_broadcast_value(dev, 0xFD8, 0); 684 } 685 686 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, 687 struct ssb_device *dev) 688 { 689 struct ssb_device *pdev = pc->dev; 690 struct ssb_bus *bus; 691 int err = 0; 692 u32 tmp; 693 694 if (dev->bus->bustype != SSB_BUSTYPE_PCI) { 695 /* This SSB device is not on a PCI host-bus. So the IRQs are 696 * not routed through the PCI core. 697 * So we must not enable routing through the PCI core. */ 698 goto out; 699 } 700 701 if (!pdev) 702 goto out; 703 bus = pdev->bus; 704 705 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI); 706 707 /* Enable interrupts for this device. */ 708 if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) { 709 u32 coremask; 710 711 /* Calculate the "coremask" for the device. */ 712 coremask = (1 << dev->core_index); 713 714 SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI); 715 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); 716 if (err) 717 goto out; 718 tmp |= coremask << 8; 719 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp); 720 if (err) 721 goto out; 722 } else { 723 u32 intvec; 724 725 intvec = ssb_read32(pdev, SSB_INTVEC); 726 tmp = ssb_read32(dev, SSB_TPSFLAG); 727 tmp &= SSB_TPSFLAG_BPFLAG; 728 intvec |= (1 << tmp); 729 ssb_write32(pdev, SSB_INTVEC, intvec); 730 } 731 732 /* Setup PCIcore operation. */ 733 if (pc->setup_done) 734 goto out; 735 if (pdev->id.coreid == SSB_DEV_PCI) { 736 ssb_pcicore_pci_setup_workarounds(pc); 737 } else { 738 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE); 739 ssb_pcicore_pcie_setup_workarounds(pc); 740 } 741 pc->setup_done = 1; 742 out: 743 return err; 744 } 745 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable); 746