1 /* 2 * Sonics Silicon Backplane 3 * Broadcom PCI-core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include <linux/ssb/ssb.h> 12 #include <linux/pci.h> 13 #include <linux/delay.h> 14 #include <linux/ssb/ssb_embedded.h> 15 16 #include "ssb_private.h" 17 18 19 static inline 20 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) 21 { 22 return ssb_read32(pc->dev, offset); 23 } 24 25 static inline 26 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value) 27 { 28 ssb_write32(pc->dev, offset, value); 29 } 30 31 static inline 32 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset) 33 { 34 return ssb_read16(pc->dev, offset); 35 } 36 37 static inline 38 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value) 39 { 40 ssb_write16(pc->dev, offset, value); 41 } 42 43 /************************************************** 44 * Code for hostmode operation. 45 **************************************************/ 46 47 #ifdef CONFIG_SSB_PCICORE_HOSTMODE 48 49 #include <asm/paccess.h> 50 /* Probe a 32bit value on the bus and catch bus exceptions. 51 * Returns nonzero on a bus exception. 52 * This is MIPS specific */ 53 #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) 54 55 /* Assume one-hot slot wiring */ 56 #define SSB_PCI_SLOT_MAX 16 57 58 /* Global lock is OK, as we won't have more than one extpci anyway. */ 59 static DEFINE_SPINLOCK(cfgspace_lock); 60 /* Core to access the external PCI config space. Can only have one. */ 61 static struct ssb_pcicore *extpci_core; 62 63 64 static u32 get_cfgspace_addr(struct ssb_pcicore *pc, 65 unsigned int bus, unsigned int dev, 66 unsigned int func, unsigned int off) 67 { 68 u32 addr = 0; 69 u32 tmp; 70 71 /* We do only have one cardbus device behind the bridge. */ 72 if (pc->cardbusmode && (dev >= 1)) 73 goto out; 74 75 if (bus == 0) { 76 /* Type 0 transaction */ 77 if (unlikely(dev >= SSB_PCI_SLOT_MAX)) 78 goto out; 79 /* Slide the window */ 80 tmp = SSB_PCICORE_SBTOPCI_CFG0; 81 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK); 82 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp); 83 /* Calculate the address */ 84 addr = SSB_PCI_CFG; 85 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK); 86 addr |= (func << 8); 87 addr |= (off & ~3); 88 } else { 89 /* Type 1 transaction */ 90 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, 91 SSB_PCICORE_SBTOPCI_CFG1); 92 /* Calculate the address */ 93 addr = SSB_PCI_CFG; 94 addr |= (bus << 16); 95 addr |= (dev << 11); 96 addr |= (func << 8); 97 addr |= (off & ~3); 98 } 99 out: 100 return addr; 101 } 102 103 static int ssb_extpci_read_config(struct ssb_pcicore *pc, 104 unsigned int bus, unsigned int dev, 105 unsigned int func, unsigned int off, 106 void *buf, int len) 107 { 108 int err = -EINVAL; 109 u32 addr, val; 110 void __iomem *mmio; 111 112 SSB_WARN_ON(!pc->hostmode); 113 if (unlikely(len != 1 && len != 2 && len != 4)) 114 goto out; 115 addr = get_cfgspace_addr(pc, bus, dev, func, off); 116 if (unlikely(!addr)) 117 goto out; 118 err = -ENOMEM; 119 mmio = ioremap_nocache(addr, len); 120 if (!mmio) 121 goto out; 122 123 if (mips_busprobe32(val, mmio)) { 124 val = 0xffffffff; 125 goto unmap; 126 } 127 128 val = readl(mmio); 129 val >>= (8 * (off & 3)); 130 131 switch (len) { 132 case 1: 133 *((u8 *)buf) = (u8)val; 134 break; 135 case 2: 136 *((u16 *)buf) = (u16)val; 137 break; 138 case 4: 139 *((u32 *)buf) = (u32)val; 140 break; 141 } 142 err = 0; 143 unmap: 144 iounmap(mmio); 145 out: 146 return err; 147 } 148 149 static int ssb_extpci_write_config(struct ssb_pcicore *pc, 150 unsigned int bus, unsigned int dev, 151 unsigned int func, unsigned int off, 152 const void *buf, int len) 153 { 154 int err = -EINVAL; 155 u32 addr, val = 0; 156 void __iomem *mmio; 157 158 SSB_WARN_ON(!pc->hostmode); 159 if (unlikely(len != 1 && len != 2 && len != 4)) 160 goto out; 161 addr = get_cfgspace_addr(pc, bus, dev, func, off); 162 if (unlikely(!addr)) 163 goto out; 164 err = -ENOMEM; 165 mmio = ioremap_nocache(addr, len); 166 if (!mmio) 167 goto out; 168 169 if (mips_busprobe32(val, mmio)) { 170 val = 0xffffffff; 171 goto unmap; 172 } 173 174 switch (len) { 175 case 1: 176 val = readl(mmio); 177 val &= ~(0xFF << (8 * (off & 3))); 178 val |= *((const u8 *)buf) << (8 * (off & 3)); 179 break; 180 case 2: 181 val = readl(mmio); 182 val &= ~(0xFFFF << (8 * (off & 3))); 183 val |= *((const u16 *)buf) << (8 * (off & 3)); 184 break; 185 case 4: 186 val = *((const u32 *)buf); 187 break; 188 } 189 writel(val, mmio); 190 191 err = 0; 192 unmap: 193 iounmap(mmio); 194 out: 195 return err; 196 } 197 198 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn, 199 int reg, int size, u32 *val) 200 { 201 unsigned long flags; 202 int err; 203 204 spin_lock_irqsave(&cfgspace_lock, flags); 205 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn), 206 PCI_FUNC(devfn), reg, val, size); 207 spin_unlock_irqrestore(&cfgspace_lock, flags); 208 209 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 210 } 211 212 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn, 213 int reg, int size, u32 val) 214 { 215 unsigned long flags; 216 int err; 217 218 spin_lock_irqsave(&cfgspace_lock, flags); 219 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn), 220 PCI_FUNC(devfn), reg, &val, size); 221 spin_unlock_irqrestore(&cfgspace_lock, flags); 222 223 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 224 } 225 226 static struct pci_ops ssb_pcicore_pciops = { 227 .read = ssb_pcicore_read_config, 228 .write = ssb_pcicore_write_config, 229 }; 230 231 static struct resource ssb_pcicore_mem_resource = { 232 .name = "SSB PCIcore external memory", 233 .start = SSB_PCI_DMA, 234 .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1, 235 .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED, 236 }; 237 238 static struct resource ssb_pcicore_io_resource = { 239 .name = "SSB PCIcore external I/O", 240 .start = 0x100, 241 .end = 0x7FF, 242 .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED, 243 }; 244 245 static struct pci_controller ssb_pcicore_controller = { 246 .pci_ops = &ssb_pcicore_pciops, 247 .io_resource = &ssb_pcicore_io_resource, 248 .mem_resource = &ssb_pcicore_mem_resource, 249 }; 250 251 /* This function is called when doing a pci_enable_device(). 252 * We must first check if the device is a device on the PCI-core bridge. */ 253 int ssb_pcicore_plat_dev_init(struct pci_dev *d) 254 { 255 if (d->bus->ops != &ssb_pcicore_pciops) { 256 /* This is not a device on the PCI-core bridge. */ 257 return -ENODEV; 258 } 259 260 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", 261 pci_name(d)); 262 263 /* Fix up interrupt lines */ 264 d->irq = ssb_mips_irq(extpci_core->dev) + 2; 265 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); 266 267 return 0; 268 } 269 270 /* Early PCI fixup for a device on the PCI-core bridge. */ 271 static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev) 272 { 273 u8 lat; 274 275 if (dev->bus->ops != &ssb_pcicore_pciops) { 276 /* This is not a device on the PCI-core bridge. */ 277 return; 278 } 279 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0) 280 return; 281 282 ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev)); 283 284 /* Enable PCI bridge bus mastering and memory space */ 285 pci_set_master(dev); 286 if (pcibios_enable_device(dev, ~0) < 0) { 287 ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n"); 288 return; 289 } 290 291 /* Enable PCI bridge BAR1 prefetch and burst */ 292 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3); 293 294 /* Make sure our latency is high enough to handle the devices behind us */ 295 lat = 168; 296 ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n", 297 pci_name(dev), lat); 298 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 299 } 300 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge); 301 302 /* PCI device IRQ mapping. */ 303 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 304 { 305 if (dev->bus->ops != &ssb_pcicore_pciops) { 306 /* This is not a device on the PCI-core bridge. */ 307 return -ENODEV; 308 } 309 return ssb_mips_irq(extpci_core->dev) + 2; 310 } 311 312 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) 313 { 314 u32 val; 315 316 if (WARN_ON(extpci_core)) 317 return; 318 extpci_core = pc; 319 320 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n"); 321 /* Reset devices on the external PCI bus */ 322 val = SSB_PCICORE_CTL_RST_OE; 323 val |= SSB_PCICORE_CTL_CLK_OE; 324 pcicore_write32(pc, SSB_PCICORE_CTL, val); 325 val |= SSB_PCICORE_CTL_CLK; /* Clock on */ 326 pcicore_write32(pc, SSB_PCICORE_CTL, val); 327 udelay(150); /* Assertion time demanded by the PCI standard */ 328 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */ 329 pcicore_write32(pc, SSB_PCICORE_CTL, val); 330 val = SSB_PCICORE_ARBCTL_INTERN; 331 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); 332 udelay(1); /* Assertion time demanded by the PCI standard */ 333 334 if (pc->dev->bus->has_cardbus_slot) { 335 ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n"); 336 pc->cardbusmode = 1; 337 /* GPIO 1 resets the bridge */ 338 ssb_gpio_out(pc->dev->bus, 1, 1); 339 ssb_gpio_outen(pc->dev->bus, 1, 1); 340 pcicore_write16(pc, SSB_PCICORE_SPROM(0), 341 pcicore_read16(pc, SSB_PCICORE_SPROM(0)) 342 | 0x0400); 343 } 344 345 /* 64MB I/O window */ 346 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0, 347 SSB_PCICORE_SBTOPCI_IO); 348 /* 64MB config space */ 349 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, 350 SSB_PCICORE_SBTOPCI_CFG0); 351 /* 1GB memory window */ 352 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, 353 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); 354 355 /* Enable PCI bridge BAR0 prefetch and burst */ 356 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 357 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); 358 /* Clear error conditions */ 359 val = 0; 360 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2); 361 362 /* Enable PCI interrupts */ 363 pcicore_write32(pc, SSB_PCICORE_IMASK, 364 SSB_PCICORE_IMASK_INTA); 365 366 /* Ok, ready to run, register it to the system. 367 * The following needs change, if we want to port hostmode 368 * to non-MIPS platform. */ 369 ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000); 370 set_io_port_base(ssb_pcicore_controller.io_map_base); 371 /* Give some time to the PCI controller to configure itself with the new 372 * values. Not waiting at this point causes crashes of the machine. */ 373 mdelay(10); 374 register_pci_controller(&ssb_pcicore_controller); 375 } 376 377 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc) 378 { 379 struct ssb_bus *bus = pc->dev->bus; 380 u16 chipid_top; 381 u32 tmp; 382 383 chipid_top = (bus->chip_id & 0xFF00); 384 if (chipid_top != 0x4700 && 385 chipid_top != 0x5300) 386 return 0; 387 388 if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI) 389 return 0; 390 391 /* The 200-pin BCM4712 package does not bond out PCI. Even when 392 * PCI is bonded out, some boards may leave the pins floating. */ 393 if (bus->chip_id == 0x4712) { 394 if (bus->chip_package == SSB_CHIPPACK_BCM4712S) 395 return 0; 396 if (bus->chip_package == SSB_CHIPPACK_BCM4712M) 397 return 0; 398 } 399 if (bus->chip_id == 0x5350) 400 return 0; 401 402 return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE))); 403 } 404 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ 405 406 407 /************************************************** 408 * Generic and Clientmode operation code. 409 **************************************************/ 410 411 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) 412 { 413 /* Disable PCI interrupts. */ 414 ssb_write32(pc->dev, SSB_INTVEC, 0); 415 } 416 417 void ssb_pcicore_init(struct ssb_pcicore *pc) 418 { 419 struct ssb_device *dev = pc->dev; 420 struct ssb_bus *bus; 421 422 if (!dev) 423 return; 424 bus = dev->bus; 425 if (!ssb_device_is_enabled(dev)) 426 ssb_device_enable(dev, 0); 427 428 #ifdef CONFIG_SSB_PCICORE_HOSTMODE 429 pc->hostmode = pcicore_is_in_hostmode(pc); 430 if (pc->hostmode) 431 ssb_pcicore_init_hostmode(pc); 432 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ 433 if (!pc->hostmode) 434 ssb_pcicore_init_clientmode(pc); 435 } 436 437 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address) 438 { 439 pcicore_write32(pc, 0x130, address); 440 return pcicore_read32(pc, 0x134); 441 } 442 443 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data) 444 { 445 pcicore_write32(pc, 0x130, address); 446 pcicore_write32(pc, 0x134, data); 447 } 448 449 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, 450 u8 address, u16 data) 451 { 452 const u16 mdio_control = 0x128; 453 const u16 mdio_data = 0x12C; 454 u32 v; 455 int i; 456 457 v = 0x80; /* Enable Preamble Sequence */ 458 v |= 0x2; /* MDIO Clock Divisor */ 459 pcicore_write32(pc, mdio_control, v); 460 461 v = (1 << 30); /* Start of Transaction */ 462 v |= (1 << 28); /* Write Transaction */ 463 v |= (1 << 17); /* Turnaround */ 464 v |= (u32)device << 22; 465 v |= (u32)address << 18; 466 v |= data; 467 pcicore_write32(pc, mdio_data, v); 468 /* Wait for the device to complete the transaction */ 469 udelay(10); 470 for (i = 0; i < 10; i++) { 471 v = pcicore_read32(pc, mdio_control); 472 if (v & 0x100 /* Trans complete */) 473 break; 474 msleep(1); 475 } 476 pcicore_write32(pc, mdio_control, 0); 477 } 478 479 static void ssb_broadcast_value(struct ssb_device *dev, 480 u32 address, u32 data) 481 { 482 /* This is used for both, PCI and ChipCommon core, so be careful. */ 483 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); 484 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); 485 486 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); 487 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ 488 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); 489 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ 490 } 491 492 static void ssb_commit_settings(struct ssb_bus *bus) 493 { 494 struct ssb_device *dev; 495 496 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; 497 if (WARN_ON(!dev)) 498 return; 499 /* This forces an update of the cached registers. */ 500 ssb_broadcast_value(dev, 0xFD8, 0); 501 } 502 503 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, 504 struct ssb_device *dev) 505 { 506 struct ssb_device *pdev = pc->dev; 507 struct ssb_bus *bus; 508 int err = 0; 509 u32 tmp; 510 511 if (dev->bus->bustype != SSB_BUSTYPE_PCI) { 512 /* This SSB device is not on a PCI host-bus. So the IRQs are 513 * not routed through the PCI core. 514 * So we must not enable routing through the PCI core. */ 515 goto out; 516 } 517 518 if (!pdev) 519 goto out; 520 bus = pdev->bus; 521 522 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI); 523 524 /* Enable interrupts for this device. */ 525 if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) { 526 u32 coremask; 527 528 /* Calculate the "coremask" for the device. */ 529 coremask = (1 << dev->core_index); 530 531 SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI); 532 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); 533 if (err) 534 goto out; 535 tmp |= coremask << 8; 536 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp); 537 if (err) 538 goto out; 539 } else { 540 u32 intvec; 541 542 intvec = ssb_read32(pdev, SSB_INTVEC); 543 tmp = ssb_read32(dev, SSB_TPSFLAG); 544 tmp &= SSB_TPSFLAG_BPFLAG; 545 intvec |= (1 << tmp); 546 ssb_write32(pdev, SSB_INTVEC, intvec); 547 } 548 549 /* Setup PCIcore operation. */ 550 if (pc->setup_done) 551 goto out; 552 if (pdev->id.coreid == SSB_DEV_PCI) { 553 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); 554 tmp |= SSB_PCICORE_SBTOPCI_PREF; 555 tmp |= SSB_PCICORE_SBTOPCI_BURST; 556 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); 557 558 if (pdev->id.revision < 5) { 559 tmp = ssb_read32(pdev, SSB_IMCFGLO); 560 tmp &= ~SSB_IMCFGLO_SERTO; 561 tmp |= 2; 562 tmp &= ~SSB_IMCFGLO_REQTO; 563 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT; 564 ssb_write32(pdev, SSB_IMCFGLO, tmp); 565 ssb_commit_settings(bus); 566 } else if (pdev->id.revision >= 11) { 567 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); 568 tmp |= SSB_PCICORE_SBTOPCI_MRM; 569 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); 570 } 571 } else { 572 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE); 573 //TODO: Better make defines for all these magic PCIE values. 574 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) { 575 /* TLP Workaround register. */ 576 tmp = ssb_pcie_read(pc, 0x4); 577 tmp |= 0x8; 578 ssb_pcie_write(pc, 0x4, tmp); 579 } 580 if (pdev->id.revision == 0) { 581 const u8 serdes_rx_device = 0x1F; 582 583 ssb_pcie_mdio_write(pc, serdes_rx_device, 584 2 /* Timer */, 0x8128); 585 ssb_pcie_mdio_write(pc, serdes_rx_device, 586 6 /* CDR */, 0x0100); 587 ssb_pcie_mdio_write(pc, serdes_rx_device, 588 7 /* CDR BW */, 0x1466); 589 } else if (pdev->id.revision == 1) { 590 /* DLLP Link Control register. */ 591 tmp = ssb_pcie_read(pc, 0x100); 592 tmp |= 0x40; 593 ssb_pcie_write(pc, 0x100, tmp); 594 } 595 } 596 pc->setup_done = 1; 597 out: 598 return err; 599 } 600 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable); 601