1 /* 2 * Sonics Silicon Backplane 3 * Broadcom ChipCommon core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include <linux/ssb/ssb.h> 12 #include <linux/ssb/ssb_regs.h> 13 #include <linux/pci.h> 14 15 #include "ssb_private.h" 16 17 18 /* Clock sources */ 19 enum ssb_clksrc { 20 /* PCI clock */ 21 SSB_CHIPCO_CLKSRC_PCI, 22 /* Crystal slow clock oscillator */ 23 SSB_CHIPCO_CLKSRC_XTALOS, 24 /* Low power oscillator */ 25 SSB_CHIPCO_CLKSRC_LOPWROS, 26 }; 27 28 29 static inline u32 chipco_read32(struct ssb_chipcommon *cc, 30 u16 offset) 31 { 32 return ssb_read32(cc->dev, offset); 33 } 34 35 static inline void chipco_write32(struct ssb_chipcommon *cc, 36 u16 offset, 37 u32 value) 38 { 39 ssb_write32(cc->dev, offset, value); 40 } 41 42 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset, 43 u32 mask, u32 value) 44 { 45 value &= mask; 46 value |= chipco_read32(cc, offset) & ~mask; 47 chipco_write32(cc, offset, value); 48 49 return value; 50 } 51 52 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, 53 enum ssb_clkmode mode) 54 { 55 struct ssb_device *ccdev = cc->dev; 56 struct ssb_bus *bus; 57 u32 tmp; 58 59 if (!ccdev) 60 return; 61 bus = ccdev->bus; 62 /* chipcommon cores prior to rev6 don't support dynamic clock control */ 63 if (ccdev->id.revision < 6) 64 return; 65 /* chipcommon cores rev10 are a whole new ball game */ 66 if (ccdev->id.revision >= 10) 67 return; 68 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) 69 return; 70 71 switch (mode) { 72 case SSB_CLKMODE_SLOW: 73 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 74 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW; 75 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); 76 break; 77 case SSB_CLKMODE_FAST: 78 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */ 79 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 80 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; 81 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL; 82 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); 83 break; 84 case SSB_CLKMODE_DYNAMIC: 85 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 86 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW; 87 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL; 88 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL; 89 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL) 90 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL; 91 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp); 92 93 /* for dynamic control, we have to release our xtal_pu "force on" */ 94 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL) 95 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0); 96 break; 97 default: 98 SSB_WARN_ON(1); 99 } 100 } 101 102 /* Get the Slow Clock Source */ 103 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc) 104 { 105 struct ssb_bus *bus = cc->dev->bus; 106 u32 uninitialized_var(tmp); 107 108 if (cc->dev->id.revision < 6) { 109 if (bus->bustype == SSB_BUSTYPE_SSB || 110 bus->bustype == SSB_BUSTYPE_PCMCIA) 111 return SSB_CHIPCO_CLKSRC_XTALOS; 112 if (bus->bustype == SSB_BUSTYPE_PCI) { 113 pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp); 114 if (tmp & 0x10) 115 return SSB_CHIPCO_CLKSRC_PCI; 116 return SSB_CHIPCO_CLKSRC_XTALOS; 117 } 118 } 119 if (cc->dev->id.revision < 10) { 120 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 121 tmp &= 0x7; 122 if (tmp == 0) 123 return SSB_CHIPCO_CLKSRC_LOPWROS; 124 if (tmp == 1) 125 return SSB_CHIPCO_CLKSRC_XTALOS; 126 if (tmp == 2) 127 return SSB_CHIPCO_CLKSRC_PCI; 128 } 129 130 return SSB_CHIPCO_CLKSRC_XTALOS; 131 } 132 133 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */ 134 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max) 135 { 136 int uninitialized_var(limit); 137 enum ssb_clksrc clocksrc; 138 int divisor = 1; 139 u32 tmp; 140 141 clocksrc = chipco_pctl_get_slowclksrc(cc); 142 if (cc->dev->id.revision < 6) { 143 switch (clocksrc) { 144 case SSB_CHIPCO_CLKSRC_PCI: 145 divisor = 64; 146 break; 147 case SSB_CHIPCO_CLKSRC_XTALOS: 148 divisor = 32; 149 break; 150 default: 151 SSB_WARN_ON(1); 152 } 153 } else if (cc->dev->id.revision < 10) { 154 switch (clocksrc) { 155 case SSB_CHIPCO_CLKSRC_LOPWROS: 156 break; 157 case SSB_CHIPCO_CLKSRC_XTALOS: 158 case SSB_CHIPCO_CLKSRC_PCI: 159 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL); 160 divisor = (tmp >> 16) + 1; 161 divisor *= 4; 162 break; 163 } 164 } else { 165 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL); 166 divisor = (tmp >> 16) + 1; 167 divisor *= 4; 168 } 169 170 switch (clocksrc) { 171 case SSB_CHIPCO_CLKSRC_LOPWROS: 172 if (get_max) 173 limit = 43000; 174 else 175 limit = 25000; 176 break; 177 case SSB_CHIPCO_CLKSRC_XTALOS: 178 if (get_max) 179 limit = 20200000; 180 else 181 limit = 19800000; 182 break; 183 case SSB_CHIPCO_CLKSRC_PCI: 184 if (get_max) 185 limit = 34000000; 186 else 187 limit = 25000000; 188 break; 189 } 190 limit /= divisor; 191 192 return limit; 193 } 194 195 static void chipco_powercontrol_init(struct ssb_chipcommon *cc) 196 { 197 struct ssb_bus *bus = cc->dev->bus; 198 199 if (bus->chip_id == 0x4321) { 200 if (bus->chip_rev == 0) 201 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4); 202 else if (bus->chip_rev == 1) 203 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4); 204 } 205 206 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) 207 return; 208 209 if (cc->dev->id.revision >= 10) { 210 /* Set Idle Power clock rate to 1Mhz */ 211 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL, 212 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) & 213 0x0000FFFF) | 0x00040000); 214 } else { 215 int maxfreq; 216 217 maxfreq = chipco_pctl_clockfreqlimit(cc, 1); 218 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY, 219 (maxfreq * 150 + 999999) / 1000000); 220 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY, 221 (maxfreq * 15 + 999999) / 1000000); 222 } 223 } 224 225 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc) 226 { 227 struct ssb_bus *bus = cc->dev->bus; 228 int minfreq; 229 unsigned int tmp; 230 u32 pll_on_delay; 231 232 if (bus->bustype != SSB_BUSTYPE_PCI) 233 return; 234 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL)) 235 return; 236 237 minfreq = chipco_pctl_clockfreqlimit(cc, 0); 238 pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY); 239 tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq; 240 SSB_WARN_ON(tmp & ~0xFFFF); 241 242 cc->fast_pwrup_delay = tmp; 243 } 244 245 void ssb_chipcommon_init(struct ssb_chipcommon *cc) 246 { 247 if (!cc->dev) 248 return; /* We don't have a ChipCommon */ 249 chipco_powercontrol_init(cc); 250 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); 251 calc_fast_powerup_delay(cc); 252 } 253 254 void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state) 255 { 256 if (!cc->dev) 257 return; 258 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); 259 } 260 261 void ssb_chipco_resume(struct ssb_chipcommon *cc) 262 { 263 if (!cc->dev) 264 return; 265 chipco_powercontrol_init(cc); 266 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); 267 } 268 269 /* Get the processor clock */ 270 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, 271 u32 *plltype, u32 *n, u32 *m) 272 { 273 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); 274 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); 275 switch (*plltype) { 276 case SSB_PLLTYPE_2: 277 case SSB_PLLTYPE_4: 278 case SSB_PLLTYPE_6: 279 case SSB_PLLTYPE_7: 280 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); 281 break; 282 case SSB_PLLTYPE_3: 283 /* 5350 uses m2 to control mips */ 284 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); 285 break; 286 default: 287 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); 288 break; 289 } 290 } 291 292 /* Get the bus clock */ 293 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, 294 u32 *plltype, u32 *n, u32 *m) 295 { 296 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N); 297 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); 298 switch (*plltype) { 299 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ 300 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS); 301 break; 302 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ 303 if (cc->dev->bus->chip_id != 0x5365) { 304 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2); 305 break; 306 } 307 /* Fallthough */ 308 default: 309 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB); 310 } 311 } 312 313 void ssb_chipco_timing_init(struct ssb_chipcommon *cc, 314 unsigned long ns) 315 { 316 struct ssb_device *dev = cc->dev; 317 struct ssb_bus *bus = dev->bus; 318 u32 tmp; 319 320 /* set register for external IO to control LED. */ 321 chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11); 322 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ 323 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */ 324 tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */ 325 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ 326 327 /* Set timing for the flash */ 328 tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */ 329 tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */ 330 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */ 331 if ((bus->chip_id == 0x5365) || 332 (dev->id.revision < 9)) 333 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp); 334 if ((bus->chip_id == 0x5365) || 335 (dev->id.revision < 9) || 336 ((bus->chip_id == 0x5350) && (bus->chip_rev == 0))) 337 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp); 338 339 if (bus->chip_id == 0x5350) { 340 /* Enable EXTIF */ 341 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ 342 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */ 343 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */ 344 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */ 345 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */ 346 } 347 } 348 349 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ 350 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks) 351 { 352 /* instant NMI */ 353 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks); 354 } 355 356 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask) 357 { 358 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask; 359 } 360 361 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value) 362 { 363 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value); 364 } 365 366 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value) 367 { 368 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value); 369 } 370 371 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value) 372 { 373 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); 374 } 375 376 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) 377 { 378 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value); 379 } 380 381 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value) 382 { 383 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value); 384 } 385 386 #ifdef CONFIG_SSB_SERIAL 387 int ssb_chipco_serial_init(struct ssb_chipcommon *cc, 388 struct ssb_serial_port *ports) 389 { 390 struct ssb_bus *bus = cc->dev->bus; 391 int nr_ports = 0; 392 u32 plltype; 393 unsigned int irq; 394 u32 baud_base, div; 395 u32 i, n; 396 unsigned int ccrev = cc->dev->id.revision; 397 398 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT); 399 irq = ssb_mips_irq(cc->dev); 400 401 if (plltype == SSB_PLLTYPE_1) { 402 /* PLL clock */ 403 baud_base = ssb_calc_clock_rate(plltype, 404 chipco_read32(cc, SSB_CHIPCO_CLOCK_N), 405 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2)); 406 div = 1; 407 } else { 408 if (ccrev == 20) { 409 /* BCM5354 uses constant 25MHz clock */ 410 baud_base = 25000000; 411 div = 48; 412 /* Set the override bit so we don't divide it */ 413 chipco_write32(cc, SSB_CHIPCO_CORECTL, 414 chipco_read32(cc, SSB_CHIPCO_CORECTL) 415 | SSB_CHIPCO_CORECTL_UARTCLK0); 416 } else if ((ccrev >= 11) && (ccrev != 15)) { 417 /* Fixed ALP clock */ 418 baud_base = 20000000; 419 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) { 420 /* FIXME: baud_base is different for devices with a PMU */ 421 SSB_WARN_ON(1); 422 } 423 div = 1; 424 if (ccrev >= 21) { 425 /* Turn off UART clock before switching clocksource. */ 426 chipco_write32(cc, SSB_CHIPCO_CORECTL, 427 chipco_read32(cc, SSB_CHIPCO_CORECTL) 428 & ~SSB_CHIPCO_CORECTL_UARTCLKEN); 429 } 430 /* Set the override bit so we don't divide it */ 431 chipco_write32(cc, SSB_CHIPCO_CORECTL, 432 chipco_read32(cc, SSB_CHIPCO_CORECTL) 433 | SSB_CHIPCO_CORECTL_UARTCLK0); 434 if (ccrev >= 21) { 435 /* Re-enable the UART clock. */ 436 chipco_write32(cc, SSB_CHIPCO_CORECTL, 437 chipco_read32(cc, SSB_CHIPCO_CORECTL) 438 | SSB_CHIPCO_CORECTL_UARTCLKEN); 439 } 440 } else if (ccrev >= 3) { 441 /* Internal backplane clock */ 442 baud_base = ssb_clockspeed(bus); 443 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV) 444 & SSB_CHIPCO_CLKDIV_UART; 445 } else { 446 /* Fixed internal backplane clock */ 447 baud_base = 88000000; 448 div = 48; 449 } 450 451 /* Clock source depends on strapping if UartClkOverride is unset */ 452 if ((ccrev > 0) && 453 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) { 454 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) == 455 SSB_CHIPCO_CAP_UARTCLK_INT) { 456 /* Internal divided backplane clock */ 457 baud_base /= div; 458 } else { 459 /* Assume external clock of 1.8432 MHz */ 460 baud_base = 1843200; 461 } 462 } 463 } 464 465 /* Determine the registers of the UARTs */ 466 n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART); 467 for (i = 0; i < n; i++) { 468 void __iomem *cc_mmio; 469 void __iomem *uart_regs; 470 471 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE); 472 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA; 473 /* Offset changed at after rev 0 */ 474 if (ccrev == 0) 475 uart_regs += (i * 8); 476 else 477 uart_regs += (i * 256); 478 479 nr_ports++; 480 ports[i].regs = uart_regs; 481 ports[i].irq = irq; 482 ports[i].baud_base = baud_base; 483 ports[i].reg_shift = 0; 484 } 485 486 return nr_ports; 487 } 488 #endif /* CONFIG_SSB_SERIAL */ 489