1 /* 2 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/irq.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/slab.h> 25 #include <linux/spmi.h> 26 27 /* PMIC Arbiter configuration registers */ 28 #define PMIC_ARB_VERSION 0x0000 29 #define PMIC_ARB_VERSION_V2_MIN 0x20010000 30 #define PMIC_ARB_INT_EN 0x0004 31 32 /* PMIC Arbiter channel registers offsets */ 33 #define PMIC_ARB_CMD 0x00 34 #define PMIC_ARB_CONFIG 0x04 35 #define PMIC_ARB_STATUS 0x08 36 #define PMIC_ARB_WDATA0 0x10 37 #define PMIC_ARB_WDATA1 0x14 38 #define PMIC_ARB_RDATA0 0x18 39 #define PMIC_ARB_RDATA1 0x1C 40 #define PMIC_ARB_REG_CHNL(N) (0x800 + 0x4 * (N)) 41 42 /* Mapping Table */ 43 #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N))) 44 #define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF) 45 #define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1) 46 #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF) 47 #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1) 48 #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF) 49 50 #define SPMI_MAPPING_TABLE_LEN 255 51 #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */ 52 #define PPID_TO_CHAN_TABLE_SZ BIT(12) /* PPID is 12bit chan is 1byte*/ 53 54 /* Ownership Table */ 55 #define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N))) 56 #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7) 57 58 /* Channel Status fields */ 59 enum pmic_arb_chnl_status { 60 PMIC_ARB_STATUS_DONE = (1 << 0), 61 PMIC_ARB_STATUS_FAILURE = (1 << 1), 62 PMIC_ARB_STATUS_DENIED = (1 << 2), 63 PMIC_ARB_STATUS_DROPPED = (1 << 3), 64 }; 65 66 /* Command register fields */ 67 #define PMIC_ARB_CMD_MAX_BYTE_COUNT 8 68 69 /* Command Opcodes */ 70 enum pmic_arb_cmd_op_code { 71 PMIC_ARB_OP_EXT_WRITEL = 0, 72 PMIC_ARB_OP_EXT_READL = 1, 73 PMIC_ARB_OP_EXT_WRITE = 2, 74 PMIC_ARB_OP_RESET = 3, 75 PMIC_ARB_OP_SLEEP = 4, 76 PMIC_ARB_OP_SHUTDOWN = 5, 77 PMIC_ARB_OP_WAKEUP = 6, 78 PMIC_ARB_OP_AUTHENTICATE = 7, 79 PMIC_ARB_OP_MSTR_READ = 8, 80 PMIC_ARB_OP_MSTR_WRITE = 9, 81 PMIC_ARB_OP_EXT_READ = 13, 82 PMIC_ARB_OP_WRITE = 14, 83 PMIC_ARB_OP_READ = 15, 84 PMIC_ARB_OP_ZERO_WRITE = 16, 85 }; 86 87 /* Maximum number of support PMIC peripherals */ 88 #define PMIC_ARB_MAX_PERIPHS 256 89 #define PMIC_ARB_MAX_CHNL 128 90 #define PMIC_ARB_PERIPH_ID_VALID (1 << 15) 91 #define PMIC_ARB_TIMEOUT_US 100 92 #define PMIC_ARB_MAX_TRANS_BYTES (8) 93 94 #define PMIC_ARB_APID_MASK 0xFF 95 #define PMIC_ARB_PPID_MASK 0xFFF 96 97 /* interrupt enable bit */ 98 #define SPMI_PIC_ACC_ENABLE_BIT BIT(0) 99 100 struct pmic_arb_ver_ops; 101 102 /** 103 * spmi_pmic_arb_dev - SPMI PMIC Arbiter object 104 * 105 * @rd_base: on v1 "core", on v2 "observer" register base off DT. 106 * @wr_base: on v1 "core", on v2 "chnls" register base off DT. 107 * @intr: address of the SPMI interrupt control registers. 108 * @cnfg: address of the PMIC Arbiter configuration registers. 109 * @lock: lock to synchronize accesses. 110 * @channel: execution environment channel to use for accesses. 111 * @irq: PMIC ARB interrupt. 112 * @ee: the current Execution Environment 113 * @min_apid: minimum APID (used for bounding IRQ search) 114 * @max_apid: maximum APID 115 * @mapping_table: in-memory copy of PPID -> APID mapping table. 116 * @domain: irq domain object for PMIC IRQ domain 117 * @spmic: SPMI controller object 118 * @apid_to_ppid: in-memory copy of APID -> PPID mapping table. 119 * @ver_ops: version dependent operations. 120 * @ppid_to_chan in-memory copy of PPID -> channel (APID) mapping table. 121 * v2 only. 122 */ 123 struct spmi_pmic_arb_dev { 124 void __iomem *rd_base; 125 void __iomem *wr_base; 126 void __iomem *intr; 127 void __iomem *cnfg; 128 raw_spinlock_t lock; 129 u8 channel; 130 int irq; 131 u8 ee; 132 u8 min_apid; 133 u8 max_apid; 134 u32 mapping_table[SPMI_MAPPING_TABLE_LEN]; 135 struct irq_domain *domain; 136 struct spmi_controller *spmic; 137 u16 apid_to_ppid[256]; 138 const struct pmic_arb_ver_ops *ver_ops; 139 u8 *ppid_to_chan; 140 }; 141 142 /** 143 * pmic_arb_ver: version dependent functionality. 144 * 145 * @non_data_cmd: on v1 issues an spmi non-data command. 146 * on v2 no HW support, returns -EOPNOTSUPP. 147 * @offset: on v1 offset of per-ee channel. 148 * on v2 offset of per-ee and per-ppid channel. 149 * @fmt_cmd: formats a GENI/SPMI command. 150 * @owner_acc_status: on v1 offset of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn 151 * on v2 offset of SPMI_PIC_OWNERm_ACC_STATUSn. 152 * @acc_enable: on v1 offset of PMIC_ARB_SPMI_PIC_ACC_ENABLEn 153 * on v2 offset of SPMI_PIC_ACC_ENABLEn. 154 * @irq_status: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_STATUSn 155 * on v2 offset of SPMI_PIC_IRQ_STATUSn. 156 * @irq_clear: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_CLEARn 157 * on v2 offset of SPMI_PIC_IRQ_CLEARn. 158 */ 159 struct pmic_arb_ver_ops { 160 /* spmi commands (read_cmd, write_cmd, cmd) functionality */ 161 u32 (*offset)(struct spmi_pmic_arb_dev *dev, u8 sid, u16 addr); 162 u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc); 163 int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid); 164 /* Interrupts controller functionality (offset of PIC registers) */ 165 u32 (*owner_acc_status)(u8 m, u8 n); 166 u32 (*acc_enable)(u8 n); 167 u32 (*irq_status)(u8 n); 168 u32 (*irq_clear)(u8 n); 169 }; 170 171 static inline void pmic_arb_base_write(struct spmi_pmic_arb_dev *dev, 172 u32 offset, u32 val) 173 { 174 writel_relaxed(val, dev->wr_base + offset); 175 } 176 177 static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb_dev *dev, 178 u32 offset, u32 val) 179 { 180 writel_relaxed(val, dev->rd_base + offset); 181 } 182 183 /** 184 * pa_read_data: reads pmic-arb's register and copy 1..4 bytes to buf 185 * @bc: byte count -1. range: 0..3 186 * @reg: register's address 187 * @buf: output parameter, length must be bc + 1 188 */ 189 static void pa_read_data(struct spmi_pmic_arb_dev *dev, u8 *buf, u32 reg, u8 bc) 190 { 191 u32 data = __raw_readl(dev->rd_base + reg); 192 memcpy(buf, &data, (bc & 3) + 1); 193 } 194 195 /** 196 * pa_write_data: write 1..4 bytes from buf to pmic-arb's register 197 * @bc: byte-count -1. range: 0..3. 198 * @reg: register's address. 199 * @buf: buffer to write. length must be bc + 1. 200 */ 201 static void 202 pa_write_data(struct spmi_pmic_arb_dev *dev, const u8 *buf, u32 reg, u8 bc) 203 { 204 u32 data = 0; 205 memcpy(&data, buf, (bc & 3) + 1); 206 __raw_writel(data, dev->wr_base + reg); 207 } 208 209 static int pmic_arb_wait_for_done(struct spmi_controller *ctrl, 210 void __iomem *base, u8 sid, u16 addr) 211 { 212 struct spmi_pmic_arb_dev *dev = spmi_controller_get_drvdata(ctrl); 213 u32 status = 0; 214 u32 timeout = PMIC_ARB_TIMEOUT_US; 215 u32 offset = dev->ver_ops->offset(dev, sid, addr) + PMIC_ARB_STATUS; 216 217 while (timeout--) { 218 status = readl_relaxed(base + offset); 219 220 if (status & PMIC_ARB_STATUS_DONE) { 221 if (status & PMIC_ARB_STATUS_DENIED) { 222 dev_err(&ctrl->dev, 223 "%s: transaction denied (0x%x)\n", 224 __func__, status); 225 return -EPERM; 226 } 227 228 if (status & PMIC_ARB_STATUS_FAILURE) { 229 dev_err(&ctrl->dev, 230 "%s: transaction failed (0x%x)\n", 231 __func__, status); 232 return -EIO; 233 } 234 235 if (status & PMIC_ARB_STATUS_DROPPED) { 236 dev_err(&ctrl->dev, 237 "%s: transaction dropped (0x%x)\n", 238 __func__, status); 239 return -EIO; 240 } 241 242 return 0; 243 } 244 udelay(1); 245 } 246 247 dev_err(&ctrl->dev, 248 "%s: timeout, status 0x%x\n", 249 __func__, status); 250 return -ETIMEDOUT; 251 } 252 253 static int 254 pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) 255 { 256 struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); 257 unsigned long flags; 258 u32 cmd; 259 int rc; 260 u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, 0); 261 262 cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20); 263 264 raw_spin_lock_irqsave(&pmic_arb->lock, flags); 265 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); 266 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0); 267 raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); 268 269 return rc; 270 } 271 272 static int 273 pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid) 274 { 275 return -EOPNOTSUPP; 276 } 277 278 /* Non-data command */ 279 static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) 280 { 281 struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); 282 283 dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); 284 285 /* Check for valid non-data command */ 286 if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) 287 return -EINVAL; 288 289 return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid); 290 } 291 292 static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, 293 u16 addr, u8 *buf, size_t len) 294 { 295 struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); 296 unsigned long flags; 297 u8 bc = len - 1; 298 u32 cmd; 299 int rc; 300 u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, addr); 301 302 if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { 303 dev_err(&ctrl->dev, 304 "pmic-arb supports 1..%d bytes per trans, but:%zu requested", 305 PMIC_ARB_MAX_TRANS_BYTES, len); 306 return -EINVAL; 307 } 308 309 /* Check the opcode */ 310 if (opc >= 0x60 && opc <= 0x7F) 311 opc = PMIC_ARB_OP_READ; 312 else if (opc >= 0x20 && opc <= 0x2F) 313 opc = PMIC_ARB_OP_EXT_READ; 314 else if (opc >= 0x38 && opc <= 0x3F) 315 opc = PMIC_ARB_OP_EXT_READL; 316 else 317 return -EINVAL; 318 319 cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); 320 321 raw_spin_lock_irqsave(&pmic_arb->lock, flags); 322 pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd); 323 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr); 324 if (rc) 325 goto done; 326 327 pa_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0, 328 min_t(u8, bc, 3)); 329 330 if (bc > 3) 331 pa_read_data(pmic_arb, buf + 4, 332 offset + PMIC_ARB_RDATA1, bc - 4); 333 334 done: 335 raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); 336 return rc; 337 } 338 339 static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, 340 u16 addr, const u8 *buf, size_t len) 341 { 342 struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); 343 unsigned long flags; 344 u8 bc = len - 1; 345 u32 cmd; 346 int rc; 347 u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, addr); 348 349 if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { 350 dev_err(&ctrl->dev, 351 "pmic-arb supports 1..%d bytes per trans, but:%zu requested", 352 PMIC_ARB_MAX_TRANS_BYTES, len); 353 return -EINVAL; 354 } 355 356 /* Check the opcode */ 357 if (opc >= 0x40 && opc <= 0x5F) 358 opc = PMIC_ARB_OP_WRITE; 359 else if (opc >= 0x00 && opc <= 0x0F) 360 opc = PMIC_ARB_OP_EXT_WRITE; 361 else if (opc >= 0x30 && opc <= 0x37) 362 opc = PMIC_ARB_OP_EXT_WRITEL; 363 else if (opc >= 0x80) 364 opc = PMIC_ARB_OP_ZERO_WRITE; 365 else 366 return -EINVAL; 367 368 cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); 369 370 /* Write data to FIFOs */ 371 raw_spin_lock_irqsave(&pmic_arb->lock, flags); 372 pa_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0, 373 min_t(u8, bc, 3)); 374 if (bc > 3) 375 pa_write_data(pmic_arb, buf + 4, 376 offset + PMIC_ARB_WDATA1, bc - 4); 377 378 /* Start the transaction */ 379 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); 380 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr); 381 raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); 382 383 return rc; 384 } 385 386 enum qpnpint_regs { 387 QPNPINT_REG_RT_STS = 0x10, 388 QPNPINT_REG_SET_TYPE = 0x11, 389 QPNPINT_REG_POLARITY_HIGH = 0x12, 390 QPNPINT_REG_POLARITY_LOW = 0x13, 391 QPNPINT_REG_LATCHED_CLR = 0x14, 392 QPNPINT_REG_EN_SET = 0x15, 393 QPNPINT_REG_EN_CLR = 0x16, 394 QPNPINT_REG_LATCHED_STS = 0x18, 395 }; 396 397 struct spmi_pmic_arb_qpnpint_type { 398 u8 type; /* 1 -> edge */ 399 u8 polarity_high; 400 u8 polarity_low; 401 } __packed; 402 403 /* Simplified accessor functions for irqchip callbacks */ 404 static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf, 405 size_t len) 406 { 407 struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); 408 u8 sid = d->hwirq >> 24; 409 u8 per = d->hwirq >> 16; 410 411 if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid, 412 (per << 8) + reg, buf, len)) 413 dev_err_ratelimited(&pa->spmic->dev, 414 "failed irqchip transaction on %x\n", 415 d->irq); 416 } 417 418 static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len) 419 { 420 struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); 421 u8 sid = d->hwirq >> 24; 422 u8 per = d->hwirq >> 16; 423 424 if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid, 425 (per << 8) + reg, buf, len)) 426 dev_err_ratelimited(&pa->spmic->dev, 427 "failed irqchip transaction on %x\n", 428 d->irq); 429 } 430 431 static void periph_interrupt(struct spmi_pmic_arb_dev *pa, u8 apid) 432 { 433 unsigned int irq; 434 u32 status; 435 int id; 436 437 status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid)); 438 while (status) { 439 id = ffs(status) - 1; 440 status &= ~(1 << id); 441 irq = irq_find_mapping(pa->domain, 442 pa->apid_to_ppid[apid] << 16 443 | id << 8 444 | apid); 445 generic_handle_irq(irq); 446 } 447 } 448 449 static void pmic_arb_chained_irq(struct irq_desc *desc) 450 { 451 struct spmi_pmic_arb_dev *pa = irq_desc_get_handler_data(desc); 452 struct irq_chip *chip = irq_desc_get_chip(desc); 453 void __iomem *intr = pa->intr; 454 int first = pa->min_apid >> 5; 455 int last = pa->max_apid >> 5; 456 u32 status; 457 int i, id; 458 459 chained_irq_enter(chip, desc); 460 461 for (i = first; i <= last; ++i) { 462 status = readl_relaxed(intr + 463 pa->ver_ops->owner_acc_status(pa->ee, i)); 464 while (status) { 465 id = ffs(status) - 1; 466 status &= ~(1 << id); 467 periph_interrupt(pa, id + i * 32); 468 } 469 } 470 471 chained_irq_exit(chip, desc); 472 } 473 474 static void qpnpint_irq_ack(struct irq_data *d) 475 { 476 struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); 477 u8 irq = d->hwirq >> 8; 478 u8 apid = d->hwirq; 479 unsigned long flags; 480 u8 data; 481 482 raw_spin_lock_irqsave(&pa->lock, flags); 483 writel_relaxed(1 << irq, pa->intr + pa->ver_ops->irq_clear(apid)); 484 raw_spin_unlock_irqrestore(&pa->lock, flags); 485 486 data = 1 << irq; 487 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); 488 } 489 490 static void qpnpint_irq_mask(struct irq_data *d) 491 { 492 struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); 493 u8 irq = d->hwirq >> 8; 494 u8 apid = d->hwirq; 495 unsigned long flags; 496 u32 status; 497 u8 data; 498 499 raw_spin_lock_irqsave(&pa->lock, flags); 500 status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid)); 501 if (status & SPMI_PIC_ACC_ENABLE_BIT) { 502 status = status & ~SPMI_PIC_ACC_ENABLE_BIT; 503 writel_relaxed(status, pa->intr + 504 pa->ver_ops->acc_enable(apid)); 505 } 506 raw_spin_unlock_irqrestore(&pa->lock, flags); 507 508 data = 1 << irq; 509 qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1); 510 } 511 512 static void qpnpint_irq_unmask(struct irq_data *d) 513 { 514 struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); 515 u8 irq = d->hwirq >> 8; 516 u8 apid = d->hwirq; 517 unsigned long flags; 518 u32 status; 519 u8 data; 520 521 raw_spin_lock_irqsave(&pa->lock, flags); 522 status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid)); 523 if (!(status & SPMI_PIC_ACC_ENABLE_BIT)) { 524 writel_relaxed(status | SPMI_PIC_ACC_ENABLE_BIT, 525 pa->intr + pa->ver_ops->acc_enable(apid)); 526 } 527 raw_spin_unlock_irqrestore(&pa->lock, flags); 528 529 data = 1 << irq; 530 qpnpint_spmi_write(d, QPNPINT_REG_EN_SET, &data, 1); 531 } 532 533 static void qpnpint_irq_enable(struct irq_data *d) 534 { 535 u8 irq = d->hwirq >> 8; 536 u8 data; 537 538 qpnpint_irq_unmask(d); 539 540 data = 1 << irq; 541 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); 542 } 543 544 static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) 545 { 546 struct spmi_pmic_arb_qpnpint_type type; 547 u8 irq = d->hwirq >> 8; 548 549 qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type)); 550 551 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 552 type.type |= 1 << irq; 553 if (flow_type & IRQF_TRIGGER_RISING) 554 type.polarity_high |= 1 << irq; 555 if (flow_type & IRQF_TRIGGER_FALLING) 556 type.polarity_low |= 1 << irq; 557 } else { 558 if ((flow_type & (IRQF_TRIGGER_HIGH)) && 559 (flow_type & (IRQF_TRIGGER_LOW))) 560 return -EINVAL; 561 562 type.type &= ~(1 << irq); /* level trig */ 563 if (flow_type & IRQF_TRIGGER_HIGH) 564 type.polarity_high |= 1 << irq; 565 else 566 type.polarity_low |= 1 << irq; 567 } 568 569 qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type)); 570 return 0; 571 } 572 573 static int qpnpint_get_irqchip_state(struct irq_data *d, 574 enum irqchip_irq_state which, 575 bool *state) 576 { 577 u8 irq = d->hwirq >> 8; 578 u8 status = 0; 579 580 if (which != IRQCHIP_STATE_LINE_LEVEL) 581 return -EINVAL; 582 583 qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1); 584 *state = !!(status & BIT(irq)); 585 586 return 0; 587 } 588 589 static struct irq_chip pmic_arb_irqchip = { 590 .name = "pmic_arb", 591 .irq_enable = qpnpint_irq_enable, 592 .irq_ack = qpnpint_irq_ack, 593 .irq_mask = qpnpint_irq_mask, 594 .irq_unmask = qpnpint_irq_unmask, 595 .irq_set_type = qpnpint_irq_set_type, 596 .irq_get_irqchip_state = qpnpint_get_irqchip_state, 597 .flags = IRQCHIP_MASK_ON_SUSPEND 598 | IRQCHIP_SKIP_SET_WAKE, 599 }; 600 601 struct spmi_pmic_arb_irq_spec { 602 unsigned slave:4; 603 unsigned per:8; 604 unsigned irq:3; 605 }; 606 607 static int search_mapping_table(struct spmi_pmic_arb_dev *pa, 608 struct spmi_pmic_arb_irq_spec *spec, 609 u8 *apid) 610 { 611 u16 ppid = spec->slave << 8 | spec->per; 612 u32 *mapping_table = pa->mapping_table; 613 int index = 0, i; 614 u32 data; 615 616 for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) { 617 data = mapping_table[index]; 618 619 if (ppid & (1 << SPMI_MAPPING_BIT_INDEX(data))) { 620 if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) { 621 index = SPMI_MAPPING_BIT_IS_1_RESULT(data); 622 } else { 623 *apid = SPMI_MAPPING_BIT_IS_1_RESULT(data); 624 return 0; 625 } 626 } else { 627 if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) { 628 index = SPMI_MAPPING_BIT_IS_0_RESULT(data); 629 } else { 630 *apid = SPMI_MAPPING_BIT_IS_0_RESULT(data); 631 return 0; 632 } 633 } 634 } 635 636 return -ENODEV; 637 } 638 639 static int qpnpint_irq_domain_dt_translate(struct irq_domain *d, 640 struct device_node *controller, 641 const u32 *intspec, 642 unsigned int intsize, 643 unsigned long *out_hwirq, 644 unsigned int *out_type) 645 { 646 struct spmi_pmic_arb_dev *pa = d->host_data; 647 struct spmi_pmic_arb_irq_spec spec; 648 int err; 649 u8 apid; 650 651 dev_dbg(&pa->spmic->dev, 652 "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n", 653 intspec[0], intspec[1], intspec[2]); 654 655 if (irq_domain_get_of_node(d) != controller) 656 return -EINVAL; 657 if (intsize != 4) 658 return -EINVAL; 659 if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7) 660 return -EINVAL; 661 662 spec.slave = intspec[0]; 663 spec.per = intspec[1]; 664 spec.irq = intspec[2]; 665 666 err = search_mapping_table(pa, &spec, &apid); 667 if (err) 668 return err; 669 670 pa->apid_to_ppid[apid] = spec.slave << 8 | spec.per; 671 672 /* Keep track of {max,min}_apid for bounding search during interrupt */ 673 if (apid > pa->max_apid) 674 pa->max_apid = apid; 675 if (apid < pa->min_apid) 676 pa->min_apid = apid; 677 678 *out_hwirq = spec.slave << 24 679 | spec.per << 16 680 | spec.irq << 8 681 | apid; 682 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; 683 684 dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq); 685 686 return 0; 687 } 688 689 static int qpnpint_irq_domain_map(struct irq_domain *d, 690 unsigned int virq, 691 irq_hw_number_t hwirq) 692 { 693 struct spmi_pmic_arb_dev *pa = d->host_data; 694 695 dev_dbg(&pa->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq); 696 697 irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq); 698 irq_set_chip_data(virq, d->host_data); 699 irq_set_noprobe(virq); 700 return 0; 701 } 702 703 /* v1 offset per ee */ 704 static u32 pmic_arb_offset_v1(struct spmi_pmic_arb_dev *pa, u8 sid, u16 addr) 705 { 706 return 0x800 + 0x80 * pa->channel; 707 } 708 709 /* v2 offset per ppid (chan) and per ee */ 710 static u32 pmic_arb_offset_v2(struct spmi_pmic_arb_dev *pa, u8 sid, u16 addr) 711 { 712 u16 ppid = (sid << 8) | (addr >> 8); 713 u8 chan = pa->ppid_to_chan[ppid]; 714 715 return 0x1000 * pa->ee + 0x8000 * chan; 716 } 717 718 static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc) 719 { 720 return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7); 721 } 722 723 static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc) 724 { 725 return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7); 726 } 727 728 static u32 pmic_arb_owner_acc_status_v1(u8 m, u8 n) 729 { 730 return 0x20 * m + 0x4 * n; 731 } 732 733 static u32 pmic_arb_owner_acc_status_v2(u8 m, u8 n) 734 { 735 return 0x100000 + 0x1000 * m + 0x4 * n; 736 } 737 738 static u32 pmic_arb_acc_enable_v1(u8 n) 739 { 740 return 0x200 + 0x4 * n; 741 } 742 743 static u32 pmic_arb_acc_enable_v2(u8 n) 744 { 745 return 0x1000 * n; 746 } 747 748 static u32 pmic_arb_irq_status_v1(u8 n) 749 { 750 return 0x600 + 0x4 * n; 751 } 752 753 static u32 pmic_arb_irq_status_v2(u8 n) 754 { 755 return 0x4 + 0x1000 * n; 756 } 757 758 static u32 pmic_arb_irq_clear_v1(u8 n) 759 { 760 return 0xA00 + 0x4 * n; 761 } 762 763 static u32 pmic_arb_irq_clear_v2(u8 n) 764 { 765 return 0x8 + 0x1000 * n; 766 } 767 768 static const struct pmic_arb_ver_ops pmic_arb_v1 = { 769 .non_data_cmd = pmic_arb_non_data_cmd_v1, 770 .offset = pmic_arb_offset_v1, 771 .fmt_cmd = pmic_arb_fmt_cmd_v1, 772 .owner_acc_status = pmic_arb_owner_acc_status_v1, 773 .acc_enable = pmic_arb_acc_enable_v1, 774 .irq_status = pmic_arb_irq_status_v1, 775 .irq_clear = pmic_arb_irq_clear_v1, 776 }; 777 778 static const struct pmic_arb_ver_ops pmic_arb_v2 = { 779 .non_data_cmd = pmic_arb_non_data_cmd_v2, 780 .offset = pmic_arb_offset_v2, 781 .fmt_cmd = pmic_arb_fmt_cmd_v2, 782 .owner_acc_status = pmic_arb_owner_acc_status_v2, 783 .acc_enable = pmic_arb_acc_enable_v2, 784 .irq_status = pmic_arb_irq_status_v2, 785 .irq_clear = pmic_arb_irq_clear_v2, 786 }; 787 788 static const struct irq_domain_ops pmic_arb_irq_domain_ops = { 789 .map = qpnpint_irq_domain_map, 790 .xlate = qpnpint_irq_domain_dt_translate, 791 }; 792 793 static int spmi_pmic_arb_probe(struct platform_device *pdev) 794 { 795 struct spmi_pmic_arb_dev *pa; 796 struct spmi_controller *ctrl; 797 struct resource *res; 798 void __iomem *core; 799 u32 channel, ee, hw_ver; 800 int err, i; 801 bool is_v1; 802 803 ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa)); 804 if (!ctrl) 805 return -ENOMEM; 806 807 pa = spmi_controller_get_drvdata(ctrl); 808 pa->spmic = ctrl; 809 810 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); 811 core = devm_ioremap_resource(&ctrl->dev, res); 812 if (IS_ERR(core)) { 813 err = PTR_ERR(core); 814 goto err_put_ctrl; 815 } 816 817 hw_ver = readl_relaxed(core + PMIC_ARB_VERSION); 818 is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN); 819 820 dev_info(&ctrl->dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), 821 hw_ver); 822 823 if (is_v1) { 824 pa->ver_ops = &pmic_arb_v1; 825 pa->wr_base = core; 826 pa->rd_base = core; 827 } else { 828 u8 chan; 829 u16 ppid; 830 u32 regval; 831 832 pa->ver_ops = &pmic_arb_v2; 833 834 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 835 "obsrvr"); 836 pa->rd_base = devm_ioremap_resource(&ctrl->dev, res); 837 if (IS_ERR(pa->rd_base)) { 838 err = PTR_ERR(pa->rd_base); 839 goto err_put_ctrl; 840 } 841 842 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 843 "chnls"); 844 pa->wr_base = devm_ioremap_resource(&ctrl->dev, res); 845 if (IS_ERR(pa->wr_base)) { 846 err = PTR_ERR(pa->wr_base); 847 goto err_put_ctrl; 848 } 849 850 pa->ppid_to_chan = devm_kzalloc(&ctrl->dev, 851 PPID_TO_CHAN_TABLE_SZ, GFP_KERNEL); 852 if (!pa->ppid_to_chan) { 853 err = -ENOMEM; 854 goto err_put_ctrl; 855 } 856 /* 857 * PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid. 858 * ppid_to_chan is an in-memory invert of that table. 859 */ 860 for (chan = 0; chan < PMIC_ARB_MAX_CHNL; ++chan) { 861 regval = readl_relaxed(core + PMIC_ARB_REG_CHNL(chan)); 862 if (!regval) 863 continue; 864 865 ppid = (regval >> 8) & 0xFFF; 866 pa->ppid_to_chan[ppid] = chan; 867 } 868 } 869 870 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr"); 871 pa->intr = devm_ioremap_resource(&ctrl->dev, res); 872 if (IS_ERR(pa->intr)) { 873 err = PTR_ERR(pa->intr); 874 goto err_put_ctrl; 875 } 876 877 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg"); 878 pa->cnfg = devm_ioremap_resource(&ctrl->dev, res); 879 if (IS_ERR(pa->cnfg)) { 880 err = PTR_ERR(pa->cnfg); 881 goto err_put_ctrl; 882 } 883 884 pa->irq = platform_get_irq_byname(pdev, "periph_irq"); 885 if (pa->irq < 0) { 886 err = pa->irq; 887 goto err_put_ctrl; 888 } 889 890 err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel); 891 if (err) { 892 dev_err(&pdev->dev, "channel unspecified.\n"); 893 goto err_put_ctrl; 894 } 895 896 if (channel > 5) { 897 dev_err(&pdev->dev, "invalid channel (%u) specified.\n", 898 channel); 899 goto err_put_ctrl; 900 } 901 902 pa->channel = channel; 903 904 err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee); 905 if (err) { 906 dev_err(&pdev->dev, "EE unspecified.\n"); 907 goto err_put_ctrl; 908 } 909 910 if (ee > 5) { 911 dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee); 912 err = -EINVAL; 913 goto err_put_ctrl; 914 } 915 916 pa->ee = ee; 917 918 for (i = 0; i < ARRAY_SIZE(pa->mapping_table); ++i) 919 pa->mapping_table[i] = readl_relaxed( 920 pa->cnfg + SPMI_MAPPING_TABLE_REG(i)); 921 922 /* Initialize max_apid/min_apid to the opposite bounds, during 923 * the irq domain translation, we are sure to update these */ 924 pa->max_apid = 0; 925 pa->min_apid = PMIC_ARB_MAX_PERIPHS - 1; 926 927 platform_set_drvdata(pdev, ctrl); 928 raw_spin_lock_init(&pa->lock); 929 930 ctrl->cmd = pmic_arb_cmd; 931 ctrl->read_cmd = pmic_arb_read_cmd; 932 ctrl->write_cmd = pmic_arb_write_cmd; 933 934 dev_dbg(&pdev->dev, "adding irq domain\n"); 935 pa->domain = irq_domain_add_tree(pdev->dev.of_node, 936 &pmic_arb_irq_domain_ops, pa); 937 if (!pa->domain) { 938 dev_err(&pdev->dev, "unable to create irq_domain\n"); 939 err = -ENOMEM; 940 goto err_put_ctrl; 941 } 942 943 irq_set_chained_handler_and_data(pa->irq, pmic_arb_chained_irq, pa); 944 945 err = spmi_controller_add(ctrl); 946 if (err) 947 goto err_domain_remove; 948 949 return 0; 950 951 err_domain_remove: 952 irq_set_chained_handler_and_data(pa->irq, NULL, NULL); 953 irq_domain_remove(pa->domain); 954 err_put_ctrl: 955 spmi_controller_put(ctrl); 956 return err; 957 } 958 959 static int spmi_pmic_arb_remove(struct platform_device *pdev) 960 { 961 struct spmi_controller *ctrl = platform_get_drvdata(pdev); 962 struct spmi_pmic_arb_dev *pa = spmi_controller_get_drvdata(ctrl); 963 spmi_controller_remove(ctrl); 964 irq_set_chained_handler_and_data(pa->irq, NULL, NULL); 965 irq_domain_remove(pa->domain); 966 spmi_controller_put(ctrl); 967 return 0; 968 } 969 970 static const struct of_device_id spmi_pmic_arb_match_table[] = { 971 { .compatible = "qcom,spmi-pmic-arb", }, 972 {}, 973 }; 974 MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table); 975 976 static struct platform_driver spmi_pmic_arb_driver = { 977 .probe = spmi_pmic_arb_probe, 978 .remove = spmi_pmic_arb_remove, 979 .driver = { 980 .name = "spmi_pmic_arb", 981 .of_match_table = spmi_pmic_arb_match_table, 982 }, 983 }; 984 module_platform_driver(spmi_pmic_arb_driver); 985 986 MODULE_LICENSE("GPL v2"); 987 MODULE_ALIAS("platform:spmi_pmic_arb"); 988