1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver 4 * (master mode only) 5 * 6 * Copyright (C) 2009 - 2015 Xilinx, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/firmware/xlnx-zynqmp.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_address.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spinlock.h> 23 #include <linux/workqueue.h> 24 25 /* Generic QSPI register offsets */ 26 #define GQSPI_CONFIG_OFST 0x00000100 27 #define GQSPI_ISR_OFST 0x00000104 28 #define GQSPI_IDR_OFST 0x0000010C 29 #define GQSPI_IER_OFST 0x00000108 30 #define GQSPI_IMASK_OFST 0x00000110 31 #define GQSPI_EN_OFST 0x00000114 32 #define GQSPI_TXD_OFST 0x0000011C 33 #define GQSPI_RXD_OFST 0x00000120 34 #define GQSPI_TX_THRESHOLD_OFST 0x00000128 35 #define GQSPI_RX_THRESHOLD_OFST 0x0000012C 36 #define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138 37 #define GQSPI_GEN_FIFO_OFST 0x00000140 38 #define GQSPI_SEL_OFST 0x00000144 39 #define GQSPI_GF_THRESHOLD_OFST 0x00000150 40 #define GQSPI_FIFO_CTRL_OFST 0x0000014C 41 #define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C 42 #define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804 43 #define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808 44 #define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814 45 #define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818 46 #define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C 47 #define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820 48 #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800 49 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828 50 51 /* GQSPI register bit masks */ 52 #define GQSPI_SEL_MASK 0x00000001 53 #define GQSPI_EN_MASK 0x00000001 54 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 55 #define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002 56 #define GQSPI_IDR_ALL_MASK 0x00000FBE 57 #define GQSPI_CFG_MODE_EN_MASK 0xC0000000 58 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000 59 #define GQSPI_CFG_ENDIAN_MASK 0x04000000 60 #define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000 61 #define GQSPI_CFG_WP_HOLD_MASK 0x00080000 62 #define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038 63 #define GQSPI_CFG_CLK_PHA_MASK 0x00000004 64 #define GQSPI_CFG_CLK_POL_MASK 0x00000002 65 #define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000 66 #define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF 67 #define GQSPI_GENFIFO_DATA_XFER 0x00000100 68 #define GQSPI_GENFIFO_EXP 0x00000200 69 #define GQSPI_GENFIFO_MODE_SPI 0x00000400 70 #define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800 71 #define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00 72 #define GQSPI_GENFIFO_MODE_MASK 0x00000C00 73 #define GQSPI_GENFIFO_CS_LOWER 0x00001000 74 #define GQSPI_GENFIFO_CS_UPPER 0x00002000 75 #define GQSPI_GENFIFO_BUS_LOWER 0x00004000 76 #define GQSPI_GENFIFO_BUS_UPPER 0x00008000 77 #define GQSPI_GENFIFO_BUS_BOTH 0x0000C000 78 #define GQSPI_GENFIFO_BUS_MASK 0x0000C000 79 #define GQSPI_GENFIFO_TX 0x00010000 80 #define GQSPI_GENFIFO_RX 0x00020000 81 #define GQSPI_GENFIFO_STRIPE 0x00040000 82 #define GQSPI_GENFIFO_POLL 0x00080000 83 #define GQSPI_GENFIFO_EXP_START 0x00000100 84 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004 85 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002 86 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001 87 #define GQSPI_ISR_RXEMPTY_MASK 0x00000800 88 #define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400 89 #define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200 90 #define GQSPI_ISR_TXEMPTY_MASK 0x00000100 91 #define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080 92 #define GQSPI_ISR_RXFULL_MASK 0x00000020 93 #define GQSPI_ISR_RXNEMPTY_MASK 0x00000010 94 #define GQSPI_ISR_TXFULL_MASK 0x00000008 95 #define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004 96 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002 97 #define GQSPI_IER_TXNOT_FULL_MASK 0x00000004 98 #define GQSPI_IER_RXEMPTY_MASK 0x00000800 99 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002 100 #define GQSPI_IER_RXNEMPTY_MASK 0x00000010 101 #define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080 102 #define GQSPI_IER_TXEMPTY_MASK 0x00000100 103 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE 104 #define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000 105 #define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000 106 #define GQSPI_ISR_IDR_MASK 0x00000994 107 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002 108 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002 109 #define GQSPI_IRQ_MASK 0x00000980 110 111 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3 112 #define GQSPI_GENFIFO_CS_SETUP 0x4 113 #define GQSPI_GENFIFO_CS_HOLD 0x3 114 #define GQSPI_TXD_DEPTH 64 115 #define GQSPI_RX_FIFO_THRESHOLD 32 116 #define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4) 117 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32 118 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\ 119 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL) 120 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10 121 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00 122 #define GQSPI_SELECT_FLASH_CS_LOWER 0x1 123 #define GQSPI_SELECT_FLASH_CS_UPPER 0x2 124 #define GQSPI_SELECT_FLASH_CS_BOTH 0x3 125 #define GQSPI_SELECT_FLASH_BUS_LOWER 0x1 126 #define GQSPI_SELECT_FLASH_BUS_UPPER 0x2 127 #define GQSPI_SELECT_FLASH_BUS_BOTH 0x3 128 #define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ 129 #define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */ 130 #define GQSPI_SELECT_MODE_SPI 0x1 131 #define GQSPI_SELECT_MODE_DUALSPI 0x2 132 #define GQSPI_SELECT_MODE_QUADSPI 0x4 133 #define GQSPI_DMA_UNALIGN 0x3 134 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */ 135 136 #define SPI_AUTOSUSPEND_TIMEOUT 3000 137 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; 138 static const struct zynqmp_eemi_ops *eemi_ops; 139 140 /** 141 * struct zynqmp_qspi - Defines qspi driver instance 142 * @regs: Virtual address of the QSPI controller registers 143 * @refclk: Pointer to the peripheral clock 144 * @pclk: Pointer to the APB clock 145 * @irq: IRQ number 146 * @dev: Pointer to struct device 147 * @txbuf: Pointer to the TX buffer 148 * @rxbuf: Pointer to the RX buffer 149 * @bytes_to_transfer: Number of bytes left to transfer 150 * @bytes_to_receive: Number of bytes left to receive 151 * @genfifocs: Used for chip select 152 * @genfifobus: Used to select the upper or lower bus 153 * @dma_rx_bytes: Remaining bytes to receive by DMA mode 154 * @dma_addr: DMA address after mapping the kernel buffer 155 * @genfifoentry: Used for storing the genfifoentry instruction. 156 * @mode: Defines the mode in which QSPI is operating 157 */ 158 struct zynqmp_qspi { 159 void __iomem *regs; 160 struct clk *refclk; 161 struct clk *pclk; 162 int irq; 163 struct device *dev; 164 const void *txbuf; 165 void *rxbuf; 166 int bytes_to_transfer; 167 int bytes_to_receive; 168 u32 genfifocs; 169 u32 genfifobus; 170 u32 dma_rx_bytes; 171 dma_addr_t dma_addr; 172 u32 genfifoentry; 173 enum mode_type mode; 174 }; 175 176 /** 177 * zynqmp_gqspi_read: For GQSPI controller read operation 178 * @xqspi: Pointer to the zynqmp_qspi structure 179 * @offset: Offset from where to read 180 */ 181 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset) 182 { 183 return readl_relaxed(xqspi->regs + offset); 184 } 185 186 /** 187 * zynqmp_gqspi_write: For GQSPI controller write operation 188 * @xqspi: Pointer to the zynqmp_qspi structure 189 * @offset: Offset where to write 190 * @val: Value to be written 191 */ 192 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset, 193 u32 val) 194 { 195 writel_relaxed(val, (xqspi->regs + offset)); 196 } 197 198 /** 199 * zynqmp_gqspi_selectslave: For selection of slave device 200 * @instanceptr: Pointer to the zynqmp_qspi structure 201 * @flashcs: For chip select 202 * @flashbus: To check which bus is selected- upper or lower 203 */ 204 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr, 205 u8 slavecs, u8 slavebus) 206 { 207 /* 208 * Bus and CS lines selected here will be updated in the instance and 209 * used for subsequent GENFIFO entries during transfer. 210 */ 211 212 /* Choose slave select line */ 213 switch (slavecs) { 214 case GQSPI_SELECT_FLASH_CS_BOTH: 215 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER | 216 GQSPI_GENFIFO_CS_UPPER; 217 break; 218 case GQSPI_SELECT_FLASH_CS_UPPER: 219 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER; 220 break; 221 case GQSPI_SELECT_FLASH_CS_LOWER: 222 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER; 223 break; 224 default: 225 dev_warn(instanceptr->dev, "Invalid slave select\n"); 226 } 227 228 /* Choose the bus */ 229 switch (slavebus) { 230 case GQSPI_SELECT_FLASH_BUS_BOTH: 231 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER | 232 GQSPI_GENFIFO_BUS_UPPER; 233 break; 234 case GQSPI_SELECT_FLASH_BUS_UPPER: 235 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER; 236 break; 237 case GQSPI_SELECT_FLASH_BUS_LOWER: 238 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER; 239 break; 240 default: 241 dev_warn(instanceptr->dev, "Invalid slave bus\n"); 242 } 243 } 244 245 /** 246 * zynqmp_qspi_init_hw: Initialize the hardware 247 * @xqspi: Pointer to the zynqmp_qspi structure 248 * 249 * The default settings of the QSPI controller's configurable parameters on 250 * reset are 251 * - Master mode 252 * - TX threshold set to 1 253 * - RX threshold set to 1 254 * - Flash memory interface mode enabled 255 * This function performs the following actions 256 * - Disable and clear all the interrupts 257 * - Enable manual slave select 258 * - Enable manual start 259 * - Deselect all the chip select lines 260 * - Set the little endian mode of TX FIFO and 261 * - Enable the QSPI controller 262 */ 263 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi) 264 { 265 u32 config_reg; 266 267 /* Select the GQSPI mode */ 268 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK); 269 /* Clear and disable interrupts */ 270 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, 271 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) | 272 GQSPI_ISR_WR_TO_CLR_MASK); 273 /* Clear the DMA STS */ 274 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST, 275 zynqmp_gqspi_read(xqspi, 276 GQSPI_QSPIDMA_DST_I_STS_OFST)); 277 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST, 278 zynqmp_gqspi_read(xqspi, 279 GQSPI_QSPIDMA_DST_STS_OFST) | 280 GQSPI_QSPIDMA_DST_STS_WTC); 281 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK); 282 zynqmp_gqspi_write(xqspi, 283 GQSPI_QSPIDMA_DST_I_DIS_OFST, 284 GQSPI_QSPIDMA_DST_INTR_ALL_MASK); 285 /* Disable the GQSPI */ 286 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0); 287 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 288 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 289 /* Manual start */ 290 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK; 291 /* Little endian by default */ 292 config_reg &= ~GQSPI_CFG_ENDIAN_MASK; 293 /* Disable poll time out */ 294 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK; 295 /* Set hold bit */ 296 config_reg |= GQSPI_CFG_WP_HOLD_MASK; 297 /* Clear pre-scalar by default */ 298 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; 299 /* CPHA 0 */ 300 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; 301 /* CPOL 0 */ 302 config_reg &= ~GQSPI_CFG_CLK_POL_MASK; 303 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 304 305 /* Clear the TX and RX FIFO */ 306 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST, 307 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK | 308 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK | 309 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK); 310 /* Set by default to allow for high frequencies */ 311 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, 312 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) | 313 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK); 314 /* Reset thresholds */ 315 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST, 316 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL); 317 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST, 318 GQSPI_RX_FIFO_THRESHOLD); 319 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST, 320 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL); 321 zynqmp_gqspi_selectslave(xqspi, 322 GQSPI_SELECT_FLASH_CS_LOWER, 323 GQSPI_SELECT_FLASH_BUS_LOWER); 324 /* Initialize DMA */ 325 zynqmp_gqspi_write(xqspi, 326 GQSPI_QSPIDMA_DST_CTRL_OFST, 327 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL); 328 329 /* Enable the GQSPI */ 330 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK); 331 } 332 333 /** 334 * zynqmp_qspi_copy_read_data: Copy data to RX buffer 335 * @xqspi: Pointer to the zynqmp_qspi structure 336 * @data: The variable where data is stored 337 * @size: Number of bytes to be copied from data to RX buffer 338 */ 339 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi, 340 ulong data, u8 size) 341 { 342 memcpy(xqspi->rxbuf, &data, size); 343 xqspi->rxbuf += size; 344 xqspi->bytes_to_receive -= size; 345 } 346 347 /** 348 * zynqmp_prepare_transfer_hardware: Prepares hardware for transfer. 349 * @master: Pointer to the spi_master structure which provides 350 * information about the controller. 351 * 352 * This function enables SPI master controller. 353 * 354 * Return: 0 on success; error value otherwise 355 */ 356 static int zynqmp_prepare_transfer_hardware(struct spi_master *master) 357 { 358 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 359 360 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK); 361 return 0; 362 } 363 364 /** 365 * zynqmp_unprepare_transfer_hardware: Relaxes hardware after transfer 366 * @master: Pointer to the spi_master structure which provides 367 * information about the controller. 368 * 369 * This function disables the SPI master controller. 370 * 371 * Return: Always 0 372 */ 373 static int zynqmp_unprepare_transfer_hardware(struct spi_master *master) 374 { 375 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 376 377 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0); 378 return 0; 379 } 380 381 /** 382 * zynqmp_qspi_chipselect: Select or deselect the chip select line 383 * @qspi: Pointer to the spi_device structure 384 * @is_high: Select(0) or deselect (1) the chip select line 385 */ 386 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) 387 { 388 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master); 389 ulong timeout; 390 u32 genfifoentry = 0x0, statusreg; 391 392 genfifoentry |= GQSPI_GENFIFO_MODE_SPI; 393 genfifoentry |= xqspi->genfifobus; 394 395 if (!is_high) { 396 genfifoentry |= xqspi->genfifocs; 397 genfifoentry |= GQSPI_GENFIFO_CS_SETUP; 398 } else { 399 genfifoentry |= GQSPI_GENFIFO_CS_HOLD; 400 } 401 402 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); 403 404 /* Manually start the generic FIFO command */ 405 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 406 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | 407 GQSPI_CFG_START_GEN_FIFO_MASK); 408 409 timeout = jiffies + msecs_to_jiffies(1000); 410 411 /* Wait until the generic FIFO command is empty */ 412 do { 413 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST); 414 415 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) && 416 (statusreg & GQSPI_ISR_TXEMPTY_MASK)) 417 break; 418 else 419 cpu_relax(); 420 } while (!time_after_eq(jiffies, timeout)); 421 422 if (time_after_eq(jiffies, timeout)) 423 dev_err(xqspi->dev, "Chip select timed out\n"); 424 } 425 426 /** 427 * zynqmp_qspi_setup_transfer: Configure QSPI controller for specified 428 * transfer 429 * @qspi: Pointer to the spi_device structure 430 * @transfer: Pointer to the spi_transfer structure which provides 431 * information about next transfer setup parameters 432 * 433 * Sets the operational mode of QSPI controller for the next QSPI transfer and 434 * sets the requested clock frequency. 435 * 436 * Return: Always 0 437 * 438 * Note: 439 * If the requested frequency is not an exact match with what can be 440 * obtained using the pre-scalar value, the driver sets the clock 441 * frequency which is lower than the requested frequency (maximum lower) 442 * for the transfer. 443 * 444 * If the requested frequency is higher or lower than that is supported 445 * by the QSPI controller the driver will set the highest or lowest 446 * frequency supported by controller. 447 */ 448 static int zynqmp_qspi_setup_transfer(struct spi_device *qspi, 449 struct spi_transfer *transfer) 450 { 451 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master); 452 ulong clk_rate; 453 u32 config_reg, req_hz, baud_rate_val = 0; 454 455 if (transfer) 456 req_hz = transfer->speed_hz; 457 else 458 req_hz = qspi->max_speed_hz; 459 460 /* Set the clock frequency */ 461 /* If req_hz == 0, default to lowest speed */ 462 clk_rate = clk_get_rate(xqspi->refclk); 463 464 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) && 465 (clk_rate / 466 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz) 467 baud_rate_val++; 468 469 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 470 471 /* Set the QSPI clock phase and clock polarity */ 472 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK); 473 474 if (qspi->mode & SPI_CPHA) 475 config_reg |= GQSPI_CFG_CLK_PHA_MASK; 476 if (qspi->mode & SPI_CPOL) 477 config_reg |= GQSPI_CFG_CLK_POL_MASK; 478 479 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; 480 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT); 481 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 482 return 0; 483 } 484 485 /** 486 * zynqmp_qspi_setup: Configure the QSPI controller 487 * @qspi: Pointer to the spi_device structure 488 * 489 * Sets the operational mode of QSPI controller for the next QSPI transfer, 490 * baud rate and divisor value to setup the requested qspi clock. 491 * 492 * Return: 0 on success; error value otherwise. 493 */ 494 static int zynqmp_qspi_setup(struct spi_device *qspi) 495 { 496 if (qspi->master->busy) 497 return -EBUSY; 498 return 0; 499 } 500 501 /** 502 * zynqmp_qspi_filltxfifo: Fills the TX FIFO as long as there is room in 503 * the FIFO or the bytes required to be 504 * transmitted. 505 * @xqspi: Pointer to the zynqmp_qspi structure 506 * @size: Number of bytes to be copied from TX buffer to TX FIFO 507 */ 508 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size) 509 { 510 u32 count = 0, intermediate; 511 512 while ((xqspi->bytes_to_transfer > 0) && (count < size)) { 513 memcpy(&intermediate, xqspi->txbuf, 4); 514 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate); 515 516 if (xqspi->bytes_to_transfer >= 4) { 517 xqspi->txbuf += 4; 518 xqspi->bytes_to_transfer -= 4; 519 } else { 520 xqspi->txbuf += xqspi->bytes_to_transfer; 521 xqspi->bytes_to_transfer = 0; 522 } 523 count++; 524 } 525 } 526 527 /** 528 * zynqmp_qspi_readrxfifo: Fills the RX FIFO as long as there is room in 529 * the FIFO. 530 * @xqspi: Pointer to the zynqmp_qspi structure 531 * @size: Number of bytes to be copied from RX buffer to RX FIFO 532 */ 533 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size) 534 { 535 ulong data; 536 int count = 0; 537 538 while ((count < size) && (xqspi->bytes_to_receive > 0)) { 539 if (xqspi->bytes_to_receive >= 4) { 540 (*(u32 *) xqspi->rxbuf) = 541 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST); 542 xqspi->rxbuf += 4; 543 xqspi->bytes_to_receive -= 4; 544 count += 4; 545 } else { 546 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST); 547 count += xqspi->bytes_to_receive; 548 zynqmp_qspi_copy_read_data(xqspi, data, 549 xqspi->bytes_to_receive); 550 xqspi->bytes_to_receive = 0; 551 } 552 } 553 } 554 555 /** 556 * zynqmp_process_dma_irq: Handler for DMA done interrupt of QSPI 557 * controller 558 * @xqspi: zynqmp_qspi instance pointer 559 * 560 * This function handles DMA interrupt only. 561 */ 562 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi) 563 { 564 u32 config_reg, genfifoentry; 565 566 dma_unmap_single(xqspi->dev, xqspi->dma_addr, 567 xqspi->dma_rx_bytes, DMA_FROM_DEVICE); 568 xqspi->rxbuf += xqspi->dma_rx_bytes; 569 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes; 570 xqspi->dma_rx_bytes = 0; 571 572 /* Disabling the DMA interrupts */ 573 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST, 574 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK); 575 576 if (xqspi->bytes_to_receive > 0) { 577 /* Switch to IO mode,for remaining bytes to receive */ 578 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 579 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 580 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 581 582 /* Initiate the transfer of remaining bytes */ 583 genfifoentry = xqspi->genfifoentry; 584 genfifoentry |= xqspi->bytes_to_receive; 585 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); 586 587 /* Dummy generic FIFO entry */ 588 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0); 589 590 /* Manual start */ 591 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 592 (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | 593 GQSPI_CFG_START_GEN_FIFO_MASK)); 594 595 /* Enable the RX interrupts for IO mode */ 596 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, 597 GQSPI_IER_GENFIFOEMPTY_MASK | 598 GQSPI_IER_RXNEMPTY_MASK | 599 GQSPI_IER_RXEMPTY_MASK); 600 } 601 } 602 603 /** 604 * zynqmp_qspi_irq: Interrupt service routine of the QSPI controller 605 * @irq: IRQ number 606 * @dev_id: Pointer to the xqspi structure 607 * 608 * This function handles TX empty only. 609 * On TX empty interrupt this function reads the received data from RX FIFO 610 * and fills the TX FIFO if there is any data remaining to be transferred. 611 * 612 * Return: IRQ_HANDLED when interrupt is handled 613 * IRQ_NONE otherwise. 614 */ 615 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id) 616 { 617 struct spi_master *master = dev_id; 618 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 619 int ret = IRQ_NONE; 620 u32 status, mask, dma_status = 0; 621 622 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST); 623 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status); 624 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST))); 625 626 /* Read and clear DMA status */ 627 if (xqspi->mode == GQSPI_MODE_DMA) { 628 dma_status = 629 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST); 630 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST, 631 dma_status); 632 } 633 634 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) { 635 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL); 636 ret = IRQ_HANDLED; 637 } 638 639 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) { 640 zynqmp_process_dma_irq(xqspi); 641 ret = IRQ_HANDLED; 642 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) && 643 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) { 644 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL); 645 ret = IRQ_HANDLED; 646 } 647 648 if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0) 649 && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) { 650 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK); 651 spi_finalize_current_transfer(master); 652 ret = IRQ_HANDLED; 653 } 654 return ret; 655 } 656 657 /** 658 * zynqmp_qspi_selectspimode: Selects SPI mode - x1 or x2 or x4. 659 * @xqspi: xqspi is a pointer to the GQSPI instance 660 * @spimode: spimode - SPI or DUAL or QUAD. 661 * Return: Mask to set desired SPI mode in GENFIFO entry. 662 */ 663 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, 664 u8 spimode) 665 { 666 u32 mask = 0; 667 668 switch (spimode) { 669 case GQSPI_SELECT_MODE_DUALSPI: 670 mask = GQSPI_GENFIFO_MODE_DUALSPI; 671 break; 672 case GQSPI_SELECT_MODE_QUADSPI: 673 mask = GQSPI_GENFIFO_MODE_QUADSPI; 674 break; 675 case GQSPI_SELECT_MODE_SPI: 676 mask = GQSPI_GENFIFO_MODE_SPI; 677 break; 678 default: 679 dev_warn(xqspi->dev, "Invalid SPI mode\n"); 680 } 681 682 return mask; 683 } 684 685 /** 686 * zynq_qspi_setuprxdma: This function sets up the RX DMA operation 687 * @xqspi: xqspi is a pointer to the GQSPI instance. 688 */ 689 static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi) 690 { 691 u32 rx_bytes, rx_rem, config_reg; 692 dma_addr_t addr; 693 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf; 694 695 if ((xqspi->bytes_to_receive < 8) || 696 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) { 697 /* Setting to IO mode */ 698 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 699 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 700 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 701 xqspi->mode = GQSPI_MODE_IO; 702 xqspi->dma_rx_bytes = 0; 703 return; 704 } 705 706 rx_rem = xqspi->bytes_to_receive % 4; 707 rx_bytes = (xqspi->bytes_to_receive - rx_rem); 708 709 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf, 710 rx_bytes, DMA_FROM_DEVICE); 711 if (dma_mapping_error(xqspi->dev, addr)) 712 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n"); 713 714 xqspi->dma_rx_bytes = rx_bytes; 715 xqspi->dma_addr = addr; 716 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST, 717 (u32)(addr & 0xffffffff)); 718 addr = ((addr >> 16) >> 16); 719 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST, 720 ((u32)addr) & 0xfff); 721 722 /* Enabling the DMA mode */ 723 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 724 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 725 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK; 726 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 727 728 /* Switch to DMA mode */ 729 xqspi->mode = GQSPI_MODE_DMA; 730 731 /* Write the number of bytes to transfer */ 732 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes); 733 } 734 735 /** 736 * zynqmp_qspi_txrxsetup: This function checks the TX/RX buffers in 737 * the transfer and sets up the GENFIFO entries, 738 * TX FIFO as required. 739 * @xqspi: xqspi is a pointer to the GQSPI instance. 740 * @transfer: It is a pointer to the structure containing transfer data. 741 * @genfifoentry: genfifoentry is pointer to the variable in which 742 * GENFIFO mask is returned to calling function 743 */ 744 static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi, 745 struct spi_transfer *transfer, 746 u32 *genfifoentry) 747 { 748 u32 config_reg; 749 750 /* Transmit */ 751 if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) { 752 /* Setup data to be TXed */ 753 *genfifoentry &= ~GQSPI_GENFIFO_RX; 754 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER; 755 *genfifoentry |= GQSPI_GENFIFO_TX; 756 *genfifoentry |= 757 zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits); 758 xqspi->bytes_to_transfer = transfer->len; 759 if (xqspi->mode == GQSPI_MODE_DMA) { 760 config_reg = zynqmp_gqspi_read(xqspi, 761 GQSPI_CONFIG_OFST); 762 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 763 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 764 config_reg); 765 xqspi->mode = GQSPI_MODE_IO; 766 } 767 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH); 768 /* Discard RX data */ 769 xqspi->bytes_to_receive = 0; 770 } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) { 771 /* Receive */ 772 773 /* TX auto fill */ 774 *genfifoentry &= ~GQSPI_GENFIFO_TX; 775 /* Setup RX */ 776 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER; 777 *genfifoentry |= GQSPI_GENFIFO_RX; 778 *genfifoentry |= 779 zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits); 780 xqspi->bytes_to_transfer = 0; 781 xqspi->bytes_to_receive = transfer->len; 782 zynq_qspi_setuprxdma(xqspi); 783 } 784 } 785 786 /** 787 * zynqmp_qspi_start_transfer: Initiates the QSPI transfer 788 * @master: Pointer to the spi_master structure which provides 789 * information about the controller. 790 * @qspi: Pointer to the spi_device structure 791 * @transfer: Pointer to the spi_transfer structure which provide information 792 * about next transfer parameters 793 * 794 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the 795 * transfer to be completed. 796 * 797 * Return: Number of bytes transferred in the last transfer 798 */ 799 static int zynqmp_qspi_start_transfer(struct spi_master *master, 800 struct spi_device *qspi, 801 struct spi_transfer *transfer) 802 { 803 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 804 u32 genfifoentry = 0x0, transfer_len; 805 806 xqspi->txbuf = transfer->tx_buf; 807 xqspi->rxbuf = transfer->rx_buf; 808 809 zynqmp_qspi_setup_transfer(qspi, transfer); 810 811 genfifoentry |= xqspi->genfifocs; 812 genfifoentry |= xqspi->genfifobus; 813 814 zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry); 815 816 if (xqspi->mode == GQSPI_MODE_DMA) 817 transfer_len = xqspi->dma_rx_bytes; 818 else 819 transfer_len = transfer->len; 820 821 xqspi->genfifoentry = genfifoentry; 822 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) { 823 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK; 824 genfifoentry |= transfer_len; 825 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); 826 } else { 827 int tempcount = transfer_len; 828 u32 exponent = 8; /* 2^8 = 256 */ 829 u8 imm_data = tempcount & 0xFF; 830 831 tempcount &= ~(tempcount & 0xFF); 832 /* Immediate entry */ 833 if (tempcount != 0) { 834 /* Exponent entries */ 835 genfifoentry |= GQSPI_GENFIFO_EXP; 836 while (tempcount != 0) { 837 if (tempcount & GQSPI_GENFIFO_EXP_START) { 838 genfifoentry &= 839 ~GQSPI_GENFIFO_IMM_DATA_MASK; 840 genfifoentry |= exponent; 841 zynqmp_gqspi_write(xqspi, 842 GQSPI_GEN_FIFO_OFST, 843 genfifoentry); 844 } 845 tempcount = tempcount >> 1; 846 exponent++; 847 } 848 } 849 if (imm_data != 0) { 850 genfifoentry &= ~GQSPI_GENFIFO_EXP; 851 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK; 852 genfifoentry |= (u8) (imm_data & 0xFF); 853 zynqmp_gqspi_write(xqspi, 854 GQSPI_GEN_FIFO_OFST, genfifoentry); 855 } 856 } 857 858 if ((xqspi->mode == GQSPI_MODE_IO) && 859 (xqspi->rxbuf != NULL)) { 860 /* Dummy generic FIFO entry */ 861 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0); 862 } 863 864 /* Since we are using manual mode */ 865 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 866 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | 867 GQSPI_CFG_START_GEN_FIFO_MASK); 868 869 if (xqspi->txbuf != NULL) 870 /* Enable interrupts for TX */ 871 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, 872 GQSPI_IER_TXEMPTY_MASK | 873 GQSPI_IER_GENFIFOEMPTY_MASK | 874 GQSPI_IER_TXNOT_FULL_MASK); 875 876 if (xqspi->rxbuf != NULL) { 877 /* Enable interrupts for RX */ 878 if (xqspi->mode == GQSPI_MODE_DMA) { 879 /* Enable DMA interrupts */ 880 zynqmp_gqspi_write(xqspi, 881 GQSPI_QSPIDMA_DST_I_EN_OFST, 882 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK); 883 } else { 884 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, 885 GQSPI_IER_GENFIFOEMPTY_MASK | 886 GQSPI_IER_RXNEMPTY_MASK | 887 GQSPI_IER_RXEMPTY_MASK); 888 } 889 } 890 891 return transfer->len; 892 } 893 894 /** 895 * zynqmp_qspi_suspend: Suspend method for the QSPI driver 896 * @_dev: Address of the platform_device structure 897 * 898 * This function stops the QSPI driver queue and disables the QSPI controller 899 * 900 * Return: Always 0 901 */ 902 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev) 903 { 904 struct spi_master *master = dev_get_drvdata(dev); 905 906 spi_master_suspend(master); 907 908 zynqmp_unprepare_transfer_hardware(master); 909 910 return 0; 911 } 912 913 /** 914 * zynqmp_qspi_resume: Resume method for the QSPI driver 915 * @dev: Address of the platform_device structure 916 * 917 * The function starts the QSPI driver queue and initializes the QSPI 918 * controller 919 * 920 * Return: 0 on success; error value otherwise 921 */ 922 static int __maybe_unused zynqmp_qspi_resume(struct device *dev) 923 { 924 struct spi_master *master = dev_get_drvdata(dev); 925 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 926 int ret = 0; 927 928 ret = clk_enable(xqspi->pclk); 929 if (ret) { 930 dev_err(dev, "Cannot enable APB clock.\n"); 931 return ret; 932 } 933 934 ret = clk_enable(xqspi->refclk); 935 if (ret) { 936 dev_err(dev, "Cannot enable device clock.\n"); 937 clk_disable(xqspi->pclk); 938 return ret; 939 } 940 941 spi_master_resume(master); 942 943 clk_disable(xqspi->refclk); 944 clk_disable(xqspi->pclk); 945 return 0; 946 } 947 948 /** 949 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver 950 * @dev: Address of the platform_device structure 951 * 952 * This function disables the clocks 953 * 954 * Return: Always 0 955 */ 956 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev) 957 { 958 struct spi_master *master = dev_get_drvdata(dev); 959 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 960 961 clk_disable(xqspi->refclk); 962 clk_disable(xqspi->pclk); 963 964 return 0; 965 } 966 967 /** 968 * zynqmp_runtime_resume - Runtime resume method for the SPI driver 969 * @dev: Address of the platform_device structure 970 * 971 * This function enables the clocks 972 * 973 * Return: 0 on success and error value on error 974 */ 975 static int __maybe_unused zynqmp_runtime_resume(struct device *dev) 976 { 977 struct spi_master *master = dev_get_drvdata(dev); 978 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 979 int ret; 980 981 ret = clk_enable(xqspi->pclk); 982 if (ret) { 983 dev_err(dev, "Cannot enable APB clock.\n"); 984 return ret; 985 } 986 987 ret = clk_enable(xqspi->refclk); 988 if (ret) { 989 dev_err(dev, "Cannot enable device clock.\n"); 990 clk_disable(xqspi->pclk); 991 return ret; 992 } 993 994 return 0; 995 } 996 997 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = { 998 SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend, 999 zynqmp_runtime_resume, NULL) 1000 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume) 1001 }; 1002 1003 /** 1004 * zynqmp_qspi_probe: Probe method for the QSPI driver 1005 * @pdev: Pointer to the platform_device structure 1006 * 1007 * This function initializes the driver data structures and the hardware. 1008 * 1009 * Return: 0 on success; error value otherwise 1010 */ 1011 static int zynqmp_qspi_probe(struct platform_device *pdev) 1012 { 1013 int ret = 0; 1014 struct spi_master *master; 1015 struct zynqmp_qspi *xqspi; 1016 struct device *dev = &pdev->dev; 1017 1018 eemi_ops = zynqmp_pm_get_eemi_ops(); 1019 if (IS_ERR(eemi_ops)) 1020 return PTR_ERR(eemi_ops); 1021 1022 master = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); 1023 if (!master) 1024 return -ENOMEM; 1025 1026 xqspi = spi_master_get_devdata(master); 1027 master->dev.of_node = pdev->dev.of_node; 1028 platform_set_drvdata(pdev, master); 1029 1030 xqspi->regs = devm_platform_ioremap_resource(pdev, 0); 1031 if (IS_ERR(xqspi->regs)) { 1032 ret = PTR_ERR(xqspi->regs); 1033 goto remove_master; 1034 } 1035 1036 xqspi->dev = dev; 1037 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk"); 1038 if (IS_ERR(xqspi->pclk)) { 1039 dev_err(dev, "pclk clock not found.\n"); 1040 ret = PTR_ERR(xqspi->pclk); 1041 goto remove_master; 1042 } 1043 1044 ret = clk_prepare_enable(xqspi->pclk); 1045 if (ret) { 1046 dev_err(dev, "Unable to enable APB clock.\n"); 1047 goto remove_master; 1048 } 1049 1050 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk"); 1051 if (IS_ERR(xqspi->refclk)) { 1052 dev_err(dev, "ref_clk clock not found.\n"); 1053 ret = PTR_ERR(xqspi->refclk); 1054 goto clk_dis_pclk; 1055 } 1056 1057 ret = clk_prepare_enable(xqspi->refclk); 1058 if (ret) { 1059 dev_err(dev, "Unable to enable device clock.\n"); 1060 goto clk_dis_pclk; 1061 } 1062 1063 pm_runtime_use_autosuspend(&pdev->dev); 1064 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 1065 pm_runtime_set_active(&pdev->dev); 1066 pm_runtime_enable(&pdev->dev); 1067 /* QSPI controller initializations */ 1068 zynqmp_qspi_init_hw(xqspi); 1069 1070 pm_runtime_mark_last_busy(&pdev->dev); 1071 pm_runtime_put_autosuspend(&pdev->dev); 1072 xqspi->irq = platform_get_irq(pdev, 0); 1073 if (xqspi->irq <= 0) { 1074 ret = -ENXIO; 1075 goto clk_dis_all; 1076 } 1077 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq, 1078 0, pdev->name, master); 1079 if (ret != 0) { 1080 ret = -ENXIO; 1081 dev_err(dev, "request_irq failed\n"); 1082 goto clk_dis_all; 1083 } 1084 1085 master->num_chipselect = GQSPI_DEFAULT_NUM_CS; 1086 1087 master->setup = zynqmp_qspi_setup; 1088 master->set_cs = zynqmp_qspi_chipselect; 1089 master->transfer_one = zynqmp_qspi_start_transfer; 1090 master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware; 1091 master->unprepare_transfer_hardware = 1092 zynqmp_unprepare_transfer_hardware; 1093 master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; 1094 master->bits_per_word_mask = SPI_BPW_MASK(8); 1095 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | 1096 SPI_TX_DUAL | SPI_TX_QUAD; 1097 1098 if (master->dev.parent == NULL) 1099 master->dev.parent = &master->dev; 1100 1101 ret = spi_register_master(master); 1102 if (ret) 1103 goto clk_dis_all; 1104 1105 return 0; 1106 1107 clk_dis_all: 1108 pm_runtime_set_suspended(&pdev->dev); 1109 pm_runtime_disable(&pdev->dev); 1110 clk_disable_unprepare(xqspi->refclk); 1111 clk_dis_pclk: 1112 clk_disable_unprepare(xqspi->pclk); 1113 remove_master: 1114 spi_master_put(master); 1115 1116 return ret; 1117 } 1118 1119 /** 1120 * zynqmp_qspi_remove: Remove method for the QSPI driver 1121 * @pdev: Pointer to the platform_device structure 1122 * 1123 * This function is called if a device is physically removed from the system or 1124 * if the driver module is being unloaded. It frees all resources allocated to 1125 * the device. 1126 * 1127 * Return: 0 Always 1128 */ 1129 static int zynqmp_qspi_remove(struct platform_device *pdev) 1130 { 1131 struct spi_master *master = platform_get_drvdata(pdev); 1132 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 1133 1134 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0); 1135 clk_disable_unprepare(xqspi->refclk); 1136 clk_disable_unprepare(xqspi->pclk); 1137 pm_runtime_set_suspended(&pdev->dev); 1138 pm_runtime_disable(&pdev->dev); 1139 1140 spi_unregister_master(master); 1141 1142 return 0; 1143 } 1144 1145 static const struct of_device_id zynqmp_qspi_of_match[] = { 1146 { .compatible = "xlnx,zynqmp-qspi-1.0", }, 1147 { /* End of table */ } 1148 }; 1149 1150 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match); 1151 1152 static struct platform_driver zynqmp_qspi_driver = { 1153 .probe = zynqmp_qspi_probe, 1154 .remove = zynqmp_qspi_remove, 1155 .driver = { 1156 .name = "zynqmp-qspi", 1157 .of_match_table = zynqmp_qspi_of_match, 1158 .pm = &zynqmp_qspi_dev_pm_ops, 1159 }, 1160 }; 1161 1162 module_platform_driver(zynqmp_qspi_driver); 1163 1164 MODULE_AUTHOR("Xilinx, Inc."); 1165 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver"); 1166 MODULE_LICENSE("GPL"); 1167