1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver 4 * (master mode only) 5 * 6 * Copyright (C) 2009 - 2015 Xilinx, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/firmware/xlnx-zynqmp.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_address.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spinlock.h> 23 #include <linux/workqueue.h> 24 25 /* Generic QSPI register offsets */ 26 #define GQSPI_CONFIG_OFST 0x00000100 27 #define GQSPI_ISR_OFST 0x00000104 28 #define GQSPI_IDR_OFST 0x0000010C 29 #define GQSPI_IER_OFST 0x00000108 30 #define GQSPI_IMASK_OFST 0x00000110 31 #define GQSPI_EN_OFST 0x00000114 32 #define GQSPI_TXD_OFST 0x0000011C 33 #define GQSPI_RXD_OFST 0x00000120 34 #define GQSPI_TX_THRESHOLD_OFST 0x00000128 35 #define GQSPI_RX_THRESHOLD_OFST 0x0000012C 36 #define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138 37 #define GQSPI_GEN_FIFO_OFST 0x00000140 38 #define GQSPI_SEL_OFST 0x00000144 39 #define GQSPI_GF_THRESHOLD_OFST 0x00000150 40 #define GQSPI_FIFO_CTRL_OFST 0x0000014C 41 #define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C 42 #define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804 43 #define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808 44 #define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814 45 #define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818 46 #define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C 47 #define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820 48 #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800 49 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828 50 51 /* GQSPI register bit masks */ 52 #define GQSPI_SEL_MASK 0x00000001 53 #define GQSPI_EN_MASK 0x00000001 54 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 55 #define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002 56 #define GQSPI_IDR_ALL_MASK 0x00000FBE 57 #define GQSPI_CFG_MODE_EN_MASK 0xC0000000 58 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000 59 #define GQSPI_CFG_ENDIAN_MASK 0x04000000 60 #define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000 61 #define GQSPI_CFG_WP_HOLD_MASK 0x00080000 62 #define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038 63 #define GQSPI_CFG_CLK_PHA_MASK 0x00000004 64 #define GQSPI_CFG_CLK_POL_MASK 0x00000002 65 #define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000 66 #define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF 67 #define GQSPI_GENFIFO_DATA_XFER 0x00000100 68 #define GQSPI_GENFIFO_EXP 0x00000200 69 #define GQSPI_GENFIFO_MODE_SPI 0x00000400 70 #define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800 71 #define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00 72 #define GQSPI_GENFIFO_MODE_MASK 0x00000C00 73 #define GQSPI_GENFIFO_CS_LOWER 0x00001000 74 #define GQSPI_GENFIFO_CS_UPPER 0x00002000 75 #define GQSPI_GENFIFO_BUS_LOWER 0x00004000 76 #define GQSPI_GENFIFO_BUS_UPPER 0x00008000 77 #define GQSPI_GENFIFO_BUS_BOTH 0x0000C000 78 #define GQSPI_GENFIFO_BUS_MASK 0x0000C000 79 #define GQSPI_GENFIFO_TX 0x00010000 80 #define GQSPI_GENFIFO_RX 0x00020000 81 #define GQSPI_GENFIFO_STRIPE 0x00040000 82 #define GQSPI_GENFIFO_POLL 0x00080000 83 #define GQSPI_GENFIFO_EXP_START 0x00000100 84 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004 85 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002 86 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001 87 #define GQSPI_ISR_RXEMPTY_MASK 0x00000800 88 #define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400 89 #define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200 90 #define GQSPI_ISR_TXEMPTY_MASK 0x00000100 91 #define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080 92 #define GQSPI_ISR_RXFULL_MASK 0x00000020 93 #define GQSPI_ISR_RXNEMPTY_MASK 0x00000010 94 #define GQSPI_ISR_TXFULL_MASK 0x00000008 95 #define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004 96 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002 97 #define GQSPI_IER_TXNOT_FULL_MASK 0x00000004 98 #define GQSPI_IER_RXEMPTY_MASK 0x00000800 99 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002 100 #define GQSPI_IER_RXNEMPTY_MASK 0x00000010 101 #define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080 102 #define GQSPI_IER_TXEMPTY_MASK 0x00000100 103 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE 104 #define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000 105 #define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000 106 #define GQSPI_ISR_IDR_MASK 0x00000994 107 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002 108 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002 109 #define GQSPI_IRQ_MASK 0x00000980 110 111 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3 112 #define GQSPI_GENFIFO_CS_SETUP 0x4 113 #define GQSPI_GENFIFO_CS_HOLD 0x3 114 #define GQSPI_TXD_DEPTH 64 115 #define GQSPI_RX_FIFO_THRESHOLD 32 116 #define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4) 117 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32 118 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\ 119 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL) 120 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10 121 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00 122 #define GQSPI_SELECT_FLASH_CS_LOWER 0x1 123 #define GQSPI_SELECT_FLASH_CS_UPPER 0x2 124 #define GQSPI_SELECT_FLASH_CS_BOTH 0x3 125 #define GQSPI_SELECT_FLASH_BUS_LOWER 0x1 126 #define GQSPI_SELECT_FLASH_BUS_UPPER 0x2 127 #define GQSPI_SELECT_FLASH_BUS_BOTH 0x3 128 #define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ 129 #define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */ 130 #define GQSPI_SELECT_MODE_SPI 0x1 131 #define GQSPI_SELECT_MODE_DUALSPI 0x2 132 #define GQSPI_SELECT_MODE_QUADSPI 0x4 133 #define GQSPI_DMA_UNALIGN 0x3 134 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */ 135 136 #define SPI_AUTOSUSPEND_TIMEOUT 3000 137 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; 138 static const struct zynqmp_eemi_ops *eemi_ops; 139 140 /** 141 * struct zynqmp_qspi - Defines qspi driver instance 142 * @regs: Virtual address of the QSPI controller registers 143 * @refclk: Pointer to the peripheral clock 144 * @pclk: Pointer to the APB clock 145 * @irq: IRQ number 146 * @dev: Pointer to struct device 147 * @txbuf: Pointer to the TX buffer 148 * @rxbuf: Pointer to the RX buffer 149 * @bytes_to_transfer: Number of bytes left to transfer 150 * @bytes_to_receive: Number of bytes left to receive 151 * @genfifocs: Used for chip select 152 * @genfifobus: Used to select the upper or lower bus 153 * @dma_rx_bytes: Remaining bytes to receive by DMA mode 154 * @dma_addr: DMA address after mapping the kernel buffer 155 * @genfifoentry: Used for storing the genfifoentry instruction. 156 * @mode: Defines the mode in which QSPI is operating 157 */ 158 struct zynqmp_qspi { 159 void __iomem *regs; 160 struct clk *refclk; 161 struct clk *pclk; 162 int irq; 163 struct device *dev; 164 const void *txbuf; 165 void *rxbuf; 166 int bytes_to_transfer; 167 int bytes_to_receive; 168 u32 genfifocs; 169 u32 genfifobus; 170 u32 dma_rx_bytes; 171 dma_addr_t dma_addr; 172 u32 genfifoentry; 173 enum mode_type mode; 174 }; 175 176 /** 177 * zynqmp_gqspi_read: For GQSPI controller read operation 178 * @xqspi: Pointer to the zynqmp_qspi structure 179 * @offset: Offset from where to read 180 */ 181 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset) 182 { 183 return readl_relaxed(xqspi->regs + offset); 184 } 185 186 /** 187 * zynqmp_gqspi_write: For GQSPI controller write operation 188 * @xqspi: Pointer to the zynqmp_qspi structure 189 * @offset: Offset where to write 190 * @val: Value to be written 191 */ 192 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset, 193 u32 val) 194 { 195 writel_relaxed(val, (xqspi->regs + offset)); 196 } 197 198 /** 199 * zynqmp_gqspi_selectslave: For selection of slave device 200 * @instanceptr: Pointer to the zynqmp_qspi structure 201 * @flashcs: For chip select 202 * @flashbus: To check which bus is selected- upper or lower 203 */ 204 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr, 205 u8 slavecs, u8 slavebus) 206 { 207 /* 208 * Bus and CS lines selected here will be updated in the instance and 209 * used for subsequent GENFIFO entries during transfer. 210 */ 211 212 /* Choose slave select line */ 213 switch (slavecs) { 214 case GQSPI_SELECT_FLASH_CS_BOTH: 215 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER | 216 GQSPI_GENFIFO_CS_UPPER; 217 break; 218 case GQSPI_SELECT_FLASH_CS_UPPER: 219 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER; 220 break; 221 case GQSPI_SELECT_FLASH_CS_LOWER: 222 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER; 223 break; 224 default: 225 dev_warn(instanceptr->dev, "Invalid slave select\n"); 226 } 227 228 /* Choose the bus */ 229 switch (slavebus) { 230 case GQSPI_SELECT_FLASH_BUS_BOTH: 231 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER | 232 GQSPI_GENFIFO_BUS_UPPER; 233 break; 234 case GQSPI_SELECT_FLASH_BUS_UPPER: 235 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER; 236 break; 237 case GQSPI_SELECT_FLASH_BUS_LOWER: 238 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER; 239 break; 240 default: 241 dev_warn(instanceptr->dev, "Invalid slave bus\n"); 242 } 243 } 244 245 /** 246 * zynqmp_qspi_init_hw: Initialize the hardware 247 * @xqspi: Pointer to the zynqmp_qspi structure 248 * 249 * The default settings of the QSPI controller's configurable parameters on 250 * reset are 251 * - Master mode 252 * - TX threshold set to 1 253 * - RX threshold set to 1 254 * - Flash memory interface mode enabled 255 * This function performs the following actions 256 * - Disable and clear all the interrupts 257 * - Enable manual slave select 258 * - Enable manual start 259 * - Deselect all the chip select lines 260 * - Set the little endian mode of TX FIFO and 261 * - Enable the QSPI controller 262 */ 263 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi) 264 { 265 u32 config_reg; 266 267 /* Select the GQSPI mode */ 268 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK); 269 /* Clear and disable interrupts */ 270 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, 271 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) | 272 GQSPI_ISR_WR_TO_CLR_MASK); 273 /* Clear the DMA STS */ 274 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST, 275 zynqmp_gqspi_read(xqspi, 276 GQSPI_QSPIDMA_DST_I_STS_OFST)); 277 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST, 278 zynqmp_gqspi_read(xqspi, 279 GQSPI_QSPIDMA_DST_STS_OFST) | 280 GQSPI_QSPIDMA_DST_STS_WTC); 281 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK); 282 zynqmp_gqspi_write(xqspi, 283 GQSPI_QSPIDMA_DST_I_DIS_OFST, 284 GQSPI_QSPIDMA_DST_INTR_ALL_MASK); 285 /* Disable the GQSPI */ 286 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0); 287 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 288 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 289 /* Manual start */ 290 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK; 291 /* Little endian by default */ 292 config_reg &= ~GQSPI_CFG_ENDIAN_MASK; 293 /* Disable poll time out */ 294 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK; 295 /* Set hold bit */ 296 config_reg |= GQSPI_CFG_WP_HOLD_MASK; 297 /* Clear pre-scalar by default */ 298 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; 299 /* CPHA 0 */ 300 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; 301 /* CPOL 0 */ 302 config_reg &= ~GQSPI_CFG_CLK_POL_MASK; 303 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 304 305 /* Clear the TX and RX FIFO */ 306 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST, 307 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK | 308 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK | 309 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK); 310 /* Set by default to allow for high frequencies */ 311 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, 312 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) | 313 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK); 314 /* Reset thresholds */ 315 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST, 316 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL); 317 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST, 318 GQSPI_RX_FIFO_THRESHOLD); 319 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST, 320 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL); 321 zynqmp_gqspi_selectslave(xqspi, 322 GQSPI_SELECT_FLASH_CS_LOWER, 323 GQSPI_SELECT_FLASH_BUS_LOWER); 324 /* Initialize DMA */ 325 zynqmp_gqspi_write(xqspi, 326 GQSPI_QSPIDMA_DST_CTRL_OFST, 327 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL); 328 329 /* Enable the GQSPI */ 330 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK); 331 } 332 333 /** 334 * zynqmp_qspi_copy_read_data: Copy data to RX buffer 335 * @xqspi: Pointer to the zynqmp_qspi structure 336 * @data: The variable where data is stored 337 * @size: Number of bytes to be copied from data to RX buffer 338 */ 339 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi, 340 ulong data, u8 size) 341 { 342 memcpy(xqspi->rxbuf, &data, size); 343 xqspi->rxbuf += size; 344 xqspi->bytes_to_receive -= size; 345 } 346 347 /** 348 * zynqmp_prepare_transfer_hardware: Prepares hardware for transfer. 349 * @master: Pointer to the spi_master structure which provides 350 * information about the controller. 351 * 352 * This function enables SPI master controller. 353 * 354 * Return: 0 on success; error value otherwise 355 */ 356 static int zynqmp_prepare_transfer_hardware(struct spi_master *master) 357 { 358 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 359 360 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK); 361 return 0; 362 } 363 364 /** 365 * zynqmp_unprepare_transfer_hardware: Relaxes hardware after transfer 366 * @master: Pointer to the spi_master structure which provides 367 * information about the controller. 368 * 369 * This function disables the SPI master controller. 370 * 371 * Return: Always 0 372 */ 373 static int zynqmp_unprepare_transfer_hardware(struct spi_master *master) 374 { 375 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 376 377 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0); 378 return 0; 379 } 380 381 /** 382 * zynqmp_qspi_chipselect: Select or deselect the chip select line 383 * @qspi: Pointer to the spi_device structure 384 * @is_high: Select(0) or deselect (1) the chip select line 385 */ 386 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) 387 { 388 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master); 389 ulong timeout; 390 u32 genfifoentry = 0x0, statusreg; 391 392 genfifoentry |= GQSPI_GENFIFO_MODE_SPI; 393 genfifoentry |= xqspi->genfifobus; 394 395 if (!is_high) { 396 genfifoentry |= xqspi->genfifocs; 397 genfifoentry |= GQSPI_GENFIFO_CS_SETUP; 398 } else { 399 genfifoentry |= GQSPI_GENFIFO_CS_HOLD; 400 } 401 402 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); 403 404 /* Dummy generic FIFO entry */ 405 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0); 406 407 /* Manually start the generic FIFO command */ 408 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 409 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | 410 GQSPI_CFG_START_GEN_FIFO_MASK); 411 412 timeout = jiffies + msecs_to_jiffies(1000); 413 414 /* Wait until the generic FIFO command is empty */ 415 do { 416 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST); 417 418 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) && 419 (statusreg & GQSPI_ISR_TXEMPTY_MASK)) 420 break; 421 else 422 cpu_relax(); 423 } while (!time_after_eq(jiffies, timeout)); 424 425 if (time_after_eq(jiffies, timeout)) 426 dev_err(xqspi->dev, "Chip select timed out\n"); 427 } 428 429 /** 430 * zynqmp_qspi_setup_transfer: Configure QSPI controller for specified 431 * transfer 432 * @qspi: Pointer to the spi_device structure 433 * @transfer: Pointer to the spi_transfer structure which provides 434 * information about next transfer setup parameters 435 * 436 * Sets the operational mode of QSPI controller for the next QSPI transfer and 437 * sets the requested clock frequency. 438 * 439 * Return: Always 0 440 * 441 * Note: 442 * If the requested frequency is not an exact match with what can be 443 * obtained using the pre-scalar value, the driver sets the clock 444 * frequency which is lower than the requested frequency (maximum lower) 445 * for the transfer. 446 * 447 * If the requested frequency is higher or lower than that is supported 448 * by the QSPI controller the driver will set the highest or lowest 449 * frequency supported by controller. 450 */ 451 static int zynqmp_qspi_setup_transfer(struct spi_device *qspi, 452 struct spi_transfer *transfer) 453 { 454 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master); 455 ulong clk_rate; 456 u32 config_reg, req_hz, baud_rate_val = 0; 457 458 if (transfer) 459 req_hz = transfer->speed_hz; 460 else 461 req_hz = qspi->max_speed_hz; 462 463 /* Set the clock frequency */ 464 /* If req_hz == 0, default to lowest speed */ 465 clk_rate = clk_get_rate(xqspi->refclk); 466 467 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) && 468 (clk_rate / 469 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz) 470 baud_rate_val++; 471 472 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 473 474 /* Set the QSPI clock phase and clock polarity */ 475 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK); 476 477 if (qspi->mode & SPI_CPHA) 478 config_reg |= GQSPI_CFG_CLK_PHA_MASK; 479 if (qspi->mode & SPI_CPOL) 480 config_reg |= GQSPI_CFG_CLK_POL_MASK; 481 482 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; 483 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT); 484 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 485 return 0; 486 } 487 488 /** 489 * zynqmp_qspi_setup: Configure the QSPI controller 490 * @qspi: Pointer to the spi_device structure 491 * 492 * Sets the operational mode of QSPI controller for the next QSPI transfer, 493 * baud rate and divisor value to setup the requested qspi clock. 494 * 495 * Return: 0 on success; error value otherwise. 496 */ 497 static int zynqmp_qspi_setup(struct spi_device *qspi) 498 { 499 if (qspi->master->busy) 500 return -EBUSY; 501 return 0; 502 } 503 504 /** 505 * zynqmp_qspi_filltxfifo: Fills the TX FIFO as long as there is room in 506 * the FIFO or the bytes required to be 507 * transmitted. 508 * @xqspi: Pointer to the zynqmp_qspi structure 509 * @size: Number of bytes to be copied from TX buffer to TX FIFO 510 */ 511 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size) 512 { 513 u32 count = 0, intermediate; 514 515 while ((xqspi->bytes_to_transfer > 0) && (count < size)) { 516 memcpy(&intermediate, xqspi->txbuf, 4); 517 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate); 518 519 if (xqspi->bytes_to_transfer >= 4) { 520 xqspi->txbuf += 4; 521 xqspi->bytes_to_transfer -= 4; 522 } else { 523 xqspi->txbuf += xqspi->bytes_to_transfer; 524 xqspi->bytes_to_transfer = 0; 525 } 526 count++; 527 } 528 } 529 530 /** 531 * zynqmp_qspi_readrxfifo: Fills the RX FIFO as long as there is room in 532 * the FIFO. 533 * @xqspi: Pointer to the zynqmp_qspi structure 534 * @size: Number of bytes to be copied from RX buffer to RX FIFO 535 */ 536 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size) 537 { 538 ulong data; 539 int count = 0; 540 541 while ((count < size) && (xqspi->bytes_to_receive > 0)) { 542 if (xqspi->bytes_to_receive >= 4) { 543 (*(u32 *) xqspi->rxbuf) = 544 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST); 545 xqspi->rxbuf += 4; 546 xqspi->bytes_to_receive -= 4; 547 count += 4; 548 } else { 549 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST); 550 count += xqspi->bytes_to_receive; 551 zynqmp_qspi_copy_read_data(xqspi, data, 552 xqspi->bytes_to_receive); 553 xqspi->bytes_to_receive = 0; 554 } 555 } 556 } 557 558 /** 559 * zynqmp_process_dma_irq: Handler for DMA done interrupt of QSPI 560 * controller 561 * @xqspi: zynqmp_qspi instance pointer 562 * 563 * This function handles DMA interrupt only. 564 */ 565 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi) 566 { 567 u32 config_reg, genfifoentry; 568 569 dma_unmap_single(xqspi->dev, xqspi->dma_addr, 570 xqspi->dma_rx_bytes, DMA_FROM_DEVICE); 571 xqspi->rxbuf += xqspi->dma_rx_bytes; 572 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes; 573 xqspi->dma_rx_bytes = 0; 574 575 /* Disabling the DMA interrupts */ 576 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST, 577 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK); 578 579 if (xqspi->bytes_to_receive > 0) { 580 /* Switch to IO mode,for remaining bytes to receive */ 581 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 582 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 583 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 584 585 /* Initiate the transfer of remaining bytes */ 586 genfifoentry = xqspi->genfifoentry; 587 genfifoentry |= xqspi->bytes_to_receive; 588 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); 589 590 /* Dummy generic FIFO entry */ 591 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0); 592 593 /* Manual start */ 594 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 595 (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | 596 GQSPI_CFG_START_GEN_FIFO_MASK)); 597 598 /* Enable the RX interrupts for IO mode */ 599 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, 600 GQSPI_IER_GENFIFOEMPTY_MASK | 601 GQSPI_IER_RXNEMPTY_MASK | 602 GQSPI_IER_RXEMPTY_MASK); 603 } 604 } 605 606 /** 607 * zynqmp_qspi_irq: Interrupt service routine of the QSPI controller 608 * @irq: IRQ number 609 * @dev_id: Pointer to the xqspi structure 610 * 611 * This function handles TX empty only. 612 * On TX empty interrupt this function reads the received data from RX FIFO 613 * and fills the TX FIFO if there is any data remaining to be transferred. 614 * 615 * Return: IRQ_HANDLED when interrupt is handled 616 * IRQ_NONE otherwise. 617 */ 618 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id) 619 { 620 struct spi_master *master = dev_id; 621 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 622 int ret = IRQ_NONE; 623 u32 status, mask, dma_status = 0; 624 625 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST); 626 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status); 627 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST))); 628 629 /* Read and clear DMA status */ 630 if (xqspi->mode == GQSPI_MODE_DMA) { 631 dma_status = 632 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST); 633 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST, 634 dma_status); 635 } 636 637 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) { 638 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL); 639 ret = IRQ_HANDLED; 640 } 641 642 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) { 643 zynqmp_process_dma_irq(xqspi); 644 ret = IRQ_HANDLED; 645 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) && 646 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) { 647 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL); 648 ret = IRQ_HANDLED; 649 } 650 651 if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0) 652 && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) { 653 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK); 654 spi_finalize_current_transfer(master); 655 ret = IRQ_HANDLED; 656 } 657 return ret; 658 } 659 660 /** 661 * zynqmp_qspi_selectspimode: Selects SPI mode - x1 or x2 or x4. 662 * @xqspi: xqspi is a pointer to the GQSPI instance 663 * @spimode: spimode - SPI or DUAL or QUAD. 664 * Return: Mask to set desired SPI mode in GENFIFO entry. 665 */ 666 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, 667 u8 spimode) 668 { 669 u32 mask = 0; 670 671 switch (spimode) { 672 case GQSPI_SELECT_MODE_DUALSPI: 673 mask = GQSPI_GENFIFO_MODE_DUALSPI; 674 break; 675 case GQSPI_SELECT_MODE_QUADSPI: 676 mask = GQSPI_GENFIFO_MODE_QUADSPI; 677 break; 678 case GQSPI_SELECT_MODE_SPI: 679 mask = GQSPI_GENFIFO_MODE_SPI; 680 break; 681 default: 682 dev_warn(xqspi->dev, "Invalid SPI mode\n"); 683 } 684 685 return mask; 686 } 687 688 /** 689 * zynq_qspi_setuprxdma: This function sets up the RX DMA operation 690 * @xqspi: xqspi is a pointer to the GQSPI instance. 691 */ 692 static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi) 693 { 694 u32 rx_bytes, rx_rem, config_reg; 695 dma_addr_t addr; 696 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf; 697 698 if ((xqspi->bytes_to_receive < 8) || 699 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) { 700 /* Setting to IO mode */ 701 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 702 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 703 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 704 xqspi->mode = GQSPI_MODE_IO; 705 xqspi->dma_rx_bytes = 0; 706 return; 707 } 708 709 rx_rem = xqspi->bytes_to_receive % 4; 710 rx_bytes = (xqspi->bytes_to_receive - rx_rem); 711 712 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf, 713 rx_bytes, DMA_FROM_DEVICE); 714 if (dma_mapping_error(xqspi->dev, addr)) 715 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n"); 716 717 xqspi->dma_rx_bytes = rx_bytes; 718 xqspi->dma_addr = addr; 719 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST, 720 (u32)(addr & 0xffffffff)); 721 addr = ((addr >> 16) >> 16); 722 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST, 723 ((u32)addr) & 0xfff); 724 725 /* Enabling the DMA mode */ 726 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 727 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 728 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK; 729 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 730 731 /* Switch to DMA mode */ 732 xqspi->mode = GQSPI_MODE_DMA; 733 734 /* Write the number of bytes to transfer */ 735 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes); 736 } 737 738 /** 739 * zynqmp_qspi_txrxsetup: This function checks the TX/RX buffers in 740 * the transfer and sets up the GENFIFO entries, 741 * TX FIFO as required. 742 * @xqspi: xqspi is a pointer to the GQSPI instance. 743 * @transfer: It is a pointer to the structure containing transfer data. 744 * @genfifoentry: genfifoentry is pointer to the variable in which 745 * GENFIFO mask is returned to calling function 746 */ 747 static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi, 748 struct spi_transfer *transfer, 749 u32 *genfifoentry) 750 { 751 u32 config_reg; 752 753 /* Transmit */ 754 if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) { 755 /* Setup data to be TXed */ 756 *genfifoentry &= ~GQSPI_GENFIFO_RX; 757 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER; 758 *genfifoentry |= GQSPI_GENFIFO_TX; 759 *genfifoentry |= 760 zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits); 761 xqspi->bytes_to_transfer = transfer->len; 762 if (xqspi->mode == GQSPI_MODE_DMA) { 763 config_reg = zynqmp_gqspi_read(xqspi, 764 GQSPI_CONFIG_OFST); 765 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 766 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 767 config_reg); 768 xqspi->mode = GQSPI_MODE_IO; 769 } 770 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH); 771 /* Discard RX data */ 772 xqspi->bytes_to_receive = 0; 773 } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) { 774 /* Receive */ 775 776 /* TX auto fill */ 777 *genfifoentry &= ~GQSPI_GENFIFO_TX; 778 /* Setup RX */ 779 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER; 780 *genfifoentry |= GQSPI_GENFIFO_RX; 781 *genfifoentry |= 782 zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits); 783 xqspi->bytes_to_transfer = 0; 784 xqspi->bytes_to_receive = transfer->len; 785 zynq_qspi_setuprxdma(xqspi); 786 } 787 } 788 789 /** 790 * zynqmp_qspi_start_transfer: Initiates the QSPI transfer 791 * @master: Pointer to the spi_master structure which provides 792 * information about the controller. 793 * @qspi: Pointer to the spi_device structure 794 * @transfer: Pointer to the spi_transfer structure which provide information 795 * about next transfer parameters 796 * 797 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the 798 * transfer to be completed. 799 * 800 * Return: Number of bytes transferred in the last transfer 801 */ 802 static int zynqmp_qspi_start_transfer(struct spi_master *master, 803 struct spi_device *qspi, 804 struct spi_transfer *transfer) 805 { 806 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 807 u32 genfifoentry = 0x0, transfer_len; 808 809 xqspi->txbuf = transfer->tx_buf; 810 xqspi->rxbuf = transfer->rx_buf; 811 812 zynqmp_qspi_setup_transfer(qspi, transfer); 813 814 genfifoentry |= xqspi->genfifocs; 815 genfifoentry |= xqspi->genfifobus; 816 817 zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry); 818 819 if (xqspi->mode == GQSPI_MODE_DMA) 820 transfer_len = xqspi->dma_rx_bytes; 821 else 822 transfer_len = transfer->len; 823 824 xqspi->genfifoentry = genfifoentry; 825 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) { 826 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK; 827 genfifoentry |= transfer_len; 828 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); 829 } else { 830 int tempcount = transfer_len; 831 u32 exponent = 8; /* 2^8 = 256 */ 832 u8 imm_data = tempcount & 0xFF; 833 834 tempcount &= ~(tempcount & 0xFF); 835 /* Immediate entry */ 836 if (tempcount != 0) { 837 /* Exponent entries */ 838 genfifoentry |= GQSPI_GENFIFO_EXP; 839 while (tempcount != 0) { 840 if (tempcount & GQSPI_GENFIFO_EXP_START) { 841 genfifoentry &= 842 ~GQSPI_GENFIFO_IMM_DATA_MASK; 843 genfifoentry |= exponent; 844 zynqmp_gqspi_write(xqspi, 845 GQSPI_GEN_FIFO_OFST, 846 genfifoentry); 847 } 848 tempcount = tempcount >> 1; 849 exponent++; 850 } 851 } 852 if (imm_data != 0) { 853 genfifoentry &= ~GQSPI_GENFIFO_EXP; 854 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK; 855 genfifoentry |= (u8) (imm_data & 0xFF); 856 zynqmp_gqspi_write(xqspi, 857 GQSPI_GEN_FIFO_OFST, genfifoentry); 858 } 859 } 860 861 if ((xqspi->mode == GQSPI_MODE_IO) && 862 (xqspi->rxbuf != NULL)) { 863 /* Dummy generic FIFO entry */ 864 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0); 865 } 866 867 /* Since we are using manual mode */ 868 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 869 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | 870 GQSPI_CFG_START_GEN_FIFO_MASK); 871 872 if (xqspi->txbuf != NULL) 873 /* Enable interrupts for TX */ 874 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, 875 GQSPI_IER_TXEMPTY_MASK | 876 GQSPI_IER_GENFIFOEMPTY_MASK | 877 GQSPI_IER_TXNOT_FULL_MASK); 878 879 if (xqspi->rxbuf != NULL) { 880 /* Enable interrupts for RX */ 881 if (xqspi->mode == GQSPI_MODE_DMA) { 882 /* Enable DMA interrupts */ 883 zynqmp_gqspi_write(xqspi, 884 GQSPI_QSPIDMA_DST_I_EN_OFST, 885 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK); 886 } else { 887 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, 888 GQSPI_IER_GENFIFOEMPTY_MASK | 889 GQSPI_IER_RXNEMPTY_MASK | 890 GQSPI_IER_RXEMPTY_MASK); 891 } 892 } 893 894 return transfer->len; 895 } 896 897 /** 898 * zynqmp_qspi_suspend: Suspend method for the QSPI driver 899 * @_dev: Address of the platform_device structure 900 * 901 * This function stops the QSPI driver queue and disables the QSPI controller 902 * 903 * Return: Always 0 904 */ 905 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev) 906 { 907 struct spi_master *master = dev_get_drvdata(dev); 908 909 spi_master_suspend(master); 910 911 zynqmp_unprepare_transfer_hardware(master); 912 913 return 0; 914 } 915 916 /** 917 * zynqmp_qspi_resume: Resume method for the QSPI driver 918 * @dev: Address of the platform_device structure 919 * 920 * The function starts the QSPI driver queue and initializes the QSPI 921 * controller 922 * 923 * Return: 0 on success; error value otherwise 924 */ 925 static int __maybe_unused zynqmp_qspi_resume(struct device *dev) 926 { 927 struct spi_master *master = dev_get_drvdata(dev); 928 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 929 int ret = 0; 930 931 ret = clk_enable(xqspi->pclk); 932 if (ret) { 933 dev_err(dev, "Cannot enable APB clock.\n"); 934 return ret; 935 } 936 937 ret = clk_enable(xqspi->refclk); 938 if (ret) { 939 dev_err(dev, "Cannot enable device clock.\n"); 940 clk_disable(xqspi->pclk); 941 return ret; 942 } 943 944 spi_master_resume(master); 945 946 clk_disable(xqspi->refclk); 947 clk_disable(xqspi->pclk); 948 return 0; 949 } 950 951 /** 952 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver 953 * @dev: Address of the platform_device structure 954 * 955 * This function disables the clocks 956 * 957 * Return: Always 0 958 */ 959 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev) 960 { 961 struct spi_master *master = dev_get_drvdata(dev); 962 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 963 964 clk_disable(xqspi->refclk); 965 clk_disable(xqspi->pclk); 966 967 return 0; 968 } 969 970 /** 971 * zynqmp_runtime_resume - Runtime resume method for the SPI driver 972 * @dev: Address of the platform_device structure 973 * 974 * This function enables the clocks 975 * 976 * Return: 0 on success and error value on error 977 */ 978 static int __maybe_unused zynqmp_runtime_resume(struct device *dev) 979 { 980 struct spi_master *master = dev_get_drvdata(dev); 981 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 982 int ret; 983 984 ret = clk_enable(xqspi->pclk); 985 if (ret) { 986 dev_err(dev, "Cannot enable APB clock.\n"); 987 return ret; 988 } 989 990 ret = clk_enable(xqspi->refclk); 991 if (ret) { 992 dev_err(dev, "Cannot enable device clock.\n"); 993 clk_disable(xqspi->pclk); 994 return ret; 995 } 996 997 return 0; 998 } 999 1000 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = { 1001 SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend, 1002 zynqmp_runtime_resume, NULL) 1003 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume) 1004 }; 1005 1006 /** 1007 * zynqmp_qspi_probe: Probe method for the QSPI driver 1008 * @pdev: Pointer to the platform_device structure 1009 * 1010 * This function initializes the driver data structures and the hardware. 1011 * 1012 * Return: 0 on success; error value otherwise 1013 */ 1014 static int zynqmp_qspi_probe(struct platform_device *pdev) 1015 { 1016 int ret = 0; 1017 struct spi_master *master; 1018 struct zynqmp_qspi *xqspi; 1019 struct resource *res; 1020 struct device *dev = &pdev->dev; 1021 1022 eemi_ops = zynqmp_pm_get_eemi_ops(); 1023 if (IS_ERR(eemi_ops)) 1024 return PTR_ERR(eemi_ops); 1025 1026 master = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); 1027 if (!master) 1028 return -ENOMEM; 1029 1030 xqspi = spi_master_get_devdata(master); 1031 master->dev.of_node = pdev->dev.of_node; 1032 platform_set_drvdata(pdev, master); 1033 1034 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1035 xqspi->regs = devm_ioremap_resource(&pdev->dev, res); 1036 if (IS_ERR(xqspi->regs)) { 1037 ret = PTR_ERR(xqspi->regs); 1038 goto remove_master; 1039 } 1040 1041 xqspi->dev = dev; 1042 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk"); 1043 if (IS_ERR(xqspi->pclk)) { 1044 dev_err(dev, "pclk clock not found.\n"); 1045 ret = PTR_ERR(xqspi->pclk); 1046 goto remove_master; 1047 } 1048 1049 ret = clk_prepare_enable(xqspi->pclk); 1050 if (ret) { 1051 dev_err(dev, "Unable to enable APB clock.\n"); 1052 goto remove_master; 1053 } 1054 1055 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk"); 1056 if (IS_ERR(xqspi->refclk)) { 1057 dev_err(dev, "ref_clk clock not found.\n"); 1058 ret = PTR_ERR(xqspi->refclk); 1059 goto clk_dis_pclk; 1060 } 1061 1062 ret = clk_prepare_enable(xqspi->refclk); 1063 if (ret) { 1064 dev_err(dev, "Unable to enable device clock.\n"); 1065 goto clk_dis_pclk; 1066 } 1067 1068 pm_runtime_use_autosuspend(&pdev->dev); 1069 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 1070 pm_runtime_set_active(&pdev->dev); 1071 pm_runtime_enable(&pdev->dev); 1072 /* QSPI controller initializations */ 1073 zynqmp_qspi_init_hw(xqspi); 1074 1075 pm_runtime_mark_last_busy(&pdev->dev); 1076 pm_runtime_put_autosuspend(&pdev->dev); 1077 xqspi->irq = platform_get_irq(pdev, 0); 1078 if (xqspi->irq <= 0) { 1079 ret = -ENXIO; 1080 dev_err(dev, "irq resource not found\n"); 1081 goto clk_dis_all; 1082 } 1083 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq, 1084 0, pdev->name, master); 1085 if (ret != 0) { 1086 ret = -ENXIO; 1087 dev_err(dev, "request_irq failed\n"); 1088 goto clk_dis_all; 1089 } 1090 1091 master->num_chipselect = GQSPI_DEFAULT_NUM_CS; 1092 1093 master->setup = zynqmp_qspi_setup; 1094 master->set_cs = zynqmp_qspi_chipselect; 1095 master->transfer_one = zynqmp_qspi_start_transfer; 1096 master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware; 1097 master->unprepare_transfer_hardware = 1098 zynqmp_unprepare_transfer_hardware; 1099 master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; 1100 master->bits_per_word_mask = SPI_BPW_MASK(8); 1101 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | 1102 SPI_TX_DUAL | SPI_TX_QUAD; 1103 1104 if (master->dev.parent == NULL) 1105 master->dev.parent = &master->dev; 1106 1107 ret = spi_register_master(master); 1108 if (ret) 1109 goto clk_dis_all; 1110 1111 return 0; 1112 1113 clk_dis_all: 1114 pm_runtime_set_suspended(&pdev->dev); 1115 pm_runtime_disable(&pdev->dev); 1116 clk_disable_unprepare(xqspi->refclk); 1117 clk_dis_pclk: 1118 clk_disable_unprepare(xqspi->pclk); 1119 remove_master: 1120 spi_master_put(master); 1121 1122 return ret; 1123 } 1124 1125 /** 1126 * zynqmp_qspi_remove: Remove method for the QSPI driver 1127 * @pdev: Pointer to the platform_device structure 1128 * 1129 * This function is called if a device is physically removed from the system or 1130 * if the driver module is being unloaded. It frees all resources allocated to 1131 * the device. 1132 * 1133 * Return: 0 Always 1134 */ 1135 static int zynqmp_qspi_remove(struct platform_device *pdev) 1136 { 1137 struct spi_master *master = platform_get_drvdata(pdev); 1138 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); 1139 1140 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0); 1141 clk_disable_unprepare(xqspi->refclk); 1142 clk_disable_unprepare(xqspi->pclk); 1143 pm_runtime_set_suspended(&pdev->dev); 1144 pm_runtime_disable(&pdev->dev); 1145 1146 spi_unregister_master(master); 1147 1148 return 0; 1149 } 1150 1151 static const struct of_device_id zynqmp_qspi_of_match[] = { 1152 { .compatible = "xlnx,zynqmp-qspi-1.0", }, 1153 { /* End of table */ } 1154 }; 1155 1156 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match); 1157 1158 static struct platform_driver zynqmp_qspi_driver = { 1159 .probe = zynqmp_qspi_probe, 1160 .remove = zynqmp_qspi_remove, 1161 .driver = { 1162 .name = "zynqmp-qspi", 1163 .of_match_table = zynqmp_qspi_of_match, 1164 .pm = &zynqmp_qspi_dev_pm_ops, 1165 }, 1166 }; 1167 1168 module_platform_driver(zynqmp_qspi_driver); 1169 1170 MODULE_AUTHOR("Xilinx, Inc."); 1171 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver"); 1172 MODULE_LICENSE("GPL"); 1173