1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
4  * (master mode only)
5  *
6  * Copyright (C) 2009 - 2015 Xilinx, Inc.
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spinlock.h>
24 #include <linux/workqueue.h>
25 #include <linux/spi/spi-mem.h>
26 
27 /* Generic QSPI register offsets */
28 #define GQSPI_CONFIG_OFST		0x00000100
29 #define GQSPI_ISR_OFST			0x00000104
30 #define GQSPI_IDR_OFST			0x0000010C
31 #define GQSPI_IER_OFST			0x00000108
32 #define GQSPI_IMASK_OFST		0x00000110
33 #define GQSPI_EN_OFST			0x00000114
34 #define GQSPI_TXD_OFST			0x0000011C
35 #define GQSPI_RXD_OFST			0x00000120
36 #define GQSPI_TX_THRESHOLD_OFST		0x00000128
37 #define GQSPI_RX_THRESHOLD_OFST		0x0000012C
38 #define IOU_TAPDLY_BYPASS_OFST		0x0000003C
39 #define GQSPI_LPBK_DLY_ADJ_OFST		0x00000138
40 #define GQSPI_GEN_FIFO_OFST		0x00000140
41 #define GQSPI_SEL_OFST			0x00000144
42 #define GQSPI_GF_THRESHOLD_OFST		0x00000150
43 #define GQSPI_FIFO_CTRL_OFST		0x0000014C
44 #define GQSPI_QSPIDMA_DST_CTRL_OFST	0x0000080C
45 #define GQSPI_QSPIDMA_DST_SIZE_OFST	0x00000804
46 #define GQSPI_QSPIDMA_DST_STS_OFST	0x00000808
47 #define GQSPI_QSPIDMA_DST_I_STS_OFST	0x00000814
48 #define GQSPI_QSPIDMA_DST_I_EN_OFST	0x00000818
49 #define GQSPI_QSPIDMA_DST_I_DIS_OFST	0x0000081C
50 #define GQSPI_QSPIDMA_DST_I_MASK_OFST	0x00000820
51 #define GQSPI_QSPIDMA_DST_ADDR_OFST	0x00000800
52 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
53 #define GQSPI_DATA_DLY_ADJ_OFST         0x000001F8
54 
55 /* GQSPI register bit masks */
56 #define GQSPI_SEL_MASK				0x00000001
57 #define GQSPI_EN_MASK				0x00000001
58 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK	0x00000020
59 #define GQSPI_ISR_WR_TO_CLR_MASK		0x00000002
60 #define GQSPI_IDR_ALL_MASK			0x00000FBE
61 #define GQSPI_CFG_MODE_EN_MASK			0xC0000000
62 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK	0x20000000
63 #define GQSPI_CFG_ENDIAN_MASK			0x04000000
64 #define GQSPI_CFG_EN_POLL_TO_MASK		0x00100000
65 #define GQSPI_CFG_WP_HOLD_MASK			0x00080000
66 #define GQSPI_CFG_BAUD_RATE_DIV_MASK		0x00000038
67 #define GQSPI_CFG_CLK_PHA_MASK			0x00000004
68 #define GQSPI_CFG_CLK_POL_MASK			0x00000002
69 #define GQSPI_CFG_START_GEN_FIFO_MASK		0x10000000
70 #define GQSPI_GENFIFO_IMM_DATA_MASK		0x000000FF
71 #define GQSPI_GENFIFO_DATA_XFER			0x00000100
72 #define GQSPI_GENFIFO_EXP			0x00000200
73 #define GQSPI_GENFIFO_MODE_SPI			0x00000400
74 #define GQSPI_GENFIFO_MODE_DUALSPI		0x00000800
75 #define GQSPI_GENFIFO_MODE_QUADSPI		0x00000C00
76 #define GQSPI_GENFIFO_MODE_MASK			0x00000C00
77 #define GQSPI_GENFIFO_CS_LOWER			0x00001000
78 #define GQSPI_GENFIFO_CS_UPPER			0x00002000
79 #define GQSPI_GENFIFO_BUS_LOWER			0x00004000
80 #define GQSPI_GENFIFO_BUS_UPPER			0x00008000
81 #define GQSPI_GENFIFO_BUS_BOTH			0x0000C000
82 #define GQSPI_GENFIFO_BUS_MASK			0x0000C000
83 #define GQSPI_GENFIFO_TX			0x00010000
84 #define GQSPI_GENFIFO_RX			0x00020000
85 #define GQSPI_GENFIFO_STRIPE			0x00040000
86 #define GQSPI_GENFIFO_POLL			0x00080000
87 #define GQSPI_GENFIFO_EXP_START			0x00000100
88 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK	0x00000004
89 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK	0x00000002
90 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK	0x00000001
91 #define GQSPI_ISR_RXEMPTY_MASK			0x00000800
92 #define GQSPI_ISR_GENFIFOFULL_MASK		0x00000400
93 #define GQSPI_ISR_GENFIFONOT_FULL_MASK		0x00000200
94 #define GQSPI_ISR_TXEMPTY_MASK			0x00000100
95 #define GQSPI_ISR_GENFIFOEMPTY_MASK		0x00000080
96 #define GQSPI_ISR_RXFULL_MASK			0x00000020
97 #define GQSPI_ISR_RXNEMPTY_MASK			0x00000010
98 #define GQSPI_ISR_TXFULL_MASK			0x00000008
99 #define GQSPI_ISR_TXNOT_FULL_MASK		0x00000004
100 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK		0x00000002
101 #define GQSPI_IER_TXNOT_FULL_MASK		0x00000004
102 #define GQSPI_IER_RXEMPTY_MASK			0x00000800
103 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK		0x00000002
104 #define GQSPI_IER_RXNEMPTY_MASK			0x00000010
105 #define GQSPI_IER_GENFIFOEMPTY_MASK		0x00000080
106 #define GQSPI_IER_TXEMPTY_MASK			0x00000100
107 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK		0x000000FE
108 #define GQSPI_QSPIDMA_DST_STS_WTC		0x0000E000
109 #define GQSPI_CFG_MODE_EN_DMA_MASK		0x80000000
110 #define GQSPI_ISR_IDR_MASK			0x00000994
111 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK	0x00000002
112 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK	0x00000002
113 #define GQSPI_IRQ_MASK				0x00000980
114 
115 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT		3
116 #define GQSPI_GENFIFO_CS_SETUP			0x4
117 #define GQSPI_GENFIFO_CS_HOLD			0x3
118 #define GQSPI_TXD_DEPTH				64
119 #define GQSPI_RX_FIFO_THRESHOLD			32
120 #define GQSPI_RX_FIFO_FILL	(GQSPI_RX_FIFO_THRESHOLD * 4)
121 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL	32
122 #define GQSPI_TX_FIFO_FILL	(GQSPI_TXD_DEPTH -\
123 				GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
124 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL	0X10
125 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL	0x803FFA00
126 #define GQSPI_SELECT_FLASH_CS_LOWER		0x1
127 #define GQSPI_SELECT_FLASH_CS_UPPER		0x2
128 #define GQSPI_SELECT_FLASH_CS_BOTH		0x3
129 #define GQSPI_SELECT_FLASH_BUS_LOWER		0x1
130 #define GQSPI_SELECT_FLASH_BUS_UPPER		0x2
131 #define GQSPI_SELECT_FLASH_BUS_BOTH		0x3
132 #define GQSPI_BAUD_DIV_MAX	7	/* Baud rate divisor maximum */
133 #define GQSPI_BAUD_DIV_SHIFT	2	/* Baud rate divisor shift */
134 #define GQSPI_SELECT_MODE_SPI		0x1
135 #define GQSPI_SELECT_MODE_DUALSPI	0x2
136 #define GQSPI_SELECT_MODE_QUADSPI	0x4
137 #define GQSPI_DMA_UNALIGN		0x3
138 #define GQSPI_DEFAULT_NUM_CS	1	/* Default number of chip selects */
139 
140 #define GQSPI_MAX_NUM_CS	2	/* Maximum number of chip selects */
141 
142 #define GQSPI_USE_DATA_DLY		0x1
143 #define GQSPI_USE_DATA_DLY_SHIFT	31
144 #define GQSPI_DATA_DLY_ADJ_VALUE	0x2
145 #define GQSPI_DATA_DLY_ADJ_SHIFT	28
146 #define GQSPI_LPBK_DLY_ADJ_DLY_1	0x1
147 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT	0x3
148 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE	0x1
149 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT	0x2
150 
151 /* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
152 #define QSPI_QUIRK_HAS_TAPDELAY		BIT(0)
153 
154 #define GQSPI_FREQ_37_5MHZ	37500000
155 #define GQSPI_FREQ_40MHZ	40000000
156 #define GQSPI_FREQ_100MHZ	100000000
157 #define GQSPI_FREQ_150MHZ	150000000
158 
159 #define SPI_AUTOSUSPEND_TIMEOUT		3000
160 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
161 
162 /**
163  * struct qspi_platform_data - zynqmp qspi platform data structure
164  * @quirks:    Flags is used to identify the platform
165  */
166 struct qspi_platform_data {
167 	u32 quirks;
168 };
169 
170 /**
171  * struct zynqmp_qspi - Defines qspi driver instance
172  * @ctlr:		Pointer to the spi controller information
173  * @regs:		Virtual address of the QSPI controller registers
174  * @refclk:		Pointer to the peripheral clock
175  * @pclk:		Pointer to the APB clock
176  * @irq:		IRQ number
177  * @dev:		Pointer to struct device
178  * @txbuf:		Pointer to the TX buffer
179  * @rxbuf:		Pointer to the RX buffer
180  * @bytes_to_transfer:	Number of bytes left to transfer
181  * @bytes_to_receive:	Number of bytes left to receive
182  * @genfifocs:		Used for chip select
183  * @genfifobus:		Used to select the upper or lower bus
184  * @dma_rx_bytes:	Remaining bytes to receive by DMA mode
185  * @dma_addr:		DMA address after mapping the kernel buffer
186  * @genfifoentry:	Used for storing the genfifoentry instruction.
187  * @mode:		Defines the mode in which QSPI is operating
188  * @data_completion:	completion structure
189  * @op_lock:		Operational lock
190  * @speed_hz:          Current SPI bus clock speed in hz
191  * @has_tapdelay:	Used for tapdelay register available in qspi
192  */
193 struct zynqmp_qspi {
194 	struct spi_controller *ctlr;
195 	void __iomem *regs;
196 	struct clk *refclk;
197 	struct clk *pclk;
198 	int irq;
199 	struct device *dev;
200 	const void *txbuf;
201 	void *rxbuf;
202 	int bytes_to_transfer;
203 	int bytes_to_receive;
204 	u32 genfifocs;
205 	u32 genfifobus;
206 	u32 dma_rx_bytes;
207 	dma_addr_t dma_addr;
208 	u32 genfifoentry;
209 	enum mode_type mode;
210 	struct completion data_completion;
211 	struct mutex op_lock;
212 	u32 speed_hz;
213 	bool has_tapdelay;
214 };
215 
216 /**
217  * zynqmp_gqspi_read - For GQSPI controller read operation
218  * @xqspi:	Pointer to the zynqmp_qspi structure
219  * @offset:	Offset from where to read
220  * Return:      Value at the offset
221  */
222 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
223 {
224 	return readl_relaxed(xqspi->regs + offset);
225 }
226 
227 /**
228  * zynqmp_gqspi_write - For GQSPI controller write operation
229  * @xqspi:	Pointer to the zynqmp_qspi structure
230  * @offset:	Offset where to write
231  * @val:	Value to be written
232  */
233 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
234 				      u32 val)
235 {
236 	writel_relaxed(val, (xqspi->regs + offset));
237 }
238 
239 /**
240  * zynqmp_gqspi_selectslave - For selection of slave device
241  * @instanceptr:	Pointer to the zynqmp_qspi structure
242  * @slavecs:	For chip select
243  * @slavebus:	To check which bus is selected- upper or lower
244  */
245 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
246 				     u8 slavecs, u8 slavebus)
247 {
248 	/*
249 	 * Bus and CS lines selected here will be updated in the instance and
250 	 * used for subsequent GENFIFO entries during transfer.
251 	 */
252 
253 	/* Choose slave select line */
254 	switch (slavecs) {
255 	case GQSPI_SELECT_FLASH_CS_BOTH:
256 		instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
257 			GQSPI_GENFIFO_CS_UPPER;
258 		break;
259 	case GQSPI_SELECT_FLASH_CS_UPPER:
260 		instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
261 		break;
262 	case GQSPI_SELECT_FLASH_CS_LOWER:
263 		instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
264 		break;
265 	default:
266 		dev_warn(instanceptr->dev, "Invalid slave select\n");
267 	}
268 
269 	/* Choose the bus */
270 	switch (slavebus) {
271 	case GQSPI_SELECT_FLASH_BUS_BOTH:
272 		instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
273 			GQSPI_GENFIFO_BUS_UPPER;
274 		break;
275 	case GQSPI_SELECT_FLASH_BUS_UPPER:
276 		instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
277 		break;
278 	case GQSPI_SELECT_FLASH_BUS_LOWER:
279 		instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
280 		break;
281 	default:
282 		dev_warn(instanceptr->dev, "Invalid slave bus\n");
283 	}
284 }
285 
286 /**
287  * zynqmp_qspi_set_tapdelay:   To configure qspi tap delays
288  * @xqspi:             Pointer to the zynqmp_qspi structure
289  * @baudrateval:       Buadrate to configure
290  */
291 static void zynqmp_qspi_set_tapdelay(struct zynqmp_qspi *xqspi, u32 baudrateval)
292 {
293 	u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;
294 	u32 reqhz = 0;
295 
296 	clk_rate = clk_get_rate(xqspi->refclk);
297 	reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));
298 
299 	if (!xqspi->has_tapdelay) {
300 		if (reqhz <= GQSPI_FREQ_40MHZ) {
301 			zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,
302 						      PM_TAPDELAY_BYPASS_ENABLE);
303 		} else if (reqhz <= GQSPI_FREQ_100MHZ) {
304 			zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,
305 						      PM_TAPDELAY_BYPASS_ENABLE);
306 			lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
307 			datadlyadj |= ((GQSPI_USE_DATA_DLY <<
308 					GQSPI_USE_DATA_DLY_SHIFT)
309 					| (GQSPI_DATA_DLY_ADJ_VALUE <<
310 						GQSPI_DATA_DLY_ADJ_SHIFT));
311 		} else if (reqhz <= GQSPI_FREQ_150MHZ) {
312 			lpbkdlyadj |= GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK;
313 		}
314 	} else {
315 		if (reqhz <= GQSPI_FREQ_37_5MHZ) {
316 			tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
317 					TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
318 		} else if (reqhz <= GQSPI_FREQ_100MHZ) {
319 			tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
320 					TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
321 			lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
322 			datadlyadj |= (GQSPI_USE_DATA_DLY <<
323 					GQSPI_USE_DATA_DLY_SHIFT);
324 		} else if (reqhz <= GQSPI_FREQ_150MHZ) {
325 			lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK
326 				       | (GQSPI_LPBK_DLY_ADJ_DLY_1 <<
327 					       GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT));
328 		}
329 		zynqmp_gqspi_write(xqspi,
330 				   IOU_TAPDLY_BYPASS_OFST, tapdlybypass);
331 	}
332 	zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, lpbkdlyadj);
333 	zynqmp_gqspi_write(xqspi, GQSPI_DATA_DLY_ADJ_OFST, datadlyadj);
334 }
335 
336 /**
337  * zynqmp_qspi_init_hw - Initialize the hardware
338  * @xqspi:	Pointer to the zynqmp_qspi structure
339  *
340  * The default settings of the QSPI controller's configurable parameters on
341  * reset are
342  *	- Master mode
343  *	- TX threshold set to 1
344  *	- RX threshold set to 1
345  *	- Flash memory interface mode enabled
346  * This function performs the following actions
347  *	- Disable and clear all the interrupts
348  *	- Enable manual slave select
349  *	- Enable manual start
350  *	- Deselect all the chip select lines
351  *	- Set the little endian mode of TX FIFO
352  *	- Set clock phase
353  *	- Set clock polarity and
354  *	- Enable the QSPI controller
355  */
356 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
357 {
358 	u32 config_reg, baud_rate_val = 0;
359 	ulong clk_rate;
360 
361 	/* Select the GQSPI mode */
362 	zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
363 	/* Clear and disable interrupts */
364 	zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
365 			   zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
366 			   GQSPI_ISR_WR_TO_CLR_MASK);
367 	/* Clear the DMA STS */
368 	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
369 			   zynqmp_gqspi_read(xqspi,
370 					     GQSPI_QSPIDMA_DST_I_STS_OFST));
371 	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
372 			   zynqmp_gqspi_read(xqspi,
373 					     GQSPI_QSPIDMA_DST_STS_OFST) |
374 					     GQSPI_QSPIDMA_DST_STS_WTC);
375 	zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
376 	zynqmp_gqspi_write(xqspi,
377 			   GQSPI_QSPIDMA_DST_I_DIS_OFST,
378 			   GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
379 	/* Disable the GQSPI */
380 	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
381 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
382 	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
383 	/* Manual start */
384 	config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
385 	/* Little endian by default */
386 	config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
387 	/* Disable poll time out */
388 	config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
389 	/* Set hold bit */
390 	config_reg |= GQSPI_CFG_WP_HOLD_MASK;
391 	/* Clear pre-scalar by default */
392 	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
393 	/* Set CPHA */
394 	if (xqspi->ctlr->mode_bits & SPI_CPHA)
395 		config_reg |= GQSPI_CFG_CLK_PHA_MASK;
396 	else
397 		config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
398 	/* Set CPOL */
399 	if (xqspi->ctlr->mode_bits & SPI_CPOL)
400 		config_reg |= GQSPI_CFG_CLK_POL_MASK;
401 	else
402 		config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
403 
404 	/* Set the clock frequency */
405 	clk_rate = clk_get_rate(xqspi->refclk);
406 	while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
407 	       (clk_rate /
408 		(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > xqspi->speed_hz)
409 		baud_rate_val++;
410 
411 	config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
412 	config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
413 
414 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
415 
416 	/* Set the tapdelay for clock frequency */
417 	zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
418 
419 	/* Clear the TX and RX FIFO */
420 	zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
421 			   GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
422 			   GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
423 			   GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
424 	/* Reset thresholds */
425 	zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
426 			   GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
427 	zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
428 			   GQSPI_RX_FIFO_THRESHOLD);
429 	zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
430 			   GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
431 	zynqmp_gqspi_selectslave(xqspi,
432 				 GQSPI_SELECT_FLASH_CS_LOWER,
433 				 GQSPI_SELECT_FLASH_BUS_LOWER);
434 	/* Initialize DMA */
435 	zynqmp_gqspi_write(xqspi,
436 			   GQSPI_QSPIDMA_DST_CTRL_OFST,
437 			   GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
438 
439 	/* Enable the GQSPI */
440 	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
441 }
442 
443 /**
444  * zynqmp_qspi_copy_read_data - Copy data to RX buffer
445  * @xqspi:	Pointer to the zynqmp_qspi structure
446  * @data:	The variable where data is stored
447  * @size:	Number of bytes to be copied from data to RX buffer
448  */
449 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
450 				       ulong data, u8 size)
451 {
452 	memcpy(xqspi->rxbuf, &data, size);
453 	xqspi->rxbuf += size;
454 	xqspi->bytes_to_receive -= size;
455 }
456 
457 /**
458  * zynqmp_qspi_chipselect - Select or deselect the chip select line
459  * @qspi:	Pointer to the spi_device structure
460  * @is_high:	Select(0) or deselect (1) the chip select line
461  */
462 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
463 {
464 	struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
465 	ulong timeout;
466 	u32 genfifoentry = 0, statusreg;
467 
468 	genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
469 
470 	if (!is_high) {
471 		if (!spi_get_chipselect(qspi, 0)) {
472 			xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
473 			xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;
474 		} else {
475 			xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
476 			xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER;
477 		}
478 		genfifoentry |= xqspi->genfifobus;
479 		genfifoentry |= xqspi->genfifocs;
480 		genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
481 	} else {
482 		genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
483 	}
484 
485 	zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
486 
487 	/* Manually start the generic FIFO command */
488 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
489 			   zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
490 			   GQSPI_CFG_START_GEN_FIFO_MASK);
491 
492 	timeout = jiffies + msecs_to_jiffies(1000);
493 
494 	/* Wait until the generic FIFO command is empty */
495 	do {
496 		statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
497 
498 		if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
499 		    (statusreg & GQSPI_ISR_TXEMPTY_MASK))
500 			break;
501 		cpu_relax();
502 	} while (!time_after_eq(jiffies, timeout));
503 
504 	if (time_after_eq(jiffies, timeout))
505 		dev_err(xqspi->dev, "Chip select timed out\n");
506 }
507 
508 /**
509  * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.
510  * @xqspi:	xqspi is a pointer to the GQSPI instance
511  * @spimode:	spimode - SPI or DUAL or QUAD.
512  * Return:	Mask to set desired SPI mode in GENFIFO entry.
513  */
514 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
515 					    u8 spimode)
516 {
517 	u32 mask = 0;
518 
519 	switch (spimode) {
520 	case GQSPI_SELECT_MODE_DUALSPI:
521 		mask = GQSPI_GENFIFO_MODE_DUALSPI;
522 		break;
523 	case GQSPI_SELECT_MODE_QUADSPI:
524 		mask = GQSPI_GENFIFO_MODE_QUADSPI;
525 		break;
526 	case GQSPI_SELECT_MODE_SPI:
527 		mask = GQSPI_GENFIFO_MODE_SPI;
528 		break;
529 	default:
530 		dev_warn(xqspi->dev, "Invalid SPI mode\n");
531 	}
532 
533 	return mask;
534 }
535 
536 /**
537  * zynqmp_qspi_config_op - Configure QSPI controller for specified
538  *				transfer
539  * @xqspi:	Pointer to the zynqmp_qspi structure
540  * @qspi:	Pointer to the spi_device structure
541  *
542  * Sets the operational mode of QSPI controller for the next QSPI transfer and
543  * sets the requested clock frequency.
544  *
545  * Return:	Always 0
546  *
547  * Note:
548  *	If the requested frequency is not an exact match with what can be
549  *	obtained using the pre-scalar value, the driver sets the clock
550  *	frequency which is lower than the requested frequency (maximum lower)
551  *	for the transfer.
552  *
553  *	If the requested frequency is higher or lower than that is supported
554  *	by the QSPI controller the driver will set the highest or lowest
555  *	frequency supported by controller.
556  */
557 static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,
558 				 struct spi_device *qspi)
559 {
560 	ulong clk_rate;
561 	u32 config_reg, req_speed_hz, baud_rate_val = 0;
562 
563 	req_speed_hz = qspi->max_speed_hz;
564 
565 	if (xqspi->speed_hz != req_speed_hz) {
566 		xqspi->speed_hz = req_speed_hz;
567 
568 		/* Set the clock frequency */
569 		/* If req_speed_hz == 0, default to lowest speed */
570 		clk_rate = clk_get_rate(xqspi->refclk);
571 
572 		while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
573 		       (clk_rate /
574 			(GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) >
575 		       req_speed_hz)
576 			baud_rate_val++;
577 
578 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
579 
580 		config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
581 		config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
582 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
583 		zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);
584 	}
585 	return 0;
586 }
587 
588 /**
589  * zynqmp_qspi_setup_op - Configure the QSPI controller
590  * @qspi:	Pointer to the spi_device structure
591  *
592  * Sets the operational mode of QSPI controller for the next QSPI transfer,
593  * baud rate and divisor value to setup the requested qspi clock.
594  *
595  * Return:	0 on success; error value otherwise.
596  */
597 static int zynqmp_qspi_setup_op(struct spi_device *qspi)
598 {
599 	struct spi_controller *ctlr = qspi->master;
600 	struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);
601 
602 	if (ctlr->busy)
603 		return -EBUSY;
604 
605 	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
606 
607 	return 0;
608 }
609 
610 /**
611  * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in
612  *				the FIFO or the bytes required to be
613  *				transmitted.
614  * @xqspi:	Pointer to the zynqmp_qspi structure
615  * @size:	Number of bytes to be copied from TX buffer to TX FIFO
616  */
617 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
618 {
619 	u32 count = 0, intermediate;
620 
621 	while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {
622 		if (xqspi->bytes_to_transfer >= 4) {
623 			memcpy(&intermediate, xqspi->txbuf, 4);
624 			xqspi->txbuf += 4;
625 			xqspi->bytes_to_transfer -= 4;
626 			count += 4;
627 		} else {
628 			memcpy(&intermediate, xqspi->txbuf,
629 			       xqspi->bytes_to_transfer);
630 			xqspi->txbuf += xqspi->bytes_to_transfer;
631 			xqspi->bytes_to_transfer = 0;
632 			count += xqspi->bytes_to_transfer;
633 		}
634 		zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
635 	}
636 }
637 
638 /**
639  * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in
640  *				the FIFO.
641  * @xqspi:	Pointer to the zynqmp_qspi structure
642  * @size:	Number of bytes to be copied from RX buffer to RX FIFO
643  */
644 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
645 {
646 	ulong data;
647 	int count = 0;
648 
649 	while ((count < size) && (xqspi->bytes_to_receive > 0)) {
650 		if (xqspi->bytes_to_receive >= 4) {
651 			(*(u32 *)xqspi->rxbuf) =
652 			zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
653 			xqspi->rxbuf += 4;
654 			xqspi->bytes_to_receive -= 4;
655 			count += 4;
656 		} else {
657 			data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
658 			count += xqspi->bytes_to_receive;
659 			zynqmp_qspi_copy_read_data(xqspi, data,
660 						   xqspi->bytes_to_receive);
661 			xqspi->bytes_to_receive = 0;
662 		}
663 	}
664 }
665 
666 /**
667  * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.
668  * @xqspi:	Pointer to the zynqmp_qspi structure
669  * @nbits:	Transfer/Receive buswidth.
670  * @genfifoentry:       Variable in which GENFIFO mask is saved
671  */
672 static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,
673 				    u32 genfifoentry)
674 {
675 	u32 transfer_len = 0;
676 
677 	if (xqspi->txbuf) {
678 		genfifoentry &= ~GQSPI_GENFIFO_RX;
679 		genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
680 		genfifoentry |= GQSPI_GENFIFO_TX;
681 		transfer_len = xqspi->bytes_to_transfer;
682 	} else if (xqspi->rxbuf) {
683 		genfifoentry &= ~GQSPI_GENFIFO_TX;
684 		genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
685 		genfifoentry |= GQSPI_GENFIFO_RX;
686 		if (xqspi->mode == GQSPI_MODE_DMA)
687 			transfer_len = xqspi->dma_rx_bytes;
688 		else
689 			transfer_len = xqspi->bytes_to_receive;
690 	} else {
691 		/* Sending dummy circles here */
692 		genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);
693 		genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
694 		transfer_len = xqspi->bytes_to_transfer;
695 	}
696 	genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);
697 	xqspi->genfifoentry = genfifoentry;
698 
699 	if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
700 		genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
701 		genfifoentry |= transfer_len;
702 		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
703 	} else {
704 		int tempcount = transfer_len;
705 		u32 exponent = 8;	/* 2^8 = 256 */
706 		u8 imm_data = tempcount & 0xFF;
707 
708 		tempcount &= ~(tempcount & 0xFF);
709 		/* Immediate entry */
710 		if (tempcount != 0) {
711 			/* Exponent entries */
712 			genfifoentry |= GQSPI_GENFIFO_EXP;
713 			while (tempcount != 0) {
714 				if (tempcount & GQSPI_GENFIFO_EXP_START) {
715 					genfifoentry &=
716 						~GQSPI_GENFIFO_IMM_DATA_MASK;
717 					genfifoentry |= exponent;
718 					zynqmp_gqspi_write(xqspi,
719 							   GQSPI_GEN_FIFO_OFST,
720 							   genfifoentry);
721 				}
722 				tempcount = tempcount >> 1;
723 				exponent++;
724 			}
725 		}
726 		if (imm_data != 0) {
727 			genfifoentry &= ~GQSPI_GENFIFO_EXP;
728 			genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
729 			genfifoentry |= (u8)(imm_data & 0xFF);
730 			zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,
731 					   genfifoentry);
732 		}
733 	}
734 	if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {
735 		/* Dummy generic FIFO entry */
736 		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
737 	}
738 }
739 
740 /**
741  * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI
742  *				controller
743  * @xqspi:	zynqmp_qspi instance pointer
744  *
745  * This function handles DMA interrupt only.
746  */
747 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
748 {
749 	u32 config_reg, genfifoentry;
750 
751 	dma_unmap_single(xqspi->dev, xqspi->dma_addr,
752 			 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
753 	xqspi->rxbuf += xqspi->dma_rx_bytes;
754 	xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
755 	xqspi->dma_rx_bytes = 0;
756 
757 	/* Disabling the DMA interrupts */
758 	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
759 			   GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
760 
761 	if (xqspi->bytes_to_receive > 0) {
762 		/* Switch to IO mode,for remaining bytes to receive */
763 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
764 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
765 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
766 
767 		/* Initiate the transfer of remaining bytes */
768 		genfifoentry = xqspi->genfifoentry;
769 		genfifoentry |= xqspi->bytes_to_receive;
770 		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
771 
772 		/* Dummy generic FIFO entry */
773 		zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
774 
775 		/* Manual start */
776 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
777 				   (zynqmp_gqspi_read(xqspi,
778 						      GQSPI_CONFIG_OFST) |
779 				   GQSPI_CFG_START_GEN_FIFO_MASK));
780 
781 		/* Enable the RX interrupts for IO mode */
782 		zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
783 				   GQSPI_IER_GENFIFOEMPTY_MASK |
784 				   GQSPI_IER_RXNEMPTY_MASK |
785 				   GQSPI_IER_RXEMPTY_MASK);
786 	}
787 }
788 
789 /**
790  * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller
791  * @irq:	IRQ number
792  * @dev_id:	Pointer to the xqspi structure
793  *
794  * This function handles TX empty only.
795  * On TX empty interrupt this function reads the received data from RX FIFO
796  * and fills the TX FIFO if there is any data remaining to be transferred.
797  *
798  * Return:	IRQ_HANDLED when interrupt is handled
799  *		IRQ_NONE otherwise.
800  */
801 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
802 {
803 	struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;
804 	irqreturn_t ret = IRQ_NONE;
805 	u32 status, mask, dma_status = 0;
806 
807 	status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
808 	zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
809 	mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
810 
811 	/* Read and clear DMA status */
812 	if (xqspi->mode == GQSPI_MODE_DMA) {
813 		dma_status =
814 			zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
815 		zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
816 				   dma_status);
817 	}
818 
819 	if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
820 		zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
821 		ret = IRQ_HANDLED;
822 	}
823 
824 	if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
825 		zynqmp_process_dma_irq(xqspi);
826 		ret = IRQ_HANDLED;
827 	} else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
828 			(mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
829 		zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
830 		ret = IRQ_HANDLED;
831 	}
832 
833 	if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&
834 	    ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
835 		zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
836 		complete(&xqspi->data_completion);
837 		ret = IRQ_HANDLED;
838 	}
839 	return ret;
840 }
841 
842 /**
843  * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation
844  * @xqspi:	xqspi is a pointer to the GQSPI instance.
845  *
846  * Return:	0 on success; error value otherwise.
847  */
848 static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
849 {
850 	u32 rx_bytes, rx_rem, config_reg;
851 	dma_addr_t addr;
852 	u64 dma_align =  (u64)(uintptr_t)xqspi->rxbuf;
853 
854 	if (xqspi->bytes_to_receive < 8 ||
855 	    ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
856 		/* Setting to IO mode */
857 		config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
858 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
859 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
860 		xqspi->mode = GQSPI_MODE_IO;
861 		xqspi->dma_rx_bytes = 0;
862 		return 0;
863 	}
864 
865 	rx_rem = xqspi->bytes_to_receive % 4;
866 	rx_bytes = (xqspi->bytes_to_receive - rx_rem);
867 
868 	addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
869 			      rx_bytes, DMA_FROM_DEVICE);
870 	if (dma_mapping_error(xqspi->dev, addr)) {
871 		dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
872 		return -ENOMEM;
873 	}
874 
875 	xqspi->dma_rx_bytes = rx_bytes;
876 	xqspi->dma_addr = addr;
877 	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
878 			   (u32)(addr & 0xffffffff));
879 	addr = ((addr >> 16) >> 16);
880 	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
881 			   ((u32)addr) & 0xfff);
882 
883 	/* Enabling the DMA mode */
884 	config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
885 	config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
886 	config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
887 	zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
888 
889 	/* Switch to DMA mode */
890 	xqspi->mode = GQSPI_MODE_DMA;
891 
892 	/* Write the number of bytes to transfer */
893 	zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
894 
895 	return 0;
896 }
897 
898 /**
899  * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,
900  *			TX FIFO, and fills the TX FIFO with as many
901  *			bytes as possible.
902  * @xqspi:	Pointer to the GQSPI instance.
903  * @tx_nbits:	Transfer buswidth.
904  * @genfifoentry:	Variable in which GENFIFO mask is returned
905  *			to calling function
906  */
907 static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,
908 				 u32 genfifoentry)
909 {
910 	u32 config_reg;
911 
912 	zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);
913 	zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
914 	if (xqspi->mode == GQSPI_MODE_DMA) {
915 		config_reg = zynqmp_gqspi_read(xqspi,
916 					       GQSPI_CONFIG_OFST);
917 		config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
918 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
919 				   config_reg);
920 		xqspi->mode = GQSPI_MODE_IO;
921 	}
922 }
923 
924 /**
925  * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and
926  *				RX DMA operation.
927  * @xqspi:	xqspi is a pointer to the GQSPI instance.
928  * @rx_nbits:	Receive buswidth.
929  * @genfifoentry:	genfifoentry is pointer to the variable in which
930  *			GENFIFO	mask is returned to calling function
931  *
932  * Return:	0 on success; error value otherwise.
933  */
934 static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,
935 				u32 genfifoentry)
936 {
937 	int ret;
938 
939 	ret = zynqmp_qspi_setuprxdma(xqspi);
940 	if (ret)
941 		return ret;
942 	zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);
943 
944 	return 0;
945 }
946 
947 /**
948  * zynqmp_qspi_suspend - Suspend method for the QSPI driver
949  * @dev:	Address of the platform_device structure
950  *
951  * This function stops the QSPI driver queue and disables the QSPI controller
952  *
953  * Return:	Always 0
954  */
955 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
956 {
957 	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
958 	struct spi_controller *ctlr = xqspi->ctlr;
959 	int ret;
960 
961 	ret = spi_controller_suspend(ctlr);
962 	if (ret)
963 		return ret;
964 
965 	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
966 
967 	return 0;
968 }
969 
970 /**
971  * zynqmp_qspi_resume - Resume method for the QSPI driver
972  * @dev:	Address of the platform_device structure
973  *
974  * The function starts the QSPI driver queue and initializes the QSPI
975  * controller
976  *
977  * Return:	0 on success; error value otherwise
978  */
979 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
980 {
981 	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
982 	struct spi_controller *ctlr = xqspi->ctlr;
983 
984 	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
985 
986 	spi_controller_resume(ctlr);
987 
988 	return 0;
989 }
990 
991 /**
992  * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
993  * @dev:	Address of the platform_device structure
994  *
995  * This function disables the clocks
996  *
997  * Return:	Always 0
998  */
999 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
1000 {
1001 	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
1002 
1003 	clk_disable_unprepare(xqspi->refclk);
1004 	clk_disable_unprepare(xqspi->pclk);
1005 
1006 	return 0;
1007 }
1008 
1009 /**
1010  * zynqmp_runtime_resume - Runtime resume method for the SPI driver
1011  * @dev:	Address of the platform_device structure
1012  *
1013  * This function enables the clocks
1014  *
1015  * Return:	0 on success and error value on error
1016  */
1017 static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
1018 {
1019 	struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);
1020 	int ret;
1021 
1022 	ret = clk_prepare_enable(xqspi->pclk);
1023 	if (ret) {
1024 		dev_err(dev, "Cannot enable APB clock.\n");
1025 		return ret;
1026 	}
1027 
1028 	ret = clk_prepare_enable(xqspi->refclk);
1029 	if (ret) {
1030 		dev_err(dev, "Cannot enable device clock.\n");
1031 		clk_disable_unprepare(xqspi->pclk);
1032 		return ret;
1033 	}
1034 
1035 	return 0;
1036 }
1037 
1038 /**
1039  * zynqmp_qspi_exec_op() - Initiates the QSPI transfer
1040  * @mem: The SPI memory
1041  * @op: The memory operation to execute
1042  *
1043  * Executes a memory operation.
1044  *
1045  * This function first selects the chip and starts the memory operation.
1046  *
1047  * Return: 0 in case of success, a negative error code otherwise.
1048  */
1049 static int zynqmp_qspi_exec_op(struct spi_mem *mem,
1050 			       const struct spi_mem_op *op)
1051 {
1052 	struct zynqmp_qspi *xqspi = spi_controller_get_devdata
1053 				    (mem->spi->master);
1054 	int err = 0, i;
1055 	u32 genfifoentry = 0;
1056 	u16 opcode = op->cmd.opcode;
1057 	u64 opaddr;
1058 
1059 	dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",
1060 		op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
1061 		op->dummy.buswidth, op->data.buswidth);
1062 
1063 	mutex_lock(&xqspi->op_lock);
1064 	zynqmp_qspi_config_op(xqspi, mem->spi);
1065 	zynqmp_qspi_chipselect(mem->spi, false);
1066 	genfifoentry |= xqspi->genfifocs;
1067 	genfifoentry |= xqspi->genfifobus;
1068 
1069 	if (op->cmd.opcode) {
1070 		reinit_completion(&xqspi->data_completion);
1071 		xqspi->txbuf = &opcode;
1072 		xqspi->rxbuf = NULL;
1073 		xqspi->bytes_to_transfer = op->cmd.nbytes;
1074 		xqspi->bytes_to_receive = 0;
1075 		zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);
1076 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1077 				   zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1078 				   GQSPI_CFG_START_GEN_FIFO_MASK);
1079 		zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1080 				   GQSPI_IER_GENFIFOEMPTY_MASK |
1081 				   GQSPI_IER_TXNOT_FULL_MASK);
1082 		if (!wait_for_completion_timeout
1083 		    (&xqspi->data_completion, msecs_to_jiffies(1000))) {
1084 			err = -ETIMEDOUT;
1085 			goto return_err;
1086 		}
1087 	}
1088 
1089 	if (op->addr.nbytes) {
1090 		xqspi->txbuf = &opaddr;
1091 		for (i = 0; i < op->addr.nbytes; i++) {
1092 			*(((u8 *)xqspi->txbuf) + i) = op->addr.val >>
1093 					(8 * (op->addr.nbytes - i - 1));
1094 		}
1095 
1096 		reinit_completion(&xqspi->data_completion);
1097 		xqspi->rxbuf = NULL;
1098 		xqspi->bytes_to_transfer = op->addr.nbytes;
1099 		xqspi->bytes_to_receive = 0;
1100 		zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);
1101 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1102 				   zynqmp_gqspi_read(xqspi,
1103 						     GQSPI_CONFIG_OFST) |
1104 				   GQSPI_CFG_START_GEN_FIFO_MASK);
1105 		zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1106 				   GQSPI_IER_TXEMPTY_MASK |
1107 				   GQSPI_IER_GENFIFOEMPTY_MASK |
1108 				   GQSPI_IER_TXNOT_FULL_MASK);
1109 		if (!wait_for_completion_timeout
1110 		    (&xqspi->data_completion, msecs_to_jiffies(1000))) {
1111 			err = -ETIMEDOUT;
1112 			goto return_err;
1113 		}
1114 	}
1115 
1116 	if (op->dummy.nbytes) {
1117 		xqspi->txbuf = NULL;
1118 		xqspi->rxbuf = NULL;
1119 		/*
1120 		 * xqspi->bytes_to_transfer here represents the dummy circles
1121 		 * which need to be sent.
1122 		 */
1123 		xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;
1124 		xqspi->bytes_to_receive = 0;
1125 		/*
1126 		 * Using op->data.buswidth instead of op->dummy.buswidth here because
1127 		 * we need to use it to configure the correct SPI mode.
1128 		 */
1129 		zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1130 				     genfifoentry);
1131 		zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1132 				   zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
1133 				   GQSPI_CFG_START_GEN_FIFO_MASK);
1134 	}
1135 
1136 	if (op->data.nbytes) {
1137 		reinit_completion(&xqspi->data_completion);
1138 		if (op->data.dir == SPI_MEM_DATA_OUT) {
1139 			xqspi->txbuf = (u8 *)op->data.buf.out;
1140 			xqspi->rxbuf = NULL;
1141 			xqspi->bytes_to_transfer = op->data.nbytes;
1142 			xqspi->bytes_to_receive = 0;
1143 			zynqmp_qspi_write_op(xqspi, op->data.buswidth,
1144 					     genfifoentry);
1145 			zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1146 					   zynqmp_gqspi_read
1147 					   (xqspi, GQSPI_CONFIG_OFST) |
1148 					   GQSPI_CFG_START_GEN_FIFO_MASK);
1149 			zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1150 					   GQSPI_IER_TXEMPTY_MASK |
1151 					   GQSPI_IER_GENFIFOEMPTY_MASK |
1152 					   GQSPI_IER_TXNOT_FULL_MASK);
1153 		} else {
1154 			xqspi->txbuf = NULL;
1155 			xqspi->rxbuf = (u8 *)op->data.buf.in;
1156 			xqspi->bytes_to_receive = op->data.nbytes;
1157 			xqspi->bytes_to_transfer = 0;
1158 			err = zynqmp_qspi_read_op(xqspi, op->data.buswidth,
1159 					    genfifoentry);
1160 			if (err)
1161 				goto return_err;
1162 
1163 			zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
1164 					   zynqmp_gqspi_read
1165 					   (xqspi, GQSPI_CONFIG_OFST) |
1166 					   GQSPI_CFG_START_GEN_FIFO_MASK);
1167 			if (xqspi->mode == GQSPI_MODE_DMA) {
1168 				zynqmp_gqspi_write
1169 					(xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,
1170 					 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
1171 			} else {
1172 				zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
1173 						   GQSPI_IER_GENFIFOEMPTY_MASK |
1174 						   GQSPI_IER_RXNEMPTY_MASK |
1175 						   GQSPI_IER_RXEMPTY_MASK);
1176 			}
1177 		}
1178 		if (!wait_for_completion_timeout
1179 		    (&xqspi->data_completion, msecs_to_jiffies(1000)))
1180 			err = -ETIMEDOUT;
1181 	}
1182 
1183 return_err:
1184 
1185 	zynqmp_qspi_chipselect(mem->spi, true);
1186 	mutex_unlock(&xqspi->op_lock);
1187 
1188 	return err;
1189 }
1190 
1191 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1192 	SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1193 			   zynqmp_runtime_resume, NULL)
1194 	SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1195 };
1196 
1197 static const struct qspi_platform_data versal_qspi_def = {
1198 	.quirks = QSPI_QUIRK_HAS_TAPDELAY,
1199 };
1200 
1201 static const struct of_device_id zynqmp_qspi_of_match[] = {
1202 	{ .compatible = "xlnx,zynqmp-qspi-1.0"},
1203 	{ .compatible = "xlnx,versal-qspi-1.0", .data = &versal_qspi_def },
1204 	{ /* End of table */ }
1205 };
1206 
1207 static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
1208 	.exec_op = zynqmp_qspi_exec_op,
1209 };
1210 
1211 /**
1212  * zynqmp_qspi_probe - Probe method for the QSPI driver
1213  * @pdev:	Pointer to the platform_device structure
1214  *
1215  * This function initializes the driver data structures and the hardware.
1216  *
1217  * Return:	0 on success; error value otherwise
1218  */
1219 static int zynqmp_qspi_probe(struct platform_device *pdev)
1220 {
1221 	int ret = 0;
1222 	struct spi_controller *ctlr;
1223 	struct zynqmp_qspi *xqspi;
1224 	struct device *dev = &pdev->dev;
1225 	struct device_node *np = dev->of_node;
1226 	u32 num_cs;
1227 	const struct qspi_platform_data *p_data;
1228 
1229 	ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1230 	if (!ctlr)
1231 		return -ENOMEM;
1232 
1233 	xqspi = spi_controller_get_devdata(ctlr);
1234 	xqspi->dev = dev;
1235 	xqspi->ctlr = ctlr;
1236 	platform_set_drvdata(pdev, xqspi);
1237 
1238 	p_data = of_device_get_match_data(&pdev->dev);
1239 	if (p_data && (p_data->quirks & QSPI_QUIRK_HAS_TAPDELAY))
1240 		xqspi->has_tapdelay = true;
1241 
1242 	xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
1243 	if (IS_ERR(xqspi->regs)) {
1244 		ret = PTR_ERR(xqspi->regs);
1245 		goto remove_master;
1246 	}
1247 
1248 	xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1249 	if (IS_ERR(xqspi->pclk)) {
1250 		dev_err(dev, "pclk clock not found.\n");
1251 		ret = PTR_ERR(xqspi->pclk);
1252 		goto remove_master;
1253 	}
1254 
1255 	xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1256 	if (IS_ERR(xqspi->refclk)) {
1257 		dev_err(dev, "ref_clk clock not found.\n");
1258 		ret = PTR_ERR(xqspi->refclk);
1259 		goto remove_master;
1260 	}
1261 
1262 	ret = clk_prepare_enable(xqspi->pclk);
1263 	if (ret) {
1264 		dev_err(dev, "Unable to enable APB clock.\n");
1265 		goto remove_master;
1266 	}
1267 
1268 	ret = clk_prepare_enable(xqspi->refclk);
1269 	if (ret) {
1270 		dev_err(dev, "Unable to enable device clock.\n");
1271 		goto clk_dis_pclk;
1272 	}
1273 
1274 	init_completion(&xqspi->data_completion);
1275 
1276 	mutex_init(&xqspi->op_lock);
1277 
1278 	pm_runtime_use_autosuspend(&pdev->dev);
1279 	pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1280 	pm_runtime_set_active(&pdev->dev);
1281 	pm_runtime_enable(&pdev->dev);
1282 
1283 	ret = pm_runtime_get_sync(&pdev->dev);
1284 	if (ret < 0) {
1285 		dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret);
1286 		goto clk_dis_all;
1287 	}
1288 
1289 	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1290 		SPI_TX_DUAL | SPI_TX_QUAD;
1291 	ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1292 	xqspi->speed_hz = ctlr->max_speed_hz;
1293 
1294 	/* QSPI controller initializations */
1295 	zynqmp_qspi_init_hw(xqspi);
1296 
1297 	xqspi->irq = platform_get_irq(pdev, 0);
1298 	if (xqspi->irq <= 0) {
1299 		ret = -ENXIO;
1300 		goto clk_dis_all;
1301 	}
1302 	ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1303 			       0, pdev->name, xqspi);
1304 	if (ret != 0) {
1305 		ret = -ENXIO;
1306 		dev_err(dev, "request_irq failed\n");
1307 		goto clk_dis_all;
1308 	}
1309 
1310 	ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
1311 	if (ret)
1312 		goto clk_dis_all;
1313 
1314 	ret = of_property_read_u32(np, "num-cs", &num_cs);
1315 	if (ret < 0) {
1316 		ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1317 	} else if (num_cs > GQSPI_MAX_NUM_CS) {
1318 		ret = -EINVAL;
1319 		dev_err(&pdev->dev, "only %d chip selects are available\n",
1320 			GQSPI_MAX_NUM_CS);
1321 		goto clk_dis_all;
1322 	} else {
1323 		ctlr->num_chipselect = num_cs;
1324 	}
1325 
1326 	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1327 	ctlr->mem_ops = &zynqmp_qspi_mem_ops;
1328 	ctlr->setup = zynqmp_qspi_setup_op;
1329 	ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
1330 	ctlr->dev.of_node = np;
1331 	ctlr->auto_runtime_pm = true;
1332 
1333 	ret = devm_spi_register_controller(&pdev->dev, ctlr);
1334 	if (ret) {
1335 		dev_err(&pdev->dev, "spi_register_controller failed\n");
1336 		goto clk_dis_all;
1337 	}
1338 
1339 	pm_runtime_mark_last_busy(&pdev->dev);
1340 	pm_runtime_put_autosuspend(&pdev->dev);
1341 
1342 	return 0;
1343 
1344 clk_dis_all:
1345 	pm_runtime_put_sync(&pdev->dev);
1346 	pm_runtime_set_suspended(&pdev->dev);
1347 	pm_runtime_disable(&pdev->dev);
1348 	clk_disable_unprepare(xqspi->refclk);
1349 clk_dis_pclk:
1350 	clk_disable_unprepare(xqspi->pclk);
1351 remove_master:
1352 	spi_controller_put(ctlr);
1353 
1354 	return ret;
1355 }
1356 
1357 /**
1358  * zynqmp_qspi_remove - Remove method for the QSPI driver
1359  * @pdev:	Pointer to the platform_device structure
1360  *
1361  * This function is called if a device is physically removed from the system or
1362  * if the driver module is being unloaded. It frees all resources allocated to
1363  * the device.
1364  *
1365  * Return:	0 Always
1366  */
1367 static void zynqmp_qspi_remove(struct platform_device *pdev)
1368 {
1369 	struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);
1370 
1371 	zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1372 	clk_disable_unprepare(xqspi->refclk);
1373 	clk_disable_unprepare(xqspi->pclk);
1374 	pm_runtime_set_suspended(&pdev->dev);
1375 	pm_runtime_disable(&pdev->dev);
1376 }
1377 
1378 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1379 
1380 static struct platform_driver zynqmp_qspi_driver = {
1381 	.probe = zynqmp_qspi_probe,
1382 	.remove_new = zynqmp_qspi_remove,
1383 	.driver = {
1384 		.name = "zynqmp-qspi",
1385 		.of_match_table = zynqmp_qspi_of_match,
1386 		.pm = &zynqmp_qspi_dev_pm_ops,
1387 	},
1388 };
1389 
1390 module_platform_driver(zynqmp_qspi_driver);
1391 
1392 MODULE_AUTHOR("Xilinx, Inc.");
1393 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1394 MODULE_LICENSE("GPL");
1395