1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Xilinx, Inc. 4 * 5 * Author: Naga Sureshkumar Relli <nagasure@xilinx.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/gpio.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_address.h> 16 #include <linux/platform_device.h> 17 #include <linux/spi/spi.h> 18 #include <linux/workqueue.h> 19 #include <linux/spi/spi-mem.h> 20 21 /* Register offset definitions */ 22 #define ZYNQ_QSPI_CONFIG_OFFSET 0x00 /* Configuration Register, RW */ 23 #define ZYNQ_QSPI_STATUS_OFFSET 0x04 /* Interrupt Status Register, RO */ 24 #define ZYNQ_QSPI_IEN_OFFSET 0x08 /* Interrupt Enable Register, WO */ 25 #define ZYNQ_QSPI_IDIS_OFFSET 0x0C /* Interrupt Disable Reg, WO */ 26 #define ZYNQ_QSPI_IMASK_OFFSET 0x10 /* Interrupt Enabled Mask Reg,RO */ 27 #define ZYNQ_QSPI_ENABLE_OFFSET 0x14 /* Enable/Disable Register, RW */ 28 #define ZYNQ_QSPI_DELAY_OFFSET 0x18 /* Delay Register, RW */ 29 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */ 30 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */ 31 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */ 32 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */ 33 #define ZYNQ_QSPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */ 34 #define ZYNQ_QSPI_SIC_OFFSET 0x24 /* Slave Idle Count Register, RW */ 35 #define ZYNQ_QSPI_TX_THRESH_OFFSET 0x28 /* TX FIFO Watermark Reg, RW */ 36 #define ZYNQ_QSPI_RX_THRESH_OFFSET 0x2C /* RX FIFO Watermark Reg, RW */ 37 #define ZYNQ_QSPI_GPIO_OFFSET 0x30 /* GPIO Register, RW */ 38 #define ZYNQ_QSPI_LINEAR_CFG_OFFSET 0xA0 /* Linear Adapter Config Ref, RW */ 39 #define ZYNQ_QSPI_MOD_ID_OFFSET 0xFC /* Module ID Register, RO */ 40 41 /* 42 * QSPI Configuration Register bit Masks 43 * 44 * This register contains various control bits that effect the operation 45 * of the QSPI controller 46 */ 47 #define ZYNQ_QSPI_CONFIG_IFMODE_MASK BIT(31) /* Flash Memory Interface */ 48 #define ZYNQ_QSPI_CONFIG_MANSRT_MASK BIT(16) /* Manual TX Start */ 49 #define ZYNQ_QSPI_CONFIG_MANSRTEN_MASK BIT(15) /* Enable Manual TX Mode */ 50 #define ZYNQ_QSPI_CONFIG_SSFORCE_MASK BIT(14) /* Manual Chip Select */ 51 #define ZYNQ_QSPI_CONFIG_BDRATE_MASK GENMASK(5, 3) /* Baud Rate Mask */ 52 #define ZYNQ_QSPI_CONFIG_CPHA_MASK BIT(2) /* Clock Phase Control */ 53 #define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */ 54 #define ZYNQ_QSPI_CONFIG_SSCTRL_MASK BIT(10) /* Slave Select Mask */ 55 #define ZYNQ_QSPI_CONFIG_FWIDTH_MASK GENMASK(7, 6) /* FIFO width */ 56 #define ZYNQ_QSPI_CONFIG_MSTREN_MASK BIT(0) /* Master Mode */ 57 58 /* 59 * QSPI Configuration Register - Baud rate and slave select 60 * 61 * These are the values used in the calculation of baud rate divisor and 62 * setting the slave select. 63 */ 64 #define ZYNQ_QSPI_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */ 65 #define ZYNQ_QSPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ 66 #define ZYNQ_QSPI_SS_SHIFT 10 /* Slave Select field shift in CR */ 67 68 /* 69 * QSPI Interrupt Registers bit Masks 70 * 71 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same 72 * bit definitions. 73 */ 74 #define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */ 75 #define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */ 76 #define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */ 77 #define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */ 78 #define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */ 79 #define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */ 80 #define ZYNQ_QSPI_IXR_ALL_MASK (ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK | \ 81 ZYNQ_QSPI_IXR_TXNFULL_MASK | \ 82 ZYNQ_QSPI_IXR_TXFULL_MASK | \ 83 ZYNQ_QSPI_IXR_RXNEMTY_MASK | \ 84 ZYNQ_QSPI_IXR_RXF_FULL_MASK | \ 85 ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK) 86 #define ZYNQ_QSPI_IXR_RXTX_MASK (ZYNQ_QSPI_IXR_TXNFULL_MASK | \ 87 ZYNQ_QSPI_IXR_RXNEMTY_MASK) 88 89 /* 90 * QSPI Enable Register bit Masks 91 * 92 * This register is used to enable or disable the QSPI controller 93 */ 94 #define ZYNQ_QSPI_ENABLE_ENABLE_MASK BIT(0) /* QSPI Enable Bit Mask */ 95 96 /* 97 * QSPI Linear Configuration Register 98 * 99 * It is named Linear Configuration but it controls other modes when not in 100 * linear mode also. 101 */ 102 #define ZYNQ_QSPI_LCFG_TWO_MEM_MASK BIT(30) /* LQSPI Two memories Mask */ 103 #define ZYNQ_QSPI_LCFG_SEP_BUS_MASK BIT(29) /* LQSPI Separate bus Mask */ 104 #define ZYNQ_QSPI_LCFG_U_PAGE_MASK BIT(28) /* LQSPI Upper Page Mask */ 105 106 #define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8 107 108 #define ZYNQ_QSPI_FAST_READ_QOUT_CODE 0x6B /* read instruction code */ 109 #define ZYNQ_QSPI_FIFO_DEPTH 63 /* FIFO depth in words */ 110 #define ZYNQ_QSPI_RX_THRESHOLD 32 /* Rx FIFO threshold level */ 111 #define ZYNQ_QSPI_TX_THRESHOLD 1 /* Tx FIFO threshold level */ 112 113 /* 114 * The modebits configurable by the driver to make the SPI support different 115 * data formats 116 */ 117 #define ZYNQ_QSPI_MODEBITS (SPI_CPOL | SPI_CPHA) 118 119 /* Default number of chip selects */ 120 #define ZYNQ_QSPI_DEFAULT_NUM_CS 1 121 122 /** 123 * struct zynq_qspi - Defines qspi driver instance 124 * @regs: Virtual address of the QSPI controller registers 125 * @refclk: Pointer to the peripheral clock 126 * @pclk: Pointer to the APB clock 127 * @irq: IRQ number 128 * @txbuf: Pointer to the TX buffer 129 * @rxbuf: Pointer to the RX buffer 130 * @tx_bytes: Number of bytes left to transfer 131 * @rx_bytes: Number of bytes left to receive 132 * @data_completion: completion structure 133 */ 134 struct zynq_qspi { 135 struct device *dev; 136 void __iomem *regs; 137 struct clk *refclk; 138 struct clk *pclk; 139 int irq; 140 u8 *txbuf; 141 u8 *rxbuf; 142 int tx_bytes; 143 int rx_bytes; 144 struct completion data_completion; 145 }; 146 147 /* 148 * Inline functions for the QSPI controller read/write 149 */ 150 static inline u32 zynq_qspi_read(struct zynq_qspi *xqspi, u32 offset) 151 { 152 return readl_relaxed(xqspi->regs + offset); 153 } 154 155 static inline void zynq_qspi_write(struct zynq_qspi *xqspi, u32 offset, 156 u32 val) 157 { 158 writel_relaxed(val, xqspi->regs + offset); 159 } 160 161 /** 162 * zynq_qspi_init_hw - Initialize the hardware 163 * @xqspi: Pointer to the zynq_qspi structure 164 * 165 * The default settings of the QSPI controller's configurable parameters on 166 * reset are 167 * - Master mode 168 * - Baud rate divisor is set to 2 169 * - Tx threshold set to 1l Rx threshold set to 32 170 * - Flash memory interface mode enabled 171 * - Size of the word to be transferred as 8 bit 172 * This function performs the following actions 173 * - Disable and clear all the interrupts 174 * - Enable manual slave select 175 * - Enable manual start 176 * - Deselect all the chip select lines 177 * - Set the size of the word to be transferred as 32 bit 178 * - Set the little endian mode of TX FIFO and 179 * - Enable the QSPI controller 180 */ 181 static void zynq_qspi_init_hw(struct zynq_qspi *xqspi) 182 { 183 u32 config_reg; 184 185 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0); 186 zynq_qspi_write(xqspi, ZYNQ_QSPI_IDIS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK); 187 188 /* Disable linear mode as the boot loader may have used it */ 189 zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, 0); 190 191 /* Clear the RX FIFO */ 192 while (zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET) & 193 ZYNQ_QSPI_IXR_RXNEMTY_MASK) 194 zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET); 195 196 zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK); 197 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET); 198 config_reg &= ~(ZYNQ_QSPI_CONFIG_MSTREN_MASK | 199 ZYNQ_QSPI_CONFIG_CPOL_MASK | 200 ZYNQ_QSPI_CONFIG_CPHA_MASK | 201 ZYNQ_QSPI_CONFIG_BDRATE_MASK | 202 ZYNQ_QSPI_CONFIG_SSFORCE_MASK | 203 ZYNQ_QSPI_CONFIG_MANSRTEN_MASK | 204 ZYNQ_QSPI_CONFIG_MANSRT_MASK); 205 config_reg |= (ZYNQ_QSPI_CONFIG_MSTREN_MASK | 206 ZYNQ_QSPI_CONFIG_SSFORCE_MASK | 207 ZYNQ_QSPI_CONFIG_FWIDTH_MASK | 208 ZYNQ_QSPI_CONFIG_IFMODE_MASK); 209 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg); 210 211 zynq_qspi_write(xqspi, ZYNQ_QSPI_RX_THRESH_OFFSET, 212 ZYNQ_QSPI_RX_THRESHOLD); 213 zynq_qspi_write(xqspi, ZYNQ_QSPI_TX_THRESH_OFFSET, 214 ZYNQ_QSPI_TX_THRESHOLD); 215 216 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 217 ZYNQ_QSPI_ENABLE_ENABLE_MASK); 218 } 219 220 static bool zynq_qspi_supports_op(struct spi_mem *mem, 221 const struct spi_mem_op *op) 222 { 223 if (!spi_mem_default_supports_op(mem, op)) 224 return false; 225 226 /* 227 * The number of address bytes should be equal to or less than 3 bytes. 228 */ 229 if (op->addr.nbytes > 3) 230 return false; 231 232 return true; 233 } 234 235 /** 236 * zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer 237 * @xqspi: Pointer to the zynq_qspi structure 238 * @size: Number of bytes to be read (1..4) 239 */ 240 static void zynq_qspi_rxfifo_op(struct zynq_qspi *xqspi, unsigned int size) 241 { 242 u32 data; 243 244 data = zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET); 245 246 if (xqspi->rxbuf) { 247 memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size); 248 xqspi->rxbuf += size; 249 } 250 251 xqspi->rx_bytes -= size; 252 if (xqspi->rx_bytes < 0) 253 xqspi->rx_bytes = 0; 254 } 255 256 /** 257 * zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO 258 * @xqspi: Pointer to the zynq_qspi structure 259 * @size: Number of bytes to be written (1..4) 260 */ 261 static void zynq_qspi_txfifo_op(struct zynq_qspi *xqspi, unsigned int size) 262 { 263 static const unsigned int offset[4] = { 264 ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET, 265 ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET }; 266 u32 data; 267 268 if (xqspi->txbuf) { 269 data = 0xffffffff; 270 memcpy(&data, xqspi->txbuf, size); 271 xqspi->txbuf += size; 272 } else { 273 data = 0; 274 } 275 276 xqspi->tx_bytes -= size; 277 zynq_qspi_write(xqspi, offset[size - 1], data); 278 } 279 280 /** 281 * zynq_qspi_chipselect - Select or deselect the chip select line 282 * @spi: Pointer to the spi_device structure 283 * @assert: 1 for select or 0 for deselect the chip select line 284 */ 285 static void zynq_qspi_chipselect(struct spi_device *spi, bool assert) 286 { 287 struct spi_controller *ctrl = spi->master; 288 struct zynq_qspi *xqspi = spi_controller_get_devdata(ctrl); 289 u32 config_reg; 290 291 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET); 292 if (assert) { 293 /* Select the slave */ 294 config_reg &= ~ZYNQ_QSPI_CONFIG_SSCTRL_MASK; 295 config_reg |= (((~(BIT(spi->chip_select))) << 296 ZYNQ_QSPI_SS_SHIFT) & 297 ZYNQ_QSPI_CONFIG_SSCTRL_MASK); 298 } else { 299 config_reg |= ZYNQ_QSPI_CONFIG_SSCTRL_MASK; 300 } 301 302 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg); 303 } 304 305 /** 306 * zynq_qspi_config_op - Configure QSPI controller for specified transfer 307 * @xqspi: Pointer to the zynq_qspi structure 308 * @qspi: Pointer to the spi_device structure 309 * 310 * Sets the operational mode of QSPI controller for the next QSPI transfer and 311 * sets the requested clock frequency. 312 * 313 * Return: 0 on success and -EINVAL on invalid input parameter 314 * 315 * Note: If the requested frequency is not an exact match with what can be 316 * obtained using the prescalar value, the driver sets the clock frequency which 317 * is lower than the requested frequency (maximum lower) for the transfer. If 318 * the requested frequency is higher or lower than that is supported by the QSPI 319 * controller the driver will set the highest or lowest frequency supported by 320 * controller. 321 */ 322 static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi) 323 { 324 u32 config_reg, baud_rate_val = 0; 325 326 /* 327 * Set the clock frequency 328 * The baud rate divisor is not a direct mapping to the value written 329 * into the configuration register (config_reg[5:3]) 330 * i.e. 000 - divide by 2 331 * 001 - divide by 4 332 * ---------------- 333 * 111 - divide by 256 334 */ 335 while ((baud_rate_val < ZYNQ_QSPI_BAUD_DIV_MAX) && 336 (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) > 337 spi->max_speed_hz) 338 baud_rate_val++; 339 340 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET); 341 342 /* Set the QSPI clock phase and clock polarity */ 343 config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) & 344 (~ZYNQ_QSPI_CONFIG_CPOL_MASK); 345 if (spi->mode & SPI_CPHA) 346 config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK; 347 if (spi->mode & SPI_CPOL) 348 config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK; 349 350 config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK; 351 config_reg |= (baud_rate_val << ZYNQ_QSPI_BAUD_DIV_SHIFT); 352 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg); 353 354 return 0; 355 } 356 357 /** 358 * zynq_qspi_setup - Configure the QSPI controller 359 * @spi: Pointer to the spi_device structure 360 * 361 * Sets the operational mode of QSPI controller for the next QSPI transfer, baud 362 * rate and divisor value to setup the requested qspi clock. 363 * 364 * Return: 0 on success and error value on failure 365 */ 366 static int zynq_qspi_setup_op(struct spi_device *spi) 367 { 368 struct spi_controller *ctrl = spi->master; 369 struct zynq_qspi *qspi = spi_controller_get_devdata(ctrl); 370 371 if (ctrl->busy) 372 return -EBUSY; 373 374 clk_enable(qspi->refclk); 375 clk_enable(qspi->pclk); 376 zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET, 377 ZYNQ_QSPI_ENABLE_ENABLE_MASK); 378 379 return 0; 380 } 381 382 /** 383 * zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible 384 * @xqspi: Pointer to the zynq_qspi structure 385 * @txcount: Maximum number of words to write 386 * @txempty: Indicates that TxFIFO is empty 387 */ 388 static void zynq_qspi_write_op(struct zynq_qspi *xqspi, int txcount, 389 bool txempty) 390 { 391 int count, len, k; 392 393 len = xqspi->tx_bytes; 394 if (len && len < 4) { 395 /* 396 * We must empty the TxFIFO between accesses to TXD0, 397 * TXD1, TXD2, TXD3. 398 */ 399 if (txempty) 400 zynq_qspi_txfifo_op(xqspi, len); 401 402 return; 403 } 404 405 count = len / 4; 406 if (count > txcount) 407 count = txcount; 408 409 if (xqspi->txbuf) { 410 iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET, 411 xqspi->txbuf, count); 412 xqspi->txbuf += count * 4; 413 } else { 414 for (k = 0; k < count; k++) 415 writel_relaxed(0, xqspi->regs + 416 ZYNQ_QSPI_TXD_00_00_OFFSET); 417 } 418 419 xqspi->tx_bytes -= count * 4; 420 } 421 422 /** 423 * zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible 424 * @xqspi: Pointer to the zynq_qspi structure 425 * @rxcount: Maximum number of words to read 426 */ 427 static void zynq_qspi_read_op(struct zynq_qspi *xqspi, int rxcount) 428 { 429 int count, len, k; 430 431 len = xqspi->rx_bytes - xqspi->tx_bytes; 432 count = len / 4; 433 if (count > rxcount) 434 count = rxcount; 435 if (xqspi->rxbuf) { 436 ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET, 437 xqspi->rxbuf, count); 438 xqspi->rxbuf += count * 4; 439 } else { 440 for (k = 0; k < count; k++) 441 readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET); 442 } 443 xqspi->rx_bytes -= count * 4; 444 len -= count * 4; 445 446 if (len && len < 4 && count < rxcount) 447 zynq_qspi_rxfifo_op(xqspi, len); 448 } 449 450 /** 451 * zynq_qspi_irq - Interrupt service routine of the QSPI controller 452 * @irq: IRQ number 453 * @dev_id: Pointer to the xqspi structure 454 * 455 * This function handles TX empty only. 456 * On TX empty interrupt this function reads the received data from RX FIFO and 457 * fills the TX FIFO if there is any data remaining to be transferred. 458 * 459 * Return: IRQ_HANDLED when interrupt is handled; IRQ_NONE otherwise. 460 */ 461 static irqreturn_t zynq_qspi_irq(int irq, void *dev_id) 462 { 463 u32 intr_status; 464 bool txempty; 465 struct zynq_qspi *xqspi = (struct zynq_qspi *)dev_id; 466 467 intr_status = zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET); 468 zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, intr_status); 469 470 if ((intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK) || 471 (intr_status & ZYNQ_QSPI_IXR_RXNEMTY_MASK)) { 472 /* 473 * This bit is set when Tx FIFO has < THRESHOLD entries. 474 * We have the THRESHOLD value set to 1, 475 * so this bit indicates Tx FIFO is empty. 476 */ 477 txempty = !!(intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK); 478 /* Read out the data from the RX FIFO */ 479 zynq_qspi_read_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD); 480 if (xqspi->tx_bytes) { 481 /* There is more data to send */ 482 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD, 483 txempty); 484 } else { 485 /* 486 * If transfer and receive is completed then only send 487 * complete signal. 488 */ 489 if (!xqspi->rx_bytes) { 490 zynq_qspi_write(xqspi, 491 ZYNQ_QSPI_IDIS_OFFSET, 492 ZYNQ_QSPI_IXR_RXTX_MASK); 493 complete(&xqspi->data_completion); 494 } 495 } 496 return IRQ_HANDLED; 497 } 498 499 return IRQ_NONE; 500 } 501 502 /** 503 * zynq_qspi_exec_mem_op() - Initiates the QSPI transfer 504 * @mem: the SPI memory 505 * @op: the memory operation to execute 506 * 507 * Executes a memory operation. 508 * 509 * This function first selects the chip and starts the memory operation. 510 * 511 * Return: 0 in case of success, a negative error code otherwise. 512 */ 513 static int zynq_qspi_exec_mem_op(struct spi_mem *mem, 514 const struct spi_mem_op *op) 515 { 516 struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master); 517 int err = 0, i; 518 u8 *tmpbuf; 519 520 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n", 521 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, 522 op->dummy.buswidth, op->data.buswidth); 523 524 zynq_qspi_chipselect(mem->spi, true); 525 zynq_qspi_config_op(xqspi, mem->spi); 526 527 if (op->cmd.opcode) { 528 reinit_completion(&xqspi->data_completion); 529 xqspi->txbuf = (u8 *)&op->cmd.opcode; 530 xqspi->rxbuf = NULL; 531 xqspi->tx_bytes = sizeof(op->cmd.opcode); 532 xqspi->rx_bytes = sizeof(op->cmd.opcode); 533 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true); 534 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET, 535 ZYNQ_QSPI_IXR_RXTX_MASK); 536 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion, 537 msecs_to_jiffies(1000))) 538 err = -ETIMEDOUT; 539 } 540 541 if (op->addr.nbytes) { 542 for (i = 0; i < op->addr.nbytes; i++) { 543 xqspi->txbuf[i] = op->addr.val >> 544 (8 * (op->addr.nbytes - i - 1)); 545 } 546 547 reinit_completion(&xqspi->data_completion); 548 xqspi->rxbuf = NULL; 549 xqspi->tx_bytes = op->addr.nbytes; 550 xqspi->rx_bytes = op->addr.nbytes; 551 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true); 552 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET, 553 ZYNQ_QSPI_IXR_RXTX_MASK); 554 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion, 555 msecs_to_jiffies(1000))) 556 err = -ETIMEDOUT; 557 } 558 559 if (op->dummy.nbytes) { 560 tmpbuf = kzalloc(op->dummy.nbytes, GFP_KERNEL); 561 memset(tmpbuf, 0xff, op->dummy.nbytes); 562 reinit_completion(&xqspi->data_completion); 563 xqspi->txbuf = tmpbuf; 564 xqspi->rxbuf = NULL; 565 xqspi->tx_bytes = op->dummy.nbytes; 566 xqspi->rx_bytes = op->dummy.nbytes; 567 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true); 568 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET, 569 ZYNQ_QSPI_IXR_RXTX_MASK); 570 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion, 571 msecs_to_jiffies(1000))) 572 err = -ETIMEDOUT; 573 574 kfree(tmpbuf); 575 } 576 577 if (op->data.nbytes) { 578 reinit_completion(&xqspi->data_completion); 579 if (op->data.dir == SPI_MEM_DATA_OUT) { 580 xqspi->txbuf = (u8 *)op->data.buf.out; 581 xqspi->tx_bytes = op->data.nbytes; 582 xqspi->rxbuf = NULL; 583 xqspi->rx_bytes = op->data.nbytes; 584 } else { 585 xqspi->txbuf = NULL; 586 xqspi->rxbuf = (u8 *)op->data.buf.in; 587 xqspi->rx_bytes = op->data.nbytes; 588 xqspi->tx_bytes = op->data.nbytes; 589 } 590 591 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true); 592 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET, 593 ZYNQ_QSPI_IXR_RXTX_MASK); 594 if (!wait_for_completion_interruptible_timeout(&xqspi->data_completion, 595 msecs_to_jiffies(1000))) 596 err = -ETIMEDOUT; 597 } 598 zynq_qspi_chipselect(mem->spi, false); 599 600 return err; 601 } 602 603 static const struct spi_controller_mem_ops zynq_qspi_mem_ops = { 604 .supports_op = zynq_qspi_supports_op, 605 .exec_op = zynq_qspi_exec_mem_op, 606 }; 607 608 /** 609 * zynq_qspi_probe - Probe method for the QSPI driver 610 * @pdev: Pointer to the platform_device structure 611 * 612 * This function initializes the driver data structures and the hardware. 613 * 614 * Return: 0 on success and error value on failure 615 */ 616 static int zynq_qspi_probe(struct platform_device *pdev) 617 { 618 int ret = 0; 619 struct spi_controller *ctlr; 620 struct device *dev = &pdev->dev; 621 struct device_node *np = dev->of_node; 622 struct zynq_qspi *xqspi; 623 struct resource *res; 624 u32 num_cs; 625 626 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); 627 if (!ctlr) 628 return -ENOMEM; 629 630 xqspi = spi_controller_get_devdata(ctlr); 631 xqspi->dev = dev; 632 platform_set_drvdata(pdev, xqspi); 633 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 634 xqspi->regs = devm_ioremap_resource(&pdev->dev, res); 635 if (IS_ERR(xqspi->regs)) { 636 ret = PTR_ERR(xqspi->regs); 637 goto remove_master; 638 } 639 640 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk"); 641 if (IS_ERR(xqspi->pclk)) { 642 dev_err(&pdev->dev, "pclk clock not found.\n"); 643 ret = PTR_ERR(xqspi->pclk); 644 goto remove_master; 645 } 646 647 init_completion(&xqspi->data_completion); 648 649 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk"); 650 if (IS_ERR(xqspi->refclk)) { 651 dev_err(&pdev->dev, "ref_clk clock not found.\n"); 652 ret = PTR_ERR(xqspi->refclk); 653 goto remove_master; 654 } 655 656 ret = clk_prepare_enable(xqspi->pclk); 657 if (ret) { 658 dev_err(&pdev->dev, "Unable to enable APB clock.\n"); 659 goto remove_master; 660 } 661 662 ret = clk_prepare_enable(xqspi->refclk); 663 if (ret) { 664 dev_err(&pdev->dev, "Unable to enable device clock.\n"); 665 goto clk_dis_pclk; 666 } 667 668 /* QSPI controller initializations */ 669 zynq_qspi_init_hw(xqspi); 670 671 xqspi->irq = platform_get_irq(pdev, 0); 672 if (xqspi->irq <= 0) { 673 ret = -ENXIO; 674 dev_err(&pdev->dev, "irq resource not found\n"); 675 goto remove_master; 676 } 677 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq, 678 0, pdev->name, xqspi); 679 if (ret != 0) { 680 ret = -ENXIO; 681 dev_err(&pdev->dev, "request_irq failed\n"); 682 goto remove_master; 683 } 684 685 ret = of_property_read_u32(np, "num-cs", 686 &num_cs); 687 if (ret < 0) 688 ctlr->num_chipselect = ZYNQ_QSPI_DEFAULT_NUM_CS; 689 else 690 ctlr->num_chipselect = num_cs; 691 692 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | 693 SPI_TX_DUAL | SPI_TX_QUAD; 694 ctlr->mem_ops = &zynq_qspi_mem_ops; 695 ctlr->setup = zynq_qspi_setup_op; 696 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; 697 ctlr->dev.of_node = np; 698 ret = spi_register_controller(ctlr); 699 if (ret) { 700 dev_err(&pdev->dev, "spi_register_master failed\n"); 701 goto clk_dis_all; 702 } 703 704 return ret; 705 706 clk_dis_all: 707 clk_disable_unprepare(xqspi->refclk); 708 clk_dis_pclk: 709 clk_disable_unprepare(xqspi->pclk); 710 remove_master: 711 spi_controller_put(ctlr); 712 713 return ret; 714 } 715 716 /** 717 * zynq_qspi_remove - Remove method for the QSPI driver 718 * @pdev: Pointer to the platform_device structure 719 * 720 * This function is called if a device is physically removed from the system or 721 * if the driver module is being unloaded. It frees all resources allocated to 722 * the device. 723 * 724 * Return: 0 on success and error value on failure 725 */ 726 static int zynq_qspi_remove(struct platform_device *pdev) 727 { 728 struct zynq_qspi *xqspi = platform_get_drvdata(pdev); 729 730 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0); 731 732 clk_disable_unprepare(xqspi->refclk); 733 clk_disable_unprepare(xqspi->pclk); 734 735 return 0; 736 } 737 738 static const struct of_device_id zynq_qspi_of_match[] = { 739 { .compatible = "xlnx,zynq-qspi-1.0", }, 740 { /* end of table */ } 741 }; 742 743 MODULE_DEVICE_TABLE(of, zynq_qspi_of_match); 744 745 /* 746 * zynq_qspi_driver - This structure defines the QSPI platform driver 747 */ 748 static struct platform_driver zynq_qspi_driver = { 749 .probe = zynq_qspi_probe, 750 .remove = zynq_qspi_remove, 751 .driver = { 752 .name = "zynq-qspi", 753 .of_match_table = zynq_qspi_of_match, 754 }, 755 }; 756 757 module_platform_driver(zynq_qspi_driver); 758 759 MODULE_AUTHOR("Xilinx, Inc."); 760 MODULE_DESCRIPTION("Xilinx Zynq QSPI driver"); 761 MODULE_LICENSE("GPL"); 762