1 /* 2 * Xilinx SPI controller driver (master mode only) 3 * 4 * Author: MontaVista Software, Inc. 5 * source@mvista.com 6 * 7 * Copyright (c) 2010 Secret Lab Technologies, Ltd. 8 * Copyright (c) 2009 Intel Corporation 9 * 2002-2007 (c) MontaVista Software, Inc. 10 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/spi_bitbang.h> 23 #include <linux/spi/xilinx_spi.h> 24 #include <linux/io.h> 25 26 #define XILINX_SPI_NAME "xilinx_spi" 27 28 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) 29 * Product Specification", DS464 30 */ 31 #define XSPI_CR_OFFSET 0x60 /* Control Register */ 32 33 #define XSPI_CR_LOOP 0x01 34 #define XSPI_CR_ENABLE 0x02 35 #define XSPI_CR_MASTER_MODE 0x04 36 #define XSPI_CR_CPOL 0x08 37 #define XSPI_CR_CPHA 0x10 38 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL) 39 #define XSPI_CR_TXFIFO_RESET 0x20 40 #define XSPI_CR_RXFIFO_RESET 0x40 41 #define XSPI_CR_MANUAL_SSELECT 0x80 42 #define XSPI_CR_TRANS_INHIBIT 0x100 43 #define XSPI_CR_LSB_FIRST 0x200 44 45 #define XSPI_SR_OFFSET 0x64 /* Status Register */ 46 47 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ 48 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ 49 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ 50 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ 51 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ 52 53 #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ 54 #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ 55 56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ 57 58 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 59 * IPIF registers are 32 bit 60 */ 61 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ 62 #define XIPIF_V123B_GINTR_ENABLE 0x80000000 63 64 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ 65 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ 66 67 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ 68 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while 69 * disabled */ 70 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ 71 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ 72 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ 73 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ 74 #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ 75 76 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ 77 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ 78 79 struct xilinx_spi { 80 /* bitbang has to be first */ 81 struct spi_bitbang bitbang; 82 struct completion done; 83 void __iomem *regs; /* virt. address of the control registers */ 84 85 int irq; 86 87 u8 *rx_ptr; /* pointer in the Tx buffer */ 88 const u8 *tx_ptr; /* pointer in the Rx buffer */ 89 int remaining_bytes; /* the number of bytes left to transfer */ 90 u8 bits_per_word; 91 unsigned int (*read_fn) (void __iomem *); 92 void (*write_fn) (u32, void __iomem *); 93 void (*tx_fn) (struct xilinx_spi *); 94 void (*rx_fn) (struct xilinx_spi *); 95 }; 96 97 static void xspi_write32(u32 val, void __iomem *addr) 98 { 99 iowrite32(val, addr); 100 } 101 102 static unsigned int xspi_read32(void __iomem *addr) 103 { 104 return ioread32(addr); 105 } 106 107 static void xspi_write32_be(u32 val, void __iomem *addr) 108 { 109 iowrite32be(val, addr); 110 } 111 112 static unsigned int xspi_read32_be(void __iomem *addr) 113 { 114 return ioread32be(addr); 115 } 116 117 static void xspi_tx8(struct xilinx_spi *xspi) 118 { 119 xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET); 120 xspi->tx_ptr++; 121 } 122 123 static void xspi_tx16(struct xilinx_spi *xspi) 124 { 125 xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); 126 xspi->tx_ptr += 2; 127 } 128 129 static void xspi_tx32(struct xilinx_spi *xspi) 130 { 131 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); 132 xspi->tx_ptr += 4; 133 } 134 135 static void xspi_rx8(struct xilinx_spi *xspi) 136 { 137 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 138 if (xspi->rx_ptr) { 139 *xspi->rx_ptr = data & 0xff; 140 xspi->rx_ptr++; 141 } 142 } 143 144 static void xspi_rx16(struct xilinx_spi *xspi) 145 { 146 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 147 if (xspi->rx_ptr) { 148 *(u16 *)(xspi->rx_ptr) = data & 0xffff; 149 xspi->rx_ptr += 2; 150 } 151 } 152 153 static void xspi_rx32(struct xilinx_spi *xspi) 154 { 155 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 156 if (xspi->rx_ptr) { 157 *(u32 *)(xspi->rx_ptr) = data; 158 xspi->rx_ptr += 4; 159 } 160 } 161 162 static void xspi_init_hw(struct xilinx_spi *xspi) 163 { 164 void __iomem *regs_base = xspi->regs; 165 166 /* Reset the SPI device */ 167 xspi->write_fn(XIPIF_V123B_RESET_MASK, 168 regs_base + XIPIF_V123B_RESETR_OFFSET); 169 /* Disable all the interrupts just in case */ 170 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); 171 /* Enable the global IPIF interrupt */ 172 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, 173 regs_base + XIPIF_V123B_DGIER_OFFSET); 174 /* Deselect the slave on the SPI bus */ 175 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); 176 /* Disable the transmitter, enable Manual Slave Select Assertion, 177 * put SPI controller into master mode, and enable it */ 178 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT | 179 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | 180 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET); 181 } 182 183 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) 184 { 185 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 186 187 if (is_on == BITBANG_CS_INACTIVE) { 188 /* Deselect the slave on the SPI bus */ 189 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET); 190 } else if (is_on == BITBANG_CS_ACTIVE) { 191 /* Set the SPI clock phase and polarity */ 192 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) 193 & ~XSPI_CR_MODE_MASK; 194 if (spi->mode & SPI_CPHA) 195 cr |= XSPI_CR_CPHA; 196 if (spi->mode & SPI_CPOL) 197 cr |= XSPI_CR_CPOL; 198 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 199 200 /* We do not check spi->max_speed_hz here as the SPI clock 201 * frequency is not software programmable (the IP block design 202 * parameter) 203 */ 204 205 /* Activate the chip select */ 206 xspi->write_fn(~(0x0001 << spi->chip_select), 207 xspi->regs + XSPI_SSR_OFFSET); 208 } 209 } 210 211 /* spi_bitbang requires custom setup_transfer() to be defined if there is a 212 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block 213 * supports 8 or 16 bits per word which cannot be changed in software. 214 * SPI clock can't be changed in software either. 215 * Check for correct bits per word. Chip select delay calculations could be 216 * added here as soon as bitbang_work() can be made aware of the delay value. 217 */ 218 static int xilinx_spi_setup_transfer(struct spi_device *spi, 219 struct spi_transfer *t) 220 { 221 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 222 u8 bits_per_word; 223 224 bits_per_word = (t && t->bits_per_word) 225 ? t->bits_per_word : spi->bits_per_word; 226 if (bits_per_word != xspi->bits_per_word) { 227 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", 228 __func__, bits_per_word); 229 return -EINVAL; 230 } 231 232 return 0; 233 } 234 235 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) 236 { 237 u8 sr; 238 239 /* Fill the Tx FIFO with as many bytes as possible */ 240 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 241 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { 242 if (xspi->tx_ptr) 243 xspi->tx_fn(xspi); 244 else 245 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); 246 xspi->remaining_bytes -= xspi->bits_per_word / 8; 247 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 248 } 249 } 250 251 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) 252 { 253 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 254 u32 ipif_ier; 255 256 /* We get here with transmitter inhibited */ 257 258 xspi->tx_ptr = t->tx_buf; 259 xspi->rx_ptr = t->rx_buf; 260 xspi->remaining_bytes = t->len; 261 INIT_COMPLETION(xspi->done); 262 263 264 /* Enable the transmit empty interrupt, which we use to determine 265 * progress on the transmission. 266 */ 267 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET); 268 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY, 269 xspi->regs + XIPIF_V123B_IIER_OFFSET); 270 271 for (;;) { 272 u16 cr; 273 u8 sr; 274 275 xilinx_spi_fill_tx_fifo(xspi); 276 277 /* Start the transfer by not inhibiting the transmitter any 278 * longer 279 */ 280 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & 281 ~XSPI_CR_TRANS_INHIBIT; 282 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 283 284 wait_for_completion(&xspi->done); 285 286 /* A transmit has just completed. Process received data and 287 * check for more data to transmit. Always inhibit the 288 * transmitter while the Isr refills the transmit register/FIFO, 289 * or make sure it is stopped if we're done. 290 */ 291 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); 292 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, 293 xspi->regs + XSPI_CR_OFFSET); 294 295 /* Read out all the data from the Rx FIFO */ 296 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 297 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { 298 xspi->rx_fn(xspi); 299 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 300 } 301 302 /* See if there is more data to send */ 303 if (xspi->remaining_bytes <= 0) 304 break; 305 } 306 307 /* Disable the transmit empty interrupt */ 308 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET); 309 310 return t->len - xspi->remaining_bytes; 311 } 312 313 314 /* This driver supports single master mode only. Hence Tx FIFO Empty 315 * is the only interrupt we care about. 316 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode 317 * Fault are not to happen. 318 */ 319 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) 320 { 321 struct xilinx_spi *xspi = dev_id; 322 u32 ipif_isr; 323 324 /* Get the IPIF interrupts, and clear them immediately */ 325 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); 326 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); 327 328 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ 329 complete(&xspi->done); 330 } 331 332 return IRQ_HANDLED; 333 } 334 335 static const struct of_device_id xilinx_spi_of_match[] = { 336 { .compatible = "xlnx,xps-spi-2.00.a", }, 337 { .compatible = "xlnx,xps-spi-2.00.b", }, 338 {} 339 }; 340 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); 341 342 static int xilinx_spi_probe(struct platform_device *pdev) 343 { 344 struct xilinx_spi *xspi; 345 struct xspi_platform_data *pdata; 346 struct resource *res; 347 int ret, num_cs = 0, bits_per_word = 8; 348 struct spi_master *master; 349 u32 tmp; 350 u8 i; 351 352 pdata = dev_get_platdata(&pdev->dev); 353 if (pdata) { 354 num_cs = pdata->num_chipselect; 355 bits_per_word = pdata->bits_per_word; 356 } else { 357 of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits", 358 &num_cs); 359 } 360 361 if (!num_cs) { 362 dev_err(&pdev->dev, 363 "Missing slave select configuration data\n"); 364 return -EINVAL; 365 } 366 367 master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); 368 if (!master) 369 return -ENODEV; 370 371 /* the spi->mode bits understood by this driver: */ 372 master->mode_bits = SPI_CPOL | SPI_CPHA; 373 374 xspi = spi_master_get_devdata(master); 375 xspi->bitbang.master = spi_master_get(master); 376 xspi->bitbang.chipselect = xilinx_spi_chipselect; 377 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; 378 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; 379 init_completion(&xspi->done); 380 381 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 382 xspi->regs = devm_ioremap_resource(&pdev->dev, res); 383 if (IS_ERR(xspi->regs)) { 384 ret = PTR_ERR(xspi->regs); 385 goto put_master; 386 } 387 388 master->bus_num = pdev->dev.id; 389 master->num_chipselect = num_cs; 390 master->dev.of_node = pdev->dev.of_node; 391 392 /* 393 * Detect endianess on the IP via loop bit in CR. Detection 394 * must be done before reset is sent because incorrect reset 395 * value generates error interrupt. 396 * Setup little endian helper functions first and try to use them 397 * and check if bit was correctly setup or not. 398 */ 399 xspi->read_fn = xspi_read32; 400 xspi->write_fn = xspi_write32; 401 402 xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); 403 tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); 404 tmp &= XSPI_CR_LOOP; 405 if (tmp != XSPI_CR_LOOP) { 406 xspi->read_fn = xspi_read32_be; 407 xspi->write_fn = xspi_write32_be; 408 } 409 410 xspi->bits_per_word = bits_per_word; 411 if (xspi->bits_per_word == 8) { 412 xspi->tx_fn = xspi_tx8; 413 xspi->rx_fn = xspi_rx8; 414 } else if (xspi->bits_per_word == 16) { 415 xspi->tx_fn = xspi_tx16; 416 xspi->rx_fn = xspi_rx16; 417 } else if (xspi->bits_per_word == 32) { 418 xspi->tx_fn = xspi_tx32; 419 xspi->rx_fn = xspi_rx32; 420 } else { 421 ret = -EINVAL; 422 goto put_master; 423 } 424 425 /* SPI controller initializations */ 426 xspi_init_hw(xspi); 427 428 xspi->irq = platform_get_irq(pdev, 0); 429 if (xspi->irq < 0) { 430 ret = xspi->irq; 431 goto put_master; 432 } 433 434 /* Register for SPI Interrupt */ 435 ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0, 436 dev_name(&pdev->dev), xspi); 437 if (ret) 438 goto put_master; 439 440 ret = spi_bitbang_start(&xspi->bitbang); 441 if (ret) { 442 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n"); 443 goto put_master; 444 } 445 446 dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", 447 (unsigned long long)res->start, xspi->regs, xspi->irq); 448 449 if (pdata) { 450 for (i = 0; i < pdata->num_devices; i++) 451 spi_new_device(master, pdata->devices + i); 452 } 453 454 platform_set_drvdata(pdev, master); 455 return 0; 456 457 put_master: 458 spi_master_put(master); 459 460 return ret; 461 } 462 463 static int xilinx_spi_remove(struct platform_device *pdev) 464 { 465 struct spi_master *master = platform_get_drvdata(pdev); 466 struct xilinx_spi *xspi = spi_master_get_devdata(master); 467 void __iomem *regs_base = xspi->regs; 468 469 spi_bitbang_stop(&xspi->bitbang); 470 471 /* Disable all the interrupts just in case */ 472 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); 473 /* Disable the global IPIF interrupt */ 474 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); 475 476 spi_master_put(xspi->bitbang.master); 477 478 return 0; 479 } 480 481 /* work with hotplug and coldplug */ 482 MODULE_ALIAS("platform:" XILINX_SPI_NAME); 483 484 static struct platform_driver xilinx_spi_driver = { 485 .probe = xilinx_spi_probe, 486 .remove = xilinx_spi_remove, 487 .driver = { 488 .name = XILINX_SPI_NAME, 489 .owner = THIS_MODULE, 490 .of_match_table = xilinx_spi_of_match, 491 }, 492 }; 493 module_platform_driver(xilinx_spi_driver); 494 495 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); 496 MODULE_DESCRIPTION("Xilinx SPI driver"); 497 MODULE_LICENSE("GPL"); 498