1 /* 2 * Xilinx SPI controller driver (master mode only) 3 * 4 * Author: MontaVista Software, Inc. 5 * source@mvista.com 6 * 7 * Copyright (c) 2010 Secret Lab Technologies, Ltd. 8 * Copyright (c) 2009 Intel Corporation 9 * 2002-2007 (c) MontaVista Software, Inc. 10 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/spi/spi.h> 21 #include <linux/spi/spi_bitbang.h> 22 #include <linux/spi/xilinx_spi.h> 23 #include <linux/io.h> 24 25 #define XILINX_SPI_MAX_CS 32 26 27 #define XILINX_SPI_NAME "xilinx_spi" 28 29 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) 30 * Product Specification", DS464 31 */ 32 #define XSPI_CR_OFFSET 0x60 /* Control Register */ 33 34 #define XSPI_CR_LOOP 0x01 35 #define XSPI_CR_ENABLE 0x02 36 #define XSPI_CR_MASTER_MODE 0x04 37 #define XSPI_CR_CPOL 0x08 38 #define XSPI_CR_CPHA 0x10 39 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \ 40 XSPI_CR_LSB_FIRST | XSPI_CR_LOOP) 41 #define XSPI_CR_TXFIFO_RESET 0x20 42 #define XSPI_CR_RXFIFO_RESET 0x40 43 #define XSPI_CR_MANUAL_SSELECT 0x80 44 #define XSPI_CR_TRANS_INHIBIT 0x100 45 #define XSPI_CR_LSB_FIRST 0x200 46 47 #define XSPI_SR_OFFSET 0x64 /* Status Register */ 48 49 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ 50 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ 51 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ 52 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ 53 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ 54 55 #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ 56 #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ 57 58 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ 59 60 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 61 * IPIF registers are 32 bit 62 */ 63 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ 64 #define XIPIF_V123B_GINTR_ENABLE 0x80000000 65 66 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ 67 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ 68 69 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ 70 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while 71 * disabled */ 72 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ 73 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ 74 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ 75 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ 76 #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ 77 78 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ 79 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ 80 81 struct xilinx_spi { 82 /* bitbang has to be first */ 83 struct spi_bitbang bitbang; 84 struct completion done; 85 void __iomem *regs; /* virt. address of the control registers */ 86 87 int irq; 88 89 u8 *rx_ptr; /* pointer in the Tx buffer */ 90 const u8 *tx_ptr; /* pointer in the Rx buffer */ 91 u8 bytes_per_word; 92 int buffer_size; /* buffer size in words */ 93 u32 cs_inactive; /* Level of the CS pins when inactive*/ 94 unsigned int (*read_fn)(void __iomem *); 95 void (*write_fn)(u32, void __iomem *); 96 }; 97 98 static void xspi_write32(u32 val, void __iomem *addr) 99 { 100 iowrite32(val, addr); 101 } 102 103 static unsigned int xspi_read32(void __iomem *addr) 104 { 105 return ioread32(addr); 106 } 107 108 static void xspi_write32_be(u32 val, void __iomem *addr) 109 { 110 iowrite32be(val, addr); 111 } 112 113 static unsigned int xspi_read32_be(void __iomem *addr) 114 { 115 return ioread32be(addr); 116 } 117 118 static void xilinx_spi_tx(struct xilinx_spi *xspi) 119 { 120 u32 data = 0; 121 122 if (!xspi->tx_ptr) { 123 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); 124 return; 125 } 126 127 switch (xspi->bytes_per_word) { 128 case 1: 129 data = *(u8 *)(xspi->tx_ptr); 130 break; 131 case 2: 132 data = *(u16 *)(xspi->tx_ptr); 133 break; 134 case 4: 135 data = *(u32 *)(xspi->tx_ptr); 136 break; 137 } 138 139 xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET); 140 xspi->tx_ptr += xspi->bytes_per_word; 141 } 142 143 static void xilinx_spi_rx(struct xilinx_spi *xspi) 144 { 145 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 146 147 if (!xspi->rx_ptr) 148 return; 149 150 switch (xspi->bytes_per_word) { 151 case 1: 152 *(u8 *)(xspi->rx_ptr) = data; 153 break; 154 case 2: 155 *(u16 *)(xspi->rx_ptr) = data; 156 break; 157 case 4: 158 *(u32 *)(xspi->rx_ptr) = data; 159 break; 160 } 161 162 xspi->rx_ptr += xspi->bytes_per_word; 163 } 164 165 static void xspi_init_hw(struct xilinx_spi *xspi) 166 { 167 void __iomem *regs_base = xspi->regs; 168 169 /* Reset the SPI device */ 170 xspi->write_fn(XIPIF_V123B_RESET_MASK, 171 regs_base + XIPIF_V123B_RESETR_OFFSET); 172 /* Enable the transmit empty interrupt, which we use to determine 173 * progress on the transmission. 174 */ 175 xspi->write_fn(XSPI_INTR_TX_EMPTY, 176 regs_base + XIPIF_V123B_IIER_OFFSET); 177 /* Disable the global IPIF interrupt */ 178 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); 179 /* Deselect the slave on the SPI bus */ 180 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); 181 /* Disable the transmitter, enable Manual Slave Select Assertion, 182 * put SPI controller into master mode, and enable it */ 183 xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE | 184 XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET, 185 regs_base + XSPI_CR_OFFSET); 186 } 187 188 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) 189 { 190 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 191 u16 cr; 192 u32 cs; 193 194 if (is_on == BITBANG_CS_INACTIVE) { 195 /* Deselect the slave on the SPI bus */ 196 xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET); 197 return; 198 } 199 200 /* Set the SPI clock phase and polarity */ 201 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK; 202 if (spi->mode & SPI_CPHA) 203 cr |= XSPI_CR_CPHA; 204 if (spi->mode & SPI_CPOL) 205 cr |= XSPI_CR_CPOL; 206 if (spi->mode & SPI_LSB_FIRST) 207 cr |= XSPI_CR_LSB_FIRST; 208 if (spi->mode & SPI_LOOP) 209 cr |= XSPI_CR_LOOP; 210 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 211 212 /* We do not check spi->max_speed_hz here as the SPI clock 213 * frequency is not software programmable (the IP block design 214 * parameter) 215 */ 216 217 cs = xspi->cs_inactive; 218 cs ^= BIT(spi->chip_select); 219 220 /* Activate the chip select */ 221 xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET); 222 } 223 224 /* spi_bitbang requires custom setup_transfer() to be defined if there is a 225 * custom txrx_bufs(). 226 */ 227 static int xilinx_spi_setup_transfer(struct spi_device *spi, 228 struct spi_transfer *t) 229 { 230 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 231 232 if (spi->mode & SPI_CS_HIGH) 233 xspi->cs_inactive &= ~BIT(spi->chip_select); 234 else 235 xspi->cs_inactive |= BIT(spi->chip_select); 236 237 return 0; 238 } 239 240 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) 241 { 242 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 243 int remaining_words; /* the number of words left to transfer */ 244 bool use_irq = false; 245 u16 cr = 0; 246 247 /* We get here with transmitter inhibited */ 248 249 xspi->tx_ptr = t->tx_buf; 250 xspi->rx_ptr = t->rx_buf; 251 remaining_words = t->len / xspi->bytes_per_word; 252 253 if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) { 254 u32 isr; 255 use_irq = true; 256 /* Inhibit irq to avoid spurious irqs on tx_empty*/ 257 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); 258 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, 259 xspi->regs + XSPI_CR_OFFSET); 260 /* ACK old irqs (if any) */ 261 isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); 262 if (isr) 263 xspi->write_fn(isr, 264 xspi->regs + XIPIF_V123B_IISR_OFFSET); 265 /* Enable the global IPIF interrupt */ 266 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, 267 xspi->regs + XIPIF_V123B_DGIER_OFFSET); 268 reinit_completion(&xspi->done); 269 } 270 271 while (remaining_words) { 272 int n_words, tx_words, rx_words; 273 u32 sr; 274 int stalled; 275 276 n_words = min(remaining_words, xspi->buffer_size); 277 278 tx_words = n_words; 279 while (tx_words--) 280 xilinx_spi_tx(xspi); 281 282 /* Start the transfer by not inhibiting the transmitter any 283 * longer 284 */ 285 286 if (use_irq) { 287 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 288 wait_for_completion(&xspi->done); 289 /* A transmit has just completed. Process received data 290 * and check for more data to transmit. Always inhibit 291 * the transmitter while the Isr refills the transmit 292 * register/FIFO, or make sure it is stopped if we're 293 * done. 294 */ 295 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, 296 xspi->regs + XSPI_CR_OFFSET); 297 sr = XSPI_SR_TX_EMPTY_MASK; 298 } else 299 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 300 301 /* Read out all the data from the Rx FIFO */ 302 rx_words = n_words; 303 stalled = 10; 304 while (rx_words) { 305 if (rx_words == n_words && !(stalled--) && 306 !(sr & XSPI_SR_TX_EMPTY_MASK) && 307 (sr & XSPI_SR_RX_EMPTY_MASK)) { 308 dev_err(&spi->dev, 309 "Detected stall. Check C_SPI_MODE and C_SPI_MEMORY\n"); 310 xspi_init_hw(xspi); 311 return -EIO; 312 } 313 314 if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) { 315 xilinx_spi_rx(xspi); 316 rx_words--; 317 continue; 318 } 319 320 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 321 if (!(sr & XSPI_SR_RX_EMPTY_MASK)) { 322 xilinx_spi_rx(xspi); 323 rx_words--; 324 } 325 } 326 327 remaining_words -= n_words; 328 } 329 330 if (use_irq) { 331 xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET); 332 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 333 } 334 335 return t->len; 336 } 337 338 339 /* This driver supports single master mode only. Hence Tx FIFO Empty 340 * is the only interrupt we care about. 341 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode 342 * Fault are not to happen. 343 */ 344 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) 345 { 346 struct xilinx_spi *xspi = dev_id; 347 u32 ipif_isr; 348 349 /* Get the IPIF interrupts, and clear them immediately */ 350 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); 351 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); 352 353 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ 354 complete(&xspi->done); 355 return IRQ_HANDLED; 356 } 357 358 return IRQ_NONE; 359 } 360 361 static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi) 362 { 363 u8 sr; 364 int n_words = 0; 365 366 /* 367 * Before the buffer_size detection we reset the core 368 * to make sure we start with a clean state. 369 */ 370 xspi->write_fn(XIPIF_V123B_RESET_MASK, 371 xspi->regs + XIPIF_V123B_RESETR_OFFSET); 372 373 /* Fill the Tx FIFO with as many words as possible */ 374 do { 375 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); 376 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 377 n_words++; 378 } while (!(sr & XSPI_SR_TX_FULL_MASK)); 379 380 return n_words; 381 } 382 383 static const struct of_device_id xilinx_spi_of_match[] = { 384 { .compatible = "xlnx,axi-quad-spi-1.00.a", }, 385 { .compatible = "xlnx,xps-spi-2.00.a", }, 386 { .compatible = "xlnx,xps-spi-2.00.b", }, 387 {} 388 }; 389 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); 390 391 static int xilinx_spi_probe(struct platform_device *pdev) 392 { 393 struct xilinx_spi *xspi; 394 struct xspi_platform_data *pdata; 395 struct resource *res; 396 int ret, num_cs = 0, bits_per_word = 8; 397 struct spi_master *master; 398 u32 tmp; 399 u8 i; 400 401 pdata = dev_get_platdata(&pdev->dev); 402 if (pdata) { 403 num_cs = pdata->num_chipselect; 404 bits_per_word = pdata->bits_per_word; 405 } else { 406 of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits", 407 &num_cs); 408 } 409 410 if (!num_cs) { 411 dev_err(&pdev->dev, 412 "Missing slave select configuration data\n"); 413 return -EINVAL; 414 } 415 416 if (num_cs > XILINX_SPI_MAX_CS) { 417 dev_err(&pdev->dev, "Invalid number of spi slaves\n"); 418 return -EINVAL; 419 } 420 421 master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); 422 if (!master) 423 return -ENODEV; 424 425 /* the spi->mode bits understood by this driver: */ 426 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | 427 SPI_CS_HIGH; 428 429 xspi = spi_master_get_devdata(master); 430 xspi->cs_inactive = 0xffffffff; 431 xspi->bitbang.master = master; 432 xspi->bitbang.chipselect = xilinx_spi_chipselect; 433 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; 434 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; 435 init_completion(&xspi->done); 436 437 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 438 xspi->regs = devm_ioremap_resource(&pdev->dev, res); 439 if (IS_ERR(xspi->regs)) { 440 ret = PTR_ERR(xspi->regs); 441 goto put_master; 442 } 443 444 master->bus_num = pdev->id; 445 master->num_chipselect = num_cs; 446 master->dev.of_node = pdev->dev.of_node; 447 448 /* 449 * Detect endianess on the IP via loop bit in CR. Detection 450 * must be done before reset is sent because incorrect reset 451 * value generates error interrupt. 452 * Setup little endian helper functions first and try to use them 453 * and check if bit was correctly setup or not. 454 */ 455 xspi->read_fn = xspi_read32; 456 xspi->write_fn = xspi_write32; 457 458 xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); 459 tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); 460 tmp &= XSPI_CR_LOOP; 461 if (tmp != XSPI_CR_LOOP) { 462 xspi->read_fn = xspi_read32_be; 463 xspi->write_fn = xspi_write32_be; 464 } 465 466 master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word); 467 xspi->bytes_per_word = bits_per_word / 8; 468 xspi->buffer_size = xilinx_spi_find_buffer_size(xspi); 469 470 xspi->irq = platform_get_irq(pdev, 0); 471 if (xspi->irq < 0 && xspi->irq != -ENXIO) { 472 ret = xspi->irq; 473 goto put_master; 474 } else if (xspi->irq >= 0) { 475 /* Register for SPI Interrupt */ 476 ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0, 477 dev_name(&pdev->dev), xspi); 478 if (ret) 479 goto put_master; 480 } 481 482 /* SPI controller initializations */ 483 xspi_init_hw(xspi); 484 485 ret = spi_bitbang_start(&xspi->bitbang); 486 if (ret) { 487 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n"); 488 goto put_master; 489 } 490 491 dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", 492 (unsigned long long)res->start, xspi->regs, xspi->irq); 493 494 if (pdata) { 495 for (i = 0; i < pdata->num_devices; i++) 496 spi_new_device(master, pdata->devices + i); 497 } 498 499 platform_set_drvdata(pdev, master); 500 return 0; 501 502 put_master: 503 spi_master_put(master); 504 505 return ret; 506 } 507 508 static int xilinx_spi_remove(struct platform_device *pdev) 509 { 510 struct spi_master *master = platform_get_drvdata(pdev); 511 struct xilinx_spi *xspi = spi_master_get_devdata(master); 512 void __iomem *regs_base = xspi->regs; 513 514 spi_bitbang_stop(&xspi->bitbang); 515 516 /* Disable all the interrupts just in case */ 517 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); 518 /* Disable the global IPIF interrupt */ 519 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); 520 521 spi_master_put(xspi->bitbang.master); 522 523 return 0; 524 } 525 526 /* work with hotplug and coldplug */ 527 MODULE_ALIAS("platform:" XILINX_SPI_NAME); 528 529 static struct platform_driver xilinx_spi_driver = { 530 .probe = xilinx_spi_probe, 531 .remove = xilinx_spi_remove, 532 .driver = { 533 .name = XILINX_SPI_NAME, 534 .of_match_table = xilinx_spi_of_match, 535 }, 536 }; 537 module_platform_driver(xilinx_spi_driver); 538 539 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); 540 MODULE_DESCRIPTION("Xilinx SPI driver"); 541 MODULE_LICENSE("GPL"); 542