1 /* 2 * Xilinx SPI controller driver (master mode only) 3 * 4 * Author: MontaVista Software, Inc. 5 * source@mvista.com 6 * 7 * Copyright (c) 2010 Secret Lab Technologies, Ltd. 8 * Copyright (c) 2009 Intel Corporation 9 * 2002-2007 (c) MontaVista Software, Inc. 10 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/spi_bitbang.h> 23 #include <linux/spi/xilinx_spi.h> 24 #include <linux/io.h> 25 26 #define XILINX_SPI_NAME "xilinx_spi" 27 28 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) 29 * Product Specification", DS464 30 */ 31 #define XSPI_CR_OFFSET 0x60 /* Control Register */ 32 33 #define XSPI_CR_LOOP 0x01 34 #define XSPI_CR_ENABLE 0x02 35 #define XSPI_CR_MASTER_MODE 0x04 36 #define XSPI_CR_CPOL 0x08 37 #define XSPI_CR_CPHA 0x10 38 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL) 39 #define XSPI_CR_TXFIFO_RESET 0x20 40 #define XSPI_CR_RXFIFO_RESET 0x40 41 #define XSPI_CR_MANUAL_SSELECT 0x80 42 #define XSPI_CR_TRANS_INHIBIT 0x100 43 #define XSPI_CR_LSB_FIRST 0x200 44 45 #define XSPI_SR_OFFSET 0x64 /* Status Register */ 46 47 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ 48 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ 49 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ 50 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ 51 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ 52 53 #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ 54 #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ 55 56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ 57 58 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 59 * IPIF registers are 32 bit 60 */ 61 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ 62 #define XIPIF_V123B_GINTR_ENABLE 0x80000000 63 64 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ 65 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ 66 67 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ 68 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while 69 * disabled */ 70 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ 71 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ 72 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ 73 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ 74 #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ 75 76 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ 77 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ 78 79 struct xilinx_spi { 80 /* bitbang has to be first */ 81 struct spi_bitbang bitbang; 82 struct completion done; 83 struct resource mem; /* phys mem */ 84 void __iomem *regs; /* virt. address of the control registers */ 85 86 u32 irq; 87 88 u8 *rx_ptr; /* pointer in the Tx buffer */ 89 const u8 *tx_ptr; /* pointer in the Rx buffer */ 90 int remaining_bytes; /* the number of bytes left to transfer */ 91 u8 bits_per_word; 92 unsigned int (*read_fn) (void __iomem *); 93 void (*write_fn) (u32, void __iomem *); 94 void (*tx_fn) (struct xilinx_spi *); 95 void (*rx_fn) (struct xilinx_spi *); 96 }; 97 98 static void xspi_write32(u32 val, void __iomem *addr) 99 { 100 iowrite32(val, addr); 101 } 102 103 static unsigned int xspi_read32(void __iomem *addr) 104 { 105 return ioread32(addr); 106 } 107 108 static void xspi_write32_be(u32 val, void __iomem *addr) 109 { 110 iowrite32be(val, addr); 111 } 112 113 static unsigned int xspi_read32_be(void __iomem *addr) 114 { 115 return ioread32be(addr); 116 } 117 118 static void xspi_tx8(struct xilinx_spi *xspi) 119 { 120 xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET); 121 xspi->tx_ptr++; 122 } 123 124 static void xspi_tx16(struct xilinx_spi *xspi) 125 { 126 xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); 127 xspi->tx_ptr += 2; 128 } 129 130 static void xspi_tx32(struct xilinx_spi *xspi) 131 { 132 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); 133 xspi->tx_ptr += 4; 134 } 135 136 static void xspi_rx8(struct xilinx_spi *xspi) 137 { 138 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 139 if (xspi->rx_ptr) { 140 *xspi->rx_ptr = data & 0xff; 141 xspi->rx_ptr++; 142 } 143 } 144 145 static void xspi_rx16(struct xilinx_spi *xspi) 146 { 147 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 148 if (xspi->rx_ptr) { 149 *(u16 *)(xspi->rx_ptr) = data & 0xffff; 150 xspi->rx_ptr += 2; 151 } 152 } 153 154 static void xspi_rx32(struct xilinx_spi *xspi) 155 { 156 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 157 if (xspi->rx_ptr) { 158 *(u32 *)(xspi->rx_ptr) = data; 159 xspi->rx_ptr += 4; 160 } 161 } 162 163 static void xspi_init_hw(struct xilinx_spi *xspi) 164 { 165 void __iomem *regs_base = xspi->regs; 166 167 /* Reset the SPI device */ 168 xspi->write_fn(XIPIF_V123B_RESET_MASK, 169 regs_base + XIPIF_V123B_RESETR_OFFSET); 170 /* Disable all the interrupts just in case */ 171 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); 172 /* Enable the global IPIF interrupt */ 173 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, 174 regs_base + XIPIF_V123B_DGIER_OFFSET); 175 /* Deselect the slave on the SPI bus */ 176 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); 177 /* Disable the transmitter, enable Manual Slave Select Assertion, 178 * put SPI controller into master mode, and enable it */ 179 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT | 180 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | 181 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET); 182 } 183 184 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) 185 { 186 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 187 188 if (is_on == BITBANG_CS_INACTIVE) { 189 /* Deselect the slave on the SPI bus */ 190 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET); 191 } else if (is_on == BITBANG_CS_ACTIVE) { 192 /* Set the SPI clock phase and polarity */ 193 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) 194 & ~XSPI_CR_MODE_MASK; 195 if (spi->mode & SPI_CPHA) 196 cr |= XSPI_CR_CPHA; 197 if (spi->mode & SPI_CPOL) 198 cr |= XSPI_CR_CPOL; 199 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 200 201 /* We do not check spi->max_speed_hz here as the SPI clock 202 * frequency is not software programmable (the IP block design 203 * parameter) 204 */ 205 206 /* Activate the chip select */ 207 xspi->write_fn(~(0x0001 << spi->chip_select), 208 xspi->regs + XSPI_SSR_OFFSET); 209 } 210 } 211 212 /* spi_bitbang requires custom setup_transfer() to be defined if there is a 213 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block 214 * supports 8 or 16 bits per word which cannot be changed in software. 215 * SPI clock can't be changed in software either. 216 * Check for correct bits per word. Chip select delay calculations could be 217 * added here as soon as bitbang_work() can be made aware of the delay value. 218 */ 219 static int xilinx_spi_setup_transfer(struct spi_device *spi, 220 struct spi_transfer *t) 221 { 222 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 223 u8 bits_per_word; 224 225 bits_per_word = (t && t->bits_per_word) 226 ? t->bits_per_word : spi->bits_per_word; 227 if (bits_per_word != xspi->bits_per_word) { 228 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", 229 __func__, bits_per_word); 230 return -EINVAL; 231 } 232 233 return 0; 234 } 235 236 static int xilinx_spi_setup(struct spi_device *spi) 237 { 238 /* always return 0, we can not check the number of bits. 239 * There are cases when SPI setup is called before any driver is 240 * there, in that case the SPI core defaults to 8 bits, which we 241 * do not support in some cases. But if we return an error, the 242 * SPI device would not be registered and no driver can get hold of it 243 * When the driver is there, it will call SPI setup again with the 244 * correct number of bits per transfer. 245 * If a driver setups with the wrong bit number, it will fail when 246 * it tries to do a transfer 247 */ 248 return 0; 249 } 250 251 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) 252 { 253 u8 sr; 254 255 /* Fill the Tx FIFO with as many bytes as possible */ 256 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 257 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { 258 if (xspi->tx_ptr) 259 xspi->tx_fn(xspi); 260 else 261 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); 262 xspi->remaining_bytes -= xspi->bits_per_word / 8; 263 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 264 } 265 } 266 267 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) 268 { 269 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 270 u32 ipif_ier; 271 272 /* We get here with transmitter inhibited */ 273 274 xspi->tx_ptr = t->tx_buf; 275 xspi->rx_ptr = t->rx_buf; 276 xspi->remaining_bytes = t->len; 277 INIT_COMPLETION(xspi->done); 278 279 280 /* Enable the transmit empty interrupt, which we use to determine 281 * progress on the transmission. 282 */ 283 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET); 284 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY, 285 xspi->regs + XIPIF_V123B_IIER_OFFSET); 286 287 for (;;) { 288 u16 cr; 289 u8 sr; 290 291 xilinx_spi_fill_tx_fifo(xspi); 292 293 /* Start the transfer by not inhibiting the transmitter any 294 * longer 295 */ 296 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & 297 ~XSPI_CR_TRANS_INHIBIT; 298 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 299 300 wait_for_completion(&xspi->done); 301 302 /* A transmit has just completed. Process received data and 303 * check for more data to transmit. Always inhibit the 304 * transmitter while the Isr refills the transmit register/FIFO, 305 * or make sure it is stopped if we're done. 306 */ 307 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); 308 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, 309 xspi->regs + XSPI_CR_OFFSET); 310 311 /* Read out all the data from the Rx FIFO */ 312 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 313 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { 314 xspi->rx_fn(xspi); 315 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 316 } 317 318 /* See if there is more data to send */ 319 if (xspi->remaining_bytes <= 0) 320 break; 321 } 322 323 /* Disable the transmit empty interrupt */ 324 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET); 325 326 return t->len - xspi->remaining_bytes; 327 } 328 329 330 /* This driver supports single master mode only. Hence Tx FIFO Empty 331 * is the only interrupt we care about. 332 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode 333 * Fault are not to happen. 334 */ 335 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) 336 { 337 struct xilinx_spi *xspi = dev_id; 338 u32 ipif_isr; 339 340 /* Get the IPIF interrupts, and clear them immediately */ 341 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); 342 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); 343 344 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ 345 complete(&xspi->done); 346 } 347 348 return IRQ_HANDLED; 349 } 350 351 static const struct of_device_id xilinx_spi_of_match[] = { 352 { .compatible = "xlnx,xps-spi-2.00.a", }, 353 { .compatible = "xlnx,xps-spi-2.00.b", }, 354 {} 355 }; 356 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); 357 358 struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem, 359 u32 irq, s16 bus_num, int num_cs, int bits_per_word) 360 { 361 struct spi_master *master; 362 struct xilinx_spi *xspi; 363 int ret; 364 u32 tmp; 365 366 master = spi_alloc_master(dev, sizeof(struct xilinx_spi)); 367 if (!master) 368 return NULL; 369 370 /* the spi->mode bits understood by this driver: */ 371 master->mode_bits = SPI_CPOL | SPI_CPHA; 372 373 xspi = spi_master_get_devdata(master); 374 xspi->bitbang.master = spi_master_get(master); 375 xspi->bitbang.chipselect = xilinx_spi_chipselect; 376 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; 377 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; 378 xspi->bitbang.master->setup = xilinx_spi_setup; 379 init_completion(&xspi->done); 380 381 if (!request_mem_region(mem->start, resource_size(mem), 382 XILINX_SPI_NAME)) 383 goto put_master; 384 385 xspi->regs = ioremap(mem->start, resource_size(mem)); 386 if (xspi->regs == NULL) { 387 dev_warn(dev, "ioremap failure\n"); 388 goto map_failed; 389 } 390 391 master->bus_num = bus_num; 392 master->num_chipselect = num_cs; 393 master->dev.of_node = dev->of_node; 394 395 xspi->mem = *mem; 396 xspi->irq = irq; 397 398 /* 399 * Detect endianess on the IP via loop bit in CR. Detection 400 * must be done before reset is sent because incorrect reset 401 * value generates error interrupt. 402 * Setup little endian helper functions first and try to use them 403 * and check if bit was correctly setup or not. 404 */ 405 xspi->read_fn = xspi_read32; 406 xspi->write_fn = xspi_write32; 407 408 xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); 409 tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); 410 tmp &= XSPI_CR_LOOP; 411 if (tmp != XSPI_CR_LOOP) { 412 xspi->read_fn = xspi_read32_be; 413 xspi->write_fn = xspi_write32_be; 414 } 415 416 xspi->bits_per_word = bits_per_word; 417 if (xspi->bits_per_word == 8) { 418 xspi->tx_fn = xspi_tx8; 419 xspi->rx_fn = xspi_rx8; 420 } else if (xspi->bits_per_word == 16) { 421 xspi->tx_fn = xspi_tx16; 422 xspi->rx_fn = xspi_rx16; 423 } else if (xspi->bits_per_word == 32) { 424 xspi->tx_fn = xspi_tx32; 425 xspi->rx_fn = xspi_rx32; 426 } else 427 goto unmap_io; 428 429 430 /* SPI controller initializations */ 431 xspi_init_hw(xspi); 432 433 /* Register for SPI Interrupt */ 434 ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi); 435 if (ret) 436 goto unmap_io; 437 438 ret = spi_bitbang_start(&xspi->bitbang); 439 if (ret) { 440 dev_err(dev, "spi_bitbang_start FAILED\n"); 441 goto free_irq; 442 } 443 444 dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", 445 (unsigned long long)mem->start, xspi->regs, xspi->irq); 446 return master; 447 448 free_irq: 449 free_irq(xspi->irq, xspi); 450 unmap_io: 451 iounmap(xspi->regs); 452 map_failed: 453 release_mem_region(mem->start, resource_size(mem)); 454 put_master: 455 spi_master_put(master); 456 return NULL; 457 } 458 EXPORT_SYMBOL(xilinx_spi_init); 459 460 void xilinx_spi_deinit(struct spi_master *master) 461 { 462 struct xilinx_spi *xspi; 463 464 xspi = spi_master_get_devdata(master); 465 466 spi_bitbang_stop(&xspi->bitbang); 467 free_irq(xspi->irq, xspi); 468 iounmap(xspi->regs); 469 470 release_mem_region(xspi->mem.start, resource_size(&xspi->mem)); 471 spi_master_put(xspi->bitbang.master); 472 } 473 EXPORT_SYMBOL(xilinx_spi_deinit); 474 475 static int xilinx_spi_probe(struct platform_device *dev) 476 { 477 struct xspi_platform_data *pdata; 478 struct resource *r; 479 int irq, num_cs = 0, bits_per_word = 8; 480 struct spi_master *master; 481 u8 i; 482 483 pdata = dev->dev.platform_data; 484 if (pdata) { 485 num_cs = pdata->num_chipselect; 486 bits_per_word = pdata->bits_per_word; 487 } 488 489 #ifdef CONFIG_OF 490 if (dev->dev.of_node) { 491 const __be32 *prop; 492 int len; 493 494 /* number of slave select bits is required */ 495 prop = of_get_property(dev->dev.of_node, "xlnx,num-ss-bits", 496 &len); 497 if (prop && len >= sizeof(*prop)) 498 num_cs = __be32_to_cpup(prop); 499 } 500 #endif 501 502 if (!num_cs) { 503 dev_err(&dev->dev, "Missing slave select configuration data\n"); 504 return -EINVAL; 505 } 506 507 508 r = platform_get_resource(dev, IORESOURCE_MEM, 0); 509 if (!r) 510 return -ENODEV; 511 512 irq = platform_get_irq(dev, 0); 513 if (irq < 0) 514 return -ENXIO; 515 516 master = xilinx_spi_init(&dev->dev, r, irq, dev->id, num_cs, 517 bits_per_word); 518 if (!master) 519 return -ENODEV; 520 521 if (pdata) { 522 for (i = 0; i < pdata->num_devices; i++) 523 spi_new_device(master, pdata->devices + i); 524 } 525 526 platform_set_drvdata(dev, master); 527 return 0; 528 } 529 530 static int xilinx_spi_remove(struct platform_device *dev) 531 { 532 xilinx_spi_deinit(platform_get_drvdata(dev)); 533 534 return 0; 535 } 536 537 /* work with hotplug and coldplug */ 538 MODULE_ALIAS("platform:" XILINX_SPI_NAME); 539 540 static struct platform_driver xilinx_spi_driver = { 541 .probe = xilinx_spi_probe, 542 .remove = xilinx_spi_remove, 543 .driver = { 544 .name = XILINX_SPI_NAME, 545 .owner = THIS_MODULE, 546 .of_match_table = xilinx_spi_of_match, 547 }, 548 }; 549 module_platform_driver(xilinx_spi_driver); 550 551 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); 552 MODULE_DESCRIPTION("Xilinx SPI driver"); 553 MODULE_LICENSE("GPL"); 554