1 /* 2 * Xilinx SPI controller driver (master mode only) 3 * 4 * Author: MontaVista Software, Inc. 5 * source@mvista.com 6 * 7 * Copyright (c) 2010 Secret Lab Technologies, Ltd. 8 * Copyright (c) 2009 Intel Corporation 9 * 2002-2007 (c) MontaVista Software, Inc. 10 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/spi_bitbang.h> 23 #include <linux/spi/xilinx_spi.h> 24 #include <linux/io.h> 25 26 #define XILINX_SPI_NAME "xilinx_spi" 27 28 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) 29 * Product Specification", DS464 30 */ 31 #define XSPI_CR_OFFSET 0x60 /* Control Register */ 32 33 #define XSPI_CR_LOOP 0x01 34 #define XSPI_CR_ENABLE 0x02 35 #define XSPI_CR_MASTER_MODE 0x04 36 #define XSPI_CR_CPOL 0x08 37 #define XSPI_CR_CPHA 0x10 38 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL) 39 #define XSPI_CR_TXFIFO_RESET 0x20 40 #define XSPI_CR_RXFIFO_RESET 0x40 41 #define XSPI_CR_MANUAL_SSELECT 0x80 42 #define XSPI_CR_TRANS_INHIBIT 0x100 43 #define XSPI_CR_LSB_FIRST 0x200 44 45 #define XSPI_SR_OFFSET 0x64 /* Status Register */ 46 47 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ 48 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ 49 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ 50 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ 51 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ 52 53 #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ 54 #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ 55 56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ 57 58 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 59 * IPIF registers are 32 bit 60 */ 61 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ 62 #define XIPIF_V123B_GINTR_ENABLE 0x80000000 63 64 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ 65 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ 66 67 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ 68 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while 69 * disabled */ 70 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ 71 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ 72 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ 73 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ 74 #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ 75 76 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ 77 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ 78 79 struct xilinx_spi { 80 /* bitbang has to be first */ 81 struct spi_bitbang bitbang; 82 struct completion done; 83 struct resource mem; /* phys mem */ 84 void __iomem *regs; /* virt. address of the control registers */ 85 86 u32 irq; 87 88 u8 *rx_ptr; /* pointer in the Tx buffer */ 89 const u8 *tx_ptr; /* pointer in the Rx buffer */ 90 int remaining_bytes; /* the number of bytes left to transfer */ 91 u8 bits_per_word; 92 unsigned int (*read_fn) (void __iomem *); 93 void (*write_fn) (u32, void __iomem *); 94 void (*tx_fn) (struct xilinx_spi *); 95 void (*rx_fn) (struct xilinx_spi *); 96 }; 97 98 static void xspi_write32(u32 val, void __iomem *addr) 99 { 100 iowrite32(val, addr); 101 } 102 103 static unsigned int xspi_read32(void __iomem *addr) 104 { 105 return ioread32(addr); 106 } 107 108 static void xspi_write32_be(u32 val, void __iomem *addr) 109 { 110 iowrite32be(val, addr); 111 } 112 113 static unsigned int xspi_read32_be(void __iomem *addr) 114 { 115 return ioread32be(addr); 116 } 117 118 static void xspi_tx8(struct xilinx_spi *xspi) 119 { 120 xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET); 121 xspi->tx_ptr++; 122 } 123 124 static void xspi_tx16(struct xilinx_spi *xspi) 125 { 126 xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); 127 xspi->tx_ptr += 2; 128 } 129 130 static void xspi_tx32(struct xilinx_spi *xspi) 131 { 132 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); 133 xspi->tx_ptr += 4; 134 } 135 136 static void xspi_rx8(struct xilinx_spi *xspi) 137 { 138 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 139 if (xspi->rx_ptr) { 140 *xspi->rx_ptr = data & 0xff; 141 xspi->rx_ptr++; 142 } 143 } 144 145 static void xspi_rx16(struct xilinx_spi *xspi) 146 { 147 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 148 if (xspi->rx_ptr) { 149 *(u16 *)(xspi->rx_ptr) = data & 0xffff; 150 xspi->rx_ptr += 2; 151 } 152 } 153 154 static void xspi_rx32(struct xilinx_spi *xspi) 155 { 156 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 157 if (xspi->rx_ptr) { 158 *(u32 *)(xspi->rx_ptr) = data; 159 xspi->rx_ptr += 4; 160 } 161 } 162 163 static void xspi_init_hw(struct xilinx_spi *xspi) 164 { 165 void __iomem *regs_base = xspi->regs; 166 167 /* Reset the SPI device */ 168 xspi->write_fn(XIPIF_V123B_RESET_MASK, 169 regs_base + XIPIF_V123B_RESETR_OFFSET); 170 /* Disable all the interrupts just in case */ 171 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); 172 /* Enable the global IPIF interrupt */ 173 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, 174 regs_base + XIPIF_V123B_DGIER_OFFSET); 175 /* Deselect the slave on the SPI bus */ 176 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); 177 /* Disable the transmitter, enable Manual Slave Select Assertion, 178 * put SPI controller into master mode, and enable it */ 179 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT | 180 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | 181 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET); 182 } 183 184 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) 185 { 186 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 187 188 if (is_on == BITBANG_CS_INACTIVE) { 189 /* Deselect the slave on the SPI bus */ 190 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET); 191 } else if (is_on == BITBANG_CS_ACTIVE) { 192 /* Set the SPI clock phase and polarity */ 193 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) 194 & ~XSPI_CR_MODE_MASK; 195 if (spi->mode & SPI_CPHA) 196 cr |= XSPI_CR_CPHA; 197 if (spi->mode & SPI_CPOL) 198 cr |= XSPI_CR_CPOL; 199 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 200 201 /* We do not check spi->max_speed_hz here as the SPI clock 202 * frequency is not software programmable (the IP block design 203 * parameter) 204 */ 205 206 /* Activate the chip select */ 207 xspi->write_fn(~(0x0001 << spi->chip_select), 208 xspi->regs + XSPI_SSR_OFFSET); 209 } 210 } 211 212 /* spi_bitbang requires custom setup_transfer() to be defined if there is a 213 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block 214 * supports 8 or 16 bits per word which cannot be changed in software. 215 * SPI clock can't be changed in software either. 216 * Check for correct bits per word. Chip select delay calculations could be 217 * added here as soon as bitbang_work() can be made aware of the delay value. 218 */ 219 static int xilinx_spi_setup_transfer(struct spi_device *spi, 220 struct spi_transfer *t) 221 { 222 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 223 u8 bits_per_word; 224 225 bits_per_word = (t && t->bits_per_word) 226 ? t->bits_per_word : spi->bits_per_word; 227 if (bits_per_word != xspi->bits_per_word) { 228 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", 229 __func__, bits_per_word); 230 return -EINVAL; 231 } 232 233 return 0; 234 } 235 236 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) 237 { 238 u8 sr; 239 240 /* Fill the Tx FIFO with as many bytes as possible */ 241 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 242 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { 243 if (xspi->tx_ptr) 244 xspi->tx_fn(xspi); 245 else 246 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); 247 xspi->remaining_bytes -= xspi->bits_per_word / 8; 248 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 249 } 250 } 251 252 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) 253 { 254 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 255 u32 ipif_ier; 256 257 /* We get here with transmitter inhibited */ 258 259 xspi->tx_ptr = t->tx_buf; 260 xspi->rx_ptr = t->rx_buf; 261 xspi->remaining_bytes = t->len; 262 INIT_COMPLETION(xspi->done); 263 264 265 /* Enable the transmit empty interrupt, which we use to determine 266 * progress on the transmission. 267 */ 268 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET); 269 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY, 270 xspi->regs + XIPIF_V123B_IIER_OFFSET); 271 272 for (;;) { 273 u16 cr; 274 u8 sr; 275 276 xilinx_spi_fill_tx_fifo(xspi); 277 278 /* Start the transfer by not inhibiting the transmitter any 279 * longer 280 */ 281 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & 282 ~XSPI_CR_TRANS_INHIBIT; 283 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 284 285 wait_for_completion(&xspi->done); 286 287 /* A transmit has just completed. Process received data and 288 * check for more data to transmit. Always inhibit the 289 * transmitter while the Isr refills the transmit register/FIFO, 290 * or make sure it is stopped if we're done. 291 */ 292 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); 293 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, 294 xspi->regs + XSPI_CR_OFFSET); 295 296 /* Read out all the data from the Rx FIFO */ 297 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 298 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { 299 xspi->rx_fn(xspi); 300 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 301 } 302 303 /* See if there is more data to send */ 304 if (xspi->remaining_bytes <= 0) 305 break; 306 } 307 308 /* Disable the transmit empty interrupt */ 309 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET); 310 311 return t->len - xspi->remaining_bytes; 312 } 313 314 315 /* This driver supports single master mode only. Hence Tx FIFO Empty 316 * is the only interrupt we care about. 317 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode 318 * Fault are not to happen. 319 */ 320 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) 321 { 322 struct xilinx_spi *xspi = dev_id; 323 u32 ipif_isr; 324 325 /* Get the IPIF interrupts, and clear them immediately */ 326 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); 327 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); 328 329 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ 330 complete(&xspi->done); 331 } 332 333 return IRQ_HANDLED; 334 } 335 336 static const struct of_device_id xilinx_spi_of_match[] = { 337 { .compatible = "xlnx,xps-spi-2.00.a", }, 338 { .compatible = "xlnx,xps-spi-2.00.b", }, 339 {} 340 }; 341 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); 342 343 struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem, 344 u32 irq, s16 bus_num, int num_cs, int bits_per_word) 345 { 346 struct spi_master *master; 347 struct xilinx_spi *xspi; 348 int ret; 349 u32 tmp; 350 351 master = spi_alloc_master(dev, sizeof(struct xilinx_spi)); 352 if (!master) 353 return NULL; 354 355 /* the spi->mode bits understood by this driver: */ 356 master->mode_bits = SPI_CPOL | SPI_CPHA; 357 358 xspi = spi_master_get_devdata(master); 359 xspi->bitbang.master = spi_master_get(master); 360 xspi->bitbang.chipselect = xilinx_spi_chipselect; 361 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; 362 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; 363 init_completion(&xspi->done); 364 365 if (!request_mem_region(mem->start, resource_size(mem), 366 XILINX_SPI_NAME)) 367 goto put_master; 368 369 xspi->regs = ioremap(mem->start, resource_size(mem)); 370 if (xspi->regs == NULL) { 371 dev_warn(dev, "ioremap failure\n"); 372 goto map_failed; 373 } 374 375 master->bus_num = bus_num; 376 master->num_chipselect = num_cs; 377 master->dev.of_node = dev->of_node; 378 379 xspi->mem = *mem; 380 xspi->irq = irq; 381 382 /* 383 * Detect endianess on the IP via loop bit in CR. Detection 384 * must be done before reset is sent because incorrect reset 385 * value generates error interrupt. 386 * Setup little endian helper functions first and try to use them 387 * and check if bit was correctly setup or not. 388 */ 389 xspi->read_fn = xspi_read32; 390 xspi->write_fn = xspi_write32; 391 392 xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); 393 tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); 394 tmp &= XSPI_CR_LOOP; 395 if (tmp != XSPI_CR_LOOP) { 396 xspi->read_fn = xspi_read32_be; 397 xspi->write_fn = xspi_write32_be; 398 } 399 400 xspi->bits_per_word = bits_per_word; 401 if (xspi->bits_per_word == 8) { 402 xspi->tx_fn = xspi_tx8; 403 xspi->rx_fn = xspi_rx8; 404 } else if (xspi->bits_per_word == 16) { 405 xspi->tx_fn = xspi_tx16; 406 xspi->rx_fn = xspi_rx16; 407 } else if (xspi->bits_per_word == 32) { 408 xspi->tx_fn = xspi_tx32; 409 xspi->rx_fn = xspi_rx32; 410 } else 411 goto unmap_io; 412 413 414 /* SPI controller initializations */ 415 xspi_init_hw(xspi); 416 417 /* Register for SPI Interrupt */ 418 ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi); 419 if (ret) 420 goto unmap_io; 421 422 ret = spi_bitbang_start(&xspi->bitbang); 423 if (ret) { 424 dev_err(dev, "spi_bitbang_start FAILED\n"); 425 goto free_irq; 426 } 427 428 dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", 429 (unsigned long long)mem->start, xspi->regs, xspi->irq); 430 return master; 431 432 free_irq: 433 free_irq(xspi->irq, xspi); 434 unmap_io: 435 iounmap(xspi->regs); 436 map_failed: 437 release_mem_region(mem->start, resource_size(mem)); 438 put_master: 439 spi_master_put(master); 440 return NULL; 441 } 442 EXPORT_SYMBOL(xilinx_spi_init); 443 444 void xilinx_spi_deinit(struct spi_master *master) 445 { 446 struct xilinx_spi *xspi; 447 448 xspi = spi_master_get_devdata(master); 449 450 spi_bitbang_stop(&xspi->bitbang); 451 free_irq(xspi->irq, xspi); 452 iounmap(xspi->regs); 453 454 release_mem_region(xspi->mem.start, resource_size(&xspi->mem)); 455 spi_master_put(xspi->bitbang.master); 456 } 457 EXPORT_SYMBOL(xilinx_spi_deinit); 458 459 static int xilinx_spi_probe(struct platform_device *dev) 460 { 461 struct xspi_platform_data *pdata; 462 struct resource *r; 463 int irq, num_cs = 0, bits_per_word = 8; 464 struct spi_master *master; 465 u8 i; 466 467 pdata = dev->dev.platform_data; 468 if (pdata) { 469 num_cs = pdata->num_chipselect; 470 bits_per_word = pdata->bits_per_word; 471 } 472 473 #ifdef CONFIG_OF 474 if (dev->dev.of_node) { 475 const __be32 *prop; 476 int len; 477 478 /* number of slave select bits is required */ 479 prop = of_get_property(dev->dev.of_node, "xlnx,num-ss-bits", 480 &len); 481 if (prop && len >= sizeof(*prop)) 482 num_cs = __be32_to_cpup(prop); 483 } 484 #endif 485 486 if (!num_cs) { 487 dev_err(&dev->dev, "Missing slave select configuration data\n"); 488 return -EINVAL; 489 } 490 491 492 r = platform_get_resource(dev, IORESOURCE_MEM, 0); 493 if (!r) 494 return -ENODEV; 495 496 irq = platform_get_irq(dev, 0); 497 if (irq < 0) 498 return -ENXIO; 499 500 master = xilinx_spi_init(&dev->dev, r, irq, dev->id, num_cs, 501 bits_per_word); 502 if (!master) 503 return -ENODEV; 504 505 if (pdata) { 506 for (i = 0; i < pdata->num_devices; i++) 507 spi_new_device(master, pdata->devices + i); 508 } 509 510 platform_set_drvdata(dev, master); 511 return 0; 512 } 513 514 static int xilinx_spi_remove(struct platform_device *dev) 515 { 516 xilinx_spi_deinit(platform_get_drvdata(dev)); 517 518 return 0; 519 } 520 521 /* work with hotplug and coldplug */ 522 MODULE_ALIAS("platform:" XILINX_SPI_NAME); 523 524 static struct platform_driver xilinx_spi_driver = { 525 .probe = xilinx_spi_probe, 526 .remove = xilinx_spi_remove, 527 .driver = { 528 .name = XILINX_SPI_NAME, 529 .owner = THIS_MODULE, 530 .of_match_table = xilinx_spi_of_match, 531 }, 532 }; 533 module_platform_driver(xilinx_spi_driver); 534 535 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); 536 MODULE_DESCRIPTION("Xilinx SPI driver"); 537 MODULE_LICENSE("GPL"); 538