1 /* 2 * Xilinx SPI controller driver (master mode only) 3 * 4 * Author: MontaVista Software, Inc. 5 * source@mvista.com 6 * 7 * Copyright (c) 2010 Secret Lab Technologies, Ltd. 8 * Copyright (c) 2009 Intel Corporation 9 * 2002-2007 (c) MontaVista Software, Inc. 10 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spi/spi_bitbang.h> 23 #include <linux/spi/xilinx_spi.h> 24 #include <linux/io.h> 25 26 #define XILINX_SPI_NAME "xilinx_spi" 27 28 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) 29 * Product Specification", DS464 30 */ 31 #define XSPI_CR_OFFSET 0x60 /* Control Register */ 32 33 #define XSPI_CR_ENABLE 0x02 34 #define XSPI_CR_MASTER_MODE 0x04 35 #define XSPI_CR_CPOL 0x08 36 #define XSPI_CR_CPHA 0x10 37 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL) 38 #define XSPI_CR_TXFIFO_RESET 0x20 39 #define XSPI_CR_RXFIFO_RESET 0x40 40 #define XSPI_CR_MANUAL_SSELECT 0x80 41 #define XSPI_CR_TRANS_INHIBIT 0x100 42 #define XSPI_CR_LSB_FIRST 0x200 43 44 #define XSPI_SR_OFFSET 0x64 /* Status Register */ 45 46 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ 47 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ 48 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ 49 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ 50 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ 51 52 #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ 53 #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ 54 55 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ 56 57 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 58 * IPIF registers are 32 bit 59 */ 60 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ 61 #define XIPIF_V123B_GINTR_ENABLE 0x80000000 62 63 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ 64 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ 65 66 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ 67 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while 68 * disabled */ 69 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ 70 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ 71 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ 72 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ 73 #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ 74 75 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ 76 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ 77 78 struct xilinx_spi { 79 /* bitbang has to be first */ 80 struct spi_bitbang bitbang; 81 struct completion done; 82 struct resource mem; /* phys mem */ 83 void __iomem *regs; /* virt. address of the control registers */ 84 85 u32 irq; 86 87 u8 *rx_ptr; /* pointer in the Tx buffer */ 88 const u8 *tx_ptr; /* pointer in the Rx buffer */ 89 int remaining_bytes; /* the number of bytes left to transfer */ 90 u8 bits_per_word; 91 unsigned int (*read_fn) (void __iomem *); 92 void (*write_fn) (u32, void __iomem *); 93 void (*tx_fn) (struct xilinx_spi *); 94 void (*rx_fn) (struct xilinx_spi *); 95 }; 96 97 static void xspi_write32(u32 val, void __iomem *addr) 98 { 99 iowrite32(val, addr); 100 } 101 102 static unsigned int xspi_read32(void __iomem *addr) 103 { 104 return ioread32(addr); 105 } 106 107 static void xspi_write32_be(u32 val, void __iomem *addr) 108 { 109 iowrite32be(val, addr); 110 } 111 112 static unsigned int xspi_read32_be(void __iomem *addr) 113 { 114 return ioread32be(addr); 115 } 116 117 static void xspi_tx8(struct xilinx_spi *xspi) 118 { 119 xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET); 120 xspi->tx_ptr++; 121 } 122 123 static void xspi_tx16(struct xilinx_spi *xspi) 124 { 125 xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); 126 xspi->tx_ptr += 2; 127 } 128 129 static void xspi_tx32(struct xilinx_spi *xspi) 130 { 131 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET); 132 xspi->tx_ptr += 4; 133 } 134 135 static void xspi_rx8(struct xilinx_spi *xspi) 136 { 137 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 138 if (xspi->rx_ptr) { 139 *xspi->rx_ptr = data & 0xff; 140 xspi->rx_ptr++; 141 } 142 } 143 144 static void xspi_rx16(struct xilinx_spi *xspi) 145 { 146 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 147 if (xspi->rx_ptr) { 148 *(u16 *)(xspi->rx_ptr) = data & 0xffff; 149 xspi->rx_ptr += 2; 150 } 151 } 152 153 static void xspi_rx32(struct xilinx_spi *xspi) 154 { 155 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); 156 if (xspi->rx_ptr) { 157 *(u32 *)(xspi->rx_ptr) = data; 158 xspi->rx_ptr += 4; 159 } 160 } 161 162 static void xspi_init_hw(struct xilinx_spi *xspi) 163 { 164 void __iomem *regs_base = xspi->regs; 165 166 /* Reset the SPI device */ 167 xspi->write_fn(XIPIF_V123B_RESET_MASK, 168 regs_base + XIPIF_V123B_RESETR_OFFSET); 169 /* Disable all the interrupts just in case */ 170 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); 171 /* Enable the global IPIF interrupt */ 172 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, 173 regs_base + XIPIF_V123B_DGIER_OFFSET); 174 /* Deselect the slave on the SPI bus */ 175 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); 176 /* Disable the transmitter, enable Manual Slave Select Assertion, 177 * put SPI controller into master mode, and enable it */ 178 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT | 179 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | 180 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET); 181 } 182 183 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) 184 { 185 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 186 187 if (is_on == BITBANG_CS_INACTIVE) { 188 /* Deselect the slave on the SPI bus */ 189 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET); 190 } else if (is_on == BITBANG_CS_ACTIVE) { 191 /* Set the SPI clock phase and polarity */ 192 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) 193 & ~XSPI_CR_MODE_MASK; 194 if (spi->mode & SPI_CPHA) 195 cr |= XSPI_CR_CPHA; 196 if (spi->mode & SPI_CPOL) 197 cr |= XSPI_CR_CPOL; 198 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 199 200 /* We do not check spi->max_speed_hz here as the SPI clock 201 * frequency is not software programmable (the IP block design 202 * parameter) 203 */ 204 205 /* Activate the chip select */ 206 xspi->write_fn(~(0x0001 << spi->chip_select), 207 xspi->regs + XSPI_SSR_OFFSET); 208 } 209 } 210 211 /* spi_bitbang requires custom setup_transfer() to be defined if there is a 212 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block 213 * supports 8 or 16 bits per word which cannot be changed in software. 214 * SPI clock can't be changed in software either. 215 * Check for correct bits per word. Chip select delay calculations could be 216 * added here as soon as bitbang_work() can be made aware of the delay value. 217 */ 218 static int xilinx_spi_setup_transfer(struct spi_device *spi, 219 struct spi_transfer *t) 220 { 221 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 222 u8 bits_per_word; 223 224 bits_per_word = (t && t->bits_per_word) 225 ? t->bits_per_word : spi->bits_per_word; 226 if (bits_per_word != xspi->bits_per_word) { 227 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", 228 __func__, bits_per_word); 229 return -EINVAL; 230 } 231 232 return 0; 233 } 234 235 static int xilinx_spi_setup(struct spi_device *spi) 236 { 237 /* always return 0, we can not check the number of bits. 238 * There are cases when SPI setup is called before any driver is 239 * there, in that case the SPI core defaults to 8 bits, which we 240 * do not support in some cases. But if we return an error, the 241 * SPI device would not be registered and no driver can get hold of it 242 * When the driver is there, it will call SPI setup again with the 243 * correct number of bits per transfer. 244 * If a driver setups with the wrong bit number, it will fail when 245 * it tries to do a transfer 246 */ 247 return 0; 248 } 249 250 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi) 251 { 252 u8 sr; 253 254 /* Fill the Tx FIFO with as many bytes as possible */ 255 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 256 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { 257 if (xspi->tx_ptr) 258 xspi->tx_fn(xspi); 259 else 260 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); 261 xspi->remaining_bytes -= xspi->bits_per_word / 8; 262 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 263 } 264 } 265 266 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) 267 { 268 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); 269 u32 ipif_ier; 270 u16 cr; 271 272 /* We get here with transmitter inhibited */ 273 274 xspi->tx_ptr = t->tx_buf; 275 xspi->rx_ptr = t->rx_buf; 276 xspi->remaining_bytes = t->len; 277 INIT_COMPLETION(xspi->done); 278 279 xilinx_spi_fill_tx_fifo(xspi); 280 281 /* Enable the transmit empty interrupt, which we use to determine 282 * progress on the transmission. 283 */ 284 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET); 285 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY, 286 xspi->regs + XIPIF_V123B_IIER_OFFSET); 287 288 /* Start the transfer by not inhibiting the transmitter any longer */ 289 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & 290 ~XSPI_CR_TRANS_INHIBIT; 291 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 292 293 wait_for_completion(&xspi->done); 294 295 /* Disable the transmit empty interrupt */ 296 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET); 297 298 return t->len - xspi->remaining_bytes; 299 } 300 301 302 /* This driver supports single master mode only. Hence Tx FIFO Empty 303 * is the only interrupt we care about. 304 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode 305 * Fault are not to happen. 306 */ 307 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) 308 { 309 struct xilinx_spi *xspi = dev_id; 310 u32 ipif_isr; 311 312 /* Get the IPIF interrupts, and clear them immediately */ 313 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); 314 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); 315 316 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ 317 u16 cr; 318 u8 sr; 319 320 /* A transmit has just completed. Process received data and 321 * check for more data to transmit. Always inhibit the 322 * transmitter while the Isr refills the transmit register/FIFO, 323 * or make sure it is stopped if we're done. 324 */ 325 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); 326 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, 327 xspi->regs + XSPI_CR_OFFSET); 328 329 /* Read out all the data from the Rx FIFO */ 330 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 331 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { 332 xspi->rx_fn(xspi); 333 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); 334 } 335 336 /* See if there is more data to send */ 337 if (xspi->remaining_bytes > 0) { 338 xilinx_spi_fill_tx_fifo(xspi); 339 /* Start the transfer by not inhibiting the 340 * transmitter any longer 341 */ 342 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); 343 } else { 344 /* No more data to send. 345 * Indicate the transfer is completed. 346 */ 347 complete(&xspi->done); 348 } 349 } 350 351 return IRQ_HANDLED; 352 } 353 354 static const struct of_device_id xilinx_spi_of_match[] = { 355 { .compatible = "xlnx,xps-spi-2.00.a", }, 356 { .compatible = "xlnx,xps-spi-2.00.b", }, 357 {} 358 }; 359 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); 360 361 struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem, 362 u32 irq, s16 bus_num, int num_cs, int little_endian, int bits_per_word) 363 { 364 struct spi_master *master; 365 struct xilinx_spi *xspi; 366 int ret; 367 368 master = spi_alloc_master(dev, sizeof(struct xilinx_spi)); 369 if (!master) 370 return NULL; 371 372 /* the spi->mode bits understood by this driver: */ 373 master->mode_bits = SPI_CPOL | SPI_CPHA; 374 375 xspi = spi_master_get_devdata(master); 376 xspi->bitbang.master = spi_master_get(master); 377 xspi->bitbang.chipselect = xilinx_spi_chipselect; 378 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; 379 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; 380 xspi->bitbang.master->setup = xilinx_spi_setup; 381 init_completion(&xspi->done); 382 383 if (!request_mem_region(mem->start, resource_size(mem), 384 XILINX_SPI_NAME)) 385 goto put_master; 386 387 xspi->regs = ioremap(mem->start, resource_size(mem)); 388 if (xspi->regs == NULL) { 389 dev_warn(dev, "ioremap failure\n"); 390 goto map_failed; 391 } 392 393 master->bus_num = bus_num; 394 master->num_chipselect = num_cs; 395 master->dev.of_node = dev->of_node; 396 397 xspi->mem = *mem; 398 xspi->irq = irq; 399 if (little_endian) { 400 xspi->read_fn = xspi_read32; 401 xspi->write_fn = xspi_write32; 402 } else { 403 xspi->read_fn = xspi_read32_be; 404 xspi->write_fn = xspi_write32_be; 405 } 406 xspi->bits_per_word = bits_per_word; 407 if (xspi->bits_per_word == 8) { 408 xspi->tx_fn = xspi_tx8; 409 xspi->rx_fn = xspi_rx8; 410 } else if (xspi->bits_per_word == 16) { 411 xspi->tx_fn = xspi_tx16; 412 xspi->rx_fn = xspi_rx16; 413 } else if (xspi->bits_per_word == 32) { 414 xspi->tx_fn = xspi_tx32; 415 xspi->rx_fn = xspi_rx32; 416 } else 417 goto unmap_io; 418 419 420 /* SPI controller initializations */ 421 xspi_init_hw(xspi); 422 423 /* Register for SPI Interrupt */ 424 ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi); 425 if (ret) 426 goto unmap_io; 427 428 ret = spi_bitbang_start(&xspi->bitbang); 429 if (ret) { 430 dev_err(dev, "spi_bitbang_start FAILED\n"); 431 goto free_irq; 432 } 433 434 dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", 435 (unsigned long long)mem->start, xspi->regs, xspi->irq); 436 return master; 437 438 free_irq: 439 free_irq(xspi->irq, xspi); 440 unmap_io: 441 iounmap(xspi->regs); 442 map_failed: 443 release_mem_region(mem->start, resource_size(mem)); 444 put_master: 445 spi_master_put(master); 446 return NULL; 447 } 448 EXPORT_SYMBOL(xilinx_spi_init); 449 450 void xilinx_spi_deinit(struct spi_master *master) 451 { 452 struct xilinx_spi *xspi; 453 454 xspi = spi_master_get_devdata(master); 455 456 spi_bitbang_stop(&xspi->bitbang); 457 free_irq(xspi->irq, xspi); 458 iounmap(xspi->regs); 459 460 release_mem_region(xspi->mem.start, resource_size(&xspi->mem)); 461 spi_master_put(xspi->bitbang.master); 462 } 463 EXPORT_SYMBOL(xilinx_spi_deinit); 464 465 static int xilinx_spi_probe(struct platform_device *dev) 466 { 467 struct xspi_platform_data *pdata; 468 struct resource *r; 469 int irq, num_cs = 0, little_endian = 0, bits_per_word = 8; 470 struct spi_master *master; 471 u8 i; 472 473 pdata = dev->dev.platform_data; 474 if (pdata) { 475 num_cs = pdata->num_chipselect; 476 little_endian = pdata->little_endian; 477 bits_per_word = pdata->bits_per_word; 478 } 479 480 #ifdef CONFIG_OF 481 if (dev->dev.of_node) { 482 const __be32 *prop; 483 int len; 484 485 /* number of slave select bits is required */ 486 prop = of_get_property(dev->dev.of_node, "xlnx,num-ss-bits", 487 &len); 488 if (prop && len >= sizeof(*prop)) 489 num_cs = __be32_to_cpup(prop); 490 } 491 #endif 492 493 if (!num_cs) { 494 dev_err(&dev->dev, "Missing slave select configuration data\n"); 495 return -EINVAL; 496 } 497 498 499 r = platform_get_resource(dev, IORESOURCE_MEM, 0); 500 if (!r) 501 return -ENODEV; 502 503 irq = platform_get_irq(dev, 0); 504 if (irq < 0) 505 return -ENXIO; 506 507 master = xilinx_spi_init(&dev->dev, r, irq, dev->id, num_cs, 508 little_endian, bits_per_word); 509 if (!master) 510 return -ENODEV; 511 512 if (pdata) { 513 for (i = 0; i < pdata->num_devices; i++) 514 spi_new_device(master, pdata->devices + i); 515 } 516 517 platform_set_drvdata(dev, master); 518 return 0; 519 } 520 521 static int xilinx_spi_remove(struct platform_device *dev) 522 { 523 xilinx_spi_deinit(platform_get_drvdata(dev)); 524 platform_set_drvdata(dev, 0); 525 526 return 0; 527 } 528 529 /* work with hotplug and coldplug */ 530 MODULE_ALIAS("platform:" XILINX_SPI_NAME); 531 532 static struct platform_driver xilinx_spi_driver = { 533 .probe = xilinx_spi_probe, 534 .remove = xilinx_spi_remove, 535 .driver = { 536 .name = XILINX_SPI_NAME, 537 .owner = THIS_MODULE, 538 .of_match_table = xilinx_spi_of_match, 539 }, 540 }; 541 module_platform_driver(xilinx_spi_driver); 542 543 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); 544 MODULE_DESCRIPTION("Xilinx SPI driver"); 545 MODULE_LICENSE("GPL"); 546