1 /*
2  * SPI bus driver for the Topcliff PCH used by Intel SoCs
3  *
4  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
18  */
19 
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/wait.h>
23 #include <linux/spi/spi.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/spi/spidev.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 
31 #include <linux/dmaengine.h>
32 #include <linux/pch_dma.h>
33 
34 /* Register offsets */
35 #define PCH_SPCR		0x00	/* SPI control register */
36 #define PCH_SPBRR		0x04	/* SPI baud rate register */
37 #define PCH_SPSR		0x08	/* SPI status register */
38 #define PCH_SPDWR		0x0C	/* SPI write data register */
39 #define PCH_SPDRR		0x10	/* SPI read data register */
40 #define PCH_SSNXCR		0x18	/* SSN Expand Control Register */
41 #define PCH_SRST		0x1C	/* SPI reset register */
42 #define PCH_ADDRESS_SIZE	0x20
43 
44 #define PCH_SPSR_TFD		0x000007C0
45 #define PCH_SPSR_RFD		0x0000F800
46 
47 #define PCH_READABLE(x)		(((x) & PCH_SPSR_RFD)>>11)
48 #define PCH_WRITABLE(x)		(((x) & PCH_SPSR_TFD)>>6)
49 
50 #define PCH_RX_THOLD		7
51 #define PCH_RX_THOLD_MAX	15
52 
53 #define PCH_TX_THOLD		2
54 
55 #define PCH_MAX_BAUDRATE	5000000
56 #define PCH_MAX_FIFO_DEPTH	16
57 
58 #define STATUS_RUNNING		1
59 #define STATUS_EXITING		2
60 #define PCH_SLEEP_TIME		10
61 
62 #define SSN_LOW			0x02U
63 #define SSN_HIGH		0x03U
64 #define SSN_NO_CONTROL		0x00U
65 #define PCH_MAX_CS		0xFF
66 #define PCI_DEVICE_ID_GE_SPI	0x8816
67 
68 #define SPCR_SPE_BIT		(1 << 0)
69 #define SPCR_MSTR_BIT		(1 << 1)
70 #define SPCR_LSBF_BIT		(1 << 4)
71 #define SPCR_CPHA_BIT		(1 << 5)
72 #define SPCR_CPOL_BIT		(1 << 6)
73 #define SPCR_TFIE_BIT		(1 << 8)
74 #define SPCR_RFIE_BIT		(1 << 9)
75 #define SPCR_FIE_BIT		(1 << 10)
76 #define SPCR_ORIE_BIT		(1 << 11)
77 #define SPCR_MDFIE_BIT		(1 << 12)
78 #define SPCR_FICLR_BIT		(1 << 24)
79 #define SPSR_TFI_BIT		(1 << 0)
80 #define SPSR_RFI_BIT		(1 << 1)
81 #define SPSR_FI_BIT		(1 << 2)
82 #define SPSR_ORF_BIT		(1 << 3)
83 #define SPBRR_SIZE_BIT		(1 << 10)
84 
85 #define PCH_ALL			(SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
86 				SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
87 
88 #define SPCR_RFIC_FIELD		20
89 #define SPCR_TFIC_FIELD		16
90 
91 #define MASK_SPBRR_SPBR_BITS	((1 << 10) - 1)
92 #define MASK_RFIC_SPCR_BITS	(0xf << SPCR_RFIC_FIELD)
93 #define MASK_TFIC_SPCR_BITS	(0xf << SPCR_TFIC_FIELD)
94 
95 #define PCH_CLOCK_HZ		50000000
96 #define PCH_MAX_SPBR		1023
97 
98 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
99 #define PCI_VENDOR_ID_ROHM		0x10DB
100 #define PCI_DEVICE_ID_ML7213_SPI	0x802c
101 #define PCI_DEVICE_ID_ML7223_SPI	0x800F
102 #define PCI_DEVICE_ID_ML7831_SPI	0x8816
103 
104 /*
105  * Set the number of SPI instance max
106  * Intel EG20T PCH :		1ch
107  * LAPIS Semiconductor ML7213 IOH :	2ch
108  * LAPIS Semiconductor ML7223 IOH :	1ch
109  * LAPIS Semiconductor ML7831 IOH :	1ch
110 */
111 #define PCH_SPI_MAX_DEV			2
112 
113 #define PCH_BUF_SIZE		4096
114 #define PCH_DMA_TRANS_SIZE	12
115 
116 static int use_dma = 1;
117 
118 struct pch_spi_dma_ctrl {
119 	struct dma_async_tx_descriptor	*desc_tx;
120 	struct dma_async_tx_descriptor	*desc_rx;
121 	struct pch_dma_slave		param_tx;
122 	struct pch_dma_slave		param_rx;
123 	struct dma_chan		*chan_tx;
124 	struct dma_chan		*chan_rx;
125 	struct scatterlist		*sg_tx_p;
126 	struct scatterlist		*sg_rx_p;
127 	struct scatterlist		sg_tx;
128 	struct scatterlist		sg_rx;
129 	int				nent;
130 	void				*tx_buf_virt;
131 	void				*rx_buf_virt;
132 	dma_addr_t			tx_buf_dma;
133 	dma_addr_t			rx_buf_dma;
134 };
135 /**
136  * struct pch_spi_data - Holds the SPI channel specific details
137  * @io_remap_addr:		The remapped PCI base address
138  * @master:			Pointer to the SPI master structure
139  * @work:			Reference to work queue handler
140  * @wk:				Workqueue for carrying out execution of the
141  *				requests
142  * @wait:			Wait queue for waking up upon receiving an
143  *				interrupt.
144  * @transfer_complete:		Status of SPI Transfer
145  * @bcurrent_msg_processing:	Status flag for message processing
146  * @lock:			Lock for protecting this structure
147  * @queue:			SPI Message queue
148  * @status:			Status of the SPI driver
149  * @bpw_len:			Length of data to be transferred in bits per
150  *				word
151  * @transfer_active:		Flag showing active transfer
152  * @tx_index:			Transmit data count; for bookkeeping during
153  *				transfer
154  * @rx_index:			Receive data count; for bookkeeping during
155  *				transfer
156  * @tx_buff:			Buffer for data to be transmitted
157  * @rx_index:			Buffer for Received data
158  * @n_curnt_chip:		The chip number that this SPI driver currently
159  *				operates on
160  * @current_chip:		Reference to the current chip that this SPI
161  *				driver currently operates on
162  * @current_msg:		The current message that this SPI driver is
163  *				handling
164  * @cur_trans:			The current transfer that this SPI driver is
165  *				handling
166  * @board_dat:			Reference to the SPI device data structure
167  * @plat_dev:			platform_device structure
168  * @ch:				SPI channel number
169  * @irq_reg_sts:		Status of IRQ registration
170  */
171 struct pch_spi_data {
172 	void __iomem *io_remap_addr;
173 	unsigned long io_base_addr;
174 	struct spi_master *master;
175 	struct work_struct work;
176 	struct workqueue_struct *wk;
177 	wait_queue_head_t wait;
178 	u8 transfer_complete;
179 	u8 bcurrent_msg_processing;
180 	spinlock_t lock;
181 	struct list_head queue;
182 	u8 status;
183 	u32 bpw_len;
184 	u8 transfer_active;
185 	u32 tx_index;
186 	u32 rx_index;
187 	u16 *pkt_tx_buff;
188 	u16 *pkt_rx_buff;
189 	u8 n_curnt_chip;
190 	struct spi_device *current_chip;
191 	struct spi_message *current_msg;
192 	struct spi_transfer *cur_trans;
193 	struct pch_spi_board_data *board_dat;
194 	struct platform_device	*plat_dev;
195 	int ch;
196 	struct pch_spi_dma_ctrl dma;
197 	int use_dma;
198 	u8 irq_reg_sts;
199 	int save_total_len;
200 };
201 
202 /**
203  * struct pch_spi_board_data - Holds the SPI device specific details
204  * @pdev:		Pointer to the PCI device
205  * @suspend_sts:	Status of suspend
206  * @num:		The number of SPI device instance
207  */
208 struct pch_spi_board_data {
209 	struct pci_dev *pdev;
210 	u8 suspend_sts;
211 	int num;
212 };
213 
214 struct pch_pd_dev_save {
215 	int num;
216 	struct platform_device *pd_save[PCH_SPI_MAX_DEV];
217 	struct pch_spi_board_data *board_dat;
218 };
219 
220 static const struct pci_device_id pch_spi_pcidev_id[] = {
221 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),    1, },
222 	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
223 	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
224 	{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
225 	{ }
226 };
227 
228 /**
229  * pch_spi_writereg() - Performs  register writes
230  * @master:	Pointer to struct spi_master.
231  * @idx:	Register offset.
232  * @val:	Value to be written to register.
233  */
234 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
235 {
236 	struct pch_spi_data *data = spi_master_get_devdata(master);
237 	iowrite32(val, (data->io_remap_addr + idx));
238 }
239 
240 /**
241  * pch_spi_readreg() - Performs register reads
242  * @master:	Pointer to struct spi_master.
243  * @idx:	Register offset.
244  */
245 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
246 {
247 	struct pch_spi_data *data = spi_master_get_devdata(master);
248 	return ioread32(data->io_remap_addr + idx);
249 }
250 
251 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
252 				      u32 set, u32 clr)
253 {
254 	u32 tmp = pch_spi_readreg(master, idx);
255 	tmp = (tmp & ~clr) | set;
256 	pch_spi_writereg(master, idx, tmp);
257 }
258 
259 static void pch_spi_set_master_mode(struct spi_master *master)
260 {
261 	pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
262 }
263 
264 /**
265  * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
266  * @master:	Pointer to struct spi_master.
267  */
268 static void pch_spi_clear_fifo(struct spi_master *master)
269 {
270 	pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
271 	pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
272 }
273 
274 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
275 				void __iomem *io_remap_addr)
276 {
277 	u32 n_read, tx_index, rx_index, bpw_len;
278 	u16 *pkt_rx_buffer, *pkt_tx_buff;
279 	int read_cnt;
280 	u32 reg_spcr_val;
281 	void __iomem *spsr;
282 	void __iomem *spdrr;
283 	void __iomem *spdwr;
284 
285 	spsr = io_remap_addr + PCH_SPSR;
286 	iowrite32(reg_spsr_val, spsr);
287 
288 	if (data->transfer_active) {
289 		rx_index = data->rx_index;
290 		tx_index = data->tx_index;
291 		bpw_len = data->bpw_len;
292 		pkt_rx_buffer = data->pkt_rx_buff;
293 		pkt_tx_buff = data->pkt_tx_buff;
294 
295 		spdrr = io_remap_addr + PCH_SPDRR;
296 		spdwr = io_remap_addr + PCH_SPDWR;
297 
298 		n_read = PCH_READABLE(reg_spsr_val);
299 
300 		for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
301 			pkt_rx_buffer[rx_index++] = ioread32(spdrr);
302 			if (tx_index < bpw_len)
303 				iowrite32(pkt_tx_buff[tx_index++], spdwr);
304 		}
305 
306 		/* disable RFI if not needed */
307 		if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
308 			reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
309 			reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
310 
311 			/* reset rx threshold */
312 			reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
313 			reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
314 
315 			iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
316 		}
317 
318 		/* update counts */
319 		data->tx_index = tx_index;
320 		data->rx_index = rx_index;
321 
322 		/* if transfer complete interrupt */
323 		if (reg_spsr_val & SPSR_FI_BIT) {
324 			if ((tx_index == bpw_len) && (rx_index == tx_index)) {
325 				/* disable interrupts */
326 				pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
327 						   PCH_ALL);
328 
329 				/* transfer is completed;
330 				   inform pch_spi_process_messages */
331 				data->transfer_complete = true;
332 				data->transfer_active = false;
333 				wake_up(&data->wait);
334 			} else {
335 				dev_vdbg(&data->master->dev,
336 					"%s : Transfer is not completed",
337 					__func__);
338 			}
339 		}
340 	}
341 }
342 
343 /**
344  * pch_spi_handler() - Interrupt handler
345  * @irq:	The interrupt number.
346  * @dev_id:	Pointer to struct pch_spi_board_data.
347  */
348 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
349 {
350 	u32 reg_spsr_val;
351 	void __iomem *spsr;
352 	void __iomem *io_remap_addr;
353 	irqreturn_t ret = IRQ_NONE;
354 	struct pch_spi_data *data = dev_id;
355 	struct pch_spi_board_data *board_dat = data->board_dat;
356 
357 	if (board_dat->suspend_sts) {
358 		dev_dbg(&board_dat->pdev->dev,
359 			"%s returning due to suspend\n", __func__);
360 		return IRQ_NONE;
361 	}
362 
363 	io_remap_addr = data->io_remap_addr;
364 	spsr = io_remap_addr + PCH_SPSR;
365 
366 	reg_spsr_val = ioread32(spsr);
367 
368 	if (reg_spsr_val & SPSR_ORF_BIT) {
369 		dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
370 		if (data->current_msg->complete) {
371 			data->transfer_complete = true;
372 			data->current_msg->status = -EIO;
373 			data->current_msg->complete(data->current_msg->context);
374 			data->bcurrent_msg_processing = false;
375 			data->current_msg = NULL;
376 			data->cur_trans = NULL;
377 		}
378 	}
379 
380 	if (data->use_dma)
381 		return IRQ_NONE;
382 
383 	/* Check if the interrupt is for SPI device */
384 	if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
385 		pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
386 		ret = IRQ_HANDLED;
387 	}
388 
389 	dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
390 		__func__, ret);
391 
392 	return ret;
393 }
394 
395 /**
396  * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
397  * @master:	Pointer to struct spi_master.
398  * @speed_hz:	Baud rate.
399  */
400 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
401 {
402 	u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
403 
404 	/* if baud rate is less than we can support limit it */
405 	if (n_spbr > PCH_MAX_SPBR)
406 		n_spbr = PCH_MAX_SPBR;
407 
408 	pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
409 }
410 
411 /**
412  * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
413  * @master:		Pointer to struct spi_master.
414  * @bits_per_word:	Bits per word for SPI transfer.
415  */
416 static void pch_spi_set_bits_per_word(struct spi_master *master,
417 				      u8 bits_per_word)
418 {
419 	if (bits_per_word == 8)
420 		pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
421 	else
422 		pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
423 }
424 
425 /**
426  * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
427  * @spi:	Pointer to struct spi_device.
428  */
429 static void pch_spi_setup_transfer(struct spi_device *spi)
430 {
431 	u32 flags = 0;
432 
433 	dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
434 		__func__, pch_spi_readreg(spi->master, PCH_SPBRR),
435 		spi->max_speed_hz);
436 	pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
437 
438 	/* set bits per word */
439 	pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
440 
441 	if (!(spi->mode & SPI_LSB_FIRST))
442 		flags |= SPCR_LSBF_BIT;
443 	if (spi->mode & SPI_CPOL)
444 		flags |= SPCR_CPOL_BIT;
445 	if (spi->mode & SPI_CPHA)
446 		flags |= SPCR_CPHA_BIT;
447 	pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
448 			   (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
449 
450 	/* Clear the FIFO by toggling  FICLR to 1 and back to 0 */
451 	pch_spi_clear_fifo(spi->master);
452 }
453 
454 /**
455  * pch_spi_reset() - Clears SPI registers
456  * @master:	Pointer to struct spi_master.
457  */
458 static void pch_spi_reset(struct spi_master *master)
459 {
460 	/* write 1 to reset SPI */
461 	pch_spi_writereg(master, PCH_SRST, 0x1);
462 
463 	/* clear reset */
464 	pch_spi_writereg(master, PCH_SRST, 0x0);
465 }
466 
467 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
468 {
469 
470 	struct spi_transfer *transfer;
471 	struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
472 	int retval;
473 	unsigned long flags;
474 
475 	spin_lock_irqsave(&data->lock, flags);
476 	/* validate Tx/Rx buffers and Transfer length */
477 	list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
478 		if (!transfer->tx_buf && !transfer->rx_buf) {
479 			dev_err(&pspi->dev,
480 				"%s Tx and Rx buffer NULL\n", __func__);
481 			retval = -EINVAL;
482 			goto err_return_spinlock;
483 		}
484 
485 		if (!transfer->len) {
486 			dev_err(&pspi->dev, "%s Transfer length invalid\n",
487 				__func__);
488 			retval = -EINVAL;
489 			goto err_return_spinlock;
490 		}
491 
492 		dev_dbg(&pspi->dev,
493 			"%s Tx/Rx buffer valid. Transfer length valid\n",
494 			__func__);
495 	}
496 	spin_unlock_irqrestore(&data->lock, flags);
497 
498 	/* We won't process any messages if we have been asked to terminate */
499 	if (data->status == STATUS_EXITING) {
500 		dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
501 		retval = -ESHUTDOWN;
502 		goto err_out;
503 	}
504 
505 	/* If suspended ,return -EINVAL */
506 	if (data->board_dat->suspend_sts) {
507 		dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
508 		retval = -EINVAL;
509 		goto err_out;
510 	}
511 
512 	/* set status of message */
513 	pmsg->actual_length = 0;
514 	dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
515 
516 	pmsg->status = -EINPROGRESS;
517 	spin_lock_irqsave(&data->lock, flags);
518 	/* add message to queue */
519 	list_add_tail(&pmsg->queue, &data->queue);
520 	spin_unlock_irqrestore(&data->lock, flags);
521 
522 	dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
523 
524 	/* schedule work queue to run */
525 	queue_work(data->wk, &data->work);
526 	dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
527 
528 	retval = 0;
529 
530 err_out:
531 	dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
532 	return retval;
533 err_return_spinlock:
534 	dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
535 	spin_unlock_irqrestore(&data->lock, flags);
536 	return retval;
537 }
538 
539 static inline void pch_spi_select_chip(struct pch_spi_data *data,
540 				       struct spi_device *pspi)
541 {
542 	if (data->current_chip != NULL) {
543 		if (pspi->chip_select != data->n_curnt_chip) {
544 			dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
545 			data->current_chip = NULL;
546 		}
547 	}
548 
549 	data->current_chip = pspi;
550 
551 	data->n_curnt_chip = data->current_chip->chip_select;
552 
553 	dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
554 	pch_spi_setup_transfer(pspi);
555 }
556 
557 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
558 {
559 	int size;
560 	u32 n_writes;
561 	int j;
562 	struct spi_message *pmsg, *tmp;
563 	const u8 *tx_buf;
564 	const u16 *tx_sbuf;
565 
566 	/* set baud rate if needed */
567 	if (data->cur_trans->speed_hz) {
568 		dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
569 		pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
570 	}
571 
572 	/* set bits per word if needed */
573 	if (data->cur_trans->bits_per_word &&
574 	    (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
575 		dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
576 		pch_spi_set_bits_per_word(data->master,
577 					  data->cur_trans->bits_per_word);
578 		*bpw = data->cur_trans->bits_per_word;
579 	} else {
580 		*bpw = data->current_msg->spi->bits_per_word;
581 	}
582 
583 	/* reset Tx/Rx index */
584 	data->tx_index = 0;
585 	data->rx_index = 0;
586 
587 	data->bpw_len = data->cur_trans->len / (*bpw / 8);
588 
589 	/* find alloc size */
590 	size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
591 
592 	/* allocate memory for pkt_tx_buff & pkt_rx_buffer */
593 	data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
594 	if (data->pkt_tx_buff != NULL) {
595 		data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
596 		if (!data->pkt_rx_buff)
597 			kfree(data->pkt_tx_buff);
598 	}
599 
600 	if (!data->pkt_rx_buff) {
601 		/* flush queue and set status of all transfers to -ENOMEM */
602 		dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
603 		list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
604 			pmsg->status = -ENOMEM;
605 
606 			if (pmsg->complete)
607 				pmsg->complete(pmsg->context);
608 
609 			/* delete from queue */
610 			list_del_init(&pmsg->queue);
611 		}
612 		return;
613 	}
614 
615 	/* copy Tx Data */
616 	if (data->cur_trans->tx_buf != NULL) {
617 		if (*bpw == 8) {
618 			tx_buf = data->cur_trans->tx_buf;
619 			for (j = 0; j < data->bpw_len; j++)
620 				data->pkt_tx_buff[j] = *tx_buf++;
621 		} else {
622 			tx_sbuf = data->cur_trans->tx_buf;
623 			for (j = 0; j < data->bpw_len; j++)
624 				data->pkt_tx_buff[j] = *tx_sbuf++;
625 		}
626 	}
627 
628 	/* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
629 	n_writes = data->bpw_len;
630 	if (n_writes > PCH_MAX_FIFO_DEPTH)
631 		n_writes = PCH_MAX_FIFO_DEPTH;
632 
633 	dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
634 		"0x2 to SSNXCR\n", __func__);
635 	pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
636 
637 	for (j = 0; j < n_writes; j++)
638 		pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
639 
640 	/* update tx_index */
641 	data->tx_index = j;
642 
643 	/* reset transfer complete flag */
644 	data->transfer_complete = false;
645 	data->transfer_active = true;
646 }
647 
648 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
649 {
650 	struct spi_message *pmsg, *tmp;
651 	dev_dbg(&data->master->dev, "%s called\n", __func__);
652 	/* Invoke complete callback
653 	 * [To the spi core..indicating end of transfer] */
654 	data->current_msg->status = 0;
655 
656 	if (data->current_msg->complete) {
657 		dev_dbg(&data->master->dev,
658 			"%s:Invoking callback of SPI core\n", __func__);
659 		data->current_msg->complete(data->current_msg->context);
660 	}
661 
662 	/* update status in global variable */
663 	data->bcurrent_msg_processing = false;
664 
665 	dev_dbg(&data->master->dev,
666 		"%s:data->bcurrent_msg_processing = false\n", __func__);
667 
668 	data->current_msg = NULL;
669 	data->cur_trans = NULL;
670 
671 	/* check if we have items in list and not suspending
672 	 * return 1 if list empty */
673 	if ((list_empty(&data->queue) == 0) &&
674 	    (!data->board_dat->suspend_sts) &&
675 	    (data->status != STATUS_EXITING)) {
676 		/* We have some more work to do (either there is more tranint
677 		 * bpw;sfer requests in the current message or there are
678 		 *more messages)
679 		 */
680 		dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
681 		queue_work(data->wk, &data->work);
682 	} else if (data->board_dat->suspend_sts ||
683 		   data->status == STATUS_EXITING) {
684 		dev_dbg(&data->master->dev,
685 			"%s suspend/remove initiated, flushing queue\n",
686 			__func__);
687 		list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
688 			pmsg->status = -EIO;
689 
690 			if (pmsg->complete)
691 				pmsg->complete(pmsg->context);
692 
693 			/* delete from queue */
694 			list_del_init(&pmsg->queue);
695 		}
696 	}
697 }
698 
699 static void pch_spi_set_ir(struct pch_spi_data *data)
700 {
701 	/* enable interrupts, set threshold, enable SPI */
702 	if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
703 		/* set receive threshold to PCH_RX_THOLD */
704 		pch_spi_setclr_reg(data->master, PCH_SPCR,
705 				   PCH_RX_THOLD << SPCR_RFIC_FIELD |
706 				   SPCR_FIE_BIT | SPCR_RFIE_BIT |
707 				   SPCR_ORIE_BIT | SPCR_SPE_BIT,
708 				   MASK_RFIC_SPCR_BITS | PCH_ALL);
709 	else
710 		/* set receive threshold to maximum */
711 		pch_spi_setclr_reg(data->master, PCH_SPCR,
712 				   PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
713 				   SPCR_FIE_BIT | SPCR_ORIE_BIT |
714 				   SPCR_SPE_BIT,
715 				   MASK_RFIC_SPCR_BITS | PCH_ALL);
716 
717 	/* Wait until the transfer completes; go to sleep after
718 				 initiating the transfer. */
719 	dev_dbg(&data->master->dev,
720 		"%s:waiting for transfer to get over\n", __func__);
721 
722 	wait_event_interruptible(data->wait, data->transfer_complete);
723 
724 	/* clear all interrupts */
725 	pch_spi_writereg(data->master, PCH_SPSR,
726 			 pch_spi_readreg(data->master, PCH_SPSR));
727 	/* Disable interrupts and SPI transfer */
728 	pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
729 	/* clear FIFO */
730 	pch_spi_clear_fifo(data->master);
731 }
732 
733 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
734 {
735 	int j;
736 	u8 *rx_buf;
737 	u16 *rx_sbuf;
738 
739 	/* copy Rx Data */
740 	if (!data->cur_trans->rx_buf)
741 		return;
742 
743 	if (bpw == 8) {
744 		rx_buf = data->cur_trans->rx_buf;
745 		for (j = 0; j < data->bpw_len; j++)
746 			*rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
747 	} else {
748 		rx_sbuf = data->cur_trans->rx_buf;
749 		for (j = 0; j < data->bpw_len; j++)
750 			*rx_sbuf++ = data->pkt_rx_buff[j];
751 	}
752 }
753 
754 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
755 {
756 	int j;
757 	u8 *rx_buf;
758 	u16 *rx_sbuf;
759 	const u8 *rx_dma_buf;
760 	const u16 *rx_dma_sbuf;
761 
762 	/* copy Rx Data */
763 	if (!data->cur_trans->rx_buf)
764 		return;
765 
766 	if (bpw == 8) {
767 		rx_buf = data->cur_trans->rx_buf;
768 		rx_dma_buf = data->dma.rx_buf_virt;
769 		for (j = 0; j < data->bpw_len; j++)
770 			*rx_buf++ = *rx_dma_buf++ & 0xFF;
771 		data->cur_trans->rx_buf = rx_buf;
772 	} else {
773 		rx_sbuf = data->cur_trans->rx_buf;
774 		rx_dma_sbuf = data->dma.rx_buf_virt;
775 		for (j = 0; j < data->bpw_len; j++)
776 			*rx_sbuf++ = *rx_dma_sbuf++;
777 		data->cur_trans->rx_buf = rx_sbuf;
778 	}
779 }
780 
781 static int pch_spi_start_transfer(struct pch_spi_data *data)
782 {
783 	struct pch_spi_dma_ctrl *dma;
784 	unsigned long flags;
785 	int rtn;
786 
787 	dma = &data->dma;
788 
789 	spin_lock_irqsave(&data->lock, flags);
790 
791 	/* disable interrupts, SPI set enable */
792 	pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
793 
794 	spin_unlock_irqrestore(&data->lock, flags);
795 
796 	/* Wait until the transfer completes; go to sleep after
797 				 initiating the transfer. */
798 	dev_dbg(&data->master->dev,
799 		"%s:waiting for transfer to get over\n", __func__);
800 	rtn = wait_event_interruptible_timeout(data->wait,
801 					       data->transfer_complete,
802 					       msecs_to_jiffies(2 * HZ));
803 	if (!rtn)
804 		dev_err(&data->master->dev,
805 			"%s wait-event timeout\n", __func__);
806 
807 	dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
808 			    DMA_FROM_DEVICE);
809 
810 	dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
811 			    DMA_FROM_DEVICE);
812 	memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
813 
814 	async_tx_ack(dma->desc_rx);
815 	async_tx_ack(dma->desc_tx);
816 	kfree(dma->sg_tx_p);
817 	kfree(dma->sg_rx_p);
818 
819 	spin_lock_irqsave(&data->lock, flags);
820 
821 	/* clear fifo threshold, disable interrupts, disable SPI transfer */
822 	pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
823 			   MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
824 			   SPCR_SPE_BIT);
825 	/* clear all interrupts */
826 	pch_spi_writereg(data->master, PCH_SPSR,
827 			 pch_spi_readreg(data->master, PCH_SPSR));
828 	/* clear FIFO */
829 	pch_spi_clear_fifo(data->master);
830 
831 	spin_unlock_irqrestore(&data->lock, flags);
832 
833 	return rtn;
834 }
835 
836 static void pch_dma_rx_complete(void *arg)
837 {
838 	struct pch_spi_data *data = arg;
839 
840 	/* transfer is completed;inform pch_spi_process_messages_dma */
841 	data->transfer_complete = true;
842 	wake_up_interruptible(&data->wait);
843 }
844 
845 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
846 {
847 	struct pch_dma_slave *param = slave;
848 
849 	if ((chan->chan_id == param->chan_id) &&
850 	    (param->dma_dev == chan->device->dev)) {
851 		chan->private = param;
852 		return true;
853 	} else {
854 		return false;
855 	}
856 }
857 
858 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
859 {
860 	dma_cap_mask_t mask;
861 	struct dma_chan *chan;
862 	struct pci_dev *dma_dev;
863 	struct pch_dma_slave *param;
864 	struct pch_spi_dma_ctrl *dma;
865 	unsigned int width;
866 
867 	if (bpw == 8)
868 		width = PCH_DMA_WIDTH_1_BYTE;
869 	else
870 		width = PCH_DMA_WIDTH_2_BYTES;
871 
872 	dma = &data->dma;
873 	dma_cap_zero(mask);
874 	dma_cap_set(DMA_SLAVE, mask);
875 
876 	/* Get DMA's dev information */
877 	dma_dev = pci_get_slot(data->board_dat->pdev->bus,
878 			PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
879 
880 	/* Set Tx DMA */
881 	param = &dma->param_tx;
882 	param->dma_dev = &dma_dev->dev;
883 	param->chan_id = data->ch * 2; /* Tx = 0, 2 */;
884 	param->tx_reg = data->io_base_addr + PCH_SPDWR;
885 	param->width = width;
886 	chan = dma_request_channel(mask, pch_spi_filter, param);
887 	if (!chan) {
888 		dev_err(&data->master->dev,
889 			"ERROR: dma_request_channel FAILS(Tx)\n");
890 		data->use_dma = 0;
891 		return;
892 	}
893 	dma->chan_tx = chan;
894 
895 	/* Set Rx DMA */
896 	param = &dma->param_rx;
897 	param->dma_dev = &dma_dev->dev;
898 	param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */;
899 	param->rx_reg = data->io_base_addr + PCH_SPDRR;
900 	param->width = width;
901 	chan = dma_request_channel(mask, pch_spi_filter, param);
902 	if (!chan) {
903 		dev_err(&data->master->dev,
904 			"ERROR: dma_request_channel FAILS(Rx)\n");
905 		dma_release_channel(dma->chan_tx);
906 		dma->chan_tx = NULL;
907 		data->use_dma = 0;
908 		return;
909 	}
910 	dma->chan_rx = chan;
911 }
912 
913 static void pch_spi_release_dma(struct pch_spi_data *data)
914 {
915 	struct pch_spi_dma_ctrl *dma;
916 
917 	dma = &data->dma;
918 	if (dma->chan_tx) {
919 		dma_release_channel(dma->chan_tx);
920 		dma->chan_tx = NULL;
921 	}
922 	if (dma->chan_rx) {
923 		dma_release_channel(dma->chan_rx);
924 		dma->chan_rx = NULL;
925 	}
926 	return;
927 }
928 
929 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
930 {
931 	const u8 *tx_buf;
932 	const u16 *tx_sbuf;
933 	u8 *tx_dma_buf;
934 	u16 *tx_dma_sbuf;
935 	struct scatterlist *sg;
936 	struct dma_async_tx_descriptor *desc_tx;
937 	struct dma_async_tx_descriptor *desc_rx;
938 	int num;
939 	int i;
940 	int size;
941 	int rem;
942 	int head;
943 	unsigned long flags;
944 	struct pch_spi_dma_ctrl *dma;
945 
946 	dma = &data->dma;
947 
948 	/* set baud rate if needed */
949 	if (data->cur_trans->speed_hz) {
950 		dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
951 		spin_lock_irqsave(&data->lock, flags);
952 		pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
953 		spin_unlock_irqrestore(&data->lock, flags);
954 	}
955 
956 	/* set bits per word if needed */
957 	if (data->cur_trans->bits_per_word &&
958 	    (data->current_msg->spi->bits_per_word !=
959 	     data->cur_trans->bits_per_word)) {
960 		dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
961 		spin_lock_irqsave(&data->lock, flags);
962 		pch_spi_set_bits_per_word(data->master,
963 					  data->cur_trans->bits_per_word);
964 		spin_unlock_irqrestore(&data->lock, flags);
965 		*bpw = data->cur_trans->bits_per_word;
966 	} else {
967 		*bpw = data->current_msg->spi->bits_per_word;
968 	}
969 	data->bpw_len = data->cur_trans->len / (*bpw / 8);
970 
971 	if (data->bpw_len > PCH_BUF_SIZE) {
972 		data->bpw_len = PCH_BUF_SIZE;
973 		data->cur_trans->len -= PCH_BUF_SIZE;
974 	}
975 
976 	/* copy Tx Data */
977 	if (data->cur_trans->tx_buf != NULL) {
978 		if (*bpw == 8) {
979 			tx_buf = data->cur_trans->tx_buf;
980 			tx_dma_buf = dma->tx_buf_virt;
981 			for (i = 0; i < data->bpw_len; i++)
982 				*tx_dma_buf++ = *tx_buf++;
983 		} else {
984 			tx_sbuf = data->cur_trans->tx_buf;
985 			tx_dma_sbuf = dma->tx_buf_virt;
986 			for (i = 0; i < data->bpw_len; i++)
987 				*tx_dma_sbuf++ = *tx_sbuf++;
988 		}
989 	}
990 
991 	/* Calculate Rx parameter for DMA transmitting */
992 	if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
993 		if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
994 			num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
995 			rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
996 		} else {
997 			num = data->bpw_len / PCH_DMA_TRANS_SIZE;
998 			rem = PCH_DMA_TRANS_SIZE;
999 		}
1000 		size = PCH_DMA_TRANS_SIZE;
1001 	} else {
1002 		num = 1;
1003 		size = data->bpw_len;
1004 		rem = data->bpw_len;
1005 	}
1006 	dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1007 		__func__, num, size, rem);
1008 	spin_lock_irqsave(&data->lock, flags);
1009 
1010 	/* set receive fifo threshold and transmit fifo threshold */
1011 	pch_spi_setclr_reg(data->master, PCH_SPCR,
1012 			   ((size - 1) << SPCR_RFIC_FIELD) |
1013 			   (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1014 			   MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1015 
1016 	spin_unlock_irqrestore(&data->lock, flags);
1017 
1018 	/* RX */
1019 	dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1020 	sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1021 	/* offset, length setting */
1022 	sg = dma->sg_rx_p;
1023 	for (i = 0; i < num; i++, sg++) {
1024 		if (i == (num - 2)) {
1025 			sg->offset = size * i;
1026 			sg->offset = sg->offset * (*bpw / 8);
1027 			sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1028 				    sg->offset);
1029 			sg_dma_len(sg) = rem;
1030 		} else if (i == (num - 1)) {
1031 			sg->offset = size * (i - 1) + rem;
1032 			sg->offset = sg->offset * (*bpw / 8);
1033 			sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1034 				    sg->offset);
1035 			sg_dma_len(sg) = size;
1036 		} else {
1037 			sg->offset = size * i;
1038 			sg->offset = sg->offset * (*bpw / 8);
1039 			sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1040 				    sg->offset);
1041 			sg_dma_len(sg) = size;
1042 		}
1043 		sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1044 	}
1045 	sg = dma->sg_rx_p;
1046 	desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1047 					num, DMA_DEV_TO_MEM,
1048 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1049 	if (!desc_rx) {
1050 		dev_err(&data->master->dev,
1051 			"%s:dmaengine_prep_slave_sg Failed\n", __func__);
1052 		return;
1053 	}
1054 	dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1055 	desc_rx->callback = pch_dma_rx_complete;
1056 	desc_rx->callback_param = data;
1057 	dma->nent = num;
1058 	dma->desc_rx = desc_rx;
1059 
1060 	/* Calculate Tx parameter for DMA transmitting */
1061 	if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1062 		head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1063 		if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1064 			num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1065 			rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1066 		} else {
1067 			num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1068 			rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1069 			      PCH_DMA_TRANS_SIZE - head;
1070 		}
1071 		size = PCH_DMA_TRANS_SIZE;
1072 	} else {
1073 		num = 1;
1074 		size = data->bpw_len;
1075 		rem = data->bpw_len;
1076 		head = 0;
1077 	}
1078 
1079 	dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1080 	sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1081 	/* offset, length setting */
1082 	sg = dma->sg_tx_p;
1083 	for (i = 0; i < num; i++, sg++) {
1084 		if (i == 0) {
1085 			sg->offset = 0;
1086 			sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1087 				    sg->offset);
1088 			sg_dma_len(sg) = size + head;
1089 		} else if (i == (num - 1)) {
1090 			sg->offset = head + size * i;
1091 			sg->offset = sg->offset * (*bpw / 8);
1092 			sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1093 				    sg->offset);
1094 			sg_dma_len(sg) = rem;
1095 		} else {
1096 			sg->offset = head + size * i;
1097 			sg->offset = sg->offset * (*bpw / 8);
1098 			sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1099 				    sg->offset);
1100 			sg_dma_len(sg) = size;
1101 		}
1102 		sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1103 	}
1104 	sg = dma->sg_tx_p;
1105 	desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1106 					sg, num, DMA_MEM_TO_DEV,
1107 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1108 	if (!desc_tx) {
1109 		dev_err(&data->master->dev,
1110 			"%s:dmaengine_prep_slave_sg Failed\n", __func__);
1111 		return;
1112 	}
1113 	dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1114 	desc_tx->callback = NULL;
1115 	desc_tx->callback_param = data;
1116 	dma->nent = num;
1117 	dma->desc_tx = desc_tx;
1118 
1119 	dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1120 
1121 	spin_lock_irqsave(&data->lock, flags);
1122 	pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1123 	desc_rx->tx_submit(desc_rx);
1124 	desc_tx->tx_submit(desc_tx);
1125 	spin_unlock_irqrestore(&data->lock, flags);
1126 
1127 	/* reset transfer complete flag */
1128 	data->transfer_complete = false;
1129 }
1130 
1131 static void pch_spi_process_messages(struct work_struct *pwork)
1132 {
1133 	struct spi_message *pmsg, *tmp;
1134 	struct pch_spi_data *data;
1135 	int bpw;
1136 
1137 	data = container_of(pwork, struct pch_spi_data, work);
1138 	dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1139 
1140 	spin_lock(&data->lock);
1141 	/* check if suspend has been initiated;if yes flush queue */
1142 	if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1143 		dev_dbg(&data->master->dev,
1144 			"%s suspend/remove initiated, flushing queue\n", __func__);
1145 		list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1146 			pmsg->status = -EIO;
1147 
1148 			if (pmsg->complete) {
1149 				spin_unlock(&data->lock);
1150 				pmsg->complete(pmsg->context);
1151 				spin_lock(&data->lock);
1152 			}
1153 
1154 			/* delete from queue */
1155 			list_del_init(&pmsg->queue);
1156 		}
1157 
1158 		spin_unlock(&data->lock);
1159 		return;
1160 	}
1161 
1162 	data->bcurrent_msg_processing = true;
1163 	dev_dbg(&data->master->dev,
1164 		"%s Set data->bcurrent_msg_processing= true\n", __func__);
1165 
1166 	/* Get the message from the queue and delete it from there. */
1167 	data->current_msg = list_entry(data->queue.next, struct spi_message,
1168 					queue);
1169 
1170 	list_del_init(&data->current_msg->queue);
1171 
1172 	data->current_msg->status = 0;
1173 
1174 	pch_spi_select_chip(data, data->current_msg->spi);
1175 
1176 	spin_unlock(&data->lock);
1177 
1178 	if (data->use_dma)
1179 		pch_spi_request_dma(data,
1180 				    data->current_msg->spi->bits_per_word);
1181 	pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1182 	do {
1183 		int cnt;
1184 		/* If we are already processing a message get the next
1185 		transfer structure from the message otherwise retrieve
1186 		the 1st transfer request from the message. */
1187 		spin_lock(&data->lock);
1188 		if (data->cur_trans == NULL) {
1189 			data->cur_trans =
1190 				list_entry(data->current_msg->transfers.next,
1191 					   struct spi_transfer, transfer_list);
1192 			dev_dbg(&data->master->dev, "%s "
1193 				":Getting 1st transfer message\n", __func__);
1194 		} else {
1195 			data->cur_trans =
1196 				list_entry(data->cur_trans->transfer_list.next,
1197 					   struct spi_transfer, transfer_list);
1198 			dev_dbg(&data->master->dev, "%s "
1199 				":Getting next transfer message\n", __func__);
1200 		}
1201 		spin_unlock(&data->lock);
1202 
1203 		if (!data->cur_trans->len)
1204 			goto out;
1205 		cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1206 		data->save_total_len = data->cur_trans->len;
1207 		if (data->use_dma) {
1208 			int i;
1209 			char *save_rx_buf = data->cur_trans->rx_buf;
1210 			for (i = 0; i < cnt; i ++) {
1211 				pch_spi_handle_dma(data, &bpw);
1212 				if (!pch_spi_start_transfer(data)) {
1213 					data->transfer_complete = true;
1214 					data->current_msg->status = -EIO;
1215 					data->current_msg->complete
1216 						   (data->current_msg->context);
1217 					data->bcurrent_msg_processing = false;
1218 					data->current_msg = NULL;
1219 					data->cur_trans = NULL;
1220 					goto out;
1221 				}
1222 				pch_spi_copy_rx_data_for_dma(data, bpw);
1223 			}
1224 			data->cur_trans->rx_buf = save_rx_buf;
1225 		} else {
1226 			pch_spi_set_tx(data, &bpw);
1227 			pch_spi_set_ir(data);
1228 			pch_spi_copy_rx_data(data, bpw);
1229 			kfree(data->pkt_rx_buff);
1230 			data->pkt_rx_buff = NULL;
1231 			kfree(data->pkt_tx_buff);
1232 			data->pkt_tx_buff = NULL;
1233 		}
1234 		/* increment message count */
1235 		data->cur_trans->len = data->save_total_len;
1236 		data->current_msg->actual_length += data->cur_trans->len;
1237 
1238 		dev_dbg(&data->master->dev,
1239 			"%s:data->current_msg->actual_length=%d\n",
1240 			__func__, data->current_msg->actual_length);
1241 
1242 		/* check for delay */
1243 		if (data->cur_trans->delay_usecs) {
1244 			dev_dbg(&data->master->dev, "%s:"
1245 				"delay in usec=%d\n", __func__,
1246 				data->cur_trans->delay_usecs);
1247 			udelay(data->cur_trans->delay_usecs);
1248 		}
1249 
1250 		spin_lock(&data->lock);
1251 
1252 		/* No more transfer in this message. */
1253 		if ((data->cur_trans->transfer_list.next) ==
1254 		    &(data->current_msg->transfers)) {
1255 			pch_spi_nomore_transfer(data);
1256 		}
1257 
1258 		spin_unlock(&data->lock);
1259 
1260 	} while (data->cur_trans != NULL);
1261 
1262 out:
1263 	pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1264 	if (data->use_dma)
1265 		pch_spi_release_dma(data);
1266 }
1267 
1268 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1269 				   struct pch_spi_data *data)
1270 {
1271 	dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1272 
1273 	/* free workqueue */
1274 	if (data->wk != NULL) {
1275 		destroy_workqueue(data->wk);
1276 		data->wk = NULL;
1277 		dev_dbg(&board_dat->pdev->dev,
1278 			"%s destroy_workqueue invoked successfully\n",
1279 			__func__);
1280 	}
1281 }
1282 
1283 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1284 				 struct pch_spi_data *data)
1285 {
1286 	int retval = 0;
1287 
1288 	dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1289 
1290 	/* create workqueue */
1291 	data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1292 	if (!data->wk) {
1293 		dev_err(&board_dat->pdev->dev,
1294 			"%s create_singlet hread_workqueue failed\n", __func__);
1295 		retval = -EBUSY;
1296 		goto err_return;
1297 	}
1298 
1299 	/* reset PCH SPI h/w */
1300 	pch_spi_reset(data->master);
1301 	dev_dbg(&board_dat->pdev->dev,
1302 		"%s pch_spi_reset invoked successfully\n", __func__);
1303 
1304 	dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1305 
1306 err_return:
1307 	if (retval != 0) {
1308 		dev_err(&board_dat->pdev->dev,
1309 			"%s FAIL:invoking pch_spi_free_resources\n", __func__);
1310 		pch_spi_free_resources(board_dat, data);
1311 	}
1312 
1313 	dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1314 
1315 	return retval;
1316 }
1317 
1318 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1319 			     struct pch_spi_data *data)
1320 {
1321 	struct pch_spi_dma_ctrl *dma;
1322 
1323 	dma = &data->dma;
1324 	if (dma->tx_buf_dma)
1325 		dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1326 				  dma->tx_buf_virt, dma->tx_buf_dma);
1327 	if (dma->rx_buf_dma)
1328 		dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1329 				  dma->rx_buf_virt, dma->rx_buf_dma);
1330 	return;
1331 }
1332 
1333 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1334 			      struct pch_spi_data *data)
1335 {
1336 	struct pch_spi_dma_ctrl *dma;
1337 
1338 	dma = &data->dma;
1339 	/* Get Consistent memory for Tx DMA */
1340 	dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1341 				PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1342 	/* Get Consistent memory for Rx DMA */
1343 	dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1344 				PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1345 }
1346 
1347 static int pch_spi_pd_probe(struct platform_device *plat_dev)
1348 {
1349 	int ret;
1350 	struct spi_master *master;
1351 	struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1352 	struct pch_spi_data *data;
1353 
1354 	dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1355 
1356 	master = spi_alloc_master(&board_dat->pdev->dev,
1357 				  sizeof(struct pch_spi_data));
1358 	if (!master) {
1359 		dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1360 			plat_dev->id);
1361 		return -ENOMEM;
1362 	}
1363 
1364 	data = spi_master_get_devdata(master);
1365 	data->master = master;
1366 
1367 	platform_set_drvdata(plat_dev, data);
1368 
1369 	/* baseaddress + address offset) */
1370 	data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1371 					 PCH_ADDRESS_SIZE * plat_dev->id;
1372 	data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1373 	if (!data->io_remap_addr) {
1374 		dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1375 		ret = -ENOMEM;
1376 		goto err_pci_iomap;
1377 	}
1378 	data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
1379 
1380 	dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1381 		plat_dev->id, data->io_remap_addr);
1382 
1383 	/* initialize members of SPI master */
1384 	master->num_chipselect = PCH_MAX_CS;
1385 	master->transfer = pch_spi_transfer;
1386 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1387 	master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1388 	master->max_speed_hz = PCH_MAX_BAUDRATE;
1389 
1390 	data->board_dat = board_dat;
1391 	data->plat_dev = plat_dev;
1392 	data->n_curnt_chip = 255;
1393 	data->status = STATUS_RUNNING;
1394 	data->ch = plat_dev->id;
1395 	data->use_dma = use_dma;
1396 
1397 	INIT_LIST_HEAD(&data->queue);
1398 	spin_lock_init(&data->lock);
1399 	INIT_WORK(&data->work, pch_spi_process_messages);
1400 	init_waitqueue_head(&data->wait);
1401 
1402 	ret = pch_spi_get_resources(board_dat, data);
1403 	if (ret) {
1404 		dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1405 		goto err_spi_get_resources;
1406 	}
1407 
1408 	ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1409 			  IRQF_SHARED, KBUILD_MODNAME, data);
1410 	if (ret) {
1411 		dev_err(&plat_dev->dev,
1412 			"%s request_irq failed\n", __func__);
1413 		goto err_request_irq;
1414 	}
1415 	data->irq_reg_sts = true;
1416 
1417 	pch_spi_set_master_mode(master);
1418 
1419 	if (use_dma) {
1420 		dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1421 		pch_alloc_dma_buf(board_dat, data);
1422 	}
1423 
1424 	ret = spi_register_master(master);
1425 	if (ret != 0) {
1426 		dev_err(&plat_dev->dev,
1427 			"%s spi_register_master FAILED\n", __func__);
1428 		goto err_spi_register_master;
1429 	}
1430 
1431 	return 0;
1432 
1433 err_spi_register_master:
1434 	pch_free_dma_buf(board_dat, data);
1435 	free_irq(board_dat->pdev->irq, data);
1436 err_request_irq:
1437 	pch_spi_free_resources(board_dat, data);
1438 err_spi_get_resources:
1439 	pci_iounmap(board_dat->pdev, data->io_remap_addr);
1440 err_pci_iomap:
1441 	spi_master_put(master);
1442 
1443 	return ret;
1444 }
1445 
1446 static int pch_spi_pd_remove(struct platform_device *plat_dev)
1447 {
1448 	struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1449 	struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1450 	int count;
1451 	unsigned long flags;
1452 
1453 	dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1454 		__func__, plat_dev->id, board_dat->pdev->irq);
1455 
1456 	if (use_dma)
1457 		pch_free_dma_buf(board_dat, data);
1458 
1459 	/* check for any pending messages; no action is taken if the queue
1460 	 * is still full; but at least we tried.  Unload anyway */
1461 	count = 500;
1462 	spin_lock_irqsave(&data->lock, flags);
1463 	data->status = STATUS_EXITING;
1464 	while ((list_empty(&data->queue) == 0) && --count) {
1465 		dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1466 			__func__);
1467 		spin_unlock_irqrestore(&data->lock, flags);
1468 		msleep(PCH_SLEEP_TIME);
1469 		spin_lock_irqsave(&data->lock, flags);
1470 	}
1471 	spin_unlock_irqrestore(&data->lock, flags);
1472 
1473 	pch_spi_free_resources(board_dat, data);
1474 	/* disable interrupts & free IRQ */
1475 	if (data->irq_reg_sts) {
1476 		/* disable interrupts */
1477 		pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1478 		data->irq_reg_sts = false;
1479 		free_irq(board_dat->pdev->irq, data);
1480 	}
1481 
1482 	pci_iounmap(board_dat->pdev, data->io_remap_addr);
1483 	spi_unregister_master(data->master);
1484 
1485 	return 0;
1486 }
1487 #ifdef CONFIG_PM
1488 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1489 			      pm_message_t state)
1490 {
1491 	u8 count;
1492 	struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1493 	struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1494 
1495 	dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1496 
1497 	if (!board_dat) {
1498 		dev_err(&pd_dev->dev,
1499 			"%s pci_get_drvdata returned NULL\n", __func__);
1500 		return -EFAULT;
1501 	}
1502 
1503 	/* check if the current message is processed:
1504 	   Only after thats done the transfer will be suspended */
1505 	count = 255;
1506 	while ((--count) > 0) {
1507 		if (!(data->bcurrent_msg_processing))
1508 			break;
1509 		msleep(PCH_SLEEP_TIME);
1510 	}
1511 
1512 	/* Free IRQ */
1513 	if (data->irq_reg_sts) {
1514 		/* disable all interrupts */
1515 		pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1516 		pch_spi_reset(data->master);
1517 		free_irq(board_dat->pdev->irq, data);
1518 
1519 		data->irq_reg_sts = false;
1520 		dev_dbg(&pd_dev->dev,
1521 			"%s free_irq invoked successfully.\n", __func__);
1522 	}
1523 
1524 	return 0;
1525 }
1526 
1527 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1528 {
1529 	struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1530 	struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1531 	int retval;
1532 
1533 	if (!board_dat) {
1534 		dev_err(&pd_dev->dev,
1535 			"%s pci_get_drvdata returned NULL\n", __func__);
1536 		return -EFAULT;
1537 	}
1538 
1539 	if (!data->irq_reg_sts) {
1540 		/* register IRQ */
1541 		retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1542 				     IRQF_SHARED, KBUILD_MODNAME, data);
1543 		if (retval < 0) {
1544 			dev_err(&pd_dev->dev,
1545 				"%s request_irq failed\n", __func__);
1546 			return retval;
1547 		}
1548 
1549 		/* reset PCH SPI h/w */
1550 		pch_spi_reset(data->master);
1551 		pch_spi_set_master_mode(data->master);
1552 		data->irq_reg_sts = true;
1553 	}
1554 	return 0;
1555 }
1556 #else
1557 #define pch_spi_pd_suspend NULL
1558 #define pch_spi_pd_resume NULL
1559 #endif
1560 
1561 static struct platform_driver pch_spi_pd_driver = {
1562 	.driver = {
1563 		.name = "pch-spi",
1564 	},
1565 	.probe = pch_spi_pd_probe,
1566 	.remove = pch_spi_pd_remove,
1567 	.suspend = pch_spi_pd_suspend,
1568 	.resume = pch_spi_pd_resume
1569 };
1570 
1571 static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1572 {
1573 	struct pch_spi_board_data *board_dat;
1574 	struct platform_device *pd_dev = NULL;
1575 	int retval;
1576 	int i;
1577 	struct pch_pd_dev_save *pd_dev_save;
1578 
1579 	pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1580 	if (!pd_dev_save)
1581 		return -ENOMEM;
1582 
1583 	board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1584 	if (!board_dat) {
1585 		retval = -ENOMEM;
1586 		goto err_no_mem;
1587 	}
1588 
1589 	retval = pci_request_regions(pdev, KBUILD_MODNAME);
1590 	if (retval) {
1591 		dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1592 		goto pci_request_regions;
1593 	}
1594 
1595 	board_dat->pdev = pdev;
1596 	board_dat->num = id->driver_data;
1597 	pd_dev_save->num = id->driver_data;
1598 	pd_dev_save->board_dat = board_dat;
1599 
1600 	retval = pci_enable_device(pdev);
1601 	if (retval) {
1602 		dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1603 		goto pci_enable_device;
1604 	}
1605 
1606 	for (i = 0; i < board_dat->num; i++) {
1607 		pd_dev = platform_device_alloc("pch-spi", i);
1608 		if (!pd_dev) {
1609 			dev_err(&pdev->dev, "platform_device_alloc failed\n");
1610 			retval = -ENOMEM;
1611 			goto err_platform_device;
1612 		}
1613 		pd_dev_save->pd_save[i] = pd_dev;
1614 		pd_dev->dev.parent = &pdev->dev;
1615 
1616 		retval = platform_device_add_data(pd_dev, board_dat,
1617 						  sizeof(*board_dat));
1618 		if (retval) {
1619 			dev_err(&pdev->dev,
1620 				"platform_device_add_data failed\n");
1621 			platform_device_put(pd_dev);
1622 			goto err_platform_device;
1623 		}
1624 
1625 		retval = platform_device_add(pd_dev);
1626 		if (retval) {
1627 			dev_err(&pdev->dev, "platform_device_add failed\n");
1628 			platform_device_put(pd_dev);
1629 			goto err_platform_device;
1630 		}
1631 	}
1632 
1633 	pci_set_drvdata(pdev, pd_dev_save);
1634 
1635 	return 0;
1636 
1637 err_platform_device:
1638 	while (--i >= 0)
1639 		platform_device_unregister(pd_dev_save->pd_save[i]);
1640 	pci_disable_device(pdev);
1641 pci_enable_device:
1642 	pci_release_regions(pdev);
1643 pci_request_regions:
1644 	kfree(board_dat);
1645 err_no_mem:
1646 	kfree(pd_dev_save);
1647 
1648 	return retval;
1649 }
1650 
1651 static void pch_spi_remove(struct pci_dev *pdev)
1652 {
1653 	int i;
1654 	struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1655 
1656 	dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1657 
1658 	for (i = 0; i < pd_dev_save->num; i++)
1659 		platform_device_unregister(pd_dev_save->pd_save[i]);
1660 
1661 	pci_disable_device(pdev);
1662 	pci_release_regions(pdev);
1663 	kfree(pd_dev_save->board_dat);
1664 	kfree(pd_dev_save);
1665 }
1666 
1667 #ifdef CONFIG_PM
1668 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1669 {
1670 	int retval;
1671 	struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1672 
1673 	dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1674 
1675 	pd_dev_save->board_dat->suspend_sts = true;
1676 
1677 	/* save config space */
1678 	retval = pci_save_state(pdev);
1679 	if (retval == 0) {
1680 		pci_enable_wake(pdev, PCI_D3hot, 0);
1681 		pci_disable_device(pdev);
1682 		pci_set_power_state(pdev, PCI_D3hot);
1683 	} else {
1684 		dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1685 	}
1686 
1687 	return retval;
1688 }
1689 
1690 static int pch_spi_resume(struct pci_dev *pdev)
1691 {
1692 	int retval;
1693 	struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1694 	dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1695 
1696 	pci_set_power_state(pdev, PCI_D0);
1697 	pci_restore_state(pdev);
1698 
1699 	retval = pci_enable_device(pdev);
1700 	if (retval < 0) {
1701 		dev_err(&pdev->dev,
1702 			"%s pci_enable_device failed\n", __func__);
1703 	} else {
1704 		pci_enable_wake(pdev, PCI_D3hot, 0);
1705 
1706 		/* set suspend status to false */
1707 		pd_dev_save->board_dat->suspend_sts = false;
1708 	}
1709 
1710 	return retval;
1711 }
1712 #else
1713 #define pch_spi_suspend NULL
1714 #define pch_spi_resume NULL
1715 
1716 #endif
1717 
1718 static struct pci_driver pch_spi_pcidev_driver = {
1719 	.name = "pch_spi",
1720 	.id_table = pch_spi_pcidev_id,
1721 	.probe = pch_spi_probe,
1722 	.remove = pch_spi_remove,
1723 	.suspend = pch_spi_suspend,
1724 	.resume = pch_spi_resume,
1725 };
1726 
1727 static int __init pch_spi_init(void)
1728 {
1729 	int ret;
1730 	ret = platform_driver_register(&pch_spi_pd_driver);
1731 	if (ret)
1732 		return ret;
1733 
1734 	ret = pci_register_driver(&pch_spi_pcidev_driver);
1735 	if (ret) {
1736 		platform_driver_unregister(&pch_spi_pd_driver);
1737 		return ret;
1738 	}
1739 
1740 	return 0;
1741 }
1742 module_init(pch_spi_init);
1743 
1744 static void __exit pch_spi_exit(void)
1745 {
1746 	pci_unregister_driver(&pch_spi_pcidev_driver);
1747 	platform_driver_unregister(&pch_spi_pd_driver);
1748 }
1749 module_exit(pch_spi_exit);
1750 
1751 module_param(use_dma, int, 0644);
1752 MODULE_PARM_DESC(use_dma,
1753 		 "to use DMA for data transfers pass 1 else 0; default 1");
1754 
1755 MODULE_LICENSE("GPL");
1756 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1757 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1758 
1759