1 /* 2 * SPI bus driver for the Topcliff PCH used by Intel SoCs 3 * 4 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/wait.h> 23 #include <linux/spi/spi.h> 24 #include <linux/interrupt.h> 25 #include <linux/sched.h> 26 #include <linux/spi/spidev.h> 27 #include <linux/module.h> 28 #include <linux/device.h> 29 #include <linux/platform_device.h> 30 31 #include <linux/dmaengine.h> 32 #include <linux/pch_dma.h> 33 34 /* Register offsets */ 35 #define PCH_SPCR 0x00 /* SPI control register */ 36 #define PCH_SPBRR 0x04 /* SPI baud rate register */ 37 #define PCH_SPSR 0x08 /* SPI status register */ 38 #define PCH_SPDWR 0x0C /* SPI write data register */ 39 #define PCH_SPDRR 0x10 /* SPI read data register */ 40 #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */ 41 #define PCH_SRST 0x1C /* SPI reset register */ 42 #define PCH_ADDRESS_SIZE 0x20 43 44 #define PCH_SPSR_TFD 0x000007C0 45 #define PCH_SPSR_RFD 0x0000F800 46 47 #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11) 48 #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6) 49 50 #define PCH_RX_THOLD 7 51 #define PCH_RX_THOLD_MAX 15 52 53 #define PCH_TX_THOLD 2 54 55 #define PCH_MAX_BAUDRATE 5000000 56 #define PCH_MAX_FIFO_DEPTH 16 57 58 #define STATUS_RUNNING 1 59 #define STATUS_EXITING 2 60 #define PCH_SLEEP_TIME 10 61 62 #define SSN_LOW 0x02U 63 #define SSN_HIGH 0x03U 64 #define SSN_NO_CONTROL 0x00U 65 #define PCH_MAX_CS 0xFF 66 #define PCI_DEVICE_ID_GE_SPI 0x8816 67 68 #define SPCR_SPE_BIT (1 << 0) 69 #define SPCR_MSTR_BIT (1 << 1) 70 #define SPCR_LSBF_BIT (1 << 4) 71 #define SPCR_CPHA_BIT (1 << 5) 72 #define SPCR_CPOL_BIT (1 << 6) 73 #define SPCR_TFIE_BIT (1 << 8) 74 #define SPCR_RFIE_BIT (1 << 9) 75 #define SPCR_FIE_BIT (1 << 10) 76 #define SPCR_ORIE_BIT (1 << 11) 77 #define SPCR_MDFIE_BIT (1 << 12) 78 #define SPCR_FICLR_BIT (1 << 24) 79 #define SPSR_TFI_BIT (1 << 0) 80 #define SPSR_RFI_BIT (1 << 1) 81 #define SPSR_FI_BIT (1 << 2) 82 #define SPSR_ORF_BIT (1 << 3) 83 #define SPBRR_SIZE_BIT (1 << 10) 84 85 #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\ 86 SPCR_ORIE_BIT|SPCR_MDFIE_BIT) 87 88 #define SPCR_RFIC_FIELD 20 89 #define SPCR_TFIC_FIELD 16 90 91 #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1) 92 #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD) 93 #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD) 94 95 #define PCH_CLOCK_HZ 50000000 96 #define PCH_MAX_SPBR 1023 97 98 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */ 99 #define PCI_VENDOR_ID_ROHM 0x10DB 100 #define PCI_DEVICE_ID_ML7213_SPI 0x802c 101 #define PCI_DEVICE_ID_ML7223_SPI 0x800F 102 #define PCI_DEVICE_ID_ML7831_SPI 0x8816 103 104 /* 105 * Set the number of SPI instance max 106 * Intel EG20T PCH : 1ch 107 * LAPIS Semiconductor ML7213 IOH : 2ch 108 * LAPIS Semiconductor ML7223 IOH : 1ch 109 * LAPIS Semiconductor ML7831 IOH : 1ch 110 */ 111 #define PCH_SPI_MAX_DEV 2 112 113 #define PCH_BUF_SIZE 4096 114 #define PCH_DMA_TRANS_SIZE 12 115 116 static int use_dma = 1; 117 118 struct pch_spi_dma_ctrl { 119 struct dma_async_tx_descriptor *desc_tx; 120 struct dma_async_tx_descriptor *desc_rx; 121 struct pch_dma_slave param_tx; 122 struct pch_dma_slave param_rx; 123 struct dma_chan *chan_tx; 124 struct dma_chan *chan_rx; 125 struct scatterlist *sg_tx_p; 126 struct scatterlist *sg_rx_p; 127 struct scatterlist sg_tx; 128 struct scatterlist sg_rx; 129 int nent; 130 void *tx_buf_virt; 131 void *rx_buf_virt; 132 dma_addr_t tx_buf_dma; 133 dma_addr_t rx_buf_dma; 134 }; 135 /** 136 * struct pch_spi_data - Holds the SPI channel specific details 137 * @io_remap_addr: The remapped PCI base address 138 * @master: Pointer to the SPI master structure 139 * @work: Reference to work queue handler 140 * @wk: Workqueue for carrying out execution of the 141 * requests 142 * @wait: Wait queue for waking up upon receiving an 143 * interrupt. 144 * @transfer_complete: Status of SPI Transfer 145 * @bcurrent_msg_processing: Status flag for message processing 146 * @lock: Lock for protecting this structure 147 * @queue: SPI Message queue 148 * @status: Status of the SPI driver 149 * @bpw_len: Length of data to be transferred in bits per 150 * word 151 * @transfer_active: Flag showing active transfer 152 * @tx_index: Transmit data count; for bookkeeping during 153 * transfer 154 * @rx_index: Receive data count; for bookkeeping during 155 * transfer 156 * @tx_buff: Buffer for data to be transmitted 157 * @rx_index: Buffer for Received data 158 * @n_curnt_chip: The chip number that this SPI driver currently 159 * operates on 160 * @current_chip: Reference to the current chip that this SPI 161 * driver currently operates on 162 * @current_msg: The current message that this SPI driver is 163 * handling 164 * @cur_trans: The current transfer that this SPI driver is 165 * handling 166 * @board_dat: Reference to the SPI device data structure 167 * @plat_dev: platform_device structure 168 * @ch: SPI channel number 169 * @irq_reg_sts: Status of IRQ registration 170 */ 171 struct pch_spi_data { 172 void __iomem *io_remap_addr; 173 unsigned long io_base_addr; 174 struct spi_master *master; 175 struct work_struct work; 176 struct workqueue_struct *wk; 177 wait_queue_head_t wait; 178 u8 transfer_complete; 179 u8 bcurrent_msg_processing; 180 spinlock_t lock; 181 struct list_head queue; 182 u8 status; 183 u32 bpw_len; 184 u8 transfer_active; 185 u32 tx_index; 186 u32 rx_index; 187 u16 *pkt_tx_buff; 188 u16 *pkt_rx_buff; 189 u8 n_curnt_chip; 190 struct spi_device *current_chip; 191 struct spi_message *current_msg; 192 struct spi_transfer *cur_trans; 193 struct pch_spi_board_data *board_dat; 194 struct platform_device *plat_dev; 195 int ch; 196 struct pch_spi_dma_ctrl dma; 197 int use_dma; 198 u8 irq_reg_sts; 199 int save_total_len; 200 }; 201 202 /** 203 * struct pch_spi_board_data - Holds the SPI device specific details 204 * @pdev: Pointer to the PCI device 205 * @suspend_sts: Status of suspend 206 * @num: The number of SPI device instance 207 */ 208 struct pch_spi_board_data { 209 struct pci_dev *pdev; 210 u8 suspend_sts; 211 int num; 212 }; 213 214 struct pch_pd_dev_save { 215 int num; 216 struct platform_device *pd_save[PCH_SPI_MAX_DEV]; 217 struct pch_spi_board_data *board_dat; 218 }; 219 220 static const struct pci_device_id pch_spi_pcidev_id[] = { 221 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, }, 222 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, }, 223 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, }, 224 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, }, 225 { } 226 }; 227 228 /** 229 * pch_spi_writereg() - Performs register writes 230 * @master: Pointer to struct spi_master. 231 * @idx: Register offset. 232 * @val: Value to be written to register. 233 */ 234 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val) 235 { 236 struct pch_spi_data *data = spi_master_get_devdata(master); 237 iowrite32(val, (data->io_remap_addr + idx)); 238 } 239 240 /** 241 * pch_spi_readreg() - Performs register reads 242 * @master: Pointer to struct spi_master. 243 * @idx: Register offset. 244 */ 245 static inline u32 pch_spi_readreg(struct spi_master *master, int idx) 246 { 247 struct pch_spi_data *data = spi_master_get_devdata(master); 248 return ioread32(data->io_remap_addr + idx); 249 } 250 251 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx, 252 u32 set, u32 clr) 253 { 254 u32 tmp = pch_spi_readreg(master, idx); 255 tmp = (tmp & ~clr) | set; 256 pch_spi_writereg(master, idx, tmp); 257 } 258 259 static void pch_spi_set_master_mode(struct spi_master *master) 260 { 261 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0); 262 } 263 264 /** 265 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs 266 * @master: Pointer to struct spi_master. 267 */ 268 static void pch_spi_clear_fifo(struct spi_master *master) 269 { 270 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0); 271 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT); 272 } 273 274 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val, 275 void __iomem *io_remap_addr) 276 { 277 u32 n_read, tx_index, rx_index, bpw_len; 278 u16 *pkt_rx_buffer, *pkt_tx_buff; 279 int read_cnt; 280 u32 reg_spcr_val; 281 void __iomem *spsr; 282 void __iomem *spdrr; 283 void __iomem *spdwr; 284 285 spsr = io_remap_addr + PCH_SPSR; 286 iowrite32(reg_spsr_val, spsr); 287 288 if (data->transfer_active) { 289 rx_index = data->rx_index; 290 tx_index = data->tx_index; 291 bpw_len = data->bpw_len; 292 pkt_rx_buffer = data->pkt_rx_buff; 293 pkt_tx_buff = data->pkt_tx_buff; 294 295 spdrr = io_remap_addr + PCH_SPDRR; 296 spdwr = io_remap_addr + PCH_SPDWR; 297 298 n_read = PCH_READABLE(reg_spsr_val); 299 300 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) { 301 pkt_rx_buffer[rx_index++] = ioread32(spdrr); 302 if (tx_index < bpw_len) 303 iowrite32(pkt_tx_buff[tx_index++], spdwr); 304 } 305 306 /* disable RFI if not needed */ 307 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) { 308 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR); 309 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */ 310 311 /* reset rx threshold */ 312 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS; 313 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD); 314 315 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR)); 316 } 317 318 /* update counts */ 319 data->tx_index = tx_index; 320 data->rx_index = rx_index; 321 322 /* if transfer complete interrupt */ 323 if (reg_spsr_val & SPSR_FI_BIT) { 324 if ((tx_index == bpw_len) && (rx_index == tx_index)) { 325 /* disable interrupts */ 326 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, 327 PCH_ALL); 328 329 /* transfer is completed; 330 inform pch_spi_process_messages */ 331 data->transfer_complete = true; 332 data->transfer_active = false; 333 wake_up(&data->wait); 334 } else { 335 dev_err(&data->master->dev, 336 "%s : Transfer is not completed", 337 __func__); 338 } 339 } 340 } 341 } 342 343 /** 344 * pch_spi_handler() - Interrupt handler 345 * @irq: The interrupt number. 346 * @dev_id: Pointer to struct pch_spi_board_data. 347 */ 348 static irqreturn_t pch_spi_handler(int irq, void *dev_id) 349 { 350 u32 reg_spsr_val; 351 void __iomem *spsr; 352 void __iomem *io_remap_addr; 353 irqreturn_t ret = IRQ_NONE; 354 struct pch_spi_data *data = dev_id; 355 struct pch_spi_board_data *board_dat = data->board_dat; 356 357 if (board_dat->suspend_sts) { 358 dev_dbg(&board_dat->pdev->dev, 359 "%s returning due to suspend\n", __func__); 360 return IRQ_NONE; 361 } 362 363 io_remap_addr = data->io_remap_addr; 364 spsr = io_remap_addr + PCH_SPSR; 365 366 reg_spsr_val = ioread32(spsr); 367 368 if (reg_spsr_val & SPSR_ORF_BIT) { 369 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__); 370 if (data->current_msg->complete) { 371 data->transfer_complete = true; 372 data->current_msg->status = -EIO; 373 data->current_msg->complete(data->current_msg->context); 374 data->bcurrent_msg_processing = false; 375 data->current_msg = NULL; 376 data->cur_trans = NULL; 377 } 378 } 379 380 if (data->use_dma) 381 return IRQ_NONE; 382 383 /* Check if the interrupt is for SPI device */ 384 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) { 385 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr); 386 ret = IRQ_HANDLED; 387 } 388 389 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n", 390 __func__, ret); 391 392 return ret; 393 } 394 395 /** 396 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR 397 * @master: Pointer to struct spi_master. 398 * @speed_hz: Baud rate. 399 */ 400 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz) 401 { 402 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2); 403 404 /* if baud rate is less than we can support limit it */ 405 if (n_spbr > PCH_MAX_SPBR) 406 n_spbr = PCH_MAX_SPBR; 407 408 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS); 409 } 410 411 /** 412 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR 413 * @master: Pointer to struct spi_master. 414 * @bits_per_word: Bits per word for SPI transfer. 415 */ 416 static void pch_spi_set_bits_per_word(struct spi_master *master, 417 u8 bits_per_word) 418 { 419 if (bits_per_word == 8) 420 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT); 421 else 422 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0); 423 } 424 425 /** 426 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer 427 * @spi: Pointer to struct spi_device. 428 */ 429 static void pch_spi_setup_transfer(struct spi_device *spi) 430 { 431 u32 flags = 0; 432 433 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n", 434 __func__, pch_spi_readreg(spi->master, PCH_SPBRR), 435 spi->max_speed_hz); 436 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz); 437 438 /* set bits per word */ 439 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word); 440 441 if (!(spi->mode & SPI_LSB_FIRST)) 442 flags |= SPCR_LSBF_BIT; 443 if (spi->mode & SPI_CPOL) 444 flags |= SPCR_CPOL_BIT; 445 if (spi->mode & SPI_CPHA) 446 flags |= SPCR_CPHA_BIT; 447 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags, 448 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT)); 449 450 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */ 451 pch_spi_clear_fifo(spi->master); 452 } 453 454 /** 455 * pch_spi_reset() - Clears SPI registers 456 * @master: Pointer to struct spi_master. 457 */ 458 static void pch_spi_reset(struct spi_master *master) 459 { 460 /* write 1 to reset SPI */ 461 pch_spi_writereg(master, PCH_SRST, 0x1); 462 463 /* clear reset */ 464 pch_spi_writereg(master, PCH_SRST, 0x0); 465 } 466 467 static int pch_spi_setup(struct spi_device *pspi) 468 { 469 /* Check baud rate setting */ 470 /* if baud rate of chip is greater than 471 max we can support,return error */ 472 if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE) 473 pspi->max_speed_hz = PCH_MAX_BAUDRATE; 474 475 dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__, 476 (pspi->mode) & (SPI_CPOL | SPI_CPHA)); 477 478 return 0; 479 } 480 481 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg) 482 { 483 484 struct spi_transfer *transfer; 485 struct pch_spi_data *data = spi_master_get_devdata(pspi->master); 486 int retval; 487 unsigned long flags; 488 489 /* validate spi message and baud rate */ 490 if (unlikely(list_empty(&pmsg->transfers) == 1)) { 491 dev_err(&pspi->dev, "%s list empty\n", __func__); 492 retval = -EINVAL; 493 goto err_out; 494 } 495 496 if (unlikely(pspi->max_speed_hz == 0)) { 497 dev_err(&pspi->dev, "%s pch_spi_transfer maxspeed=%d\n", 498 __func__, pspi->max_speed_hz); 499 retval = -EINVAL; 500 goto err_out; 501 } 502 503 dev_dbg(&pspi->dev, 504 "%s Transfer List not empty. Transfer Speed is set.\n", __func__); 505 506 spin_lock_irqsave(&data->lock, flags); 507 /* validate Tx/Rx buffers and Transfer length */ 508 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) { 509 if (!transfer->tx_buf && !transfer->rx_buf) { 510 dev_err(&pspi->dev, 511 "%s Tx and Rx buffer NULL\n", __func__); 512 retval = -EINVAL; 513 goto err_return_spinlock; 514 } 515 516 if (!transfer->len) { 517 dev_err(&pspi->dev, "%s Transfer length invalid\n", 518 __func__); 519 retval = -EINVAL; 520 goto err_return_spinlock; 521 } 522 523 dev_dbg(&pspi->dev, 524 "%s Tx/Rx buffer valid. Transfer length valid\n", 525 __func__); 526 527 /* if baud rate has been specified validate the same */ 528 if (transfer->speed_hz > PCH_MAX_BAUDRATE) 529 transfer->speed_hz = PCH_MAX_BAUDRATE; 530 } 531 spin_unlock_irqrestore(&data->lock, flags); 532 533 /* We won't process any messages if we have been asked to terminate */ 534 if (data->status == STATUS_EXITING) { 535 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__); 536 retval = -ESHUTDOWN; 537 goto err_out; 538 } 539 540 /* If suspended ,return -EINVAL */ 541 if (data->board_dat->suspend_sts) { 542 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__); 543 retval = -EINVAL; 544 goto err_out; 545 } 546 547 /* set status of message */ 548 pmsg->actual_length = 0; 549 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status); 550 551 pmsg->status = -EINPROGRESS; 552 spin_lock_irqsave(&data->lock, flags); 553 /* add message to queue */ 554 list_add_tail(&pmsg->queue, &data->queue); 555 spin_unlock_irqrestore(&data->lock, flags); 556 557 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__); 558 559 /* schedule work queue to run */ 560 queue_work(data->wk, &data->work); 561 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__); 562 563 retval = 0; 564 565 err_out: 566 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); 567 return retval; 568 err_return_spinlock: 569 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); 570 spin_unlock_irqrestore(&data->lock, flags); 571 return retval; 572 } 573 574 static inline void pch_spi_select_chip(struct pch_spi_data *data, 575 struct spi_device *pspi) 576 { 577 if (data->current_chip != NULL) { 578 if (pspi->chip_select != data->n_curnt_chip) { 579 dev_dbg(&pspi->dev, "%s : different slave\n", __func__); 580 data->current_chip = NULL; 581 } 582 } 583 584 data->current_chip = pspi; 585 586 data->n_curnt_chip = data->current_chip->chip_select; 587 588 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__); 589 pch_spi_setup_transfer(pspi); 590 } 591 592 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw) 593 { 594 int size; 595 u32 n_writes; 596 int j; 597 struct spi_message *pmsg, *tmp; 598 const u8 *tx_buf; 599 const u16 *tx_sbuf; 600 601 /* set baud rate if needed */ 602 if (data->cur_trans->speed_hz) { 603 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); 604 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); 605 } 606 607 /* set bits per word if needed */ 608 if (data->cur_trans->bits_per_word && 609 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) { 610 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); 611 pch_spi_set_bits_per_word(data->master, 612 data->cur_trans->bits_per_word); 613 *bpw = data->cur_trans->bits_per_word; 614 } else { 615 *bpw = data->current_msg->spi->bits_per_word; 616 } 617 618 /* reset Tx/Rx index */ 619 data->tx_index = 0; 620 data->rx_index = 0; 621 622 data->bpw_len = data->cur_trans->len / (*bpw / 8); 623 624 /* find alloc size */ 625 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff); 626 627 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */ 628 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL); 629 if (data->pkt_tx_buff != NULL) { 630 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL); 631 if (!data->pkt_rx_buff) 632 kfree(data->pkt_tx_buff); 633 } 634 635 if (!data->pkt_rx_buff) { 636 /* flush queue and set status of all transfers to -ENOMEM */ 637 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__); 638 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { 639 pmsg->status = -ENOMEM; 640 641 if (pmsg->complete) 642 pmsg->complete(pmsg->context); 643 644 /* delete from queue */ 645 list_del_init(&pmsg->queue); 646 } 647 return; 648 } 649 650 /* copy Tx Data */ 651 if (data->cur_trans->tx_buf != NULL) { 652 if (*bpw == 8) { 653 tx_buf = data->cur_trans->tx_buf; 654 for (j = 0; j < data->bpw_len; j++) 655 data->pkt_tx_buff[j] = *tx_buf++; 656 } else { 657 tx_sbuf = data->cur_trans->tx_buf; 658 for (j = 0; j < data->bpw_len; j++) 659 data->pkt_tx_buff[j] = *tx_sbuf++; 660 } 661 } 662 663 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */ 664 n_writes = data->bpw_len; 665 if (n_writes > PCH_MAX_FIFO_DEPTH) 666 n_writes = PCH_MAX_FIFO_DEPTH; 667 668 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing " 669 "0x2 to SSNXCR\n", __func__); 670 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); 671 672 for (j = 0; j < n_writes; j++) 673 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]); 674 675 /* update tx_index */ 676 data->tx_index = j; 677 678 /* reset transfer complete flag */ 679 data->transfer_complete = false; 680 data->transfer_active = true; 681 } 682 683 static void pch_spi_nomore_transfer(struct pch_spi_data *data) 684 { 685 struct spi_message *pmsg, *tmp; 686 dev_dbg(&data->master->dev, "%s called\n", __func__); 687 /* Invoke complete callback 688 * [To the spi core..indicating end of transfer] */ 689 data->current_msg->status = 0; 690 691 if (data->current_msg->complete) { 692 dev_dbg(&data->master->dev, 693 "%s:Invoking callback of SPI core\n", __func__); 694 data->current_msg->complete(data->current_msg->context); 695 } 696 697 /* update status in global variable */ 698 data->bcurrent_msg_processing = false; 699 700 dev_dbg(&data->master->dev, 701 "%s:data->bcurrent_msg_processing = false\n", __func__); 702 703 data->current_msg = NULL; 704 data->cur_trans = NULL; 705 706 /* check if we have items in list and not suspending 707 * return 1 if list empty */ 708 if ((list_empty(&data->queue) == 0) && 709 (!data->board_dat->suspend_sts) && 710 (data->status != STATUS_EXITING)) { 711 /* We have some more work to do (either there is more tranint 712 * bpw;sfer requests in the current message or there are 713 *more messages) 714 */ 715 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__); 716 queue_work(data->wk, &data->work); 717 } else if (data->board_dat->suspend_sts || 718 data->status == STATUS_EXITING) { 719 dev_dbg(&data->master->dev, 720 "%s suspend/remove initiated, flushing queue\n", 721 __func__); 722 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { 723 pmsg->status = -EIO; 724 725 if (pmsg->complete) 726 pmsg->complete(pmsg->context); 727 728 /* delete from queue */ 729 list_del_init(&pmsg->queue); 730 } 731 } 732 } 733 734 static void pch_spi_set_ir(struct pch_spi_data *data) 735 { 736 /* enable interrupts, set threshold, enable SPI */ 737 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) 738 /* set receive threshold to PCH_RX_THOLD */ 739 pch_spi_setclr_reg(data->master, PCH_SPCR, 740 PCH_RX_THOLD << SPCR_RFIC_FIELD | 741 SPCR_FIE_BIT | SPCR_RFIE_BIT | 742 SPCR_ORIE_BIT | SPCR_SPE_BIT, 743 MASK_RFIC_SPCR_BITS | PCH_ALL); 744 else 745 /* set receive threshold to maximum */ 746 pch_spi_setclr_reg(data->master, PCH_SPCR, 747 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD | 748 SPCR_FIE_BIT | SPCR_ORIE_BIT | 749 SPCR_SPE_BIT, 750 MASK_RFIC_SPCR_BITS | PCH_ALL); 751 752 /* Wait until the transfer completes; go to sleep after 753 initiating the transfer. */ 754 dev_dbg(&data->master->dev, 755 "%s:waiting for transfer to get over\n", __func__); 756 757 wait_event_interruptible(data->wait, data->transfer_complete); 758 759 /* clear all interrupts */ 760 pch_spi_writereg(data->master, PCH_SPSR, 761 pch_spi_readreg(data->master, PCH_SPSR)); 762 /* Disable interrupts and SPI transfer */ 763 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT); 764 /* clear FIFO */ 765 pch_spi_clear_fifo(data->master); 766 } 767 768 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw) 769 { 770 int j; 771 u8 *rx_buf; 772 u16 *rx_sbuf; 773 774 /* copy Rx Data */ 775 if (!data->cur_trans->rx_buf) 776 return; 777 778 if (bpw == 8) { 779 rx_buf = data->cur_trans->rx_buf; 780 for (j = 0; j < data->bpw_len; j++) 781 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF; 782 } else { 783 rx_sbuf = data->cur_trans->rx_buf; 784 for (j = 0; j < data->bpw_len; j++) 785 *rx_sbuf++ = data->pkt_rx_buff[j]; 786 } 787 } 788 789 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw) 790 { 791 int j; 792 u8 *rx_buf; 793 u16 *rx_sbuf; 794 const u8 *rx_dma_buf; 795 const u16 *rx_dma_sbuf; 796 797 /* copy Rx Data */ 798 if (!data->cur_trans->rx_buf) 799 return; 800 801 if (bpw == 8) { 802 rx_buf = data->cur_trans->rx_buf; 803 rx_dma_buf = data->dma.rx_buf_virt; 804 for (j = 0; j < data->bpw_len; j++) 805 *rx_buf++ = *rx_dma_buf++ & 0xFF; 806 data->cur_trans->rx_buf = rx_buf; 807 } else { 808 rx_sbuf = data->cur_trans->rx_buf; 809 rx_dma_sbuf = data->dma.rx_buf_virt; 810 for (j = 0; j < data->bpw_len; j++) 811 *rx_sbuf++ = *rx_dma_sbuf++; 812 data->cur_trans->rx_buf = rx_sbuf; 813 } 814 } 815 816 static int pch_spi_start_transfer(struct pch_spi_data *data) 817 { 818 struct pch_spi_dma_ctrl *dma; 819 unsigned long flags; 820 int rtn; 821 822 dma = &data->dma; 823 824 spin_lock_irqsave(&data->lock, flags); 825 826 /* disable interrupts, SPI set enable */ 827 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL); 828 829 spin_unlock_irqrestore(&data->lock, flags); 830 831 /* Wait until the transfer completes; go to sleep after 832 initiating the transfer. */ 833 dev_dbg(&data->master->dev, 834 "%s:waiting for transfer to get over\n", __func__); 835 rtn = wait_event_interruptible_timeout(data->wait, 836 data->transfer_complete, 837 msecs_to_jiffies(2 * HZ)); 838 if (!rtn) 839 dev_err(&data->master->dev, 840 "%s wait-event timeout\n", __func__); 841 842 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent, 843 DMA_FROM_DEVICE); 844 845 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent, 846 DMA_FROM_DEVICE); 847 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE); 848 849 async_tx_ack(dma->desc_rx); 850 async_tx_ack(dma->desc_tx); 851 kfree(dma->sg_tx_p); 852 kfree(dma->sg_rx_p); 853 854 spin_lock_irqsave(&data->lock, flags); 855 856 /* clear fifo threshold, disable interrupts, disable SPI transfer */ 857 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, 858 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL | 859 SPCR_SPE_BIT); 860 /* clear all interrupts */ 861 pch_spi_writereg(data->master, PCH_SPSR, 862 pch_spi_readreg(data->master, PCH_SPSR)); 863 /* clear FIFO */ 864 pch_spi_clear_fifo(data->master); 865 866 spin_unlock_irqrestore(&data->lock, flags); 867 868 return rtn; 869 } 870 871 static void pch_dma_rx_complete(void *arg) 872 { 873 struct pch_spi_data *data = arg; 874 875 /* transfer is completed;inform pch_spi_process_messages_dma */ 876 data->transfer_complete = true; 877 wake_up_interruptible(&data->wait); 878 } 879 880 static bool pch_spi_filter(struct dma_chan *chan, void *slave) 881 { 882 struct pch_dma_slave *param = slave; 883 884 if ((chan->chan_id == param->chan_id) && 885 (param->dma_dev == chan->device->dev)) { 886 chan->private = param; 887 return true; 888 } else { 889 return false; 890 } 891 } 892 893 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw) 894 { 895 dma_cap_mask_t mask; 896 struct dma_chan *chan; 897 struct pci_dev *dma_dev; 898 struct pch_dma_slave *param; 899 struct pch_spi_dma_ctrl *dma; 900 unsigned int width; 901 902 if (bpw == 8) 903 width = PCH_DMA_WIDTH_1_BYTE; 904 else 905 width = PCH_DMA_WIDTH_2_BYTES; 906 907 dma = &data->dma; 908 dma_cap_zero(mask); 909 dma_cap_set(DMA_SLAVE, mask); 910 911 /* Get DMA's dev information */ 912 dma_dev = pci_get_bus_and_slot(data->board_dat->pdev->bus->number, 913 PCI_DEVFN(12, 0)); 914 915 /* Set Tx DMA */ 916 param = &dma->param_tx; 917 param->dma_dev = &dma_dev->dev; 918 param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */ 919 param->tx_reg = data->io_base_addr + PCH_SPDWR; 920 param->width = width; 921 chan = dma_request_channel(mask, pch_spi_filter, param); 922 if (!chan) { 923 dev_err(&data->master->dev, 924 "ERROR: dma_request_channel FAILS(Tx)\n"); 925 data->use_dma = 0; 926 return; 927 } 928 dma->chan_tx = chan; 929 930 /* Set Rx DMA */ 931 param = &dma->param_rx; 932 param->dma_dev = &dma_dev->dev; 933 param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */ 934 param->rx_reg = data->io_base_addr + PCH_SPDRR; 935 param->width = width; 936 chan = dma_request_channel(mask, pch_spi_filter, param); 937 if (!chan) { 938 dev_err(&data->master->dev, 939 "ERROR: dma_request_channel FAILS(Rx)\n"); 940 dma_release_channel(dma->chan_tx); 941 dma->chan_tx = NULL; 942 data->use_dma = 0; 943 return; 944 } 945 dma->chan_rx = chan; 946 } 947 948 static void pch_spi_release_dma(struct pch_spi_data *data) 949 { 950 struct pch_spi_dma_ctrl *dma; 951 952 dma = &data->dma; 953 if (dma->chan_tx) { 954 dma_release_channel(dma->chan_tx); 955 dma->chan_tx = NULL; 956 } 957 if (dma->chan_rx) { 958 dma_release_channel(dma->chan_rx); 959 dma->chan_rx = NULL; 960 } 961 return; 962 } 963 964 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) 965 { 966 const u8 *tx_buf; 967 const u16 *tx_sbuf; 968 u8 *tx_dma_buf; 969 u16 *tx_dma_sbuf; 970 struct scatterlist *sg; 971 struct dma_async_tx_descriptor *desc_tx; 972 struct dma_async_tx_descriptor *desc_rx; 973 int num; 974 int i; 975 int size; 976 int rem; 977 int head; 978 unsigned long flags; 979 struct pch_spi_dma_ctrl *dma; 980 981 dma = &data->dma; 982 983 /* set baud rate if needed */ 984 if (data->cur_trans->speed_hz) { 985 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); 986 spin_lock_irqsave(&data->lock, flags); 987 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); 988 spin_unlock_irqrestore(&data->lock, flags); 989 } 990 991 /* set bits per word if needed */ 992 if (data->cur_trans->bits_per_word && 993 (data->current_msg->spi->bits_per_word != 994 data->cur_trans->bits_per_word)) { 995 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); 996 spin_lock_irqsave(&data->lock, flags); 997 pch_spi_set_bits_per_word(data->master, 998 data->cur_trans->bits_per_word); 999 spin_unlock_irqrestore(&data->lock, flags); 1000 *bpw = data->cur_trans->bits_per_word; 1001 } else { 1002 *bpw = data->current_msg->spi->bits_per_word; 1003 } 1004 data->bpw_len = data->cur_trans->len / (*bpw / 8); 1005 1006 if (data->bpw_len > PCH_BUF_SIZE) { 1007 data->bpw_len = PCH_BUF_SIZE; 1008 data->cur_trans->len -= PCH_BUF_SIZE; 1009 } 1010 1011 /* copy Tx Data */ 1012 if (data->cur_trans->tx_buf != NULL) { 1013 if (*bpw == 8) { 1014 tx_buf = data->cur_trans->tx_buf; 1015 tx_dma_buf = dma->tx_buf_virt; 1016 for (i = 0; i < data->bpw_len; i++) 1017 *tx_dma_buf++ = *tx_buf++; 1018 } else { 1019 tx_sbuf = data->cur_trans->tx_buf; 1020 tx_dma_sbuf = dma->tx_buf_virt; 1021 for (i = 0; i < data->bpw_len; i++) 1022 *tx_dma_sbuf++ = *tx_sbuf++; 1023 } 1024 } 1025 1026 /* Calculate Rx parameter for DMA transmitting */ 1027 if (data->bpw_len > PCH_DMA_TRANS_SIZE) { 1028 if (data->bpw_len % PCH_DMA_TRANS_SIZE) { 1029 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; 1030 rem = data->bpw_len % PCH_DMA_TRANS_SIZE; 1031 } else { 1032 num = data->bpw_len / PCH_DMA_TRANS_SIZE; 1033 rem = PCH_DMA_TRANS_SIZE; 1034 } 1035 size = PCH_DMA_TRANS_SIZE; 1036 } else { 1037 num = 1; 1038 size = data->bpw_len; 1039 rem = data->bpw_len; 1040 } 1041 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n", 1042 __func__, num, size, rem); 1043 spin_lock_irqsave(&data->lock, flags); 1044 1045 /* set receive fifo threshold and transmit fifo threshold */ 1046 pch_spi_setclr_reg(data->master, PCH_SPCR, 1047 ((size - 1) << SPCR_RFIC_FIELD) | 1048 (PCH_TX_THOLD << SPCR_TFIC_FIELD), 1049 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS); 1050 1051 spin_unlock_irqrestore(&data->lock, flags); 1052 1053 /* RX */ 1054 dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 1055 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */ 1056 /* offset, length setting */ 1057 sg = dma->sg_rx_p; 1058 for (i = 0; i < num; i++, sg++) { 1059 if (i == (num - 2)) { 1060 sg->offset = size * i; 1061 sg->offset = sg->offset * (*bpw / 8); 1062 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem, 1063 sg->offset); 1064 sg_dma_len(sg) = rem; 1065 } else if (i == (num - 1)) { 1066 sg->offset = size * (i - 1) + rem; 1067 sg->offset = sg->offset * (*bpw / 8); 1068 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size, 1069 sg->offset); 1070 sg_dma_len(sg) = size; 1071 } else { 1072 sg->offset = size * i; 1073 sg->offset = sg->offset * (*bpw / 8); 1074 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size, 1075 sg->offset); 1076 sg_dma_len(sg) = size; 1077 } 1078 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset; 1079 } 1080 sg = dma->sg_rx_p; 1081 desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg, 1082 num, DMA_DEV_TO_MEM, 1083 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1084 if (!desc_rx) { 1085 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", 1086 __func__); 1087 return; 1088 } 1089 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE); 1090 desc_rx->callback = pch_dma_rx_complete; 1091 desc_rx->callback_param = data; 1092 dma->nent = num; 1093 dma->desc_rx = desc_rx; 1094 1095 /* Calculate Tx parameter for DMA transmitting */ 1096 if (data->bpw_len > PCH_MAX_FIFO_DEPTH) { 1097 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE; 1098 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) { 1099 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; 1100 rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head; 1101 } else { 1102 num = data->bpw_len / PCH_DMA_TRANS_SIZE; 1103 rem = data->bpw_len % PCH_DMA_TRANS_SIZE + 1104 PCH_DMA_TRANS_SIZE - head; 1105 } 1106 size = PCH_DMA_TRANS_SIZE; 1107 } else { 1108 num = 1; 1109 size = data->bpw_len; 1110 rem = data->bpw_len; 1111 head = 0; 1112 } 1113 1114 dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 1115 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */ 1116 /* offset, length setting */ 1117 sg = dma->sg_tx_p; 1118 for (i = 0; i < num; i++, sg++) { 1119 if (i == 0) { 1120 sg->offset = 0; 1121 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head, 1122 sg->offset); 1123 sg_dma_len(sg) = size + head; 1124 } else if (i == (num - 1)) { 1125 sg->offset = head + size * i; 1126 sg->offset = sg->offset * (*bpw / 8); 1127 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem, 1128 sg->offset); 1129 sg_dma_len(sg) = rem; 1130 } else { 1131 sg->offset = head + size * i; 1132 sg->offset = sg->offset * (*bpw / 8); 1133 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size, 1134 sg->offset); 1135 sg_dma_len(sg) = size; 1136 } 1137 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset; 1138 } 1139 sg = dma->sg_tx_p; 1140 desc_tx = dmaengine_prep_slave_sg(dma->chan_tx, 1141 sg, num, DMA_MEM_TO_DEV, 1142 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1143 if (!desc_tx) { 1144 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", 1145 __func__); 1146 return; 1147 } 1148 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE); 1149 desc_tx->callback = NULL; 1150 desc_tx->callback_param = data; 1151 dma->nent = num; 1152 dma->desc_tx = desc_tx; 1153 1154 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing " 1155 "0x2 to SSNXCR\n", __func__); 1156 1157 spin_lock_irqsave(&data->lock, flags); 1158 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); 1159 desc_rx->tx_submit(desc_rx); 1160 desc_tx->tx_submit(desc_tx); 1161 spin_unlock_irqrestore(&data->lock, flags); 1162 1163 /* reset transfer complete flag */ 1164 data->transfer_complete = false; 1165 } 1166 1167 static void pch_spi_process_messages(struct work_struct *pwork) 1168 { 1169 struct spi_message *pmsg, *tmp; 1170 struct pch_spi_data *data; 1171 int bpw; 1172 1173 data = container_of(pwork, struct pch_spi_data, work); 1174 dev_dbg(&data->master->dev, "%s data initialized\n", __func__); 1175 1176 spin_lock(&data->lock); 1177 /* check if suspend has been initiated;if yes flush queue */ 1178 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) { 1179 dev_dbg(&data->master->dev, 1180 "%s suspend/remove initiated, flushing queue\n", __func__); 1181 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { 1182 pmsg->status = -EIO; 1183 1184 if (pmsg->complete) { 1185 spin_unlock(&data->lock); 1186 pmsg->complete(pmsg->context); 1187 spin_lock(&data->lock); 1188 } 1189 1190 /* delete from queue */ 1191 list_del_init(&pmsg->queue); 1192 } 1193 1194 spin_unlock(&data->lock); 1195 return; 1196 } 1197 1198 data->bcurrent_msg_processing = true; 1199 dev_dbg(&data->master->dev, 1200 "%s Set data->bcurrent_msg_processing= true\n", __func__); 1201 1202 /* Get the message from the queue and delete it from there. */ 1203 data->current_msg = list_entry(data->queue.next, struct spi_message, 1204 queue); 1205 1206 list_del_init(&data->current_msg->queue); 1207 1208 data->current_msg->status = 0; 1209 1210 pch_spi_select_chip(data, data->current_msg->spi); 1211 1212 spin_unlock(&data->lock); 1213 1214 if (data->use_dma) 1215 pch_spi_request_dma(data, 1216 data->current_msg->spi->bits_per_word); 1217 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL); 1218 do { 1219 int cnt; 1220 /* If we are already processing a message get the next 1221 transfer structure from the message otherwise retrieve 1222 the 1st transfer request from the message. */ 1223 spin_lock(&data->lock); 1224 if (data->cur_trans == NULL) { 1225 data->cur_trans = 1226 list_entry(data->current_msg->transfers.next, 1227 struct spi_transfer, transfer_list); 1228 dev_dbg(&data->master->dev, "%s " 1229 ":Getting 1st transfer message\n", __func__); 1230 } else { 1231 data->cur_trans = 1232 list_entry(data->cur_trans->transfer_list.next, 1233 struct spi_transfer, transfer_list); 1234 dev_dbg(&data->master->dev, "%s " 1235 ":Getting next transfer message\n", __func__); 1236 } 1237 spin_unlock(&data->lock); 1238 1239 if (!data->cur_trans->len) 1240 goto out; 1241 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1; 1242 data->save_total_len = data->cur_trans->len; 1243 if (data->use_dma) { 1244 int i; 1245 char *save_rx_buf = data->cur_trans->rx_buf; 1246 for (i = 0; i < cnt; i ++) { 1247 pch_spi_handle_dma(data, &bpw); 1248 if (!pch_spi_start_transfer(data)) { 1249 data->transfer_complete = true; 1250 data->current_msg->status = -EIO; 1251 data->current_msg->complete 1252 (data->current_msg->context); 1253 data->bcurrent_msg_processing = false; 1254 data->current_msg = NULL; 1255 data->cur_trans = NULL; 1256 goto out; 1257 } 1258 pch_spi_copy_rx_data_for_dma(data, bpw); 1259 } 1260 data->cur_trans->rx_buf = save_rx_buf; 1261 } else { 1262 pch_spi_set_tx(data, &bpw); 1263 pch_spi_set_ir(data); 1264 pch_spi_copy_rx_data(data, bpw); 1265 kfree(data->pkt_rx_buff); 1266 data->pkt_rx_buff = NULL; 1267 kfree(data->pkt_tx_buff); 1268 data->pkt_tx_buff = NULL; 1269 } 1270 /* increment message count */ 1271 data->cur_trans->len = data->save_total_len; 1272 data->current_msg->actual_length += data->cur_trans->len; 1273 1274 dev_dbg(&data->master->dev, 1275 "%s:data->current_msg->actual_length=%d\n", 1276 __func__, data->current_msg->actual_length); 1277 1278 /* check for delay */ 1279 if (data->cur_trans->delay_usecs) { 1280 dev_dbg(&data->master->dev, "%s:" 1281 "delay in usec=%d\n", __func__, 1282 data->cur_trans->delay_usecs); 1283 udelay(data->cur_trans->delay_usecs); 1284 } 1285 1286 spin_lock(&data->lock); 1287 1288 /* No more transfer in this message. */ 1289 if ((data->cur_trans->transfer_list.next) == 1290 &(data->current_msg->transfers)) { 1291 pch_spi_nomore_transfer(data); 1292 } 1293 1294 spin_unlock(&data->lock); 1295 1296 } while (data->cur_trans != NULL); 1297 1298 out: 1299 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH); 1300 if (data->use_dma) 1301 pch_spi_release_dma(data); 1302 } 1303 1304 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat, 1305 struct pch_spi_data *data) 1306 { 1307 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); 1308 1309 /* free workqueue */ 1310 if (data->wk != NULL) { 1311 destroy_workqueue(data->wk); 1312 data->wk = NULL; 1313 dev_dbg(&board_dat->pdev->dev, 1314 "%s destroy_workqueue invoked successfully\n", 1315 __func__); 1316 } 1317 } 1318 1319 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat, 1320 struct pch_spi_data *data) 1321 { 1322 int retval = 0; 1323 1324 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); 1325 1326 /* create workqueue */ 1327 data->wk = create_singlethread_workqueue(KBUILD_MODNAME); 1328 if (!data->wk) { 1329 dev_err(&board_dat->pdev->dev, 1330 "%s create_singlet hread_workqueue failed\n", __func__); 1331 retval = -EBUSY; 1332 goto err_return; 1333 } 1334 1335 /* reset PCH SPI h/w */ 1336 pch_spi_reset(data->master); 1337 dev_dbg(&board_dat->pdev->dev, 1338 "%s pch_spi_reset invoked successfully\n", __func__); 1339 1340 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__); 1341 1342 err_return: 1343 if (retval != 0) { 1344 dev_err(&board_dat->pdev->dev, 1345 "%s FAIL:invoking pch_spi_free_resources\n", __func__); 1346 pch_spi_free_resources(board_dat, data); 1347 } 1348 1349 dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval); 1350 1351 return retval; 1352 } 1353 1354 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat, 1355 struct pch_spi_data *data) 1356 { 1357 struct pch_spi_dma_ctrl *dma; 1358 1359 dma = &data->dma; 1360 if (dma->tx_buf_dma) 1361 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, 1362 dma->tx_buf_virt, dma->tx_buf_dma); 1363 if (dma->rx_buf_dma) 1364 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, 1365 dma->rx_buf_virt, dma->rx_buf_dma); 1366 return; 1367 } 1368 1369 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat, 1370 struct pch_spi_data *data) 1371 { 1372 struct pch_spi_dma_ctrl *dma; 1373 1374 dma = &data->dma; 1375 /* Get Consistent memory for Tx DMA */ 1376 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, 1377 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL); 1378 /* Get Consistent memory for Rx DMA */ 1379 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, 1380 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL); 1381 } 1382 1383 static int pch_spi_pd_probe(struct platform_device *plat_dev) 1384 { 1385 int ret; 1386 struct spi_master *master; 1387 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); 1388 struct pch_spi_data *data; 1389 1390 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__); 1391 1392 master = spi_alloc_master(&board_dat->pdev->dev, 1393 sizeof(struct pch_spi_data)); 1394 if (!master) { 1395 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n", 1396 plat_dev->id); 1397 return -ENOMEM; 1398 } 1399 1400 data = spi_master_get_devdata(master); 1401 data->master = master; 1402 1403 platform_set_drvdata(plat_dev, data); 1404 1405 /* baseaddress + address offset) */ 1406 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) + 1407 PCH_ADDRESS_SIZE * plat_dev->id; 1408 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0); 1409 if (!data->io_remap_addr) { 1410 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__); 1411 ret = -ENOMEM; 1412 goto err_pci_iomap; 1413 } 1414 data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id; 1415 1416 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n", 1417 plat_dev->id, data->io_remap_addr); 1418 1419 /* initialize members of SPI master */ 1420 master->num_chipselect = PCH_MAX_CS; 1421 master->setup = pch_spi_setup; 1422 master->transfer = pch_spi_transfer; 1423 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 1424 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 1425 1426 data->board_dat = board_dat; 1427 data->plat_dev = plat_dev; 1428 data->n_curnt_chip = 255; 1429 data->status = STATUS_RUNNING; 1430 data->ch = plat_dev->id; 1431 data->use_dma = use_dma; 1432 1433 INIT_LIST_HEAD(&data->queue); 1434 spin_lock_init(&data->lock); 1435 INIT_WORK(&data->work, pch_spi_process_messages); 1436 init_waitqueue_head(&data->wait); 1437 1438 ret = pch_spi_get_resources(board_dat, data); 1439 if (ret) { 1440 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret); 1441 goto err_spi_get_resources; 1442 } 1443 1444 ret = request_irq(board_dat->pdev->irq, pch_spi_handler, 1445 IRQF_SHARED, KBUILD_MODNAME, data); 1446 if (ret) { 1447 dev_err(&plat_dev->dev, 1448 "%s request_irq failed\n", __func__); 1449 goto err_request_irq; 1450 } 1451 data->irq_reg_sts = true; 1452 1453 pch_spi_set_master_mode(master); 1454 1455 ret = spi_register_master(master); 1456 if (ret != 0) { 1457 dev_err(&plat_dev->dev, 1458 "%s spi_register_master FAILED\n", __func__); 1459 goto err_spi_register_master; 1460 } 1461 1462 if (use_dma) { 1463 dev_info(&plat_dev->dev, "Use DMA for data transfers\n"); 1464 pch_alloc_dma_buf(board_dat, data); 1465 } 1466 1467 return 0; 1468 1469 err_spi_register_master: 1470 free_irq(board_dat->pdev->irq, data); 1471 err_request_irq: 1472 pch_spi_free_resources(board_dat, data); 1473 err_spi_get_resources: 1474 pci_iounmap(board_dat->pdev, data->io_remap_addr); 1475 err_pci_iomap: 1476 spi_master_put(master); 1477 1478 return ret; 1479 } 1480 1481 static int pch_spi_pd_remove(struct platform_device *plat_dev) 1482 { 1483 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); 1484 struct pch_spi_data *data = platform_get_drvdata(plat_dev); 1485 int count; 1486 unsigned long flags; 1487 1488 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n", 1489 __func__, plat_dev->id, board_dat->pdev->irq); 1490 1491 if (use_dma) 1492 pch_free_dma_buf(board_dat, data); 1493 1494 /* check for any pending messages; no action is taken if the queue 1495 * is still full; but at least we tried. Unload anyway */ 1496 count = 500; 1497 spin_lock_irqsave(&data->lock, flags); 1498 data->status = STATUS_EXITING; 1499 while ((list_empty(&data->queue) == 0) && --count) { 1500 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n", 1501 __func__); 1502 spin_unlock_irqrestore(&data->lock, flags); 1503 msleep(PCH_SLEEP_TIME); 1504 spin_lock_irqsave(&data->lock, flags); 1505 } 1506 spin_unlock_irqrestore(&data->lock, flags); 1507 1508 pch_spi_free_resources(board_dat, data); 1509 /* disable interrupts & free IRQ */ 1510 if (data->irq_reg_sts) { 1511 /* disable interrupts */ 1512 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); 1513 data->irq_reg_sts = false; 1514 free_irq(board_dat->pdev->irq, data); 1515 } 1516 1517 pci_iounmap(board_dat->pdev, data->io_remap_addr); 1518 spi_unregister_master(data->master); 1519 1520 return 0; 1521 } 1522 #ifdef CONFIG_PM 1523 static int pch_spi_pd_suspend(struct platform_device *pd_dev, 1524 pm_message_t state) 1525 { 1526 u8 count; 1527 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); 1528 struct pch_spi_data *data = platform_get_drvdata(pd_dev); 1529 1530 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__); 1531 1532 if (!board_dat) { 1533 dev_err(&pd_dev->dev, 1534 "%s pci_get_drvdata returned NULL\n", __func__); 1535 return -EFAULT; 1536 } 1537 1538 /* check if the current message is processed: 1539 Only after thats done the transfer will be suspended */ 1540 count = 255; 1541 while ((--count) > 0) { 1542 if (!(data->bcurrent_msg_processing)) 1543 break; 1544 msleep(PCH_SLEEP_TIME); 1545 } 1546 1547 /* Free IRQ */ 1548 if (data->irq_reg_sts) { 1549 /* disable all interrupts */ 1550 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); 1551 pch_spi_reset(data->master); 1552 free_irq(board_dat->pdev->irq, data); 1553 1554 data->irq_reg_sts = false; 1555 dev_dbg(&pd_dev->dev, 1556 "%s free_irq invoked successfully.\n", __func__); 1557 } 1558 1559 return 0; 1560 } 1561 1562 static int pch_spi_pd_resume(struct platform_device *pd_dev) 1563 { 1564 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); 1565 struct pch_spi_data *data = platform_get_drvdata(pd_dev); 1566 int retval; 1567 1568 if (!board_dat) { 1569 dev_err(&pd_dev->dev, 1570 "%s pci_get_drvdata returned NULL\n", __func__); 1571 return -EFAULT; 1572 } 1573 1574 if (!data->irq_reg_sts) { 1575 /* register IRQ */ 1576 retval = request_irq(board_dat->pdev->irq, pch_spi_handler, 1577 IRQF_SHARED, KBUILD_MODNAME, data); 1578 if (retval < 0) { 1579 dev_err(&pd_dev->dev, 1580 "%s request_irq failed\n", __func__); 1581 return retval; 1582 } 1583 1584 /* reset PCH SPI h/w */ 1585 pch_spi_reset(data->master); 1586 pch_spi_set_master_mode(data->master); 1587 data->irq_reg_sts = true; 1588 } 1589 return 0; 1590 } 1591 #else 1592 #define pch_spi_pd_suspend NULL 1593 #define pch_spi_pd_resume NULL 1594 #endif 1595 1596 static struct platform_driver pch_spi_pd_driver = { 1597 .driver = { 1598 .name = "pch-spi", 1599 .owner = THIS_MODULE, 1600 }, 1601 .probe = pch_spi_pd_probe, 1602 .remove = pch_spi_pd_remove, 1603 .suspend = pch_spi_pd_suspend, 1604 .resume = pch_spi_pd_resume 1605 }; 1606 1607 static int pch_spi_probe(struct pci_dev *pdev, 1608 const struct pci_device_id *id) 1609 { 1610 struct pch_spi_board_data *board_dat; 1611 struct platform_device *pd_dev = NULL; 1612 int retval; 1613 int i; 1614 struct pch_pd_dev_save *pd_dev_save; 1615 1616 pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL); 1617 if (!pd_dev_save) { 1618 dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__); 1619 return -ENOMEM; 1620 } 1621 1622 board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL); 1623 if (!board_dat) { 1624 dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__); 1625 retval = -ENOMEM; 1626 goto err_no_mem; 1627 } 1628 1629 retval = pci_request_regions(pdev, KBUILD_MODNAME); 1630 if (retval) { 1631 dev_err(&pdev->dev, "%s request_region failed\n", __func__); 1632 goto pci_request_regions; 1633 } 1634 1635 board_dat->pdev = pdev; 1636 board_dat->num = id->driver_data; 1637 pd_dev_save->num = id->driver_data; 1638 pd_dev_save->board_dat = board_dat; 1639 1640 retval = pci_enable_device(pdev); 1641 if (retval) { 1642 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__); 1643 goto pci_enable_device; 1644 } 1645 1646 for (i = 0; i < board_dat->num; i++) { 1647 pd_dev = platform_device_alloc("pch-spi", i); 1648 if (!pd_dev) { 1649 dev_err(&pdev->dev, "platform_device_alloc failed\n"); 1650 retval = -ENOMEM; 1651 goto err_platform_device; 1652 } 1653 pd_dev_save->pd_save[i] = pd_dev; 1654 pd_dev->dev.parent = &pdev->dev; 1655 1656 retval = platform_device_add_data(pd_dev, board_dat, 1657 sizeof(*board_dat)); 1658 if (retval) { 1659 dev_err(&pdev->dev, 1660 "platform_device_add_data failed\n"); 1661 platform_device_put(pd_dev); 1662 goto err_platform_device; 1663 } 1664 1665 retval = platform_device_add(pd_dev); 1666 if (retval) { 1667 dev_err(&pdev->dev, "platform_device_add failed\n"); 1668 platform_device_put(pd_dev); 1669 goto err_platform_device; 1670 } 1671 } 1672 1673 pci_set_drvdata(pdev, pd_dev_save); 1674 1675 return 0; 1676 1677 err_platform_device: 1678 pci_disable_device(pdev); 1679 pci_enable_device: 1680 pci_release_regions(pdev); 1681 pci_request_regions: 1682 kfree(board_dat); 1683 err_no_mem: 1684 kfree(pd_dev_save); 1685 1686 return retval; 1687 } 1688 1689 static void pch_spi_remove(struct pci_dev *pdev) 1690 { 1691 int i; 1692 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); 1693 1694 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev); 1695 1696 for (i = 0; i < pd_dev_save->num; i++) 1697 platform_device_unregister(pd_dev_save->pd_save[i]); 1698 1699 pci_disable_device(pdev); 1700 pci_release_regions(pdev); 1701 kfree(pd_dev_save->board_dat); 1702 kfree(pd_dev_save); 1703 } 1704 1705 #ifdef CONFIG_PM 1706 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state) 1707 { 1708 int retval; 1709 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); 1710 1711 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__); 1712 1713 pd_dev_save->board_dat->suspend_sts = true; 1714 1715 /* save config space */ 1716 retval = pci_save_state(pdev); 1717 if (retval == 0) { 1718 pci_enable_wake(pdev, PCI_D3hot, 0); 1719 pci_disable_device(pdev); 1720 pci_set_power_state(pdev, PCI_D3hot); 1721 } else { 1722 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__); 1723 } 1724 1725 return retval; 1726 } 1727 1728 static int pch_spi_resume(struct pci_dev *pdev) 1729 { 1730 int retval; 1731 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); 1732 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__); 1733 1734 pci_set_power_state(pdev, PCI_D0); 1735 pci_restore_state(pdev); 1736 1737 retval = pci_enable_device(pdev); 1738 if (retval < 0) { 1739 dev_err(&pdev->dev, 1740 "%s pci_enable_device failed\n", __func__); 1741 } else { 1742 pci_enable_wake(pdev, PCI_D3hot, 0); 1743 1744 /* set suspend status to false */ 1745 pd_dev_save->board_dat->suspend_sts = false; 1746 } 1747 1748 return retval; 1749 } 1750 #else 1751 #define pch_spi_suspend NULL 1752 #define pch_spi_resume NULL 1753 1754 #endif 1755 1756 static struct pci_driver pch_spi_pcidev_driver = { 1757 .name = "pch_spi", 1758 .id_table = pch_spi_pcidev_id, 1759 .probe = pch_spi_probe, 1760 .remove = pch_spi_remove, 1761 .suspend = pch_spi_suspend, 1762 .resume = pch_spi_resume, 1763 }; 1764 1765 static int __init pch_spi_init(void) 1766 { 1767 int ret; 1768 ret = platform_driver_register(&pch_spi_pd_driver); 1769 if (ret) 1770 return ret; 1771 1772 ret = pci_register_driver(&pch_spi_pcidev_driver); 1773 if (ret) { 1774 platform_driver_unregister(&pch_spi_pd_driver); 1775 return ret; 1776 } 1777 1778 return 0; 1779 } 1780 module_init(pch_spi_init); 1781 1782 static void __exit pch_spi_exit(void) 1783 { 1784 pci_unregister_driver(&pch_spi_pcidev_driver); 1785 platform_driver_unregister(&pch_spi_pd_driver); 1786 } 1787 module_exit(pch_spi_exit); 1788 1789 module_param(use_dma, int, 0644); 1790 MODULE_PARM_DESC(use_dma, 1791 "to use DMA for data transfers pass 1 else 0; default 1"); 1792 1793 MODULE_LICENSE("GPL"); 1794 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver"); 1795 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id); 1796 1797