1 /* 2 * SPI bus driver for the Topcliff PCH used by Intel SoCs 3 * 4 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/wait.h> 23 #include <linux/spi/spi.h> 24 #include <linux/interrupt.h> 25 #include <linux/sched.h> 26 #include <linux/spi/spidev.h> 27 #include <linux/module.h> 28 #include <linux/device.h> 29 #include <linux/platform_device.h> 30 31 #include <linux/dmaengine.h> 32 #include <linux/pch_dma.h> 33 34 /* Register offsets */ 35 #define PCH_SPCR 0x00 /* SPI control register */ 36 #define PCH_SPBRR 0x04 /* SPI baud rate register */ 37 #define PCH_SPSR 0x08 /* SPI status register */ 38 #define PCH_SPDWR 0x0C /* SPI write data register */ 39 #define PCH_SPDRR 0x10 /* SPI read data register */ 40 #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */ 41 #define PCH_SRST 0x1C /* SPI reset register */ 42 #define PCH_ADDRESS_SIZE 0x20 43 44 #define PCH_SPSR_TFD 0x000007C0 45 #define PCH_SPSR_RFD 0x0000F800 46 47 #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11) 48 #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6) 49 50 #define PCH_RX_THOLD 7 51 #define PCH_RX_THOLD_MAX 15 52 53 #define PCH_TX_THOLD 2 54 55 #define PCH_MAX_BAUDRATE 5000000 56 #define PCH_MAX_FIFO_DEPTH 16 57 58 #define STATUS_RUNNING 1 59 #define STATUS_EXITING 2 60 #define PCH_SLEEP_TIME 10 61 62 #define SSN_LOW 0x02U 63 #define SSN_HIGH 0x03U 64 #define SSN_NO_CONTROL 0x00U 65 #define PCH_MAX_CS 0xFF 66 #define PCI_DEVICE_ID_GE_SPI 0x8816 67 68 #define SPCR_SPE_BIT (1 << 0) 69 #define SPCR_MSTR_BIT (1 << 1) 70 #define SPCR_LSBF_BIT (1 << 4) 71 #define SPCR_CPHA_BIT (1 << 5) 72 #define SPCR_CPOL_BIT (1 << 6) 73 #define SPCR_TFIE_BIT (1 << 8) 74 #define SPCR_RFIE_BIT (1 << 9) 75 #define SPCR_FIE_BIT (1 << 10) 76 #define SPCR_ORIE_BIT (1 << 11) 77 #define SPCR_MDFIE_BIT (1 << 12) 78 #define SPCR_FICLR_BIT (1 << 24) 79 #define SPSR_TFI_BIT (1 << 0) 80 #define SPSR_RFI_BIT (1 << 1) 81 #define SPSR_FI_BIT (1 << 2) 82 #define SPSR_ORF_BIT (1 << 3) 83 #define SPBRR_SIZE_BIT (1 << 10) 84 85 #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\ 86 SPCR_ORIE_BIT|SPCR_MDFIE_BIT) 87 88 #define SPCR_RFIC_FIELD 20 89 #define SPCR_TFIC_FIELD 16 90 91 #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1) 92 #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD) 93 #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD) 94 95 #define PCH_CLOCK_HZ 50000000 96 #define PCH_MAX_SPBR 1023 97 98 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */ 99 #define PCI_VENDOR_ID_ROHM 0x10DB 100 #define PCI_DEVICE_ID_ML7213_SPI 0x802c 101 #define PCI_DEVICE_ID_ML7223_SPI 0x800F 102 #define PCI_DEVICE_ID_ML7831_SPI 0x8816 103 104 /* 105 * Set the number of SPI instance max 106 * Intel EG20T PCH : 1ch 107 * LAPIS Semiconductor ML7213 IOH : 2ch 108 * LAPIS Semiconductor ML7223 IOH : 1ch 109 * LAPIS Semiconductor ML7831 IOH : 1ch 110 */ 111 #define PCH_SPI_MAX_DEV 2 112 113 #define PCH_BUF_SIZE 4096 114 #define PCH_DMA_TRANS_SIZE 12 115 116 static int use_dma = 1; 117 118 struct pch_spi_dma_ctrl { 119 struct dma_async_tx_descriptor *desc_tx; 120 struct dma_async_tx_descriptor *desc_rx; 121 struct pch_dma_slave param_tx; 122 struct pch_dma_slave param_rx; 123 struct dma_chan *chan_tx; 124 struct dma_chan *chan_rx; 125 struct scatterlist *sg_tx_p; 126 struct scatterlist *sg_rx_p; 127 struct scatterlist sg_tx; 128 struct scatterlist sg_rx; 129 int nent; 130 void *tx_buf_virt; 131 void *rx_buf_virt; 132 dma_addr_t tx_buf_dma; 133 dma_addr_t rx_buf_dma; 134 }; 135 /** 136 * struct pch_spi_data - Holds the SPI channel specific details 137 * @io_remap_addr: The remapped PCI base address 138 * @master: Pointer to the SPI master structure 139 * @work: Reference to work queue handler 140 * @wk: Workqueue for carrying out execution of the 141 * requests 142 * @wait: Wait queue for waking up upon receiving an 143 * interrupt. 144 * @transfer_complete: Status of SPI Transfer 145 * @bcurrent_msg_processing: Status flag for message processing 146 * @lock: Lock for protecting this structure 147 * @queue: SPI Message queue 148 * @status: Status of the SPI driver 149 * @bpw_len: Length of data to be transferred in bits per 150 * word 151 * @transfer_active: Flag showing active transfer 152 * @tx_index: Transmit data count; for bookkeeping during 153 * transfer 154 * @rx_index: Receive data count; for bookkeeping during 155 * transfer 156 * @tx_buff: Buffer for data to be transmitted 157 * @rx_index: Buffer for Received data 158 * @n_curnt_chip: The chip number that this SPI driver currently 159 * operates on 160 * @current_chip: Reference to the current chip that this SPI 161 * driver currently operates on 162 * @current_msg: The current message that this SPI driver is 163 * handling 164 * @cur_trans: The current transfer that this SPI driver is 165 * handling 166 * @board_dat: Reference to the SPI device data structure 167 * @plat_dev: platform_device structure 168 * @ch: SPI channel number 169 * @irq_reg_sts: Status of IRQ registration 170 */ 171 struct pch_spi_data { 172 void __iomem *io_remap_addr; 173 unsigned long io_base_addr; 174 struct spi_master *master; 175 struct work_struct work; 176 struct workqueue_struct *wk; 177 wait_queue_head_t wait; 178 u8 transfer_complete; 179 u8 bcurrent_msg_processing; 180 spinlock_t lock; 181 struct list_head queue; 182 u8 status; 183 u32 bpw_len; 184 u8 transfer_active; 185 u32 tx_index; 186 u32 rx_index; 187 u16 *pkt_tx_buff; 188 u16 *pkt_rx_buff; 189 u8 n_curnt_chip; 190 struct spi_device *current_chip; 191 struct spi_message *current_msg; 192 struct spi_transfer *cur_trans; 193 struct pch_spi_board_data *board_dat; 194 struct platform_device *plat_dev; 195 int ch; 196 struct pch_spi_dma_ctrl dma; 197 int use_dma; 198 u8 irq_reg_sts; 199 int save_total_len; 200 }; 201 202 /** 203 * struct pch_spi_board_data - Holds the SPI device specific details 204 * @pdev: Pointer to the PCI device 205 * @suspend_sts: Status of suspend 206 * @num: The number of SPI device instance 207 */ 208 struct pch_spi_board_data { 209 struct pci_dev *pdev; 210 u8 suspend_sts; 211 int num; 212 }; 213 214 struct pch_pd_dev_save { 215 int num; 216 struct platform_device *pd_save[PCH_SPI_MAX_DEV]; 217 struct pch_spi_board_data *board_dat; 218 }; 219 220 static DEFINE_PCI_DEVICE_TABLE(pch_spi_pcidev_id) = { 221 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, }, 222 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, }, 223 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, }, 224 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, }, 225 { } 226 }; 227 228 /** 229 * pch_spi_writereg() - Performs register writes 230 * @master: Pointer to struct spi_master. 231 * @idx: Register offset. 232 * @val: Value to be written to register. 233 */ 234 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val) 235 { 236 struct pch_spi_data *data = spi_master_get_devdata(master); 237 iowrite32(val, (data->io_remap_addr + idx)); 238 } 239 240 /** 241 * pch_spi_readreg() - Performs register reads 242 * @master: Pointer to struct spi_master. 243 * @idx: Register offset. 244 */ 245 static inline u32 pch_spi_readreg(struct spi_master *master, int idx) 246 { 247 struct pch_spi_data *data = spi_master_get_devdata(master); 248 return ioread32(data->io_remap_addr + idx); 249 } 250 251 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx, 252 u32 set, u32 clr) 253 { 254 u32 tmp = pch_spi_readreg(master, idx); 255 tmp = (tmp & ~clr) | set; 256 pch_spi_writereg(master, idx, tmp); 257 } 258 259 static void pch_spi_set_master_mode(struct spi_master *master) 260 { 261 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0); 262 } 263 264 /** 265 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs 266 * @master: Pointer to struct spi_master. 267 */ 268 static void pch_spi_clear_fifo(struct spi_master *master) 269 { 270 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0); 271 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT); 272 } 273 274 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val, 275 void __iomem *io_remap_addr) 276 { 277 u32 n_read, tx_index, rx_index, bpw_len; 278 u16 *pkt_rx_buffer, *pkt_tx_buff; 279 int read_cnt; 280 u32 reg_spcr_val; 281 void __iomem *spsr; 282 void __iomem *spdrr; 283 void __iomem *spdwr; 284 285 spsr = io_remap_addr + PCH_SPSR; 286 iowrite32(reg_spsr_val, spsr); 287 288 if (data->transfer_active) { 289 rx_index = data->rx_index; 290 tx_index = data->tx_index; 291 bpw_len = data->bpw_len; 292 pkt_rx_buffer = data->pkt_rx_buff; 293 pkt_tx_buff = data->pkt_tx_buff; 294 295 spdrr = io_remap_addr + PCH_SPDRR; 296 spdwr = io_remap_addr + PCH_SPDWR; 297 298 n_read = PCH_READABLE(reg_spsr_val); 299 300 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) { 301 pkt_rx_buffer[rx_index++] = ioread32(spdrr); 302 if (tx_index < bpw_len) 303 iowrite32(pkt_tx_buff[tx_index++], spdwr); 304 } 305 306 /* disable RFI if not needed */ 307 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) { 308 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR); 309 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */ 310 311 /* reset rx threshold */ 312 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS; 313 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD); 314 315 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR)); 316 } 317 318 /* update counts */ 319 data->tx_index = tx_index; 320 data->rx_index = rx_index; 321 322 /* if transfer complete interrupt */ 323 if (reg_spsr_val & SPSR_FI_BIT) { 324 if ((tx_index == bpw_len) && (rx_index == tx_index)) { 325 /* disable interrupts */ 326 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, 327 PCH_ALL); 328 329 /* transfer is completed; 330 inform pch_spi_process_messages */ 331 data->transfer_complete = true; 332 data->transfer_active = false; 333 wake_up(&data->wait); 334 } else { 335 dev_err(&data->master->dev, 336 "%s : Transfer is not completed", 337 __func__); 338 } 339 } 340 } 341 } 342 343 /** 344 * pch_spi_handler() - Interrupt handler 345 * @irq: The interrupt number. 346 * @dev_id: Pointer to struct pch_spi_board_data. 347 */ 348 static irqreturn_t pch_spi_handler(int irq, void *dev_id) 349 { 350 u32 reg_spsr_val; 351 void __iomem *spsr; 352 void __iomem *io_remap_addr; 353 irqreturn_t ret = IRQ_NONE; 354 struct pch_spi_data *data = dev_id; 355 struct pch_spi_board_data *board_dat = data->board_dat; 356 357 if (board_dat->suspend_sts) { 358 dev_dbg(&board_dat->pdev->dev, 359 "%s returning due to suspend\n", __func__); 360 return IRQ_NONE; 361 } 362 363 io_remap_addr = data->io_remap_addr; 364 spsr = io_remap_addr + PCH_SPSR; 365 366 reg_spsr_val = ioread32(spsr); 367 368 if (reg_spsr_val & SPSR_ORF_BIT) { 369 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__); 370 if (data->current_msg->complete) { 371 data->transfer_complete = true; 372 data->current_msg->status = -EIO; 373 data->current_msg->complete(data->current_msg->context); 374 data->bcurrent_msg_processing = false; 375 data->current_msg = NULL; 376 data->cur_trans = NULL; 377 } 378 } 379 380 if (data->use_dma) 381 return IRQ_NONE; 382 383 /* Check if the interrupt is for SPI device */ 384 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) { 385 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr); 386 ret = IRQ_HANDLED; 387 } 388 389 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n", 390 __func__, ret); 391 392 return ret; 393 } 394 395 /** 396 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR 397 * @master: Pointer to struct spi_master. 398 * @speed_hz: Baud rate. 399 */ 400 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz) 401 { 402 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2); 403 404 /* if baud rate is less than we can support limit it */ 405 if (n_spbr > PCH_MAX_SPBR) 406 n_spbr = PCH_MAX_SPBR; 407 408 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS); 409 } 410 411 /** 412 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR 413 * @master: Pointer to struct spi_master. 414 * @bits_per_word: Bits per word for SPI transfer. 415 */ 416 static void pch_spi_set_bits_per_word(struct spi_master *master, 417 u8 bits_per_word) 418 { 419 if (bits_per_word == 8) 420 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT); 421 else 422 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0); 423 } 424 425 /** 426 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer 427 * @spi: Pointer to struct spi_device. 428 */ 429 static void pch_spi_setup_transfer(struct spi_device *spi) 430 { 431 u32 flags = 0; 432 433 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n", 434 __func__, pch_spi_readreg(spi->master, PCH_SPBRR), 435 spi->max_speed_hz); 436 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz); 437 438 /* set bits per word */ 439 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word); 440 441 if (!(spi->mode & SPI_LSB_FIRST)) 442 flags |= SPCR_LSBF_BIT; 443 if (spi->mode & SPI_CPOL) 444 flags |= SPCR_CPOL_BIT; 445 if (spi->mode & SPI_CPHA) 446 flags |= SPCR_CPHA_BIT; 447 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags, 448 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT)); 449 450 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */ 451 pch_spi_clear_fifo(spi->master); 452 } 453 454 /** 455 * pch_spi_reset() - Clears SPI registers 456 * @master: Pointer to struct spi_master. 457 */ 458 static void pch_spi_reset(struct spi_master *master) 459 { 460 /* write 1 to reset SPI */ 461 pch_spi_writereg(master, PCH_SRST, 0x1); 462 463 /* clear reset */ 464 pch_spi_writereg(master, PCH_SRST, 0x0); 465 } 466 467 static int pch_spi_setup(struct spi_device *pspi) 468 { 469 /* check bits per word */ 470 if (pspi->bits_per_word == 0) { 471 pspi->bits_per_word = 8; 472 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__); 473 } 474 475 /* Check baud rate setting */ 476 /* if baud rate of chip is greater than 477 max we can support,return error */ 478 if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE) 479 pspi->max_speed_hz = PCH_MAX_BAUDRATE; 480 481 dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__, 482 (pspi->mode) & (SPI_CPOL | SPI_CPHA)); 483 484 return 0; 485 } 486 487 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg) 488 { 489 490 struct spi_transfer *transfer; 491 struct pch_spi_data *data = spi_master_get_devdata(pspi->master); 492 int retval; 493 unsigned long flags; 494 495 /* validate spi message and baud rate */ 496 if (unlikely(list_empty(&pmsg->transfers) == 1)) { 497 dev_err(&pspi->dev, "%s list empty\n", __func__); 498 retval = -EINVAL; 499 goto err_out; 500 } 501 502 if (unlikely(pspi->max_speed_hz == 0)) { 503 dev_err(&pspi->dev, "%s pch_spi_transfer maxspeed=%d\n", 504 __func__, pspi->max_speed_hz); 505 retval = -EINVAL; 506 goto err_out; 507 } 508 509 dev_dbg(&pspi->dev, 510 "%s Transfer List not empty. Transfer Speed is set.\n", __func__); 511 512 spin_lock_irqsave(&data->lock, flags); 513 /* validate Tx/Rx buffers and Transfer length */ 514 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) { 515 if (!transfer->tx_buf && !transfer->rx_buf) { 516 dev_err(&pspi->dev, 517 "%s Tx and Rx buffer NULL\n", __func__); 518 retval = -EINVAL; 519 goto err_return_spinlock; 520 } 521 522 if (!transfer->len) { 523 dev_err(&pspi->dev, "%s Transfer length invalid\n", 524 __func__); 525 retval = -EINVAL; 526 goto err_return_spinlock; 527 } 528 529 dev_dbg(&pspi->dev, 530 "%s Tx/Rx buffer valid. Transfer length valid\n", 531 __func__); 532 533 /* if baud rate has been specified validate the same */ 534 if (transfer->speed_hz > PCH_MAX_BAUDRATE) 535 transfer->speed_hz = PCH_MAX_BAUDRATE; 536 } 537 spin_unlock_irqrestore(&data->lock, flags); 538 539 /* We won't process any messages if we have been asked to terminate */ 540 if (data->status == STATUS_EXITING) { 541 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__); 542 retval = -ESHUTDOWN; 543 goto err_out; 544 } 545 546 /* If suspended ,return -EINVAL */ 547 if (data->board_dat->suspend_sts) { 548 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__); 549 retval = -EINVAL; 550 goto err_out; 551 } 552 553 /* set status of message */ 554 pmsg->actual_length = 0; 555 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status); 556 557 pmsg->status = -EINPROGRESS; 558 spin_lock_irqsave(&data->lock, flags); 559 /* add message to queue */ 560 list_add_tail(&pmsg->queue, &data->queue); 561 spin_unlock_irqrestore(&data->lock, flags); 562 563 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__); 564 565 /* schedule work queue to run */ 566 queue_work(data->wk, &data->work); 567 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__); 568 569 retval = 0; 570 571 err_out: 572 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); 573 return retval; 574 err_return_spinlock: 575 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); 576 spin_unlock_irqrestore(&data->lock, flags); 577 return retval; 578 } 579 580 static inline void pch_spi_select_chip(struct pch_spi_data *data, 581 struct spi_device *pspi) 582 { 583 if (data->current_chip != NULL) { 584 if (pspi->chip_select != data->n_curnt_chip) { 585 dev_dbg(&pspi->dev, "%s : different slave\n", __func__); 586 data->current_chip = NULL; 587 } 588 } 589 590 data->current_chip = pspi; 591 592 data->n_curnt_chip = data->current_chip->chip_select; 593 594 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__); 595 pch_spi_setup_transfer(pspi); 596 } 597 598 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw) 599 { 600 int size; 601 u32 n_writes; 602 int j; 603 struct spi_message *pmsg, *tmp; 604 const u8 *tx_buf; 605 const u16 *tx_sbuf; 606 607 /* set baud rate if needed */ 608 if (data->cur_trans->speed_hz) { 609 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); 610 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); 611 } 612 613 /* set bits per word if needed */ 614 if (data->cur_trans->bits_per_word && 615 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) { 616 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); 617 pch_spi_set_bits_per_word(data->master, 618 data->cur_trans->bits_per_word); 619 *bpw = data->cur_trans->bits_per_word; 620 } else { 621 *bpw = data->current_msg->spi->bits_per_word; 622 } 623 624 /* reset Tx/Rx index */ 625 data->tx_index = 0; 626 data->rx_index = 0; 627 628 data->bpw_len = data->cur_trans->len / (*bpw / 8); 629 630 /* find alloc size */ 631 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff); 632 633 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */ 634 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL); 635 if (data->pkt_tx_buff != NULL) { 636 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL); 637 if (!data->pkt_rx_buff) 638 kfree(data->pkt_tx_buff); 639 } 640 641 if (!data->pkt_rx_buff) { 642 /* flush queue and set status of all transfers to -ENOMEM */ 643 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__); 644 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { 645 pmsg->status = -ENOMEM; 646 647 if (pmsg->complete) 648 pmsg->complete(pmsg->context); 649 650 /* delete from queue */ 651 list_del_init(&pmsg->queue); 652 } 653 return; 654 } 655 656 /* copy Tx Data */ 657 if (data->cur_trans->tx_buf != NULL) { 658 if (*bpw == 8) { 659 tx_buf = data->cur_trans->tx_buf; 660 for (j = 0; j < data->bpw_len; j++) 661 data->pkt_tx_buff[j] = *tx_buf++; 662 } else { 663 tx_sbuf = data->cur_trans->tx_buf; 664 for (j = 0; j < data->bpw_len; j++) 665 data->pkt_tx_buff[j] = *tx_sbuf++; 666 } 667 } 668 669 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */ 670 n_writes = data->bpw_len; 671 if (n_writes > PCH_MAX_FIFO_DEPTH) 672 n_writes = PCH_MAX_FIFO_DEPTH; 673 674 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing " 675 "0x2 to SSNXCR\n", __func__); 676 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); 677 678 for (j = 0; j < n_writes; j++) 679 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]); 680 681 /* update tx_index */ 682 data->tx_index = j; 683 684 /* reset transfer complete flag */ 685 data->transfer_complete = false; 686 data->transfer_active = true; 687 } 688 689 static void pch_spi_nomore_transfer(struct pch_spi_data *data) 690 { 691 struct spi_message *pmsg, *tmp; 692 dev_dbg(&data->master->dev, "%s called\n", __func__); 693 /* Invoke complete callback 694 * [To the spi core..indicating end of transfer] */ 695 data->current_msg->status = 0; 696 697 if (data->current_msg->complete) { 698 dev_dbg(&data->master->dev, 699 "%s:Invoking callback of SPI core\n", __func__); 700 data->current_msg->complete(data->current_msg->context); 701 } 702 703 /* update status in global variable */ 704 data->bcurrent_msg_processing = false; 705 706 dev_dbg(&data->master->dev, 707 "%s:data->bcurrent_msg_processing = false\n", __func__); 708 709 data->current_msg = NULL; 710 data->cur_trans = NULL; 711 712 /* check if we have items in list and not suspending 713 * return 1 if list empty */ 714 if ((list_empty(&data->queue) == 0) && 715 (!data->board_dat->suspend_sts) && 716 (data->status != STATUS_EXITING)) { 717 /* We have some more work to do (either there is more tranint 718 * bpw;sfer requests in the current message or there are 719 *more messages) 720 */ 721 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__); 722 queue_work(data->wk, &data->work); 723 } else if (data->board_dat->suspend_sts || 724 data->status == STATUS_EXITING) { 725 dev_dbg(&data->master->dev, 726 "%s suspend/remove initiated, flushing queue\n", 727 __func__); 728 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { 729 pmsg->status = -EIO; 730 731 if (pmsg->complete) 732 pmsg->complete(pmsg->context); 733 734 /* delete from queue */ 735 list_del_init(&pmsg->queue); 736 } 737 } 738 } 739 740 static void pch_spi_set_ir(struct pch_spi_data *data) 741 { 742 /* enable interrupts, set threshold, enable SPI */ 743 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) 744 /* set receive threshold to PCH_RX_THOLD */ 745 pch_spi_setclr_reg(data->master, PCH_SPCR, 746 PCH_RX_THOLD << SPCR_RFIC_FIELD | 747 SPCR_FIE_BIT | SPCR_RFIE_BIT | 748 SPCR_ORIE_BIT | SPCR_SPE_BIT, 749 MASK_RFIC_SPCR_BITS | PCH_ALL); 750 else 751 /* set receive threshold to maximum */ 752 pch_spi_setclr_reg(data->master, PCH_SPCR, 753 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD | 754 SPCR_FIE_BIT | SPCR_ORIE_BIT | 755 SPCR_SPE_BIT, 756 MASK_RFIC_SPCR_BITS | PCH_ALL); 757 758 /* Wait until the transfer completes; go to sleep after 759 initiating the transfer. */ 760 dev_dbg(&data->master->dev, 761 "%s:waiting for transfer to get over\n", __func__); 762 763 wait_event_interruptible(data->wait, data->transfer_complete); 764 765 /* clear all interrupts */ 766 pch_spi_writereg(data->master, PCH_SPSR, 767 pch_spi_readreg(data->master, PCH_SPSR)); 768 /* Disable interrupts and SPI transfer */ 769 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT); 770 /* clear FIFO */ 771 pch_spi_clear_fifo(data->master); 772 } 773 774 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw) 775 { 776 int j; 777 u8 *rx_buf; 778 u16 *rx_sbuf; 779 780 /* copy Rx Data */ 781 if (!data->cur_trans->rx_buf) 782 return; 783 784 if (bpw == 8) { 785 rx_buf = data->cur_trans->rx_buf; 786 for (j = 0; j < data->bpw_len; j++) 787 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF; 788 } else { 789 rx_sbuf = data->cur_trans->rx_buf; 790 for (j = 0; j < data->bpw_len; j++) 791 *rx_sbuf++ = data->pkt_rx_buff[j]; 792 } 793 } 794 795 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw) 796 { 797 int j; 798 u8 *rx_buf; 799 u16 *rx_sbuf; 800 const u8 *rx_dma_buf; 801 const u16 *rx_dma_sbuf; 802 803 /* copy Rx Data */ 804 if (!data->cur_trans->rx_buf) 805 return; 806 807 if (bpw == 8) { 808 rx_buf = data->cur_trans->rx_buf; 809 rx_dma_buf = data->dma.rx_buf_virt; 810 for (j = 0; j < data->bpw_len; j++) 811 *rx_buf++ = *rx_dma_buf++ & 0xFF; 812 data->cur_trans->rx_buf = rx_buf; 813 } else { 814 rx_sbuf = data->cur_trans->rx_buf; 815 rx_dma_sbuf = data->dma.rx_buf_virt; 816 for (j = 0; j < data->bpw_len; j++) 817 *rx_sbuf++ = *rx_dma_sbuf++; 818 data->cur_trans->rx_buf = rx_sbuf; 819 } 820 } 821 822 static int pch_spi_start_transfer(struct pch_spi_data *data) 823 { 824 struct pch_spi_dma_ctrl *dma; 825 unsigned long flags; 826 int rtn; 827 828 dma = &data->dma; 829 830 spin_lock_irqsave(&data->lock, flags); 831 832 /* disable interrupts, SPI set enable */ 833 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL); 834 835 spin_unlock_irqrestore(&data->lock, flags); 836 837 /* Wait until the transfer completes; go to sleep after 838 initiating the transfer. */ 839 dev_dbg(&data->master->dev, 840 "%s:waiting for transfer to get over\n", __func__); 841 rtn = wait_event_interruptible_timeout(data->wait, 842 data->transfer_complete, 843 msecs_to_jiffies(2 * HZ)); 844 if (!rtn) 845 dev_err(&data->master->dev, 846 "%s wait-event timeout\n", __func__); 847 848 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent, 849 DMA_FROM_DEVICE); 850 851 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent, 852 DMA_FROM_DEVICE); 853 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE); 854 855 async_tx_ack(dma->desc_rx); 856 async_tx_ack(dma->desc_tx); 857 kfree(dma->sg_tx_p); 858 kfree(dma->sg_rx_p); 859 860 spin_lock_irqsave(&data->lock, flags); 861 862 /* clear fifo threshold, disable interrupts, disable SPI transfer */ 863 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, 864 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL | 865 SPCR_SPE_BIT); 866 /* clear all interrupts */ 867 pch_spi_writereg(data->master, PCH_SPSR, 868 pch_spi_readreg(data->master, PCH_SPSR)); 869 /* clear FIFO */ 870 pch_spi_clear_fifo(data->master); 871 872 spin_unlock_irqrestore(&data->lock, flags); 873 874 return rtn; 875 } 876 877 static void pch_dma_rx_complete(void *arg) 878 { 879 struct pch_spi_data *data = arg; 880 881 /* transfer is completed;inform pch_spi_process_messages_dma */ 882 data->transfer_complete = true; 883 wake_up_interruptible(&data->wait); 884 } 885 886 static bool pch_spi_filter(struct dma_chan *chan, void *slave) 887 { 888 struct pch_dma_slave *param = slave; 889 890 if ((chan->chan_id == param->chan_id) && 891 (param->dma_dev == chan->device->dev)) { 892 chan->private = param; 893 return true; 894 } else { 895 return false; 896 } 897 } 898 899 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw) 900 { 901 dma_cap_mask_t mask; 902 struct dma_chan *chan; 903 struct pci_dev *dma_dev; 904 struct pch_dma_slave *param; 905 struct pch_spi_dma_ctrl *dma; 906 unsigned int width; 907 908 if (bpw == 8) 909 width = PCH_DMA_WIDTH_1_BYTE; 910 else 911 width = PCH_DMA_WIDTH_2_BYTES; 912 913 dma = &data->dma; 914 dma_cap_zero(mask); 915 dma_cap_set(DMA_SLAVE, mask); 916 917 /* Get DMA's dev information */ 918 dma_dev = pci_get_bus_and_slot(data->board_dat->pdev->bus->number, 919 PCI_DEVFN(12, 0)); 920 921 /* Set Tx DMA */ 922 param = &dma->param_tx; 923 param->dma_dev = &dma_dev->dev; 924 param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */ 925 param->tx_reg = data->io_base_addr + PCH_SPDWR; 926 param->width = width; 927 chan = dma_request_channel(mask, pch_spi_filter, param); 928 if (!chan) { 929 dev_err(&data->master->dev, 930 "ERROR: dma_request_channel FAILS(Tx)\n"); 931 data->use_dma = 0; 932 return; 933 } 934 dma->chan_tx = chan; 935 936 /* Set Rx DMA */ 937 param = &dma->param_rx; 938 param->dma_dev = &dma_dev->dev; 939 param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */ 940 param->rx_reg = data->io_base_addr + PCH_SPDRR; 941 param->width = width; 942 chan = dma_request_channel(mask, pch_spi_filter, param); 943 if (!chan) { 944 dev_err(&data->master->dev, 945 "ERROR: dma_request_channel FAILS(Rx)\n"); 946 dma_release_channel(dma->chan_tx); 947 dma->chan_tx = NULL; 948 data->use_dma = 0; 949 return; 950 } 951 dma->chan_rx = chan; 952 } 953 954 static void pch_spi_release_dma(struct pch_spi_data *data) 955 { 956 struct pch_spi_dma_ctrl *dma; 957 958 dma = &data->dma; 959 if (dma->chan_tx) { 960 dma_release_channel(dma->chan_tx); 961 dma->chan_tx = NULL; 962 } 963 if (dma->chan_rx) { 964 dma_release_channel(dma->chan_rx); 965 dma->chan_rx = NULL; 966 } 967 return; 968 } 969 970 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) 971 { 972 const u8 *tx_buf; 973 const u16 *tx_sbuf; 974 u8 *tx_dma_buf; 975 u16 *tx_dma_sbuf; 976 struct scatterlist *sg; 977 struct dma_async_tx_descriptor *desc_tx; 978 struct dma_async_tx_descriptor *desc_rx; 979 int num; 980 int i; 981 int size; 982 int rem; 983 int head; 984 unsigned long flags; 985 struct pch_spi_dma_ctrl *dma; 986 987 dma = &data->dma; 988 989 /* set baud rate if needed */ 990 if (data->cur_trans->speed_hz) { 991 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); 992 spin_lock_irqsave(&data->lock, flags); 993 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); 994 spin_unlock_irqrestore(&data->lock, flags); 995 } 996 997 /* set bits per word if needed */ 998 if (data->cur_trans->bits_per_word && 999 (data->current_msg->spi->bits_per_word != 1000 data->cur_trans->bits_per_word)) { 1001 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); 1002 spin_lock_irqsave(&data->lock, flags); 1003 pch_spi_set_bits_per_word(data->master, 1004 data->cur_trans->bits_per_word); 1005 spin_unlock_irqrestore(&data->lock, flags); 1006 *bpw = data->cur_trans->bits_per_word; 1007 } else { 1008 *bpw = data->current_msg->spi->bits_per_word; 1009 } 1010 data->bpw_len = data->cur_trans->len / (*bpw / 8); 1011 1012 if (data->bpw_len > PCH_BUF_SIZE) { 1013 data->bpw_len = PCH_BUF_SIZE; 1014 data->cur_trans->len -= PCH_BUF_SIZE; 1015 } 1016 1017 /* copy Tx Data */ 1018 if (data->cur_trans->tx_buf != NULL) { 1019 if (*bpw == 8) { 1020 tx_buf = data->cur_trans->tx_buf; 1021 tx_dma_buf = dma->tx_buf_virt; 1022 for (i = 0; i < data->bpw_len; i++) 1023 *tx_dma_buf++ = *tx_buf++; 1024 } else { 1025 tx_sbuf = data->cur_trans->tx_buf; 1026 tx_dma_sbuf = dma->tx_buf_virt; 1027 for (i = 0; i < data->bpw_len; i++) 1028 *tx_dma_sbuf++ = *tx_sbuf++; 1029 } 1030 } 1031 1032 /* Calculate Rx parameter for DMA transmitting */ 1033 if (data->bpw_len > PCH_DMA_TRANS_SIZE) { 1034 if (data->bpw_len % PCH_DMA_TRANS_SIZE) { 1035 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; 1036 rem = data->bpw_len % PCH_DMA_TRANS_SIZE; 1037 } else { 1038 num = data->bpw_len / PCH_DMA_TRANS_SIZE; 1039 rem = PCH_DMA_TRANS_SIZE; 1040 } 1041 size = PCH_DMA_TRANS_SIZE; 1042 } else { 1043 num = 1; 1044 size = data->bpw_len; 1045 rem = data->bpw_len; 1046 } 1047 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n", 1048 __func__, num, size, rem); 1049 spin_lock_irqsave(&data->lock, flags); 1050 1051 /* set receive fifo threshold and transmit fifo threshold */ 1052 pch_spi_setclr_reg(data->master, PCH_SPCR, 1053 ((size - 1) << SPCR_RFIC_FIELD) | 1054 (PCH_TX_THOLD << SPCR_TFIC_FIELD), 1055 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS); 1056 1057 spin_unlock_irqrestore(&data->lock, flags); 1058 1059 /* RX */ 1060 dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 1061 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */ 1062 /* offset, length setting */ 1063 sg = dma->sg_rx_p; 1064 for (i = 0; i < num; i++, sg++) { 1065 if (i == (num - 2)) { 1066 sg->offset = size * i; 1067 sg->offset = sg->offset * (*bpw / 8); 1068 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem, 1069 sg->offset); 1070 sg_dma_len(sg) = rem; 1071 } else if (i == (num - 1)) { 1072 sg->offset = size * (i - 1) + rem; 1073 sg->offset = sg->offset * (*bpw / 8); 1074 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size, 1075 sg->offset); 1076 sg_dma_len(sg) = size; 1077 } else { 1078 sg->offset = size * i; 1079 sg->offset = sg->offset * (*bpw / 8); 1080 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size, 1081 sg->offset); 1082 sg_dma_len(sg) = size; 1083 } 1084 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset; 1085 } 1086 sg = dma->sg_rx_p; 1087 desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg, 1088 num, DMA_DEV_TO_MEM, 1089 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1090 if (!desc_rx) { 1091 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", 1092 __func__); 1093 return; 1094 } 1095 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE); 1096 desc_rx->callback = pch_dma_rx_complete; 1097 desc_rx->callback_param = data; 1098 dma->nent = num; 1099 dma->desc_rx = desc_rx; 1100 1101 /* Calculate Tx parameter for DMA transmitting */ 1102 if (data->bpw_len > PCH_MAX_FIFO_DEPTH) { 1103 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE; 1104 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) { 1105 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; 1106 rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head; 1107 } else { 1108 num = data->bpw_len / PCH_DMA_TRANS_SIZE; 1109 rem = data->bpw_len % PCH_DMA_TRANS_SIZE + 1110 PCH_DMA_TRANS_SIZE - head; 1111 } 1112 size = PCH_DMA_TRANS_SIZE; 1113 } else { 1114 num = 1; 1115 size = data->bpw_len; 1116 rem = data->bpw_len; 1117 head = 0; 1118 } 1119 1120 dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 1121 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */ 1122 /* offset, length setting */ 1123 sg = dma->sg_tx_p; 1124 for (i = 0; i < num; i++, sg++) { 1125 if (i == 0) { 1126 sg->offset = 0; 1127 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head, 1128 sg->offset); 1129 sg_dma_len(sg) = size + head; 1130 } else if (i == (num - 1)) { 1131 sg->offset = head + size * i; 1132 sg->offset = sg->offset * (*bpw / 8); 1133 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem, 1134 sg->offset); 1135 sg_dma_len(sg) = rem; 1136 } else { 1137 sg->offset = head + size * i; 1138 sg->offset = sg->offset * (*bpw / 8); 1139 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size, 1140 sg->offset); 1141 sg_dma_len(sg) = size; 1142 } 1143 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset; 1144 } 1145 sg = dma->sg_tx_p; 1146 desc_tx = dmaengine_prep_slave_sg(dma->chan_tx, 1147 sg, num, DMA_MEM_TO_DEV, 1148 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1149 if (!desc_tx) { 1150 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", 1151 __func__); 1152 return; 1153 } 1154 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE); 1155 desc_tx->callback = NULL; 1156 desc_tx->callback_param = data; 1157 dma->nent = num; 1158 dma->desc_tx = desc_tx; 1159 1160 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing " 1161 "0x2 to SSNXCR\n", __func__); 1162 1163 spin_lock_irqsave(&data->lock, flags); 1164 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); 1165 desc_rx->tx_submit(desc_rx); 1166 desc_tx->tx_submit(desc_tx); 1167 spin_unlock_irqrestore(&data->lock, flags); 1168 1169 /* reset transfer complete flag */ 1170 data->transfer_complete = false; 1171 } 1172 1173 static void pch_spi_process_messages(struct work_struct *pwork) 1174 { 1175 struct spi_message *pmsg, *tmp; 1176 struct pch_spi_data *data; 1177 int bpw; 1178 1179 data = container_of(pwork, struct pch_spi_data, work); 1180 dev_dbg(&data->master->dev, "%s data initialized\n", __func__); 1181 1182 spin_lock(&data->lock); 1183 /* check if suspend has been initiated;if yes flush queue */ 1184 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) { 1185 dev_dbg(&data->master->dev, 1186 "%s suspend/remove initiated, flushing queue\n", __func__); 1187 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) { 1188 pmsg->status = -EIO; 1189 1190 if (pmsg->complete) { 1191 spin_unlock(&data->lock); 1192 pmsg->complete(pmsg->context); 1193 spin_lock(&data->lock); 1194 } 1195 1196 /* delete from queue */ 1197 list_del_init(&pmsg->queue); 1198 } 1199 1200 spin_unlock(&data->lock); 1201 return; 1202 } 1203 1204 data->bcurrent_msg_processing = true; 1205 dev_dbg(&data->master->dev, 1206 "%s Set data->bcurrent_msg_processing= true\n", __func__); 1207 1208 /* Get the message from the queue and delete it from there. */ 1209 data->current_msg = list_entry(data->queue.next, struct spi_message, 1210 queue); 1211 1212 list_del_init(&data->current_msg->queue); 1213 1214 data->current_msg->status = 0; 1215 1216 pch_spi_select_chip(data, data->current_msg->spi); 1217 1218 spin_unlock(&data->lock); 1219 1220 if (data->use_dma) 1221 pch_spi_request_dma(data, 1222 data->current_msg->spi->bits_per_word); 1223 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL); 1224 do { 1225 int cnt; 1226 /* If we are already processing a message get the next 1227 transfer structure from the message otherwise retrieve 1228 the 1st transfer request from the message. */ 1229 spin_lock(&data->lock); 1230 if (data->cur_trans == NULL) { 1231 data->cur_trans = 1232 list_entry(data->current_msg->transfers.next, 1233 struct spi_transfer, transfer_list); 1234 dev_dbg(&data->master->dev, "%s " 1235 ":Getting 1st transfer message\n", __func__); 1236 } else { 1237 data->cur_trans = 1238 list_entry(data->cur_trans->transfer_list.next, 1239 struct spi_transfer, transfer_list); 1240 dev_dbg(&data->master->dev, "%s " 1241 ":Getting next transfer message\n", __func__); 1242 } 1243 spin_unlock(&data->lock); 1244 1245 if (!data->cur_trans->len) 1246 goto out; 1247 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1; 1248 data->save_total_len = data->cur_trans->len; 1249 if (data->use_dma) { 1250 int i; 1251 char *save_rx_buf = data->cur_trans->rx_buf; 1252 for (i = 0; i < cnt; i ++) { 1253 pch_spi_handle_dma(data, &bpw); 1254 if (!pch_spi_start_transfer(data)) { 1255 data->transfer_complete = true; 1256 data->current_msg->status = -EIO; 1257 data->current_msg->complete 1258 (data->current_msg->context); 1259 data->bcurrent_msg_processing = false; 1260 data->current_msg = NULL; 1261 data->cur_trans = NULL; 1262 goto out; 1263 } 1264 pch_spi_copy_rx_data_for_dma(data, bpw); 1265 } 1266 data->cur_trans->rx_buf = save_rx_buf; 1267 } else { 1268 pch_spi_set_tx(data, &bpw); 1269 pch_spi_set_ir(data); 1270 pch_spi_copy_rx_data(data, bpw); 1271 kfree(data->pkt_rx_buff); 1272 data->pkt_rx_buff = NULL; 1273 kfree(data->pkt_tx_buff); 1274 data->pkt_tx_buff = NULL; 1275 } 1276 /* increment message count */ 1277 data->cur_trans->len = data->save_total_len; 1278 data->current_msg->actual_length += data->cur_trans->len; 1279 1280 dev_dbg(&data->master->dev, 1281 "%s:data->current_msg->actual_length=%d\n", 1282 __func__, data->current_msg->actual_length); 1283 1284 /* check for delay */ 1285 if (data->cur_trans->delay_usecs) { 1286 dev_dbg(&data->master->dev, "%s:" 1287 "delay in usec=%d\n", __func__, 1288 data->cur_trans->delay_usecs); 1289 udelay(data->cur_trans->delay_usecs); 1290 } 1291 1292 spin_lock(&data->lock); 1293 1294 /* No more transfer in this message. */ 1295 if ((data->cur_trans->transfer_list.next) == 1296 &(data->current_msg->transfers)) { 1297 pch_spi_nomore_transfer(data); 1298 } 1299 1300 spin_unlock(&data->lock); 1301 1302 } while (data->cur_trans != NULL); 1303 1304 out: 1305 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH); 1306 if (data->use_dma) 1307 pch_spi_release_dma(data); 1308 } 1309 1310 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat, 1311 struct pch_spi_data *data) 1312 { 1313 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); 1314 1315 /* free workqueue */ 1316 if (data->wk != NULL) { 1317 destroy_workqueue(data->wk); 1318 data->wk = NULL; 1319 dev_dbg(&board_dat->pdev->dev, 1320 "%s destroy_workqueue invoked successfully\n", 1321 __func__); 1322 } 1323 } 1324 1325 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat, 1326 struct pch_spi_data *data) 1327 { 1328 int retval = 0; 1329 1330 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); 1331 1332 /* create workqueue */ 1333 data->wk = create_singlethread_workqueue(KBUILD_MODNAME); 1334 if (!data->wk) { 1335 dev_err(&board_dat->pdev->dev, 1336 "%s create_singlet hread_workqueue failed\n", __func__); 1337 retval = -EBUSY; 1338 goto err_return; 1339 } 1340 1341 /* reset PCH SPI h/w */ 1342 pch_spi_reset(data->master); 1343 dev_dbg(&board_dat->pdev->dev, 1344 "%s pch_spi_reset invoked successfully\n", __func__); 1345 1346 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__); 1347 1348 err_return: 1349 if (retval != 0) { 1350 dev_err(&board_dat->pdev->dev, 1351 "%s FAIL:invoking pch_spi_free_resources\n", __func__); 1352 pch_spi_free_resources(board_dat, data); 1353 } 1354 1355 dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval); 1356 1357 return retval; 1358 } 1359 1360 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat, 1361 struct pch_spi_data *data) 1362 { 1363 struct pch_spi_dma_ctrl *dma; 1364 1365 dma = &data->dma; 1366 if (dma->tx_buf_dma) 1367 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, 1368 dma->tx_buf_virt, dma->tx_buf_dma); 1369 if (dma->rx_buf_dma) 1370 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, 1371 dma->rx_buf_virt, dma->rx_buf_dma); 1372 return; 1373 } 1374 1375 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat, 1376 struct pch_spi_data *data) 1377 { 1378 struct pch_spi_dma_ctrl *dma; 1379 1380 dma = &data->dma; 1381 /* Get Consistent memory for Tx DMA */ 1382 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, 1383 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL); 1384 /* Get Consistent memory for Rx DMA */ 1385 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, 1386 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL); 1387 } 1388 1389 static int pch_spi_pd_probe(struct platform_device *plat_dev) 1390 { 1391 int ret; 1392 struct spi_master *master; 1393 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); 1394 struct pch_spi_data *data; 1395 1396 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__); 1397 1398 master = spi_alloc_master(&board_dat->pdev->dev, 1399 sizeof(struct pch_spi_data)); 1400 if (!master) { 1401 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n", 1402 plat_dev->id); 1403 return -ENOMEM; 1404 } 1405 1406 data = spi_master_get_devdata(master); 1407 data->master = master; 1408 1409 platform_set_drvdata(plat_dev, data); 1410 1411 /* baseaddress + address offset) */ 1412 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) + 1413 PCH_ADDRESS_SIZE * plat_dev->id; 1414 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0); 1415 if (!data->io_remap_addr) { 1416 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__); 1417 ret = -ENOMEM; 1418 goto err_pci_iomap; 1419 } 1420 data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id; 1421 1422 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n", 1423 plat_dev->id, data->io_remap_addr); 1424 1425 /* initialize members of SPI master */ 1426 master->num_chipselect = PCH_MAX_CS; 1427 master->setup = pch_spi_setup; 1428 master->transfer = pch_spi_transfer; 1429 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 1430 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 1431 1432 data->board_dat = board_dat; 1433 data->plat_dev = plat_dev; 1434 data->n_curnt_chip = 255; 1435 data->status = STATUS_RUNNING; 1436 data->ch = plat_dev->id; 1437 data->use_dma = use_dma; 1438 1439 INIT_LIST_HEAD(&data->queue); 1440 spin_lock_init(&data->lock); 1441 INIT_WORK(&data->work, pch_spi_process_messages); 1442 init_waitqueue_head(&data->wait); 1443 1444 ret = pch_spi_get_resources(board_dat, data); 1445 if (ret) { 1446 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret); 1447 goto err_spi_get_resources; 1448 } 1449 1450 ret = request_irq(board_dat->pdev->irq, pch_spi_handler, 1451 IRQF_SHARED, KBUILD_MODNAME, data); 1452 if (ret) { 1453 dev_err(&plat_dev->dev, 1454 "%s request_irq failed\n", __func__); 1455 goto err_request_irq; 1456 } 1457 data->irq_reg_sts = true; 1458 1459 pch_spi_set_master_mode(master); 1460 1461 ret = spi_register_master(master); 1462 if (ret != 0) { 1463 dev_err(&plat_dev->dev, 1464 "%s spi_register_master FAILED\n", __func__); 1465 goto err_spi_register_master; 1466 } 1467 1468 if (use_dma) { 1469 dev_info(&plat_dev->dev, "Use DMA for data transfers\n"); 1470 pch_alloc_dma_buf(board_dat, data); 1471 } 1472 1473 return 0; 1474 1475 err_spi_register_master: 1476 free_irq(board_dat->pdev->irq, data); 1477 err_request_irq: 1478 pch_spi_free_resources(board_dat, data); 1479 err_spi_get_resources: 1480 pci_iounmap(board_dat->pdev, data->io_remap_addr); 1481 err_pci_iomap: 1482 spi_master_put(master); 1483 1484 return ret; 1485 } 1486 1487 static int pch_spi_pd_remove(struct platform_device *plat_dev) 1488 { 1489 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); 1490 struct pch_spi_data *data = platform_get_drvdata(plat_dev); 1491 int count; 1492 unsigned long flags; 1493 1494 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n", 1495 __func__, plat_dev->id, board_dat->pdev->irq); 1496 1497 if (use_dma) 1498 pch_free_dma_buf(board_dat, data); 1499 1500 /* check for any pending messages; no action is taken if the queue 1501 * is still full; but at least we tried. Unload anyway */ 1502 count = 500; 1503 spin_lock_irqsave(&data->lock, flags); 1504 data->status = STATUS_EXITING; 1505 while ((list_empty(&data->queue) == 0) && --count) { 1506 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n", 1507 __func__); 1508 spin_unlock_irqrestore(&data->lock, flags); 1509 msleep(PCH_SLEEP_TIME); 1510 spin_lock_irqsave(&data->lock, flags); 1511 } 1512 spin_unlock_irqrestore(&data->lock, flags); 1513 1514 pch_spi_free_resources(board_dat, data); 1515 /* disable interrupts & free IRQ */ 1516 if (data->irq_reg_sts) { 1517 /* disable interrupts */ 1518 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); 1519 data->irq_reg_sts = false; 1520 free_irq(board_dat->pdev->irq, data); 1521 } 1522 1523 pci_iounmap(board_dat->pdev, data->io_remap_addr); 1524 spi_unregister_master(data->master); 1525 1526 return 0; 1527 } 1528 #ifdef CONFIG_PM 1529 static int pch_spi_pd_suspend(struct platform_device *pd_dev, 1530 pm_message_t state) 1531 { 1532 u8 count; 1533 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); 1534 struct pch_spi_data *data = platform_get_drvdata(pd_dev); 1535 1536 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__); 1537 1538 if (!board_dat) { 1539 dev_err(&pd_dev->dev, 1540 "%s pci_get_drvdata returned NULL\n", __func__); 1541 return -EFAULT; 1542 } 1543 1544 /* check if the current message is processed: 1545 Only after thats done the transfer will be suspended */ 1546 count = 255; 1547 while ((--count) > 0) { 1548 if (!(data->bcurrent_msg_processing)) 1549 break; 1550 msleep(PCH_SLEEP_TIME); 1551 } 1552 1553 /* Free IRQ */ 1554 if (data->irq_reg_sts) { 1555 /* disable all interrupts */ 1556 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); 1557 pch_spi_reset(data->master); 1558 free_irq(board_dat->pdev->irq, data); 1559 1560 data->irq_reg_sts = false; 1561 dev_dbg(&pd_dev->dev, 1562 "%s free_irq invoked successfully.\n", __func__); 1563 } 1564 1565 return 0; 1566 } 1567 1568 static int pch_spi_pd_resume(struct platform_device *pd_dev) 1569 { 1570 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); 1571 struct pch_spi_data *data = platform_get_drvdata(pd_dev); 1572 int retval; 1573 1574 if (!board_dat) { 1575 dev_err(&pd_dev->dev, 1576 "%s pci_get_drvdata returned NULL\n", __func__); 1577 return -EFAULT; 1578 } 1579 1580 if (!data->irq_reg_sts) { 1581 /* register IRQ */ 1582 retval = request_irq(board_dat->pdev->irq, pch_spi_handler, 1583 IRQF_SHARED, KBUILD_MODNAME, data); 1584 if (retval < 0) { 1585 dev_err(&pd_dev->dev, 1586 "%s request_irq failed\n", __func__); 1587 return retval; 1588 } 1589 1590 /* reset PCH SPI h/w */ 1591 pch_spi_reset(data->master); 1592 pch_spi_set_master_mode(data->master); 1593 data->irq_reg_sts = true; 1594 } 1595 return 0; 1596 } 1597 #else 1598 #define pch_spi_pd_suspend NULL 1599 #define pch_spi_pd_resume NULL 1600 #endif 1601 1602 static struct platform_driver pch_spi_pd_driver = { 1603 .driver = { 1604 .name = "pch-spi", 1605 .owner = THIS_MODULE, 1606 }, 1607 .probe = pch_spi_pd_probe, 1608 .remove = pch_spi_pd_remove, 1609 .suspend = pch_spi_pd_suspend, 1610 .resume = pch_spi_pd_resume 1611 }; 1612 1613 static int pch_spi_probe(struct pci_dev *pdev, 1614 const struct pci_device_id *id) 1615 { 1616 struct pch_spi_board_data *board_dat; 1617 struct platform_device *pd_dev = NULL; 1618 int retval; 1619 int i; 1620 struct pch_pd_dev_save *pd_dev_save; 1621 1622 pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL); 1623 if (!pd_dev_save) { 1624 dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__); 1625 return -ENOMEM; 1626 } 1627 1628 board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL); 1629 if (!board_dat) { 1630 dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__); 1631 retval = -ENOMEM; 1632 goto err_no_mem; 1633 } 1634 1635 retval = pci_request_regions(pdev, KBUILD_MODNAME); 1636 if (retval) { 1637 dev_err(&pdev->dev, "%s request_region failed\n", __func__); 1638 goto pci_request_regions; 1639 } 1640 1641 board_dat->pdev = pdev; 1642 board_dat->num = id->driver_data; 1643 pd_dev_save->num = id->driver_data; 1644 pd_dev_save->board_dat = board_dat; 1645 1646 retval = pci_enable_device(pdev); 1647 if (retval) { 1648 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__); 1649 goto pci_enable_device; 1650 } 1651 1652 for (i = 0; i < board_dat->num; i++) { 1653 pd_dev = platform_device_alloc("pch-spi", i); 1654 if (!pd_dev) { 1655 dev_err(&pdev->dev, "platform_device_alloc failed\n"); 1656 retval = -ENOMEM; 1657 goto err_platform_device; 1658 } 1659 pd_dev_save->pd_save[i] = pd_dev; 1660 pd_dev->dev.parent = &pdev->dev; 1661 1662 retval = platform_device_add_data(pd_dev, board_dat, 1663 sizeof(*board_dat)); 1664 if (retval) { 1665 dev_err(&pdev->dev, 1666 "platform_device_add_data failed\n"); 1667 platform_device_put(pd_dev); 1668 goto err_platform_device; 1669 } 1670 1671 retval = platform_device_add(pd_dev); 1672 if (retval) { 1673 dev_err(&pdev->dev, "platform_device_add failed\n"); 1674 platform_device_put(pd_dev); 1675 goto err_platform_device; 1676 } 1677 } 1678 1679 pci_set_drvdata(pdev, pd_dev_save); 1680 1681 return 0; 1682 1683 err_platform_device: 1684 pci_disable_device(pdev); 1685 pci_enable_device: 1686 pci_release_regions(pdev); 1687 pci_request_regions: 1688 kfree(board_dat); 1689 err_no_mem: 1690 kfree(pd_dev_save); 1691 1692 return retval; 1693 } 1694 1695 static void pch_spi_remove(struct pci_dev *pdev) 1696 { 1697 int i; 1698 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); 1699 1700 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev); 1701 1702 for (i = 0; i < pd_dev_save->num; i++) 1703 platform_device_unregister(pd_dev_save->pd_save[i]); 1704 1705 pci_disable_device(pdev); 1706 pci_release_regions(pdev); 1707 kfree(pd_dev_save->board_dat); 1708 kfree(pd_dev_save); 1709 } 1710 1711 #ifdef CONFIG_PM 1712 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state) 1713 { 1714 int retval; 1715 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); 1716 1717 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__); 1718 1719 pd_dev_save->board_dat->suspend_sts = true; 1720 1721 /* save config space */ 1722 retval = pci_save_state(pdev); 1723 if (retval == 0) { 1724 pci_enable_wake(pdev, PCI_D3hot, 0); 1725 pci_disable_device(pdev); 1726 pci_set_power_state(pdev, PCI_D3hot); 1727 } else { 1728 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__); 1729 } 1730 1731 return retval; 1732 } 1733 1734 static int pch_spi_resume(struct pci_dev *pdev) 1735 { 1736 int retval; 1737 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); 1738 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__); 1739 1740 pci_set_power_state(pdev, PCI_D0); 1741 pci_restore_state(pdev); 1742 1743 retval = pci_enable_device(pdev); 1744 if (retval < 0) { 1745 dev_err(&pdev->dev, 1746 "%s pci_enable_device failed\n", __func__); 1747 } else { 1748 pci_enable_wake(pdev, PCI_D3hot, 0); 1749 1750 /* set suspend status to false */ 1751 pd_dev_save->board_dat->suspend_sts = false; 1752 } 1753 1754 return retval; 1755 } 1756 #else 1757 #define pch_spi_suspend NULL 1758 #define pch_spi_resume NULL 1759 1760 #endif 1761 1762 static struct pci_driver pch_spi_pcidev_driver = { 1763 .name = "pch_spi", 1764 .id_table = pch_spi_pcidev_id, 1765 .probe = pch_spi_probe, 1766 .remove = pch_spi_remove, 1767 .suspend = pch_spi_suspend, 1768 .resume = pch_spi_resume, 1769 }; 1770 1771 static int __init pch_spi_init(void) 1772 { 1773 int ret; 1774 ret = platform_driver_register(&pch_spi_pd_driver); 1775 if (ret) 1776 return ret; 1777 1778 ret = pci_register_driver(&pch_spi_pcidev_driver); 1779 if (ret) { 1780 platform_driver_unregister(&pch_spi_pd_driver); 1781 return ret; 1782 } 1783 1784 return 0; 1785 } 1786 module_init(pch_spi_init); 1787 1788 static void __exit pch_spi_exit(void) 1789 { 1790 pci_unregister_driver(&pch_spi_pcidev_driver); 1791 platform_driver_unregister(&pch_spi_pd_driver); 1792 } 1793 module_exit(pch_spi_exit); 1794 1795 module_param(use_dma, int, 0644); 1796 MODULE_PARM_DESC(use_dma, 1797 "to use DMA for data transfers pass 1 else 0; default 1"); 1798 1799 MODULE_LICENSE("GPL"); 1800 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver"); 1801 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id); 1802 1803