1 /* 2 * TI QSPI driver 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 5 * Author: Sourav Poddar <sourav.poddar@ti.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GPLv2. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/delay.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/dmaengine.h> 24 #include <linux/omap-dma.h> 25 #include <linux/platform_device.h> 26 #include <linux/err.h> 27 #include <linux/clk.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/pinctrl/consumer.h> 34 35 #include <linux/spi/spi.h> 36 37 struct ti_qspi_regs { 38 u32 clkctrl; 39 }; 40 41 struct ti_qspi { 42 struct completion transfer_complete; 43 44 /* list synchronization */ 45 struct mutex list_lock; 46 47 struct spi_master *master; 48 void __iomem *base; 49 void __iomem *ctrl_base; 50 void __iomem *mmap_base; 51 struct clk *fclk; 52 struct device *dev; 53 54 struct ti_qspi_regs ctx_reg; 55 56 u32 spi_max_frequency; 57 u32 cmd; 58 u32 dc; 59 60 bool ctrl_mod; 61 }; 62 63 #define QSPI_PID (0x0) 64 #define QSPI_SYSCONFIG (0x10) 65 #define QSPI_INTR_STATUS_RAW_SET (0x20) 66 #define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24) 67 #define QSPI_INTR_ENABLE_SET_REG (0x28) 68 #define QSPI_INTR_ENABLE_CLEAR_REG (0x2c) 69 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40) 70 #define QSPI_SPI_DC_REG (0x44) 71 #define QSPI_SPI_CMD_REG (0x48) 72 #define QSPI_SPI_STATUS_REG (0x4c) 73 #define QSPI_SPI_DATA_REG (0x50) 74 #define QSPI_SPI_SETUP0_REG (0x54) 75 #define QSPI_SPI_SWITCH_REG (0x64) 76 #define QSPI_SPI_SETUP1_REG (0x58) 77 #define QSPI_SPI_SETUP2_REG (0x5c) 78 #define QSPI_SPI_SETUP3_REG (0x60) 79 #define QSPI_SPI_DATA_REG_1 (0x68) 80 #define QSPI_SPI_DATA_REG_2 (0x6c) 81 #define QSPI_SPI_DATA_REG_3 (0x70) 82 83 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000) 84 85 #define QSPI_FCLK 192000000 86 87 /* Clock Control */ 88 #define QSPI_CLK_EN (1 << 31) 89 #define QSPI_CLK_DIV_MAX 0xffff 90 91 /* Command */ 92 #define QSPI_EN_CS(n) (n << 28) 93 #define QSPI_WLEN(n) ((n - 1) << 19) 94 #define QSPI_3_PIN (1 << 18) 95 #define QSPI_RD_SNGL (1 << 16) 96 #define QSPI_WR_SNGL (2 << 16) 97 #define QSPI_RD_DUAL (3 << 16) 98 #define QSPI_RD_QUAD (7 << 16) 99 #define QSPI_INVAL (4 << 16) 100 #define QSPI_WC_CMD_INT_EN (1 << 14) 101 #define QSPI_FLEN(n) ((n - 1) << 0) 102 103 /* STATUS REGISTER */ 104 #define WC 0x02 105 106 /* INTERRUPT REGISTER */ 107 #define QSPI_WC_INT_EN (1 << 1) 108 #define QSPI_WC_INT_DISABLE (1 << 1) 109 110 /* Device Control */ 111 #define QSPI_DD(m, n) (m << (3 + n * 8)) 112 #define QSPI_CKPHA(n) (1 << (2 + n * 8)) 113 #define QSPI_CSPOL(n) (1 << (1 + n * 8)) 114 #define QSPI_CKPOL(n) (1 << (n * 8)) 115 116 #define QSPI_FRAME 4096 117 118 #define QSPI_AUTOSUSPEND_TIMEOUT 2000 119 120 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, 121 unsigned long reg) 122 { 123 return readl(qspi->base + reg); 124 } 125 126 static inline void ti_qspi_write(struct ti_qspi *qspi, 127 unsigned long val, unsigned long reg) 128 { 129 writel(val, qspi->base + reg); 130 } 131 132 static int ti_qspi_setup(struct spi_device *spi) 133 { 134 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); 135 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; 136 int clk_div = 0, ret; 137 u32 clk_ctrl_reg, clk_rate, clk_mask; 138 139 if (spi->master->busy) { 140 dev_dbg(qspi->dev, "master busy doing other trasnfers\n"); 141 return -EBUSY; 142 } 143 144 if (!qspi->spi_max_frequency) { 145 dev_err(qspi->dev, "spi max frequency not defined\n"); 146 return -EINVAL; 147 } 148 149 clk_rate = clk_get_rate(qspi->fclk); 150 151 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1; 152 153 if (clk_div < 0) { 154 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n"); 155 return -EINVAL; 156 } 157 158 if (clk_div > QSPI_CLK_DIV_MAX) { 159 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n", 160 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1); 161 return -EINVAL; 162 } 163 164 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", 165 qspi->spi_max_frequency, clk_div); 166 167 ret = pm_runtime_get_sync(qspi->dev); 168 if (ret < 0) { 169 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); 170 return ret; 171 } 172 173 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); 174 175 clk_ctrl_reg &= ~QSPI_CLK_EN; 176 177 /* disable SCLK */ 178 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); 179 180 /* enable SCLK */ 181 clk_mask = QSPI_CLK_EN | clk_div; 182 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); 183 ctx_reg->clkctrl = clk_mask; 184 185 pm_runtime_mark_last_busy(qspi->dev); 186 ret = pm_runtime_put_autosuspend(qspi->dev); 187 if (ret < 0) { 188 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n"); 189 return ret; 190 } 191 192 return 0; 193 } 194 195 static void ti_qspi_restore_ctx(struct ti_qspi *qspi) 196 { 197 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; 198 199 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); 200 } 201 202 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t) 203 { 204 int wlen, count; 205 unsigned int cmd; 206 const u8 *txbuf; 207 208 txbuf = t->tx_buf; 209 cmd = qspi->cmd | QSPI_WR_SNGL; 210 count = t->len; 211 wlen = t->bits_per_word >> 3; /* in bytes */ 212 213 while (count) { 214 switch (wlen) { 215 case 1: 216 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", 217 cmd, qspi->dc, *txbuf); 218 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); 219 break; 220 case 2: 221 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", 222 cmd, qspi->dc, *txbuf); 223 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); 224 break; 225 case 4: 226 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", 227 cmd, qspi->dc, *txbuf); 228 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); 229 break; 230 } 231 232 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); 233 if (!wait_for_completion_timeout(&qspi->transfer_complete, 234 QSPI_COMPLETION_TIMEOUT)) { 235 dev_err(qspi->dev, "write timed out\n"); 236 return -ETIMEDOUT; 237 } 238 txbuf += wlen; 239 count -= wlen; 240 } 241 242 return 0; 243 } 244 245 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t) 246 { 247 int wlen, count; 248 unsigned int cmd; 249 u8 *rxbuf; 250 251 rxbuf = t->rx_buf; 252 cmd = qspi->cmd; 253 switch (t->rx_nbits) { 254 case SPI_NBITS_DUAL: 255 cmd |= QSPI_RD_DUAL; 256 break; 257 case SPI_NBITS_QUAD: 258 cmd |= QSPI_RD_QUAD; 259 break; 260 default: 261 cmd |= QSPI_RD_SNGL; 262 break; 263 } 264 count = t->len; 265 wlen = t->bits_per_word >> 3; /* in bytes */ 266 267 while (count) { 268 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); 269 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); 270 if (!wait_for_completion_timeout(&qspi->transfer_complete, 271 QSPI_COMPLETION_TIMEOUT)) { 272 dev_err(qspi->dev, "read timed out\n"); 273 return -ETIMEDOUT; 274 } 275 switch (wlen) { 276 case 1: 277 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG); 278 break; 279 case 2: 280 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); 281 break; 282 case 4: 283 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); 284 break; 285 } 286 rxbuf += wlen; 287 count -= wlen; 288 } 289 290 return 0; 291 } 292 293 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t) 294 { 295 int ret; 296 297 if (t->tx_buf) { 298 ret = qspi_write_msg(qspi, t); 299 if (ret) { 300 dev_dbg(qspi->dev, "Error while writing\n"); 301 return ret; 302 } 303 } 304 305 if (t->rx_buf) { 306 ret = qspi_read_msg(qspi, t); 307 if (ret) { 308 dev_dbg(qspi->dev, "Error while reading\n"); 309 return ret; 310 } 311 } 312 313 return 0; 314 } 315 316 static int ti_qspi_start_transfer_one(struct spi_master *master, 317 struct spi_message *m) 318 { 319 struct ti_qspi *qspi = spi_master_get_devdata(master); 320 struct spi_device *spi = m->spi; 321 struct spi_transfer *t; 322 int status = 0, ret; 323 int frame_length; 324 325 /* setup device control reg */ 326 qspi->dc = 0; 327 328 if (spi->mode & SPI_CPHA) 329 qspi->dc |= QSPI_CKPHA(spi->chip_select); 330 if (spi->mode & SPI_CPOL) 331 qspi->dc |= QSPI_CKPOL(spi->chip_select); 332 if (spi->mode & SPI_CS_HIGH) 333 qspi->dc |= QSPI_CSPOL(spi->chip_select); 334 335 frame_length = (m->frame_length << 3) / spi->bits_per_word; 336 337 frame_length = clamp(frame_length, 0, QSPI_FRAME); 338 339 /* setup command reg */ 340 qspi->cmd = 0; 341 qspi->cmd |= QSPI_EN_CS(spi->chip_select); 342 qspi->cmd |= QSPI_FLEN(frame_length); 343 qspi->cmd |= QSPI_WC_CMD_INT_EN; 344 345 ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG); 346 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); 347 348 mutex_lock(&qspi->list_lock); 349 350 list_for_each_entry(t, &m->transfers, transfer_list) { 351 qspi->cmd |= QSPI_WLEN(t->bits_per_word); 352 353 ret = qspi_transfer_msg(qspi, t); 354 if (ret) { 355 dev_dbg(qspi->dev, "transfer message failed\n"); 356 mutex_unlock(&qspi->list_lock); 357 return -EINVAL; 358 } 359 360 m->actual_length += t->len; 361 } 362 363 mutex_unlock(&qspi->list_lock); 364 365 m->status = status; 366 spi_finalize_current_message(master); 367 368 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG); 369 370 return status; 371 } 372 373 static irqreturn_t ti_qspi_isr(int irq, void *dev_id) 374 { 375 struct ti_qspi *qspi = dev_id; 376 u16 int_stat; 377 u32 stat; 378 379 irqreturn_t ret = IRQ_HANDLED; 380 381 int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR); 382 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); 383 384 if (!int_stat) { 385 dev_dbg(qspi->dev, "No IRQ triggered\n"); 386 ret = IRQ_NONE; 387 goto out; 388 } 389 390 ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, 391 QSPI_INTR_STATUS_ENABLED_CLEAR); 392 if (stat & WC) 393 complete(&qspi->transfer_complete); 394 out: 395 return ret; 396 } 397 398 static int ti_qspi_runtime_resume(struct device *dev) 399 { 400 struct ti_qspi *qspi; 401 402 qspi = dev_get_drvdata(dev); 403 ti_qspi_restore_ctx(qspi); 404 405 return 0; 406 } 407 408 static const struct of_device_id ti_qspi_match[] = { 409 {.compatible = "ti,dra7xxx-qspi" }, 410 {.compatible = "ti,am4372-qspi" }, 411 {}, 412 }; 413 MODULE_DEVICE_TABLE(of, ti_qspi_match); 414 415 static int ti_qspi_probe(struct platform_device *pdev) 416 { 417 struct ti_qspi *qspi; 418 struct spi_master *master; 419 struct resource *r, *res_ctrl, *res_mmap; 420 struct device_node *np = pdev->dev.of_node; 421 u32 max_freq; 422 int ret = 0, num_cs, irq; 423 424 master = spi_alloc_master(&pdev->dev, sizeof(*qspi)); 425 if (!master) 426 return -ENOMEM; 427 428 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD; 429 430 master->flags = SPI_MASTER_HALF_DUPLEX; 431 master->setup = ti_qspi_setup; 432 master->auto_runtime_pm = true; 433 master->transfer_one_message = ti_qspi_start_transfer_one; 434 master->dev.of_node = pdev->dev.of_node; 435 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 436 SPI_BPW_MASK(8); 437 438 if (!of_property_read_u32(np, "num-cs", &num_cs)) 439 master->num_chipselect = num_cs; 440 441 qspi = spi_master_get_devdata(master); 442 qspi->master = master; 443 qspi->dev = &pdev->dev; 444 platform_set_drvdata(pdev, qspi); 445 446 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base"); 447 if (r == NULL) { 448 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 449 if (r == NULL) { 450 dev_err(&pdev->dev, "missing platform data\n"); 451 return -ENODEV; 452 } 453 } 454 455 res_mmap = platform_get_resource_byname(pdev, 456 IORESOURCE_MEM, "qspi_mmap"); 457 if (res_mmap == NULL) { 458 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1); 459 if (res_mmap == NULL) { 460 dev_err(&pdev->dev, 461 "memory mapped resource not required\n"); 462 } 463 } 464 465 res_ctrl = platform_get_resource_byname(pdev, 466 IORESOURCE_MEM, "qspi_ctrlmod"); 467 if (res_ctrl == NULL) { 468 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2); 469 if (res_ctrl == NULL) { 470 dev_dbg(&pdev->dev, 471 "control module resources not required\n"); 472 } 473 } 474 475 irq = platform_get_irq(pdev, 0); 476 if (irq < 0) { 477 dev_err(&pdev->dev, "no irq resource?\n"); 478 return irq; 479 } 480 481 mutex_init(&qspi->list_lock); 482 483 qspi->base = devm_ioremap_resource(&pdev->dev, r); 484 if (IS_ERR(qspi->base)) { 485 ret = PTR_ERR(qspi->base); 486 goto free_master; 487 } 488 489 if (res_ctrl) { 490 qspi->ctrl_mod = true; 491 qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl); 492 if (IS_ERR(qspi->ctrl_base)) { 493 ret = PTR_ERR(qspi->ctrl_base); 494 goto free_master; 495 } 496 } 497 498 if (res_mmap) { 499 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); 500 if (IS_ERR(qspi->mmap_base)) { 501 ret = PTR_ERR(qspi->mmap_base); 502 goto free_master; 503 } 504 } 505 506 ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0, 507 dev_name(&pdev->dev), qspi); 508 if (ret < 0) { 509 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", 510 irq); 511 goto free_master; 512 } 513 514 qspi->fclk = devm_clk_get(&pdev->dev, "fck"); 515 if (IS_ERR(qspi->fclk)) { 516 ret = PTR_ERR(qspi->fclk); 517 dev_err(&pdev->dev, "could not get clk: %d\n", ret); 518 } 519 520 init_completion(&qspi->transfer_complete); 521 522 pm_runtime_use_autosuspend(&pdev->dev); 523 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT); 524 pm_runtime_enable(&pdev->dev); 525 526 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) 527 qspi->spi_max_frequency = max_freq; 528 529 ret = devm_spi_register_master(&pdev->dev, master); 530 if (ret) 531 goto free_master; 532 533 return 0; 534 535 free_master: 536 spi_master_put(master); 537 return ret; 538 } 539 540 static int ti_qspi_remove(struct platform_device *pdev) 541 { 542 struct ti_qspi *qspi = platform_get_drvdata(pdev); 543 int ret; 544 545 ret = pm_runtime_get_sync(qspi->dev); 546 if (ret < 0) { 547 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); 548 return ret; 549 } 550 551 ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG); 552 553 pm_runtime_put(qspi->dev); 554 pm_runtime_disable(&pdev->dev); 555 556 return 0; 557 } 558 559 static const struct dev_pm_ops ti_qspi_pm_ops = { 560 .runtime_resume = ti_qspi_runtime_resume, 561 }; 562 563 static struct platform_driver ti_qspi_driver = { 564 .probe = ti_qspi_probe, 565 .remove = ti_qspi_remove, 566 .driver = { 567 .name = "ti-qspi", 568 .pm = &ti_qspi_pm_ops, 569 .of_match_table = ti_qspi_match, 570 } 571 }; 572 573 module_platform_driver(ti_qspi_driver); 574 575 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>"); 576 MODULE_LICENSE("GPL v2"); 577 MODULE_DESCRIPTION("TI QSPI controller driver"); 578 MODULE_ALIAS("platform:ti-qspi"); 579