1 /* 2 * TI QSPI driver 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 5 * Author: Sourav Poddar <sourav.poddar@ti.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GPLv2. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/delay.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/dmaengine.h> 24 #include <linux/omap-dma.h> 25 #include <linux/platform_device.h> 26 #include <linux/err.h> 27 #include <linux/clk.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/pinctrl/consumer.h> 34 35 #include <linux/spi/spi.h> 36 37 struct ti_qspi_regs { 38 u32 clkctrl; 39 }; 40 41 struct ti_qspi { 42 struct completion transfer_complete; 43 44 /* list synchronization */ 45 struct mutex list_lock; 46 47 struct spi_master *master; 48 void __iomem *base; 49 void __iomem *ctrl_base; 50 void __iomem *mmap_base; 51 struct clk *fclk; 52 struct device *dev; 53 54 struct ti_qspi_regs ctx_reg; 55 56 u32 spi_max_frequency; 57 u32 cmd; 58 u32 dc; 59 60 bool ctrl_mod; 61 }; 62 63 #define QSPI_PID (0x0) 64 #define QSPI_SYSCONFIG (0x10) 65 #define QSPI_INTR_STATUS_RAW_SET (0x20) 66 #define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24) 67 #define QSPI_INTR_ENABLE_SET_REG (0x28) 68 #define QSPI_INTR_ENABLE_CLEAR_REG (0x2c) 69 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40) 70 #define QSPI_SPI_DC_REG (0x44) 71 #define QSPI_SPI_CMD_REG (0x48) 72 #define QSPI_SPI_STATUS_REG (0x4c) 73 #define QSPI_SPI_DATA_REG (0x50) 74 #define QSPI_SPI_SETUP0_REG (0x54) 75 #define QSPI_SPI_SWITCH_REG (0x64) 76 #define QSPI_SPI_SETUP1_REG (0x58) 77 #define QSPI_SPI_SETUP2_REG (0x5c) 78 #define QSPI_SPI_SETUP3_REG (0x60) 79 #define QSPI_SPI_DATA_REG_1 (0x68) 80 #define QSPI_SPI_DATA_REG_2 (0x6c) 81 #define QSPI_SPI_DATA_REG_3 (0x70) 82 83 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000) 84 85 #define QSPI_FCLK 192000000 86 87 /* Clock Control */ 88 #define QSPI_CLK_EN (1 << 31) 89 #define QSPI_CLK_DIV_MAX 0xffff 90 91 /* Command */ 92 #define QSPI_EN_CS(n) (n << 28) 93 #define QSPI_WLEN(n) ((n - 1) << 19) 94 #define QSPI_3_PIN (1 << 18) 95 #define QSPI_RD_SNGL (1 << 16) 96 #define QSPI_WR_SNGL (2 << 16) 97 #define QSPI_RD_DUAL (3 << 16) 98 #define QSPI_RD_QUAD (7 << 16) 99 #define QSPI_INVAL (4 << 16) 100 #define QSPI_WC_CMD_INT_EN (1 << 14) 101 #define QSPI_FLEN(n) ((n - 1) << 0) 102 #define QSPI_WLEN_MAX_BITS 128 103 #define QSPI_WLEN_MAX_BYTES 16 104 105 /* STATUS REGISTER */ 106 #define BUSY 0x01 107 #define WC 0x02 108 109 /* INTERRUPT REGISTER */ 110 #define QSPI_WC_INT_EN (1 << 1) 111 #define QSPI_WC_INT_DISABLE (1 << 1) 112 113 /* Device Control */ 114 #define QSPI_DD(m, n) (m << (3 + n * 8)) 115 #define QSPI_CKPHA(n) (1 << (2 + n * 8)) 116 #define QSPI_CSPOL(n) (1 << (1 + n * 8)) 117 #define QSPI_CKPOL(n) (1 << (n * 8)) 118 119 #define QSPI_FRAME 4096 120 121 #define QSPI_AUTOSUSPEND_TIMEOUT 2000 122 123 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, 124 unsigned long reg) 125 { 126 return readl(qspi->base + reg); 127 } 128 129 static inline void ti_qspi_write(struct ti_qspi *qspi, 130 unsigned long val, unsigned long reg) 131 { 132 writel(val, qspi->base + reg); 133 } 134 135 static int ti_qspi_setup(struct spi_device *spi) 136 { 137 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); 138 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; 139 int clk_div = 0, ret; 140 u32 clk_ctrl_reg, clk_rate, clk_mask; 141 142 if (spi->master->busy) { 143 dev_dbg(qspi->dev, "master busy doing other trasnfers\n"); 144 return -EBUSY; 145 } 146 147 if (!qspi->spi_max_frequency) { 148 dev_err(qspi->dev, "spi max frequency not defined\n"); 149 return -EINVAL; 150 } 151 152 clk_rate = clk_get_rate(qspi->fclk); 153 154 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1; 155 156 if (clk_div < 0) { 157 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n"); 158 return -EINVAL; 159 } 160 161 if (clk_div > QSPI_CLK_DIV_MAX) { 162 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n", 163 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1); 164 return -EINVAL; 165 } 166 167 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", 168 qspi->spi_max_frequency, clk_div); 169 170 ret = pm_runtime_get_sync(qspi->dev); 171 if (ret < 0) { 172 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); 173 return ret; 174 } 175 176 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); 177 178 clk_ctrl_reg &= ~QSPI_CLK_EN; 179 180 /* disable SCLK */ 181 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); 182 183 /* enable SCLK */ 184 clk_mask = QSPI_CLK_EN | clk_div; 185 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); 186 ctx_reg->clkctrl = clk_mask; 187 188 pm_runtime_mark_last_busy(qspi->dev); 189 ret = pm_runtime_put_autosuspend(qspi->dev); 190 if (ret < 0) { 191 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n"); 192 return ret; 193 } 194 195 return 0; 196 } 197 198 static void ti_qspi_restore_ctx(struct ti_qspi *qspi) 199 { 200 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; 201 202 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); 203 } 204 205 static inline u32 qspi_is_busy(struct ti_qspi *qspi) 206 { 207 u32 stat; 208 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT; 209 210 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); 211 while ((stat & BUSY) && time_after(timeout, jiffies)) { 212 cpu_relax(); 213 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); 214 } 215 216 WARN(stat & BUSY, "qspi busy\n"); 217 return stat & BUSY; 218 } 219 220 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t) 221 { 222 int wlen, count, xfer_len; 223 unsigned int cmd; 224 const u8 *txbuf; 225 u32 data; 226 227 txbuf = t->tx_buf; 228 cmd = qspi->cmd | QSPI_WR_SNGL; 229 count = t->len; 230 wlen = t->bits_per_word >> 3; /* in bytes */ 231 xfer_len = wlen; 232 233 while (count) { 234 if (qspi_is_busy(qspi)) 235 return -EBUSY; 236 237 switch (wlen) { 238 case 1: 239 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", 240 cmd, qspi->dc, *txbuf); 241 if (count >= QSPI_WLEN_MAX_BYTES) { 242 u32 *txp = (u32 *)txbuf; 243 244 data = cpu_to_be32(*txp++); 245 writel(data, qspi->base + 246 QSPI_SPI_DATA_REG_3); 247 data = cpu_to_be32(*txp++); 248 writel(data, qspi->base + 249 QSPI_SPI_DATA_REG_2); 250 data = cpu_to_be32(*txp++); 251 writel(data, qspi->base + 252 QSPI_SPI_DATA_REG_1); 253 data = cpu_to_be32(*txp++); 254 writel(data, qspi->base + 255 QSPI_SPI_DATA_REG); 256 xfer_len = QSPI_WLEN_MAX_BYTES; 257 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS); 258 } else { 259 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); 260 cmd = qspi->cmd | QSPI_WR_SNGL; 261 xfer_len = wlen; 262 cmd |= QSPI_WLEN(wlen); 263 } 264 break; 265 case 2: 266 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", 267 cmd, qspi->dc, *txbuf); 268 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); 269 break; 270 case 4: 271 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", 272 cmd, qspi->dc, *txbuf); 273 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); 274 break; 275 } 276 277 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); 278 if (!wait_for_completion_timeout(&qspi->transfer_complete, 279 QSPI_COMPLETION_TIMEOUT)) { 280 dev_err(qspi->dev, "write timed out\n"); 281 return -ETIMEDOUT; 282 } 283 txbuf += xfer_len; 284 count -= xfer_len; 285 } 286 287 return 0; 288 } 289 290 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t) 291 { 292 int wlen, count; 293 unsigned int cmd; 294 u8 *rxbuf; 295 296 rxbuf = t->rx_buf; 297 cmd = qspi->cmd; 298 switch (t->rx_nbits) { 299 case SPI_NBITS_DUAL: 300 cmd |= QSPI_RD_DUAL; 301 break; 302 case SPI_NBITS_QUAD: 303 cmd |= QSPI_RD_QUAD; 304 break; 305 default: 306 cmd |= QSPI_RD_SNGL; 307 break; 308 } 309 count = t->len; 310 wlen = t->bits_per_word >> 3; /* in bytes */ 311 312 while (count) { 313 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); 314 if (qspi_is_busy(qspi)) 315 return -EBUSY; 316 317 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); 318 if (!wait_for_completion_timeout(&qspi->transfer_complete, 319 QSPI_COMPLETION_TIMEOUT)) { 320 dev_err(qspi->dev, "read timed out\n"); 321 return -ETIMEDOUT; 322 } 323 switch (wlen) { 324 case 1: 325 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG); 326 break; 327 case 2: 328 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); 329 break; 330 case 4: 331 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); 332 break; 333 } 334 rxbuf += wlen; 335 count -= wlen; 336 } 337 338 return 0; 339 } 340 341 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t) 342 { 343 int ret; 344 345 if (t->tx_buf) { 346 ret = qspi_write_msg(qspi, t); 347 if (ret) { 348 dev_dbg(qspi->dev, "Error while writing\n"); 349 return ret; 350 } 351 } 352 353 if (t->rx_buf) { 354 ret = qspi_read_msg(qspi, t); 355 if (ret) { 356 dev_dbg(qspi->dev, "Error while reading\n"); 357 return ret; 358 } 359 } 360 361 return 0; 362 } 363 364 static int ti_qspi_start_transfer_one(struct spi_master *master, 365 struct spi_message *m) 366 { 367 struct ti_qspi *qspi = spi_master_get_devdata(master); 368 struct spi_device *spi = m->spi; 369 struct spi_transfer *t; 370 int status = 0, ret; 371 int frame_length; 372 373 /* setup device control reg */ 374 qspi->dc = 0; 375 376 if (spi->mode & SPI_CPHA) 377 qspi->dc |= QSPI_CKPHA(spi->chip_select); 378 if (spi->mode & SPI_CPOL) 379 qspi->dc |= QSPI_CKPOL(spi->chip_select); 380 if (spi->mode & SPI_CS_HIGH) 381 qspi->dc |= QSPI_CSPOL(spi->chip_select); 382 383 frame_length = (m->frame_length << 3) / spi->bits_per_word; 384 385 frame_length = clamp(frame_length, 0, QSPI_FRAME); 386 387 /* setup command reg */ 388 qspi->cmd = 0; 389 qspi->cmd |= QSPI_EN_CS(spi->chip_select); 390 qspi->cmd |= QSPI_FLEN(frame_length); 391 qspi->cmd |= QSPI_WC_CMD_INT_EN; 392 393 ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG); 394 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); 395 396 mutex_lock(&qspi->list_lock); 397 398 list_for_each_entry(t, &m->transfers, transfer_list) { 399 qspi->cmd |= QSPI_WLEN(t->bits_per_word); 400 401 ret = qspi_transfer_msg(qspi, t); 402 if (ret) { 403 dev_dbg(qspi->dev, "transfer message failed\n"); 404 mutex_unlock(&qspi->list_lock); 405 return -EINVAL; 406 } 407 408 m->actual_length += t->len; 409 } 410 411 mutex_unlock(&qspi->list_lock); 412 413 m->status = status; 414 spi_finalize_current_message(master); 415 416 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG); 417 418 return status; 419 } 420 421 static irqreturn_t ti_qspi_isr(int irq, void *dev_id) 422 { 423 struct ti_qspi *qspi = dev_id; 424 u16 int_stat; 425 u32 stat; 426 427 irqreturn_t ret = IRQ_HANDLED; 428 429 int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR); 430 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); 431 432 if (!int_stat) { 433 dev_dbg(qspi->dev, "No IRQ triggered\n"); 434 ret = IRQ_NONE; 435 goto out; 436 } 437 438 ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, 439 QSPI_INTR_STATUS_ENABLED_CLEAR); 440 if (stat & WC) 441 complete(&qspi->transfer_complete); 442 out: 443 return ret; 444 } 445 446 static int ti_qspi_runtime_resume(struct device *dev) 447 { 448 struct ti_qspi *qspi; 449 450 qspi = dev_get_drvdata(dev); 451 ti_qspi_restore_ctx(qspi); 452 453 return 0; 454 } 455 456 static const struct of_device_id ti_qspi_match[] = { 457 {.compatible = "ti,dra7xxx-qspi" }, 458 {.compatible = "ti,am4372-qspi" }, 459 {}, 460 }; 461 MODULE_DEVICE_TABLE(of, ti_qspi_match); 462 463 static int ti_qspi_probe(struct platform_device *pdev) 464 { 465 struct ti_qspi *qspi; 466 struct spi_master *master; 467 struct resource *r, *res_ctrl, *res_mmap; 468 struct device_node *np = pdev->dev.of_node; 469 u32 max_freq; 470 int ret = 0, num_cs, irq; 471 472 master = spi_alloc_master(&pdev->dev, sizeof(*qspi)); 473 if (!master) 474 return -ENOMEM; 475 476 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD; 477 478 master->flags = SPI_MASTER_HALF_DUPLEX; 479 master->setup = ti_qspi_setup; 480 master->auto_runtime_pm = true; 481 master->transfer_one_message = ti_qspi_start_transfer_one; 482 master->dev.of_node = pdev->dev.of_node; 483 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 484 SPI_BPW_MASK(8); 485 486 if (!of_property_read_u32(np, "num-cs", &num_cs)) 487 master->num_chipselect = num_cs; 488 489 qspi = spi_master_get_devdata(master); 490 qspi->master = master; 491 qspi->dev = &pdev->dev; 492 platform_set_drvdata(pdev, qspi); 493 494 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base"); 495 if (r == NULL) { 496 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 497 if (r == NULL) { 498 dev_err(&pdev->dev, "missing platform data\n"); 499 return -ENODEV; 500 } 501 } 502 503 res_mmap = platform_get_resource_byname(pdev, 504 IORESOURCE_MEM, "qspi_mmap"); 505 if (res_mmap == NULL) { 506 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1); 507 if (res_mmap == NULL) { 508 dev_err(&pdev->dev, 509 "memory mapped resource not required\n"); 510 } 511 } 512 513 res_ctrl = platform_get_resource_byname(pdev, 514 IORESOURCE_MEM, "qspi_ctrlmod"); 515 if (res_ctrl == NULL) { 516 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2); 517 if (res_ctrl == NULL) { 518 dev_dbg(&pdev->dev, 519 "control module resources not required\n"); 520 } 521 } 522 523 irq = platform_get_irq(pdev, 0); 524 if (irq < 0) { 525 dev_err(&pdev->dev, "no irq resource?\n"); 526 return irq; 527 } 528 529 mutex_init(&qspi->list_lock); 530 531 qspi->base = devm_ioremap_resource(&pdev->dev, r); 532 if (IS_ERR(qspi->base)) { 533 ret = PTR_ERR(qspi->base); 534 goto free_master; 535 } 536 537 if (res_ctrl) { 538 qspi->ctrl_mod = true; 539 qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl); 540 if (IS_ERR(qspi->ctrl_base)) { 541 ret = PTR_ERR(qspi->ctrl_base); 542 goto free_master; 543 } 544 } 545 546 if (res_mmap) { 547 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); 548 if (IS_ERR(qspi->mmap_base)) { 549 ret = PTR_ERR(qspi->mmap_base); 550 goto free_master; 551 } 552 } 553 554 ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0, 555 dev_name(&pdev->dev), qspi); 556 if (ret < 0) { 557 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", 558 irq); 559 goto free_master; 560 } 561 562 qspi->fclk = devm_clk_get(&pdev->dev, "fck"); 563 if (IS_ERR(qspi->fclk)) { 564 ret = PTR_ERR(qspi->fclk); 565 dev_err(&pdev->dev, "could not get clk: %d\n", ret); 566 } 567 568 init_completion(&qspi->transfer_complete); 569 570 pm_runtime_use_autosuspend(&pdev->dev); 571 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT); 572 pm_runtime_enable(&pdev->dev); 573 574 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) 575 qspi->spi_max_frequency = max_freq; 576 577 ret = devm_spi_register_master(&pdev->dev, master); 578 if (ret) 579 goto free_master; 580 581 return 0; 582 583 free_master: 584 spi_master_put(master); 585 return ret; 586 } 587 588 static int ti_qspi_remove(struct platform_device *pdev) 589 { 590 struct ti_qspi *qspi = platform_get_drvdata(pdev); 591 int ret; 592 593 ret = pm_runtime_get_sync(qspi->dev); 594 if (ret < 0) { 595 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); 596 return ret; 597 } 598 599 ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG); 600 601 pm_runtime_put(qspi->dev); 602 pm_runtime_disable(&pdev->dev); 603 604 return 0; 605 } 606 607 static const struct dev_pm_ops ti_qspi_pm_ops = { 608 .runtime_resume = ti_qspi_runtime_resume, 609 }; 610 611 static struct platform_driver ti_qspi_driver = { 612 .probe = ti_qspi_probe, 613 .remove = ti_qspi_remove, 614 .driver = { 615 .name = "ti-qspi", 616 .pm = &ti_qspi_pm_ops, 617 .of_match_table = ti_qspi_match, 618 } 619 }; 620 621 module_platform_driver(ti_qspi_driver); 622 623 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>"); 624 MODULE_LICENSE("GPL v2"); 625 MODULE_DESCRIPTION("TI QSPI controller driver"); 626 MODULE_ALIAS("platform:ti-qspi"); 627