1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller. 4 * 5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmapool.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/kthread.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_opp.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/reset.h> 26 #include <linux/spi/spi.h> 27 28 #include <soc/tegra/common.h> 29 30 #define SLINK_COMMAND 0x000 31 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) 32 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5) 33 #define SLINK_BOTH_EN (1 << 10) 34 #define SLINK_CS_SW (1 << 11) 35 #define SLINK_CS_VALUE (1 << 12) 36 #define SLINK_CS_POLARITY (1 << 13) 37 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16) 38 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16) 39 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16) 40 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16) 41 #define SLINK_IDLE_SDA_MASK (3 << 16) 42 #define SLINK_CS_POLARITY1 (1 << 20) 43 #define SLINK_CK_SDA (1 << 21) 44 #define SLINK_CS_POLARITY2 (1 << 22) 45 #define SLINK_CS_POLARITY3 (1 << 23) 46 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24) 47 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24) 48 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24) 49 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24) 50 #define SLINK_IDLE_SCLK_MASK (3 << 24) 51 #define SLINK_M_S (1 << 28) 52 #define SLINK_WAIT (1 << 29) 53 #define SLINK_GO (1 << 30) 54 #define SLINK_ENB (1 << 31) 55 56 #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA) 57 58 #define SLINK_COMMAND2 0x004 59 #define SLINK_LSBFE (1 << 0) 60 #define SLINK_SSOE (1 << 1) 61 #define SLINK_SPIE (1 << 4) 62 #define SLINK_BIDIROE (1 << 6) 63 #define SLINK_MODFEN (1 << 7) 64 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8) 65 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17) 66 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18) 67 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20) 68 #define SLINK_FIFO_REFILLS_0 (0 << 22) 69 #define SLINK_FIFO_REFILLS_1 (1 << 22) 70 #define SLINK_FIFO_REFILLS_2 (2 << 22) 71 #define SLINK_FIFO_REFILLS_3 (3 << 22) 72 #define SLINK_FIFO_REFILLS_MASK (3 << 22) 73 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26) 74 #define SLINK_SPC0 (1 << 29) 75 #define SLINK_TXEN (1 << 30) 76 #define SLINK_RXEN (1 << 31) 77 78 #define SLINK_STATUS 0x008 79 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f) 80 #define SLINK_WORD(val) (((val) >> 5) & 0x1f) 81 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff) 82 #define SLINK_MODF (1 << 16) 83 #define SLINK_RX_UNF (1 << 18) 84 #define SLINK_TX_OVF (1 << 19) 85 #define SLINK_TX_FULL (1 << 20) 86 #define SLINK_TX_EMPTY (1 << 21) 87 #define SLINK_RX_FULL (1 << 22) 88 #define SLINK_RX_EMPTY (1 << 23) 89 #define SLINK_TX_UNF (1 << 24) 90 #define SLINK_RX_OVF (1 << 25) 91 #define SLINK_TX_FLUSH (1 << 26) 92 #define SLINK_RX_FLUSH (1 << 27) 93 #define SLINK_SCLK (1 << 28) 94 #define SLINK_ERR (1 << 29) 95 #define SLINK_RDY (1 << 30) 96 #define SLINK_BSY (1 << 31) 97 #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \ 98 SLINK_TX_UNF | SLINK_RX_OVF) 99 100 #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY) 101 102 #define SLINK_MAS_DATA 0x010 103 #define SLINK_SLAVE_DATA 0x014 104 105 #define SLINK_DMA_CTL 0x018 106 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0) 107 #define SLINK_TX_TRIG_1 (0 << 16) 108 #define SLINK_TX_TRIG_4 (1 << 16) 109 #define SLINK_TX_TRIG_8 (2 << 16) 110 #define SLINK_TX_TRIG_16 (3 << 16) 111 #define SLINK_TX_TRIG_MASK (3 << 16) 112 #define SLINK_RX_TRIG_1 (0 << 18) 113 #define SLINK_RX_TRIG_4 (1 << 18) 114 #define SLINK_RX_TRIG_8 (2 << 18) 115 #define SLINK_RX_TRIG_16 (3 << 18) 116 #define SLINK_RX_TRIG_MASK (3 << 18) 117 #define SLINK_PACKED (1 << 20) 118 #define SLINK_PACK_SIZE_4 (0 << 21) 119 #define SLINK_PACK_SIZE_8 (1 << 21) 120 #define SLINK_PACK_SIZE_16 (2 << 21) 121 #define SLINK_PACK_SIZE_32 (3 << 21) 122 #define SLINK_PACK_SIZE_MASK (3 << 21) 123 #define SLINK_IE_TXC (1 << 26) 124 #define SLINK_IE_RXC (1 << 27) 125 #define SLINK_DMA_EN (1 << 31) 126 127 #define SLINK_STATUS2 0x01c 128 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0) 129 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16) 130 #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6) 131 132 #define SLINK_TX_FIFO 0x100 133 #define SLINK_RX_FIFO 0x180 134 135 #define DATA_DIR_TX (1 << 0) 136 #define DATA_DIR_RX (1 << 1) 137 138 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000)) 139 140 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024) 141 #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20) 142 #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0) 143 144 #define SLINK_STATUS2_RESET \ 145 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16) 146 147 #define MAX_CHIP_SELECT 4 148 #define SLINK_FIFO_DEPTH 32 149 150 struct tegra_slink_chip_data { 151 bool cs_hold_time; 152 }; 153 154 struct tegra_slink_data { 155 struct device *dev; 156 struct spi_master *master; 157 const struct tegra_slink_chip_data *chip_data; 158 spinlock_t lock; 159 160 struct clk *clk; 161 struct reset_control *rst; 162 void __iomem *base; 163 phys_addr_t phys; 164 unsigned irq; 165 u32 cur_speed; 166 167 struct spi_device *cur_spi; 168 unsigned cur_pos; 169 unsigned cur_len; 170 unsigned words_per_32bit; 171 unsigned bytes_per_word; 172 unsigned curr_dma_words; 173 unsigned cur_direction; 174 175 unsigned cur_rx_pos; 176 unsigned cur_tx_pos; 177 178 unsigned dma_buf_size; 179 unsigned max_buf_size; 180 bool is_curr_dma_xfer; 181 182 struct completion rx_dma_complete; 183 struct completion tx_dma_complete; 184 185 u32 tx_status; 186 u32 rx_status; 187 u32 status_reg; 188 bool is_packed; 189 u32 packed_size; 190 191 u32 command_reg; 192 u32 command2_reg; 193 u32 dma_control_reg; 194 u32 def_command_reg; 195 u32 def_command2_reg; 196 197 struct completion xfer_completion; 198 struct spi_transfer *curr_xfer; 199 struct dma_chan *rx_dma_chan; 200 u32 *rx_dma_buf; 201 dma_addr_t rx_dma_phys; 202 struct dma_async_tx_descriptor *rx_dma_desc; 203 204 struct dma_chan *tx_dma_chan; 205 u32 *tx_dma_buf; 206 dma_addr_t tx_dma_phys; 207 struct dma_async_tx_descriptor *tx_dma_desc; 208 }; 209 210 static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi, 211 unsigned long reg) 212 { 213 return readl(tspi->base + reg); 214 } 215 216 static inline void tegra_slink_writel(struct tegra_slink_data *tspi, 217 u32 val, unsigned long reg) 218 { 219 writel(val, tspi->base + reg); 220 221 /* Read back register to make sure that register writes completed */ 222 if (reg != SLINK_TX_FIFO) 223 readl(tspi->base + SLINK_MAS_DATA); 224 } 225 226 static void tegra_slink_clear_status(struct tegra_slink_data *tspi) 227 { 228 u32 val_write; 229 230 tegra_slink_readl(tspi, SLINK_STATUS); 231 232 /* Write 1 to clear status register */ 233 val_write = SLINK_RDY | SLINK_FIFO_ERROR; 234 tegra_slink_writel(tspi, val_write, SLINK_STATUS); 235 } 236 237 static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi, 238 struct spi_transfer *t) 239 { 240 switch (tspi->bytes_per_word) { 241 case 0: 242 return SLINK_PACK_SIZE_4; 243 case 1: 244 return SLINK_PACK_SIZE_8; 245 case 2: 246 return SLINK_PACK_SIZE_16; 247 case 4: 248 return SLINK_PACK_SIZE_32; 249 default: 250 return 0; 251 } 252 } 253 254 static unsigned tegra_slink_calculate_curr_xfer_param( 255 struct spi_device *spi, struct tegra_slink_data *tspi, 256 struct spi_transfer *t) 257 { 258 unsigned remain_len = t->len - tspi->cur_pos; 259 unsigned max_word; 260 unsigned bits_per_word; 261 unsigned max_len; 262 unsigned total_fifo_words; 263 264 bits_per_word = t->bits_per_word; 265 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); 266 267 if (bits_per_word == 8 || bits_per_word == 16) { 268 tspi->is_packed = true; 269 tspi->words_per_32bit = 32/bits_per_word; 270 } else { 271 tspi->is_packed = false; 272 tspi->words_per_32bit = 1; 273 } 274 tspi->packed_size = tegra_slink_get_packed_size(tspi, t); 275 276 if (tspi->is_packed) { 277 max_len = min(remain_len, tspi->max_buf_size); 278 tspi->curr_dma_words = max_len/tspi->bytes_per_word; 279 total_fifo_words = max_len/4; 280 } else { 281 max_word = (remain_len - 1) / tspi->bytes_per_word + 1; 282 max_word = min(max_word, tspi->max_buf_size/4); 283 tspi->curr_dma_words = max_word; 284 total_fifo_words = max_word; 285 } 286 return total_fifo_words; 287 } 288 289 static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf( 290 struct tegra_slink_data *tspi, struct spi_transfer *t) 291 { 292 unsigned nbytes; 293 unsigned tx_empty_count; 294 u32 fifo_status; 295 unsigned max_n_32bit; 296 unsigned i, count; 297 unsigned int written_words; 298 unsigned fifo_words_left; 299 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 300 301 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); 302 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status); 303 304 if (tspi->is_packed) { 305 fifo_words_left = tx_empty_count * tspi->words_per_32bit; 306 written_words = min(fifo_words_left, tspi->curr_dma_words); 307 nbytes = written_words * tspi->bytes_per_word; 308 max_n_32bit = DIV_ROUND_UP(nbytes, 4); 309 for (count = 0; count < max_n_32bit; count++) { 310 u32 x = 0; 311 for (i = 0; (i < 4) && nbytes; i++, nbytes--) 312 x |= (u32)(*tx_buf++) << (i * 8); 313 tegra_slink_writel(tspi, x, SLINK_TX_FIFO); 314 } 315 } else { 316 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); 317 written_words = max_n_32bit; 318 nbytes = written_words * tspi->bytes_per_word; 319 for (count = 0; count < max_n_32bit; count++) { 320 u32 x = 0; 321 for (i = 0; nbytes && (i < tspi->bytes_per_word); 322 i++, nbytes--) 323 x |= (u32)(*tx_buf++) << (i * 8); 324 tegra_slink_writel(tspi, x, SLINK_TX_FIFO); 325 } 326 } 327 tspi->cur_tx_pos += written_words * tspi->bytes_per_word; 328 return written_words; 329 } 330 331 static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf( 332 struct tegra_slink_data *tspi, struct spi_transfer *t) 333 { 334 unsigned rx_full_count; 335 u32 fifo_status; 336 unsigned i, count; 337 unsigned int read_words = 0; 338 unsigned len; 339 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; 340 341 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); 342 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status); 343 if (tspi->is_packed) { 344 len = tspi->curr_dma_words * tspi->bytes_per_word; 345 for (count = 0; count < rx_full_count; count++) { 346 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); 347 for (i = 0; len && (i < 4); i++, len--) 348 *rx_buf++ = (x >> i*8) & 0xFF; 349 } 350 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 351 read_words += tspi->curr_dma_words; 352 } else { 353 for (count = 0; count < rx_full_count; count++) { 354 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); 355 for (i = 0; (i < tspi->bytes_per_word); i++) 356 *rx_buf++ = (x >> (i*8)) & 0xFF; 357 } 358 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; 359 read_words += rx_full_count; 360 } 361 return read_words; 362 } 363 364 static void tegra_slink_copy_client_txbuf_to_spi_txbuf( 365 struct tegra_slink_data *tspi, struct spi_transfer *t) 366 { 367 /* Make the dma buffer to read by cpu */ 368 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, 369 tspi->dma_buf_size, DMA_TO_DEVICE); 370 371 if (tspi->is_packed) { 372 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; 373 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); 374 } else { 375 unsigned int i; 376 unsigned int count; 377 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 378 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; 379 380 for (count = 0; count < tspi->curr_dma_words; count++) { 381 u32 x = 0; 382 for (i = 0; consume && (i < tspi->bytes_per_word); 383 i++, consume--) 384 x |= (u32)(*tx_buf++) << (i * 8); 385 tspi->tx_dma_buf[count] = x; 386 } 387 } 388 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 389 390 /* Make the dma buffer to read by dma */ 391 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, 392 tspi->dma_buf_size, DMA_TO_DEVICE); 393 } 394 395 static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf( 396 struct tegra_slink_data *tspi, struct spi_transfer *t) 397 { 398 unsigned len; 399 400 /* Make the dma buffer to read by cpu */ 401 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, 402 tspi->dma_buf_size, DMA_FROM_DEVICE); 403 404 if (tspi->is_packed) { 405 len = tspi->curr_dma_words * tspi->bytes_per_word; 406 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); 407 } else { 408 unsigned int i; 409 unsigned int count; 410 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; 411 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; 412 413 for (count = 0; count < tspi->curr_dma_words; count++) { 414 u32 x = tspi->rx_dma_buf[count] & rx_mask; 415 for (i = 0; (i < tspi->bytes_per_word); i++) 416 *rx_buf++ = (x >> (i*8)) & 0xFF; 417 } 418 } 419 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 420 421 /* Make the dma buffer to read by dma */ 422 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, 423 tspi->dma_buf_size, DMA_FROM_DEVICE); 424 } 425 426 static void tegra_slink_dma_complete(void *args) 427 { 428 struct completion *dma_complete = args; 429 430 complete(dma_complete); 431 } 432 433 static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len) 434 { 435 reinit_completion(&tspi->tx_dma_complete); 436 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, 437 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, 438 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 439 if (!tspi->tx_dma_desc) { 440 dev_err(tspi->dev, "Not able to get desc for Tx\n"); 441 return -EIO; 442 } 443 444 tspi->tx_dma_desc->callback = tegra_slink_dma_complete; 445 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; 446 447 dmaengine_submit(tspi->tx_dma_desc); 448 dma_async_issue_pending(tspi->tx_dma_chan); 449 return 0; 450 } 451 452 static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len) 453 { 454 reinit_completion(&tspi->rx_dma_complete); 455 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, 456 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, 457 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 458 if (!tspi->rx_dma_desc) { 459 dev_err(tspi->dev, "Not able to get desc for Rx\n"); 460 return -EIO; 461 } 462 463 tspi->rx_dma_desc->callback = tegra_slink_dma_complete; 464 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; 465 466 dmaengine_submit(tspi->rx_dma_desc); 467 dma_async_issue_pending(tspi->rx_dma_chan); 468 return 0; 469 } 470 471 static int tegra_slink_start_dma_based_transfer( 472 struct tegra_slink_data *tspi, struct spi_transfer *t) 473 { 474 u32 val; 475 unsigned int len; 476 int ret = 0; 477 u32 status; 478 479 /* Make sure that Rx and Tx fifo are empty */ 480 status = tegra_slink_readl(tspi, SLINK_STATUS); 481 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) { 482 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n", 483 (unsigned)status); 484 return -EIO; 485 } 486 487 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1); 488 val |= tspi->packed_size; 489 if (tspi->is_packed) 490 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, 491 4) * 4; 492 else 493 len = tspi->curr_dma_words * 4; 494 495 /* Set attention level based on length of transfer */ 496 if (len & 0xF) 497 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1; 498 else if (((len) >> 4) & 0x1) 499 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4; 500 else 501 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8; 502 503 if (tspi->cur_direction & DATA_DIR_TX) 504 val |= SLINK_IE_TXC; 505 506 if (tspi->cur_direction & DATA_DIR_RX) 507 val |= SLINK_IE_RXC; 508 509 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 510 tspi->dma_control_reg = val; 511 512 if (tspi->cur_direction & DATA_DIR_TX) { 513 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t); 514 wmb(); 515 ret = tegra_slink_start_tx_dma(tspi, len); 516 if (ret < 0) { 517 dev_err(tspi->dev, 518 "Starting tx dma failed, err %d\n", ret); 519 return ret; 520 } 521 522 /* Wait for tx fifo to be fill before starting slink */ 523 status = tegra_slink_readl(tspi, SLINK_STATUS); 524 while (!(status & SLINK_TX_FULL)) 525 status = tegra_slink_readl(tspi, SLINK_STATUS); 526 } 527 528 if (tspi->cur_direction & DATA_DIR_RX) { 529 /* Make the dma buffer to read by dma */ 530 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, 531 tspi->dma_buf_size, DMA_FROM_DEVICE); 532 533 ret = tegra_slink_start_rx_dma(tspi, len); 534 if (ret < 0) { 535 dev_err(tspi->dev, 536 "Starting rx dma failed, err %d\n", ret); 537 if (tspi->cur_direction & DATA_DIR_TX) 538 dmaengine_terminate_all(tspi->tx_dma_chan); 539 return ret; 540 } 541 } 542 tspi->is_curr_dma_xfer = true; 543 if (tspi->is_packed) { 544 val |= SLINK_PACKED; 545 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 546 /* HW need small delay after settign Packed mode */ 547 udelay(1); 548 } 549 tspi->dma_control_reg = val; 550 551 val |= SLINK_DMA_EN; 552 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 553 return ret; 554 } 555 556 static int tegra_slink_start_cpu_based_transfer( 557 struct tegra_slink_data *tspi, struct spi_transfer *t) 558 { 559 u32 val; 560 unsigned cur_words; 561 562 val = tspi->packed_size; 563 if (tspi->cur_direction & DATA_DIR_TX) 564 val |= SLINK_IE_TXC; 565 566 if (tspi->cur_direction & DATA_DIR_RX) 567 val |= SLINK_IE_RXC; 568 569 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 570 tspi->dma_control_reg = val; 571 572 if (tspi->cur_direction & DATA_DIR_TX) 573 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t); 574 else 575 cur_words = tspi->curr_dma_words; 576 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1); 577 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 578 tspi->dma_control_reg = val; 579 580 tspi->is_curr_dma_xfer = false; 581 if (tspi->is_packed) { 582 val |= SLINK_PACKED; 583 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 584 udelay(1); 585 wmb(); 586 } 587 tspi->dma_control_reg = val; 588 val |= SLINK_DMA_EN; 589 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 590 return 0; 591 } 592 593 static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi, 594 bool dma_to_memory) 595 { 596 struct dma_chan *dma_chan; 597 u32 *dma_buf; 598 dma_addr_t dma_phys; 599 int ret; 600 struct dma_slave_config dma_sconfig; 601 602 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); 603 if (IS_ERR(dma_chan)) 604 return dev_err_probe(tspi->dev, PTR_ERR(dma_chan), 605 "Dma channel is not available\n"); 606 607 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, 608 &dma_phys, GFP_KERNEL); 609 if (!dma_buf) { 610 dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); 611 dma_release_channel(dma_chan); 612 return -ENOMEM; 613 } 614 615 if (dma_to_memory) { 616 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; 617 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 618 dma_sconfig.src_maxburst = 0; 619 } else { 620 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO; 621 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 622 dma_sconfig.dst_maxburst = 0; 623 } 624 625 ret = dmaengine_slave_config(dma_chan, &dma_sconfig); 626 if (ret) 627 goto scrub; 628 if (dma_to_memory) { 629 tspi->rx_dma_chan = dma_chan; 630 tspi->rx_dma_buf = dma_buf; 631 tspi->rx_dma_phys = dma_phys; 632 } else { 633 tspi->tx_dma_chan = dma_chan; 634 tspi->tx_dma_buf = dma_buf; 635 tspi->tx_dma_phys = dma_phys; 636 } 637 return 0; 638 639 scrub: 640 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); 641 dma_release_channel(dma_chan); 642 return ret; 643 } 644 645 static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi, 646 bool dma_to_memory) 647 { 648 u32 *dma_buf; 649 dma_addr_t dma_phys; 650 struct dma_chan *dma_chan; 651 652 if (dma_to_memory) { 653 dma_buf = tspi->rx_dma_buf; 654 dma_chan = tspi->rx_dma_chan; 655 dma_phys = tspi->rx_dma_phys; 656 tspi->rx_dma_chan = NULL; 657 tspi->rx_dma_buf = NULL; 658 } else { 659 dma_buf = tspi->tx_dma_buf; 660 dma_chan = tspi->tx_dma_chan; 661 dma_phys = tspi->tx_dma_phys; 662 tspi->tx_dma_buf = NULL; 663 tspi->tx_dma_chan = NULL; 664 } 665 if (!dma_chan) 666 return; 667 668 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); 669 dma_release_channel(dma_chan); 670 } 671 672 static int tegra_slink_start_transfer_one(struct spi_device *spi, 673 struct spi_transfer *t) 674 { 675 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); 676 u32 speed; 677 u8 bits_per_word; 678 unsigned total_fifo_words; 679 int ret; 680 u32 command; 681 u32 command2; 682 683 bits_per_word = t->bits_per_word; 684 speed = t->speed_hz; 685 if (speed != tspi->cur_speed) { 686 dev_pm_opp_set_rate(tspi->dev, speed * 4); 687 tspi->cur_speed = speed; 688 } 689 690 tspi->cur_spi = spi; 691 tspi->cur_pos = 0; 692 tspi->cur_rx_pos = 0; 693 tspi->cur_tx_pos = 0; 694 tspi->curr_xfer = t; 695 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t); 696 697 command = tspi->command_reg; 698 command &= ~SLINK_BIT_LENGTH(~0); 699 command |= SLINK_BIT_LENGTH(bits_per_word - 1); 700 701 command2 = tspi->command2_reg; 702 command2 &= ~(SLINK_RXEN | SLINK_TXEN); 703 704 tspi->cur_direction = 0; 705 if (t->rx_buf) { 706 command2 |= SLINK_RXEN; 707 tspi->cur_direction |= DATA_DIR_RX; 708 } 709 if (t->tx_buf) { 710 command2 |= SLINK_TXEN; 711 tspi->cur_direction |= DATA_DIR_TX; 712 } 713 714 /* 715 * Writing to the command2 register bevore the command register prevents 716 * a spike in chip_select line 0. This selects the chip_select line 717 * before changing the chip_select value. 718 */ 719 tegra_slink_writel(tspi, command2, SLINK_COMMAND2); 720 tspi->command2_reg = command2; 721 722 tegra_slink_writel(tspi, command, SLINK_COMMAND); 723 tspi->command_reg = command; 724 725 if (total_fifo_words > SLINK_FIFO_DEPTH) 726 ret = tegra_slink_start_dma_based_transfer(tspi, t); 727 else 728 ret = tegra_slink_start_cpu_based_transfer(tspi, t); 729 return ret; 730 } 731 732 static int tegra_slink_setup(struct spi_device *spi) 733 { 734 static const u32 cs_pol_bit[MAX_CHIP_SELECT] = { 735 SLINK_CS_POLARITY, 736 SLINK_CS_POLARITY1, 737 SLINK_CS_POLARITY2, 738 SLINK_CS_POLARITY3, 739 }; 740 741 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); 742 u32 val; 743 unsigned long flags; 744 int ret; 745 746 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", 747 spi->bits_per_word, 748 spi->mode & SPI_CPOL ? "" : "~", 749 spi->mode & SPI_CPHA ? "" : "~", 750 spi->max_speed_hz); 751 752 ret = pm_runtime_get_sync(tspi->dev); 753 if (ret < 0) { 754 pm_runtime_put_noidle(tspi->dev); 755 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); 756 return ret; 757 } 758 759 spin_lock_irqsave(&tspi->lock, flags); 760 val = tspi->def_command_reg; 761 if (spi->mode & SPI_CS_HIGH) 762 val |= cs_pol_bit[spi->chip_select]; 763 else 764 val &= ~cs_pol_bit[spi->chip_select]; 765 tspi->def_command_reg = val; 766 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 767 spin_unlock_irqrestore(&tspi->lock, flags); 768 769 pm_runtime_put(tspi->dev); 770 return 0; 771 } 772 773 static int tegra_slink_prepare_message(struct spi_master *master, 774 struct spi_message *msg) 775 { 776 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 777 struct spi_device *spi = msg->spi; 778 779 tegra_slink_clear_status(tspi); 780 781 tspi->command_reg = tspi->def_command_reg; 782 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE; 783 784 tspi->command2_reg = tspi->def_command2_reg; 785 tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select); 786 787 tspi->command_reg &= ~SLINK_MODES; 788 if (spi->mode & SPI_CPHA) 789 tspi->command_reg |= SLINK_CK_SDA; 790 791 if (spi->mode & SPI_CPOL) 792 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH; 793 else 794 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW; 795 796 return 0; 797 } 798 799 static int tegra_slink_transfer_one(struct spi_master *master, 800 struct spi_device *spi, 801 struct spi_transfer *xfer) 802 { 803 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 804 int ret; 805 806 reinit_completion(&tspi->xfer_completion); 807 ret = tegra_slink_start_transfer_one(spi, xfer); 808 if (ret < 0) { 809 dev_err(tspi->dev, 810 "spi can not start transfer, err %d\n", ret); 811 return ret; 812 } 813 814 ret = wait_for_completion_timeout(&tspi->xfer_completion, 815 SLINK_DMA_TIMEOUT); 816 if (WARN_ON(ret == 0)) { 817 dev_err(tspi->dev, 818 "spi transfer timeout, err %d\n", ret); 819 return -EIO; 820 } 821 822 if (tspi->tx_status) 823 return tspi->tx_status; 824 if (tspi->rx_status) 825 return tspi->rx_status; 826 827 return 0; 828 } 829 830 static int tegra_slink_unprepare_message(struct spi_master *master, 831 struct spi_message *msg) 832 { 833 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 834 835 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 836 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); 837 838 return 0; 839 } 840 841 static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi) 842 { 843 struct spi_transfer *t = tspi->curr_xfer; 844 unsigned long flags; 845 846 spin_lock_irqsave(&tspi->lock, flags); 847 if (tspi->tx_status || tspi->rx_status || 848 (tspi->status_reg & SLINK_BSY)) { 849 dev_err(tspi->dev, 850 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg); 851 dev_err(tspi->dev, 852 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 853 tspi->command2_reg, tspi->dma_control_reg); 854 reset_control_assert(tspi->rst); 855 udelay(2); 856 reset_control_deassert(tspi->rst); 857 complete(&tspi->xfer_completion); 858 goto exit; 859 } 860 861 if (tspi->cur_direction & DATA_DIR_RX) 862 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t); 863 864 if (tspi->cur_direction & DATA_DIR_TX) 865 tspi->cur_pos = tspi->cur_tx_pos; 866 else 867 tspi->cur_pos = tspi->cur_rx_pos; 868 869 if (tspi->cur_pos == t->len) { 870 complete(&tspi->xfer_completion); 871 goto exit; 872 } 873 874 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); 875 tegra_slink_start_cpu_based_transfer(tspi, t); 876 exit: 877 spin_unlock_irqrestore(&tspi->lock, flags); 878 return IRQ_HANDLED; 879 } 880 881 static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi) 882 { 883 struct spi_transfer *t = tspi->curr_xfer; 884 long wait_status; 885 int err = 0; 886 unsigned total_fifo_words; 887 unsigned long flags; 888 889 /* Abort dmas if any error */ 890 if (tspi->cur_direction & DATA_DIR_TX) { 891 if (tspi->tx_status) { 892 dmaengine_terminate_all(tspi->tx_dma_chan); 893 err += 1; 894 } else { 895 wait_status = wait_for_completion_interruptible_timeout( 896 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT); 897 if (wait_status <= 0) { 898 dmaengine_terminate_all(tspi->tx_dma_chan); 899 dev_err(tspi->dev, "TxDma Xfer failed\n"); 900 err += 1; 901 } 902 } 903 } 904 905 if (tspi->cur_direction & DATA_DIR_RX) { 906 if (tspi->rx_status) { 907 dmaengine_terminate_all(tspi->rx_dma_chan); 908 err += 2; 909 } else { 910 wait_status = wait_for_completion_interruptible_timeout( 911 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT); 912 if (wait_status <= 0) { 913 dmaengine_terminate_all(tspi->rx_dma_chan); 914 dev_err(tspi->dev, "RxDma Xfer failed\n"); 915 err += 2; 916 } 917 } 918 } 919 920 spin_lock_irqsave(&tspi->lock, flags); 921 if (err) { 922 dev_err(tspi->dev, 923 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg); 924 dev_err(tspi->dev, 925 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 926 tspi->command2_reg, tspi->dma_control_reg); 927 reset_control_assert(tspi->rst); 928 udelay(2); 929 reset_control_assert(tspi->rst); 930 complete(&tspi->xfer_completion); 931 spin_unlock_irqrestore(&tspi->lock, flags); 932 return IRQ_HANDLED; 933 } 934 935 if (tspi->cur_direction & DATA_DIR_RX) 936 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t); 937 938 if (tspi->cur_direction & DATA_DIR_TX) 939 tspi->cur_pos = tspi->cur_tx_pos; 940 else 941 tspi->cur_pos = tspi->cur_rx_pos; 942 943 if (tspi->cur_pos == t->len) { 944 complete(&tspi->xfer_completion); 945 goto exit; 946 } 947 948 /* Continue transfer in current message */ 949 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, 950 tspi, t); 951 if (total_fifo_words > SLINK_FIFO_DEPTH) 952 err = tegra_slink_start_dma_based_transfer(tspi, t); 953 else 954 err = tegra_slink_start_cpu_based_transfer(tspi, t); 955 956 exit: 957 spin_unlock_irqrestore(&tspi->lock, flags); 958 return IRQ_HANDLED; 959 } 960 961 static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data) 962 { 963 struct tegra_slink_data *tspi = context_data; 964 965 if (!tspi->is_curr_dma_xfer) 966 return handle_cpu_based_xfer(tspi); 967 return handle_dma_based_xfer(tspi); 968 } 969 970 static irqreturn_t tegra_slink_isr(int irq, void *context_data) 971 { 972 struct tegra_slink_data *tspi = context_data; 973 974 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS); 975 if (tspi->cur_direction & DATA_DIR_TX) 976 tspi->tx_status = tspi->status_reg & 977 (SLINK_TX_OVF | SLINK_TX_UNF); 978 979 if (tspi->cur_direction & DATA_DIR_RX) 980 tspi->rx_status = tspi->status_reg & 981 (SLINK_RX_OVF | SLINK_RX_UNF); 982 tegra_slink_clear_status(tspi); 983 984 return IRQ_WAKE_THREAD; 985 } 986 987 static const struct tegra_slink_chip_data tegra30_spi_cdata = { 988 .cs_hold_time = true, 989 }; 990 991 static const struct tegra_slink_chip_data tegra20_spi_cdata = { 992 .cs_hold_time = false, 993 }; 994 995 static const struct of_device_id tegra_slink_of_match[] = { 996 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, }, 997 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, }, 998 {} 999 }; 1000 MODULE_DEVICE_TABLE(of, tegra_slink_of_match); 1001 1002 static int tegra_slink_probe(struct platform_device *pdev) 1003 { 1004 struct spi_master *master; 1005 struct tegra_slink_data *tspi; 1006 struct resource *r; 1007 int ret, spi_irq; 1008 const struct tegra_slink_chip_data *cdata = NULL; 1009 1010 cdata = of_device_get_match_data(&pdev->dev); 1011 1012 master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); 1013 if (!master) { 1014 dev_err(&pdev->dev, "master allocation failed\n"); 1015 return -ENOMEM; 1016 } 1017 1018 /* the spi->mode bits understood by this driver: */ 1019 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1020 master->setup = tegra_slink_setup; 1021 master->prepare_message = tegra_slink_prepare_message; 1022 master->transfer_one = tegra_slink_transfer_one; 1023 master->unprepare_message = tegra_slink_unprepare_message; 1024 master->auto_runtime_pm = true; 1025 master->num_chipselect = MAX_CHIP_SELECT; 1026 1027 platform_set_drvdata(pdev, master); 1028 tspi = spi_master_get_devdata(master); 1029 tspi->master = master; 1030 tspi->dev = &pdev->dev; 1031 tspi->chip_data = cdata; 1032 spin_lock_init(&tspi->lock); 1033 1034 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency", 1035 &master->max_speed_hz)) 1036 master->max_speed_hz = 25000000; /* 25MHz */ 1037 1038 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1039 if (!r) { 1040 dev_err(&pdev->dev, "No IO memory resource\n"); 1041 ret = -ENODEV; 1042 goto exit_free_master; 1043 } 1044 tspi->phys = r->start; 1045 tspi->base = devm_ioremap_resource(&pdev->dev, r); 1046 if (IS_ERR(tspi->base)) { 1047 ret = PTR_ERR(tspi->base); 1048 goto exit_free_master; 1049 } 1050 1051 /* disabled clock may cause interrupt storm upon request */ 1052 tspi->clk = devm_clk_get(&pdev->dev, NULL); 1053 if (IS_ERR(tspi->clk)) { 1054 ret = PTR_ERR(tspi->clk); 1055 dev_err(&pdev->dev, "Can not get clock %d\n", ret); 1056 goto exit_free_master; 1057 } 1058 1059 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); 1060 if (IS_ERR(tspi->rst)) { 1061 dev_err(&pdev->dev, "can not get reset\n"); 1062 ret = PTR_ERR(tspi->rst); 1063 goto exit_free_master; 1064 } 1065 1066 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 1067 if (ret) 1068 goto exit_free_master; 1069 1070 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; 1071 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; 1072 1073 ret = tegra_slink_init_dma_param(tspi, true); 1074 if (ret < 0) 1075 goto exit_free_master; 1076 ret = tegra_slink_init_dma_param(tspi, false); 1077 if (ret < 0) 1078 goto exit_rx_dma_free; 1079 tspi->max_buf_size = tspi->dma_buf_size; 1080 init_completion(&tspi->tx_dma_complete); 1081 init_completion(&tspi->rx_dma_complete); 1082 1083 init_completion(&tspi->xfer_completion); 1084 1085 pm_runtime_enable(&pdev->dev); 1086 ret = pm_runtime_resume_and_get(&pdev->dev); 1087 if (ret) { 1088 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); 1089 goto exit_pm_disable; 1090 } 1091 1092 reset_control_assert(tspi->rst); 1093 udelay(2); 1094 reset_control_deassert(tspi->rst); 1095 1096 spi_irq = platform_get_irq(pdev, 0); 1097 tspi->irq = spi_irq; 1098 ret = request_threaded_irq(tspi->irq, tegra_slink_isr, 1099 tegra_slink_isr_thread, IRQF_ONESHOT, 1100 dev_name(&pdev->dev), tspi); 1101 if (ret < 0) { 1102 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", 1103 tspi->irq); 1104 goto exit_pm_put; 1105 } 1106 1107 tspi->def_command_reg = SLINK_M_S; 1108 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN; 1109 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 1110 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); 1111 1112 master->dev.of_node = pdev->dev.of_node; 1113 ret = spi_register_master(master); 1114 if (ret < 0) { 1115 dev_err(&pdev->dev, "can not register to master err %d\n", ret); 1116 goto exit_free_irq; 1117 } 1118 1119 pm_runtime_put(&pdev->dev); 1120 1121 return ret; 1122 1123 exit_free_irq: 1124 free_irq(spi_irq, tspi); 1125 exit_pm_put: 1126 pm_runtime_put(&pdev->dev); 1127 exit_pm_disable: 1128 pm_runtime_force_suspend(&pdev->dev); 1129 1130 tegra_slink_deinit_dma_param(tspi, false); 1131 exit_rx_dma_free: 1132 tegra_slink_deinit_dma_param(tspi, true); 1133 exit_free_master: 1134 spi_master_put(master); 1135 return ret; 1136 } 1137 1138 static int tegra_slink_remove(struct platform_device *pdev) 1139 { 1140 struct spi_master *master = platform_get_drvdata(pdev); 1141 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1142 1143 spi_unregister_master(master); 1144 1145 free_irq(tspi->irq, tspi); 1146 1147 pm_runtime_force_suspend(&pdev->dev); 1148 1149 if (tspi->tx_dma_chan) 1150 tegra_slink_deinit_dma_param(tspi, false); 1151 1152 if (tspi->rx_dma_chan) 1153 tegra_slink_deinit_dma_param(tspi, true); 1154 1155 return 0; 1156 } 1157 1158 #ifdef CONFIG_PM_SLEEP 1159 static int tegra_slink_suspend(struct device *dev) 1160 { 1161 struct spi_master *master = dev_get_drvdata(dev); 1162 1163 return spi_master_suspend(master); 1164 } 1165 1166 static int tegra_slink_resume(struct device *dev) 1167 { 1168 struct spi_master *master = dev_get_drvdata(dev); 1169 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1170 int ret; 1171 1172 ret = pm_runtime_get_sync(dev); 1173 if (ret < 0) { 1174 pm_runtime_put_noidle(dev); 1175 dev_err(dev, "pm runtime failed, e = %d\n", ret); 1176 return ret; 1177 } 1178 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND); 1179 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2); 1180 pm_runtime_put(dev); 1181 1182 return spi_master_resume(master); 1183 } 1184 #endif 1185 1186 static int __maybe_unused tegra_slink_runtime_suspend(struct device *dev) 1187 { 1188 struct spi_master *master = dev_get_drvdata(dev); 1189 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1190 1191 /* Flush all write which are in PPSB queue by reading back */ 1192 tegra_slink_readl(tspi, SLINK_MAS_DATA); 1193 1194 clk_disable_unprepare(tspi->clk); 1195 return 0; 1196 } 1197 1198 static int __maybe_unused tegra_slink_runtime_resume(struct device *dev) 1199 { 1200 struct spi_master *master = dev_get_drvdata(dev); 1201 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1202 int ret; 1203 1204 ret = clk_prepare_enable(tspi->clk); 1205 if (ret < 0) { 1206 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); 1207 return ret; 1208 } 1209 return 0; 1210 } 1211 1212 static const struct dev_pm_ops slink_pm_ops = { 1213 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend, 1214 tegra_slink_runtime_resume, NULL) 1215 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume) 1216 }; 1217 static struct platform_driver tegra_slink_driver = { 1218 .driver = { 1219 .name = "spi-tegra-slink", 1220 .pm = &slink_pm_ops, 1221 .of_match_table = tegra_slink_of_match, 1222 }, 1223 .probe = tegra_slink_probe, 1224 .remove = tegra_slink_remove, 1225 }; 1226 module_platform_driver(tegra_slink_driver); 1227 1228 MODULE_ALIAS("platform:spi-tegra-slink"); 1229 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver"); 1230 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1231 MODULE_LICENSE("GPL v2"); 1232