1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller. 4 * 5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmapool.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/kthread.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/reset.h> 25 #include <linux/spi/spi.h> 26 27 #define SLINK_COMMAND 0x000 28 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) 29 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5) 30 #define SLINK_BOTH_EN (1 << 10) 31 #define SLINK_CS_SW (1 << 11) 32 #define SLINK_CS_VALUE (1 << 12) 33 #define SLINK_CS_POLARITY (1 << 13) 34 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16) 35 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16) 36 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16) 37 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16) 38 #define SLINK_IDLE_SDA_MASK (3 << 16) 39 #define SLINK_CS_POLARITY1 (1 << 20) 40 #define SLINK_CK_SDA (1 << 21) 41 #define SLINK_CS_POLARITY2 (1 << 22) 42 #define SLINK_CS_POLARITY3 (1 << 23) 43 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24) 44 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24) 45 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24) 46 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24) 47 #define SLINK_IDLE_SCLK_MASK (3 << 24) 48 #define SLINK_M_S (1 << 28) 49 #define SLINK_WAIT (1 << 29) 50 #define SLINK_GO (1 << 30) 51 #define SLINK_ENB (1 << 31) 52 53 #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA) 54 55 #define SLINK_COMMAND2 0x004 56 #define SLINK_LSBFE (1 << 0) 57 #define SLINK_SSOE (1 << 1) 58 #define SLINK_SPIE (1 << 4) 59 #define SLINK_BIDIROE (1 << 6) 60 #define SLINK_MODFEN (1 << 7) 61 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8) 62 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17) 63 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18) 64 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20) 65 #define SLINK_FIFO_REFILLS_0 (0 << 22) 66 #define SLINK_FIFO_REFILLS_1 (1 << 22) 67 #define SLINK_FIFO_REFILLS_2 (2 << 22) 68 #define SLINK_FIFO_REFILLS_3 (3 << 22) 69 #define SLINK_FIFO_REFILLS_MASK (3 << 22) 70 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26) 71 #define SLINK_SPC0 (1 << 29) 72 #define SLINK_TXEN (1 << 30) 73 #define SLINK_RXEN (1 << 31) 74 75 #define SLINK_STATUS 0x008 76 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f) 77 #define SLINK_WORD(val) (((val) >> 5) & 0x1f) 78 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff) 79 #define SLINK_MODF (1 << 16) 80 #define SLINK_RX_UNF (1 << 18) 81 #define SLINK_TX_OVF (1 << 19) 82 #define SLINK_TX_FULL (1 << 20) 83 #define SLINK_TX_EMPTY (1 << 21) 84 #define SLINK_RX_FULL (1 << 22) 85 #define SLINK_RX_EMPTY (1 << 23) 86 #define SLINK_TX_UNF (1 << 24) 87 #define SLINK_RX_OVF (1 << 25) 88 #define SLINK_TX_FLUSH (1 << 26) 89 #define SLINK_RX_FLUSH (1 << 27) 90 #define SLINK_SCLK (1 << 28) 91 #define SLINK_ERR (1 << 29) 92 #define SLINK_RDY (1 << 30) 93 #define SLINK_BSY (1 << 31) 94 #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \ 95 SLINK_TX_UNF | SLINK_RX_OVF) 96 97 #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY) 98 99 #define SLINK_MAS_DATA 0x010 100 #define SLINK_SLAVE_DATA 0x014 101 102 #define SLINK_DMA_CTL 0x018 103 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0) 104 #define SLINK_TX_TRIG_1 (0 << 16) 105 #define SLINK_TX_TRIG_4 (1 << 16) 106 #define SLINK_TX_TRIG_8 (2 << 16) 107 #define SLINK_TX_TRIG_16 (3 << 16) 108 #define SLINK_TX_TRIG_MASK (3 << 16) 109 #define SLINK_RX_TRIG_1 (0 << 18) 110 #define SLINK_RX_TRIG_4 (1 << 18) 111 #define SLINK_RX_TRIG_8 (2 << 18) 112 #define SLINK_RX_TRIG_16 (3 << 18) 113 #define SLINK_RX_TRIG_MASK (3 << 18) 114 #define SLINK_PACKED (1 << 20) 115 #define SLINK_PACK_SIZE_4 (0 << 21) 116 #define SLINK_PACK_SIZE_8 (1 << 21) 117 #define SLINK_PACK_SIZE_16 (2 << 21) 118 #define SLINK_PACK_SIZE_32 (3 << 21) 119 #define SLINK_PACK_SIZE_MASK (3 << 21) 120 #define SLINK_IE_TXC (1 << 26) 121 #define SLINK_IE_RXC (1 << 27) 122 #define SLINK_DMA_EN (1 << 31) 123 124 #define SLINK_STATUS2 0x01c 125 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0) 126 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16) 127 #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6) 128 129 #define SLINK_TX_FIFO 0x100 130 #define SLINK_RX_FIFO 0x180 131 132 #define DATA_DIR_TX (1 << 0) 133 #define DATA_DIR_RX (1 << 1) 134 135 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000)) 136 137 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024) 138 #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20) 139 #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0) 140 141 #define SLINK_STATUS2_RESET \ 142 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16) 143 144 #define MAX_CHIP_SELECT 4 145 #define SLINK_FIFO_DEPTH 32 146 147 struct tegra_slink_chip_data { 148 bool cs_hold_time; 149 }; 150 151 struct tegra_slink_data { 152 struct device *dev; 153 struct spi_master *master; 154 const struct tegra_slink_chip_data *chip_data; 155 spinlock_t lock; 156 157 struct clk *clk; 158 struct reset_control *rst; 159 void __iomem *base; 160 phys_addr_t phys; 161 unsigned irq; 162 u32 cur_speed; 163 164 struct spi_device *cur_spi; 165 unsigned cur_pos; 166 unsigned cur_len; 167 unsigned words_per_32bit; 168 unsigned bytes_per_word; 169 unsigned curr_dma_words; 170 unsigned cur_direction; 171 172 unsigned cur_rx_pos; 173 unsigned cur_tx_pos; 174 175 unsigned dma_buf_size; 176 unsigned max_buf_size; 177 bool is_curr_dma_xfer; 178 179 struct completion rx_dma_complete; 180 struct completion tx_dma_complete; 181 182 u32 tx_status; 183 u32 rx_status; 184 u32 status_reg; 185 bool is_packed; 186 u32 packed_size; 187 188 u32 command_reg; 189 u32 command2_reg; 190 u32 dma_control_reg; 191 u32 def_command_reg; 192 u32 def_command2_reg; 193 194 struct completion xfer_completion; 195 struct spi_transfer *curr_xfer; 196 struct dma_chan *rx_dma_chan; 197 u32 *rx_dma_buf; 198 dma_addr_t rx_dma_phys; 199 struct dma_async_tx_descriptor *rx_dma_desc; 200 201 struct dma_chan *tx_dma_chan; 202 u32 *tx_dma_buf; 203 dma_addr_t tx_dma_phys; 204 struct dma_async_tx_descriptor *tx_dma_desc; 205 }; 206 207 static int tegra_slink_runtime_suspend(struct device *dev); 208 static int tegra_slink_runtime_resume(struct device *dev); 209 210 static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi, 211 unsigned long reg) 212 { 213 return readl(tspi->base + reg); 214 } 215 216 static inline void tegra_slink_writel(struct tegra_slink_data *tspi, 217 u32 val, unsigned long reg) 218 { 219 writel(val, tspi->base + reg); 220 221 /* Read back register to make sure that register writes completed */ 222 if (reg != SLINK_TX_FIFO) 223 readl(tspi->base + SLINK_MAS_DATA); 224 } 225 226 static void tegra_slink_clear_status(struct tegra_slink_data *tspi) 227 { 228 u32 val_write; 229 230 tegra_slink_readl(tspi, SLINK_STATUS); 231 232 /* Write 1 to clear status register */ 233 val_write = SLINK_RDY | SLINK_FIFO_ERROR; 234 tegra_slink_writel(tspi, val_write, SLINK_STATUS); 235 } 236 237 static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi, 238 struct spi_transfer *t) 239 { 240 switch (tspi->bytes_per_word) { 241 case 0: 242 return SLINK_PACK_SIZE_4; 243 case 1: 244 return SLINK_PACK_SIZE_8; 245 case 2: 246 return SLINK_PACK_SIZE_16; 247 case 4: 248 return SLINK_PACK_SIZE_32; 249 default: 250 return 0; 251 } 252 } 253 254 static unsigned tegra_slink_calculate_curr_xfer_param( 255 struct spi_device *spi, struct tegra_slink_data *tspi, 256 struct spi_transfer *t) 257 { 258 unsigned remain_len = t->len - tspi->cur_pos; 259 unsigned max_word; 260 unsigned bits_per_word; 261 unsigned max_len; 262 unsigned total_fifo_words; 263 264 bits_per_word = t->bits_per_word; 265 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); 266 267 if (bits_per_word == 8 || bits_per_word == 16) { 268 tspi->is_packed = true; 269 tspi->words_per_32bit = 32/bits_per_word; 270 } else { 271 tspi->is_packed = false; 272 tspi->words_per_32bit = 1; 273 } 274 tspi->packed_size = tegra_slink_get_packed_size(tspi, t); 275 276 if (tspi->is_packed) { 277 max_len = min(remain_len, tspi->max_buf_size); 278 tspi->curr_dma_words = max_len/tspi->bytes_per_word; 279 total_fifo_words = max_len/4; 280 } else { 281 max_word = (remain_len - 1) / tspi->bytes_per_word + 1; 282 max_word = min(max_word, tspi->max_buf_size/4); 283 tspi->curr_dma_words = max_word; 284 total_fifo_words = max_word; 285 } 286 return total_fifo_words; 287 } 288 289 static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf( 290 struct tegra_slink_data *tspi, struct spi_transfer *t) 291 { 292 unsigned nbytes; 293 unsigned tx_empty_count; 294 u32 fifo_status; 295 unsigned max_n_32bit; 296 unsigned i, count; 297 unsigned int written_words; 298 unsigned fifo_words_left; 299 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 300 301 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); 302 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status); 303 304 if (tspi->is_packed) { 305 fifo_words_left = tx_empty_count * tspi->words_per_32bit; 306 written_words = min(fifo_words_left, tspi->curr_dma_words); 307 nbytes = written_words * tspi->bytes_per_word; 308 max_n_32bit = DIV_ROUND_UP(nbytes, 4); 309 for (count = 0; count < max_n_32bit; count++) { 310 u32 x = 0; 311 for (i = 0; (i < 4) && nbytes; i++, nbytes--) 312 x |= (u32)(*tx_buf++) << (i * 8); 313 tegra_slink_writel(tspi, x, SLINK_TX_FIFO); 314 } 315 } else { 316 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); 317 written_words = max_n_32bit; 318 nbytes = written_words * tspi->bytes_per_word; 319 for (count = 0; count < max_n_32bit; count++) { 320 u32 x = 0; 321 for (i = 0; nbytes && (i < tspi->bytes_per_word); 322 i++, nbytes--) 323 x |= (u32)(*tx_buf++) << (i * 8); 324 tegra_slink_writel(tspi, x, SLINK_TX_FIFO); 325 } 326 } 327 tspi->cur_tx_pos += written_words * tspi->bytes_per_word; 328 return written_words; 329 } 330 331 static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf( 332 struct tegra_slink_data *tspi, struct spi_transfer *t) 333 { 334 unsigned rx_full_count; 335 u32 fifo_status; 336 unsigned i, count; 337 unsigned int read_words = 0; 338 unsigned len; 339 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; 340 341 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); 342 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status); 343 if (tspi->is_packed) { 344 len = tspi->curr_dma_words * tspi->bytes_per_word; 345 for (count = 0; count < rx_full_count; count++) { 346 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); 347 for (i = 0; len && (i < 4); i++, len--) 348 *rx_buf++ = (x >> i*8) & 0xFF; 349 } 350 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 351 read_words += tspi->curr_dma_words; 352 } else { 353 for (count = 0; count < rx_full_count; count++) { 354 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); 355 for (i = 0; (i < tspi->bytes_per_word); i++) 356 *rx_buf++ = (x >> (i*8)) & 0xFF; 357 } 358 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; 359 read_words += rx_full_count; 360 } 361 return read_words; 362 } 363 364 static void tegra_slink_copy_client_txbuf_to_spi_txbuf( 365 struct tegra_slink_data *tspi, struct spi_transfer *t) 366 { 367 /* Make the dma buffer to read by cpu */ 368 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, 369 tspi->dma_buf_size, DMA_TO_DEVICE); 370 371 if (tspi->is_packed) { 372 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; 373 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); 374 } else { 375 unsigned int i; 376 unsigned int count; 377 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 378 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; 379 380 for (count = 0; count < tspi->curr_dma_words; count++) { 381 u32 x = 0; 382 for (i = 0; consume && (i < tspi->bytes_per_word); 383 i++, consume--) 384 x |= (u32)(*tx_buf++) << (i * 8); 385 tspi->tx_dma_buf[count] = x; 386 } 387 } 388 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 389 390 /* Make the dma buffer to read by dma */ 391 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, 392 tspi->dma_buf_size, DMA_TO_DEVICE); 393 } 394 395 static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf( 396 struct tegra_slink_data *tspi, struct spi_transfer *t) 397 { 398 unsigned len; 399 400 /* Make the dma buffer to read by cpu */ 401 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, 402 tspi->dma_buf_size, DMA_FROM_DEVICE); 403 404 if (tspi->is_packed) { 405 len = tspi->curr_dma_words * tspi->bytes_per_word; 406 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); 407 } else { 408 unsigned int i; 409 unsigned int count; 410 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; 411 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; 412 413 for (count = 0; count < tspi->curr_dma_words; count++) { 414 u32 x = tspi->rx_dma_buf[count] & rx_mask; 415 for (i = 0; (i < tspi->bytes_per_word); i++) 416 *rx_buf++ = (x >> (i*8)) & 0xFF; 417 } 418 } 419 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 420 421 /* Make the dma buffer to read by dma */ 422 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, 423 tspi->dma_buf_size, DMA_FROM_DEVICE); 424 } 425 426 static void tegra_slink_dma_complete(void *args) 427 { 428 struct completion *dma_complete = args; 429 430 complete(dma_complete); 431 } 432 433 static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len) 434 { 435 reinit_completion(&tspi->tx_dma_complete); 436 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, 437 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, 438 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 439 if (!tspi->tx_dma_desc) { 440 dev_err(tspi->dev, "Not able to get desc for Tx\n"); 441 return -EIO; 442 } 443 444 tspi->tx_dma_desc->callback = tegra_slink_dma_complete; 445 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; 446 447 dmaengine_submit(tspi->tx_dma_desc); 448 dma_async_issue_pending(tspi->tx_dma_chan); 449 return 0; 450 } 451 452 static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len) 453 { 454 reinit_completion(&tspi->rx_dma_complete); 455 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, 456 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, 457 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 458 if (!tspi->rx_dma_desc) { 459 dev_err(tspi->dev, "Not able to get desc for Rx\n"); 460 return -EIO; 461 } 462 463 tspi->rx_dma_desc->callback = tegra_slink_dma_complete; 464 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; 465 466 dmaengine_submit(tspi->rx_dma_desc); 467 dma_async_issue_pending(tspi->rx_dma_chan); 468 return 0; 469 } 470 471 static int tegra_slink_start_dma_based_transfer( 472 struct tegra_slink_data *tspi, struct spi_transfer *t) 473 { 474 u32 val; 475 unsigned int len; 476 int ret = 0; 477 u32 status; 478 479 /* Make sure that Rx and Tx fifo are empty */ 480 status = tegra_slink_readl(tspi, SLINK_STATUS); 481 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) { 482 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n", 483 (unsigned)status); 484 return -EIO; 485 } 486 487 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1); 488 val |= tspi->packed_size; 489 if (tspi->is_packed) 490 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, 491 4) * 4; 492 else 493 len = tspi->curr_dma_words * 4; 494 495 /* Set attention level based on length of transfer */ 496 if (len & 0xF) 497 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1; 498 else if (((len) >> 4) & 0x1) 499 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4; 500 else 501 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8; 502 503 if (tspi->cur_direction & DATA_DIR_TX) 504 val |= SLINK_IE_TXC; 505 506 if (tspi->cur_direction & DATA_DIR_RX) 507 val |= SLINK_IE_RXC; 508 509 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 510 tspi->dma_control_reg = val; 511 512 if (tspi->cur_direction & DATA_DIR_TX) { 513 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t); 514 wmb(); 515 ret = tegra_slink_start_tx_dma(tspi, len); 516 if (ret < 0) { 517 dev_err(tspi->dev, 518 "Starting tx dma failed, err %d\n", ret); 519 return ret; 520 } 521 522 /* Wait for tx fifo to be fill before starting slink */ 523 status = tegra_slink_readl(tspi, SLINK_STATUS); 524 while (!(status & SLINK_TX_FULL)) 525 status = tegra_slink_readl(tspi, SLINK_STATUS); 526 } 527 528 if (tspi->cur_direction & DATA_DIR_RX) { 529 /* Make the dma buffer to read by dma */ 530 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, 531 tspi->dma_buf_size, DMA_FROM_DEVICE); 532 533 ret = tegra_slink_start_rx_dma(tspi, len); 534 if (ret < 0) { 535 dev_err(tspi->dev, 536 "Starting rx dma failed, err %d\n", ret); 537 if (tspi->cur_direction & DATA_DIR_TX) 538 dmaengine_terminate_all(tspi->tx_dma_chan); 539 return ret; 540 } 541 } 542 tspi->is_curr_dma_xfer = true; 543 if (tspi->is_packed) { 544 val |= SLINK_PACKED; 545 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 546 /* HW need small delay after settign Packed mode */ 547 udelay(1); 548 } 549 tspi->dma_control_reg = val; 550 551 val |= SLINK_DMA_EN; 552 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 553 return ret; 554 } 555 556 static int tegra_slink_start_cpu_based_transfer( 557 struct tegra_slink_data *tspi, struct spi_transfer *t) 558 { 559 u32 val; 560 unsigned cur_words; 561 562 val = tspi->packed_size; 563 if (tspi->cur_direction & DATA_DIR_TX) 564 val |= SLINK_IE_TXC; 565 566 if (tspi->cur_direction & DATA_DIR_RX) 567 val |= SLINK_IE_RXC; 568 569 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 570 tspi->dma_control_reg = val; 571 572 if (tspi->cur_direction & DATA_DIR_TX) 573 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t); 574 else 575 cur_words = tspi->curr_dma_words; 576 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1); 577 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 578 tspi->dma_control_reg = val; 579 580 tspi->is_curr_dma_xfer = false; 581 if (tspi->is_packed) { 582 val |= SLINK_PACKED; 583 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 584 udelay(1); 585 wmb(); 586 } 587 tspi->dma_control_reg = val; 588 val |= SLINK_DMA_EN; 589 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 590 return 0; 591 } 592 593 static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi, 594 bool dma_to_memory) 595 { 596 struct dma_chan *dma_chan; 597 u32 *dma_buf; 598 dma_addr_t dma_phys; 599 int ret; 600 struct dma_slave_config dma_sconfig; 601 602 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); 603 if (IS_ERR(dma_chan)) { 604 ret = PTR_ERR(dma_chan); 605 if (ret != -EPROBE_DEFER) 606 dev_err(tspi->dev, 607 "Dma channel is not available: %d\n", ret); 608 return ret; 609 } 610 611 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, 612 &dma_phys, GFP_KERNEL); 613 if (!dma_buf) { 614 dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); 615 dma_release_channel(dma_chan); 616 return -ENOMEM; 617 } 618 619 if (dma_to_memory) { 620 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; 621 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 622 dma_sconfig.src_maxburst = 0; 623 } else { 624 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO; 625 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 626 dma_sconfig.dst_maxburst = 0; 627 } 628 629 ret = dmaengine_slave_config(dma_chan, &dma_sconfig); 630 if (ret) 631 goto scrub; 632 if (dma_to_memory) { 633 tspi->rx_dma_chan = dma_chan; 634 tspi->rx_dma_buf = dma_buf; 635 tspi->rx_dma_phys = dma_phys; 636 } else { 637 tspi->tx_dma_chan = dma_chan; 638 tspi->tx_dma_buf = dma_buf; 639 tspi->tx_dma_phys = dma_phys; 640 } 641 return 0; 642 643 scrub: 644 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); 645 dma_release_channel(dma_chan); 646 return ret; 647 } 648 649 static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi, 650 bool dma_to_memory) 651 { 652 u32 *dma_buf; 653 dma_addr_t dma_phys; 654 struct dma_chan *dma_chan; 655 656 if (dma_to_memory) { 657 dma_buf = tspi->rx_dma_buf; 658 dma_chan = tspi->rx_dma_chan; 659 dma_phys = tspi->rx_dma_phys; 660 tspi->rx_dma_chan = NULL; 661 tspi->rx_dma_buf = NULL; 662 } else { 663 dma_buf = tspi->tx_dma_buf; 664 dma_chan = tspi->tx_dma_chan; 665 dma_phys = tspi->tx_dma_phys; 666 tspi->tx_dma_buf = NULL; 667 tspi->tx_dma_chan = NULL; 668 } 669 if (!dma_chan) 670 return; 671 672 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); 673 dma_release_channel(dma_chan); 674 } 675 676 static int tegra_slink_start_transfer_one(struct spi_device *spi, 677 struct spi_transfer *t) 678 { 679 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); 680 u32 speed; 681 u8 bits_per_word; 682 unsigned total_fifo_words; 683 int ret; 684 u32 command; 685 u32 command2; 686 687 bits_per_word = t->bits_per_word; 688 speed = t->speed_hz; 689 if (speed != tspi->cur_speed) { 690 clk_set_rate(tspi->clk, speed * 4); 691 tspi->cur_speed = speed; 692 } 693 694 tspi->cur_spi = spi; 695 tspi->cur_pos = 0; 696 tspi->cur_rx_pos = 0; 697 tspi->cur_tx_pos = 0; 698 tspi->curr_xfer = t; 699 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t); 700 701 command = tspi->command_reg; 702 command &= ~SLINK_BIT_LENGTH(~0); 703 command |= SLINK_BIT_LENGTH(bits_per_word - 1); 704 705 command2 = tspi->command2_reg; 706 command2 &= ~(SLINK_RXEN | SLINK_TXEN); 707 708 tspi->cur_direction = 0; 709 if (t->rx_buf) { 710 command2 |= SLINK_RXEN; 711 tspi->cur_direction |= DATA_DIR_RX; 712 } 713 if (t->tx_buf) { 714 command2 |= SLINK_TXEN; 715 tspi->cur_direction |= DATA_DIR_TX; 716 } 717 718 /* 719 * Writing to the command2 register bevore the command register prevents 720 * a spike in chip_select line 0. This selects the chip_select line 721 * before changing the chip_select value. 722 */ 723 tegra_slink_writel(tspi, command2, SLINK_COMMAND2); 724 tspi->command2_reg = command2; 725 726 tegra_slink_writel(tspi, command, SLINK_COMMAND); 727 tspi->command_reg = command; 728 729 if (total_fifo_words > SLINK_FIFO_DEPTH) 730 ret = tegra_slink_start_dma_based_transfer(tspi, t); 731 else 732 ret = tegra_slink_start_cpu_based_transfer(tspi, t); 733 return ret; 734 } 735 736 static int tegra_slink_setup(struct spi_device *spi) 737 { 738 static const u32 cs_pol_bit[MAX_CHIP_SELECT] = { 739 SLINK_CS_POLARITY, 740 SLINK_CS_POLARITY1, 741 SLINK_CS_POLARITY2, 742 SLINK_CS_POLARITY3, 743 }; 744 745 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); 746 u32 val; 747 unsigned long flags; 748 int ret; 749 750 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", 751 spi->bits_per_word, 752 spi->mode & SPI_CPOL ? "" : "~", 753 spi->mode & SPI_CPHA ? "" : "~", 754 spi->max_speed_hz); 755 756 ret = pm_runtime_get_sync(tspi->dev); 757 if (ret < 0) { 758 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); 759 return ret; 760 } 761 762 spin_lock_irqsave(&tspi->lock, flags); 763 val = tspi->def_command_reg; 764 if (spi->mode & SPI_CS_HIGH) 765 val |= cs_pol_bit[spi->chip_select]; 766 else 767 val &= ~cs_pol_bit[spi->chip_select]; 768 tspi->def_command_reg = val; 769 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 770 spin_unlock_irqrestore(&tspi->lock, flags); 771 772 pm_runtime_put(tspi->dev); 773 return 0; 774 } 775 776 static int tegra_slink_prepare_message(struct spi_master *master, 777 struct spi_message *msg) 778 { 779 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 780 struct spi_device *spi = msg->spi; 781 782 tegra_slink_clear_status(tspi); 783 784 tspi->command_reg = tspi->def_command_reg; 785 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE; 786 787 tspi->command2_reg = tspi->def_command2_reg; 788 tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select); 789 790 tspi->command_reg &= ~SLINK_MODES; 791 if (spi->mode & SPI_CPHA) 792 tspi->command_reg |= SLINK_CK_SDA; 793 794 if (spi->mode & SPI_CPOL) 795 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH; 796 else 797 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW; 798 799 return 0; 800 } 801 802 static int tegra_slink_transfer_one(struct spi_master *master, 803 struct spi_device *spi, 804 struct spi_transfer *xfer) 805 { 806 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 807 int ret; 808 809 reinit_completion(&tspi->xfer_completion); 810 ret = tegra_slink_start_transfer_one(spi, xfer); 811 if (ret < 0) { 812 dev_err(tspi->dev, 813 "spi can not start transfer, err %d\n", ret); 814 return ret; 815 } 816 817 ret = wait_for_completion_timeout(&tspi->xfer_completion, 818 SLINK_DMA_TIMEOUT); 819 if (WARN_ON(ret == 0)) { 820 dev_err(tspi->dev, 821 "spi transfer timeout, err %d\n", ret); 822 return -EIO; 823 } 824 825 if (tspi->tx_status) 826 return tspi->tx_status; 827 if (tspi->rx_status) 828 return tspi->rx_status; 829 830 return 0; 831 } 832 833 static int tegra_slink_unprepare_message(struct spi_master *master, 834 struct spi_message *msg) 835 { 836 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 837 838 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 839 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); 840 841 return 0; 842 } 843 844 static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi) 845 { 846 struct spi_transfer *t = tspi->curr_xfer; 847 unsigned long flags; 848 849 spin_lock_irqsave(&tspi->lock, flags); 850 if (tspi->tx_status || tspi->rx_status || 851 (tspi->status_reg & SLINK_BSY)) { 852 dev_err(tspi->dev, 853 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg); 854 dev_err(tspi->dev, 855 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 856 tspi->command2_reg, tspi->dma_control_reg); 857 reset_control_assert(tspi->rst); 858 udelay(2); 859 reset_control_deassert(tspi->rst); 860 complete(&tspi->xfer_completion); 861 goto exit; 862 } 863 864 if (tspi->cur_direction & DATA_DIR_RX) 865 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t); 866 867 if (tspi->cur_direction & DATA_DIR_TX) 868 tspi->cur_pos = tspi->cur_tx_pos; 869 else 870 tspi->cur_pos = tspi->cur_rx_pos; 871 872 if (tspi->cur_pos == t->len) { 873 complete(&tspi->xfer_completion); 874 goto exit; 875 } 876 877 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); 878 tegra_slink_start_cpu_based_transfer(tspi, t); 879 exit: 880 spin_unlock_irqrestore(&tspi->lock, flags); 881 return IRQ_HANDLED; 882 } 883 884 static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi) 885 { 886 struct spi_transfer *t = tspi->curr_xfer; 887 long wait_status; 888 int err = 0; 889 unsigned total_fifo_words; 890 unsigned long flags; 891 892 /* Abort dmas if any error */ 893 if (tspi->cur_direction & DATA_DIR_TX) { 894 if (tspi->tx_status) { 895 dmaengine_terminate_all(tspi->tx_dma_chan); 896 err += 1; 897 } else { 898 wait_status = wait_for_completion_interruptible_timeout( 899 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT); 900 if (wait_status <= 0) { 901 dmaengine_terminate_all(tspi->tx_dma_chan); 902 dev_err(tspi->dev, "TxDma Xfer failed\n"); 903 err += 1; 904 } 905 } 906 } 907 908 if (tspi->cur_direction & DATA_DIR_RX) { 909 if (tspi->rx_status) { 910 dmaengine_terminate_all(tspi->rx_dma_chan); 911 err += 2; 912 } else { 913 wait_status = wait_for_completion_interruptible_timeout( 914 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT); 915 if (wait_status <= 0) { 916 dmaengine_terminate_all(tspi->rx_dma_chan); 917 dev_err(tspi->dev, "RxDma Xfer failed\n"); 918 err += 2; 919 } 920 } 921 } 922 923 spin_lock_irqsave(&tspi->lock, flags); 924 if (err) { 925 dev_err(tspi->dev, 926 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg); 927 dev_err(tspi->dev, 928 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 929 tspi->command2_reg, tspi->dma_control_reg); 930 reset_control_assert(tspi->rst); 931 udelay(2); 932 reset_control_assert(tspi->rst); 933 complete(&tspi->xfer_completion); 934 spin_unlock_irqrestore(&tspi->lock, flags); 935 return IRQ_HANDLED; 936 } 937 938 if (tspi->cur_direction & DATA_DIR_RX) 939 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t); 940 941 if (tspi->cur_direction & DATA_DIR_TX) 942 tspi->cur_pos = tspi->cur_tx_pos; 943 else 944 tspi->cur_pos = tspi->cur_rx_pos; 945 946 if (tspi->cur_pos == t->len) { 947 complete(&tspi->xfer_completion); 948 goto exit; 949 } 950 951 /* Continue transfer in current message */ 952 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, 953 tspi, t); 954 if (total_fifo_words > SLINK_FIFO_DEPTH) 955 err = tegra_slink_start_dma_based_transfer(tspi, t); 956 else 957 err = tegra_slink_start_cpu_based_transfer(tspi, t); 958 959 exit: 960 spin_unlock_irqrestore(&tspi->lock, flags); 961 return IRQ_HANDLED; 962 } 963 964 static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data) 965 { 966 struct tegra_slink_data *tspi = context_data; 967 968 if (!tspi->is_curr_dma_xfer) 969 return handle_cpu_based_xfer(tspi); 970 return handle_dma_based_xfer(tspi); 971 } 972 973 static irqreturn_t tegra_slink_isr(int irq, void *context_data) 974 { 975 struct tegra_slink_data *tspi = context_data; 976 977 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS); 978 if (tspi->cur_direction & DATA_DIR_TX) 979 tspi->tx_status = tspi->status_reg & 980 (SLINK_TX_OVF | SLINK_TX_UNF); 981 982 if (tspi->cur_direction & DATA_DIR_RX) 983 tspi->rx_status = tspi->status_reg & 984 (SLINK_RX_OVF | SLINK_RX_UNF); 985 tegra_slink_clear_status(tspi); 986 987 return IRQ_WAKE_THREAD; 988 } 989 990 static const struct tegra_slink_chip_data tegra30_spi_cdata = { 991 .cs_hold_time = true, 992 }; 993 994 static const struct tegra_slink_chip_data tegra20_spi_cdata = { 995 .cs_hold_time = false, 996 }; 997 998 static const struct of_device_id tegra_slink_of_match[] = { 999 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, }, 1000 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, }, 1001 {} 1002 }; 1003 MODULE_DEVICE_TABLE(of, tegra_slink_of_match); 1004 1005 static int tegra_slink_probe(struct platform_device *pdev) 1006 { 1007 struct spi_master *master; 1008 struct tegra_slink_data *tspi; 1009 struct resource *r; 1010 int ret, spi_irq; 1011 const struct tegra_slink_chip_data *cdata = NULL; 1012 const struct of_device_id *match; 1013 1014 match = of_match_device(tegra_slink_of_match, &pdev->dev); 1015 if (!match) { 1016 dev_err(&pdev->dev, "Error: No device match found\n"); 1017 return -ENODEV; 1018 } 1019 cdata = match->data; 1020 1021 master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); 1022 if (!master) { 1023 dev_err(&pdev->dev, "master allocation failed\n"); 1024 return -ENOMEM; 1025 } 1026 1027 /* the spi->mode bits understood by this driver: */ 1028 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1029 master->setup = tegra_slink_setup; 1030 master->prepare_message = tegra_slink_prepare_message; 1031 master->transfer_one = tegra_slink_transfer_one; 1032 master->unprepare_message = tegra_slink_unprepare_message; 1033 master->auto_runtime_pm = true; 1034 master->num_chipselect = MAX_CHIP_SELECT; 1035 1036 platform_set_drvdata(pdev, master); 1037 tspi = spi_master_get_devdata(master); 1038 tspi->master = master; 1039 tspi->dev = &pdev->dev; 1040 tspi->chip_data = cdata; 1041 spin_lock_init(&tspi->lock); 1042 1043 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency", 1044 &master->max_speed_hz)) 1045 master->max_speed_hz = 25000000; /* 25MHz */ 1046 1047 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1048 if (!r) { 1049 dev_err(&pdev->dev, "No IO memory resource\n"); 1050 ret = -ENODEV; 1051 goto exit_free_master; 1052 } 1053 tspi->phys = r->start; 1054 tspi->base = devm_ioremap_resource(&pdev->dev, r); 1055 if (IS_ERR(tspi->base)) { 1056 ret = PTR_ERR(tspi->base); 1057 goto exit_free_master; 1058 } 1059 1060 /* disabled clock may cause interrupt storm upon request */ 1061 tspi->clk = devm_clk_get(&pdev->dev, NULL); 1062 if (IS_ERR(tspi->clk)) { 1063 ret = PTR_ERR(tspi->clk); 1064 dev_err(&pdev->dev, "Can not get clock %d\n", ret); 1065 goto exit_free_master; 1066 } 1067 ret = clk_prepare(tspi->clk); 1068 if (ret < 0) { 1069 dev_err(&pdev->dev, "Clock prepare failed %d\n", ret); 1070 goto exit_free_master; 1071 } 1072 ret = clk_enable(tspi->clk); 1073 if (ret < 0) { 1074 dev_err(&pdev->dev, "Clock enable failed %d\n", ret); 1075 goto exit_clk_unprepare; 1076 } 1077 1078 spi_irq = platform_get_irq(pdev, 0); 1079 tspi->irq = spi_irq; 1080 ret = request_threaded_irq(tspi->irq, tegra_slink_isr, 1081 tegra_slink_isr_thread, IRQF_ONESHOT, 1082 dev_name(&pdev->dev), tspi); 1083 if (ret < 0) { 1084 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", 1085 tspi->irq); 1086 goto exit_clk_disable; 1087 } 1088 1089 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); 1090 if (IS_ERR(tspi->rst)) { 1091 dev_err(&pdev->dev, "can not get reset\n"); 1092 ret = PTR_ERR(tspi->rst); 1093 goto exit_free_irq; 1094 } 1095 1096 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; 1097 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; 1098 1099 ret = tegra_slink_init_dma_param(tspi, true); 1100 if (ret < 0) 1101 goto exit_free_irq; 1102 ret = tegra_slink_init_dma_param(tspi, false); 1103 if (ret < 0) 1104 goto exit_rx_dma_free; 1105 tspi->max_buf_size = tspi->dma_buf_size; 1106 init_completion(&tspi->tx_dma_complete); 1107 init_completion(&tspi->rx_dma_complete); 1108 1109 init_completion(&tspi->xfer_completion); 1110 1111 pm_runtime_enable(&pdev->dev); 1112 if (!pm_runtime_enabled(&pdev->dev)) { 1113 ret = tegra_slink_runtime_resume(&pdev->dev); 1114 if (ret) 1115 goto exit_pm_disable; 1116 } 1117 1118 ret = pm_runtime_get_sync(&pdev->dev); 1119 if (ret < 0) { 1120 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); 1121 goto exit_pm_disable; 1122 } 1123 tspi->def_command_reg = SLINK_M_S; 1124 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN; 1125 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 1126 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); 1127 pm_runtime_put(&pdev->dev); 1128 1129 master->dev.of_node = pdev->dev.of_node; 1130 ret = devm_spi_register_master(&pdev->dev, master); 1131 if (ret < 0) { 1132 dev_err(&pdev->dev, "can not register to master err %d\n", ret); 1133 goto exit_pm_disable; 1134 } 1135 return ret; 1136 1137 exit_pm_disable: 1138 pm_runtime_disable(&pdev->dev); 1139 if (!pm_runtime_status_suspended(&pdev->dev)) 1140 tegra_slink_runtime_suspend(&pdev->dev); 1141 tegra_slink_deinit_dma_param(tspi, false); 1142 exit_rx_dma_free: 1143 tegra_slink_deinit_dma_param(tspi, true); 1144 exit_free_irq: 1145 free_irq(spi_irq, tspi); 1146 exit_clk_disable: 1147 clk_disable(tspi->clk); 1148 exit_clk_unprepare: 1149 clk_unprepare(tspi->clk); 1150 exit_free_master: 1151 spi_master_put(master); 1152 return ret; 1153 } 1154 1155 static int tegra_slink_remove(struct platform_device *pdev) 1156 { 1157 struct spi_master *master = platform_get_drvdata(pdev); 1158 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1159 1160 free_irq(tspi->irq, tspi); 1161 1162 clk_disable(tspi->clk); 1163 clk_unprepare(tspi->clk); 1164 1165 if (tspi->tx_dma_chan) 1166 tegra_slink_deinit_dma_param(tspi, false); 1167 1168 if (tspi->rx_dma_chan) 1169 tegra_slink_deinit_dma_param(tspi, true); 1170 1171 pm_runtime_disable(&pdev->dev); 1172 if (!pm_runtime_status_suspended(&pdev->dev)) 1173 tegra_slink_runtime_suspend(&pdev->dev); 1174 1175 return 0; 1176 } 1177 1178 #ifdef CONFIG_PM_SLEEP 1179 static int tegra_slink_suspend(struct device *dev) 1180 { 1181 struct spi_master *master = dev_get_drvdata(dev); 1182 1183 return spi_master_suspend(master); 1184 } 1185 1186 static int tegra_slink_resume(struct device *dev) 1187 { 1188 struct spi_master *master = dev_get_drvdata(dev); 1189 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1190 int ret; 1191 1192 ret = pm_runtime_get_sync(dev); 1193 if (ret < 0) { 1194 dev_err(dev, "pm runtime failed, e = %d\n", ret); 1195 return ret; 1196 } 1197 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND); 1198 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2); 1199 pm_runtime_put(dev); 1200 1201 return spi_master_resume(master); 1202 } 1203 #endif 1204 1205 static int tegra_slink_runtime_suspend(struct device *dev) 1206 { 1207 struct spi_master *master = dev_get_drvdata(dev); 1208 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1209 1210 /* Flush all write which are in PPSB queue by reading back */ 1211 tegra_slink_readl(tspi, SLINK_MAS_DATA); 1212 1213 clk_disable_unprepare(tspi->clk); 1214 return 0; 1215 } 1216 1217 static int tegra_slink_runtime_resume(struct device *dev) 1218 { 1219 struct spi_master *master = dev_get_drvdata(dev); 1220 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1221 int ret; 1222 1223 ret = clk_prepare_enable(tspi->clk); 1224 if (ret < 0) { 1225 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); 1226 return ret; 1227 } 1228 return 0; 1229 } 1230 1231 static const struct dev_pm_ops slink_pm_ops = { 1232 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend, 1233 tegra_slink_runtime_resume, NULL) 1234 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume) 1235 }; 1236 static struct platform_driver tegra_slink_driver = { 1237 .driver = { 1238 .name = "spi-tegra-slink", 1239 .pm = &slink_pm_ops, 1240 .of_match_table = tegra_slink_of_match, 1241 }, 1242 .probe = tegra_slink_probe, 1243 .remove = tegra_slink_remove, 1244 }; 1245 module_platform_driver(tegra_slink_driver); 1246 1247 MODULE_ALIAS("platform:spi-tegra-slink"); 1248 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver"); 1249 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1250 MODULE_LICENSE("GPL v2"); 1251