1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller. 4 * 5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmapool.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/kthread.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/reset.h> 25 #include <linux/spi/spi.h> 26 27 #define SLINK_COMMAND 0x000 28 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) 29 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5) 30 #define SLINK_BOTH_EN (1 << 10) 31 #define SLINK_CS_SW (1 << 11) 32 #define SLINK_CS_VALUE (1 << 12) 33 #define SLINK_CS_POLARITY (1 << 13) 34 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16) 35 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16) 36 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16) 37 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16) 38 #define SLINK_IDLE_SDA_MASK (3 << 16) 39 #define SLINK_CS_POLARITY1 (1 << 20) 40 #define SLINK_CK_SDA (1 << 21) 41 #define SLINK_CS_POLARITY2 (1 << 22) 42 #define SLINK_CS_POLARITY3 (1 << 23) 43 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24) 44 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24) 45 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24) 46 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24) 47 #define SLINK_IDLE_SCLK_MASK (3 << 24) 48 #define SLINK_M_S (1 << 28) 49 #define SLINK_WAIT (1 << 29) 50 #define SLINK_GO (1 << 30) 51 #define SLINK_ENB (1 << 31) 52 53 #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA) 54 55 #define SLINK_COMMAND2 0x004 56 #define SLINK_LSBFE (1 << 0) 57 #define SLINK_SSOE (1 << 1) 58 #define SLINK_SPIE (1 << 4) 59 #define SLINK_BIDIROE (1 << 6) 60 #define SLINK_MODFEN (1 << 7) 61 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8) 62 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17) 63 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18) 64 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20) 65 #define SLINK_FIFO_REFILLS_0 (0 << 22) 66 #define SLINK_FIFO_REFILLS_1 (1 << 22) 67 #define SLINK_FIFO_REFILLS_2 (2 << 22) 68 #define SLINK_FIFO_REFILLS_3 (3 << 22) 69 #define SLINK_FIFO_REFILLS_MASK (3 << 22) 70 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26) 71 #define SLINK_SPC0 (1 << 29) 72 #define SLINK_TXEN (1 << 30) 73 #define SLINK_RXEN (1 << 31) 74 75 #define SLINK_STATUS 0x008 76 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f) 77 #define SLINK_WORD(val) (((val) >> 5) & 0x1f) 78 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff) 79 #define SLINK_MODF (1 << 16) 80 #define SLINK_RX_UNF (1 << 18) 81 #define SLINK_TX_OVF (1 << 19) 82 #define SLINK_TX_FULL (1 << 20) 83 #define SLINK_TX_EMPTY (1 << 21) 84 #define SLINK_RX_FULL (1 << 22) 85 #define SLINK_RX_EMPTY (1 << 23) 86 #define SLINK_TX_UNF (1 << 24) 87 #define SLINK_RX_OVF (1 << 25) 88 #define SLINK_TX_FLUSH (1 << 26) 89 #define SLINK_RX_FLUSH (1 << 27) 90 #define SLINK_SCLK (1 << 28) 91 #define SLINK_ERR (1 << 29) 92 #define SLINK_RDY (1 << 30) 93 #define SLINK_BSY (1 << 31) 94 #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \ 95 SLINK_TX_UNF | SLINK_RX_OVF) 96 97 #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY) 98 99 #define SLINK_MAS_DATA 0x010 100 #define SLINK_SLAVE_DATA 0x014 101 102 #define SLINK_DMA_CTL 0x018 103 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0) 104 #define SLINK_TX_TRIG_1 (0 << 16) 105 #define SLINK_TX_TRIG_4 (1 << 16) 106 #define SLINK_TX_TRIG_8 (2 << 16) 107 #define SLINK_TX_TRIG_16 (3 << 16) 108 #define SLINK_TX_TRIG_MASK (3 << 16) 109 #define SLINK_RX_TRIG_1 (0 << 18) 110 #define SLINK_RX_TRIG_4 (1 << 18) 111 #define SLINK_RX_TRIG_8 (2 << 18) 112 #define SLINK_RX_TRIG_16 (3 << 18) 113 #define SLINK_RX_TRIG_MASK (3 << 18) 114 #define SLINK_PACKED (1 << 20) 115 #define SLINK_PACK_SIZE_4 (0 << 21) 116 #define SLINK_PACK_SIZE_8 (1 << 21) 117 #define SLINK_PACK_SIZE_16 (2 << 21) 118 #define SLINK_PACK_SIZE_32 (3 << 21) 119 #define SLINK_PACK_SIZE_MASK (3 << 21) 120 #define SLINK_IE_TXC (1 << 26) 121 #define SLINK_IE_RXC (1 << 27) 122 #define SLINK_DMA_EN (1 << 31) 123 124 #define SLINK_STATUS2 0x01c 125 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0) 126 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16) 127 #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6) 128 129 #define SLINK_TX_FIFO 0x100 130 #define SLINK_RX_FIFO 0x180 131 132 #define DATA_DIR_TX (1 << 0) 133 #define DATA_DIR_RX (1 << 1) 134 135 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000)) 136 137 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024) 138 #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20) 139 #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0) 140 141 #define SLINK_STATUS2_RESET \ 142 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16) 143 144 #define MAX_CHIP_SELECT 4 145 #define SLINK_FIFO_DEPTH 32 146 147 struct tegra_slink_chip_data { 148 bool cs_hold_time; 149 }; 150 151 struct tegra_slink_data { 152 struct device *dev; 153 struct spi_master *master; 154 const struct tegra_slink_chip_data *chip_data; 155 spinlock_t lock; 156 157 struct clk *clk; 158 struct reset_control *rst; 159 void __iomem *base; 160 phys_addr_t phys; 161 unsigned irq; 162 u32 cur_speed; 163 164 struct spi_device *cur_spi; 165 unsigned cur_pos; 166 unsigned cur_len; 167 unsigned words_per_32bit; 168 unsigned bytes_per_word; 169 unsigned curr_dma_words; 170 unsigned cur_direction; 171 172 unsigned cur_rx_pos; 173 unsigned cur_tx_pos; 174 175 unsigned dma_buf_size; 176 unsigned max_buf_size; 177 bool is_curr_dma_xfer; 178 179 struct completion rx_dma_complete; 180 struct completion tx_dma_complete; 181 182 u32 tx_status; 183 u32 rx_status; 184 u32 status_reg; 185 bool is_packed; 186 u32 packed_size; 187 188 u32 command_reg; 189 u32 command2_reg; 190 u32 dma_control_reg; 191 u32 def_command_reg; 192 u32 def_command2_reg; 193 194 struct completion xfer_completion; 195 struct spi_transfer *curr_xfer; 196 struct dma_chan *rx_dma_chan; 197 u32 *rx_dma_buf; 198 dma_addr_t rx_dma_phys; 199 struct dma_async_tx_descriptor *rx_dma_desc; 200 201 struct dma_chan *tx_dma_chan; 202 u32 *tx_dma_buf; 203 dma_addr_t tx_dma_phys; 204 struct dma_async_tx_descriptor *tx_dma_desc; 205 }; 206 207 static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi, 208 unsigned long reg) 209 { 210 return readl(tspi->base + reg); 211 } 212 213 static inline void tegra_slink_writel(struct tegra_slink_data *tspi, 214 u32 val, unsigned long reg) 215 { 216 writel(val, tspi->base + reg); 217 218 /* Read back register to make sure that register writes completed */ 219 if (reg != SLINK_TX_FIFO) 220 readl(tspi->base + SLINK_MAS_DATA); 221 } 222 223 static void tegra_slink_clear_status(struct tegra_slink_data *tspi) 224 { 225 u32 val_write; 226 227 tegra_slink_readl(tspi, SLINK_STATUS); 228 229 /* Write 1 to clear status register */ 230 val_write = SLINK_RDY | SLINK_FIFO_ERROR; 231 tegra_slink_writel(tspi, val_write, SLINK_STATUS); 232 } 233 234 static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi, 235 struct spi_transfer *t) 236 { 237 switch (tspi->bytes_per_word) { 238 case 0: 239 return SLINK_PACK_SIZE_4; 240 case 1: 241 return SLINK_PACK_SIZE_8; 242 case 2: 243 return SLINK_PACK_SIZE_16; 244 case 4: 245 return SLINK_PACK_SIZE_32; 246 default: 247 return 0; 248 } 249 } 250 251 static unsigned tegra_slink_calculate_curr_xfer_param( 252 struct spi_device *spi, struct tegra_slink_data *tspi, 253 struct spi_transfer *t) 254 { 255 unsigned remain_len = t->len - tspi->cur_pos; 256 unsigned max_word; 257 unsigned bits_per_word; 258 unsigned max_len; 259 unsigned total_fifo_words; 260 261 bits_per_word = t->bits_per_word; 262 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); 263 264 if (bits_per_word == 8 || bits_per_word == 16) { 265 tspi->is_packed = true; 266 tspi->words_per_32bit = 32/bits_per_word; 267 } else { 268 tspi->is_packed = false; 269 tspi->words_per_32bit = 1; 270 } 271 tspi->packed_size = tegra_slink_get_packed_size(tspi, t); 272 273 if (tspi->is_packed) { 274 max_len = min(remain_len, tspi->max_buf_size); 275 tspi->curr_dma_words = max_len/tspi->bytes_per_word; 276 total_fifo_words = max_len/4; 277 } else { 278 max_word = (remain_len - 1) / tspi->bytes_per_word + 1; 279 max_word = min(max_word, tspi->max_buf_size/4); 280 tspi->curr_dma_words = max_word; 281 total_fifo_words = max_word; 282 } 283 return total_fifo_words; 284 } 285 286 static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf( 287 struct tegra_slink_data *tspi, struct spi_transfer *t) 288 { 289 unsigned nbytes; 290 unsigned tx_empty_count; 291 u32 fifo_status; 292 unsigned max_n_32bit; 293 unsigned i, count; 294 unsigned int written_words; 295 unsigned fifo_words_left; 296 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 297 298 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); 299 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status); 300 301 if (tspi->is_packed) { 302 fifo_words_left = tx_empty_count * tspi->words_per_32bit; 303 written_words = min(fifo_words_left, tspi->curr_dma_words); 304 nbytes = written_words * tspi->bytes_per_word; 305 max_n_32bit = DIV_ROUND_UP(nbytes, 4); 306 for (count = 0; count < max_n_32bit; count++) { 307 u32 x = 0; 308 for (i = 0; (i < 4) && nbytes; i++, nbytes--) 309 x |= (u32)(*tx_buf++) << (i * 8); 310 tegra_slink_writel(tspi, x, SLINK_TX_FIFO); 311 } 312 } else { 313 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); 314 written_words = max_n_32bit; 315 nbytes = written_words * tspi->bytes_per_word; 316 for (count = 0; count < max_n_32bit; count++) { 317 u32 x = 0; 318 for (i = 0; nbytes && (i < tspi->bytes_per_word); 319 i++, nbytes--) 320 x |= (u32)(*tx_buf++) << (i * 8); 321 tegra_slink_writel(tspi, x, SLINK_TX_FIFO); 322 } 323 } 324 tspi->cur_tx_pos += written_words * tspi->bytes_per_word; 325 return written_words; 326 } 327 328 static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf( 329 struct tegra_slink_data *tspi, struct spi_transfer *t) 330 { 331 unsigned rx_full_count; 332 u32 fifo_status; 333 unsigned i, count; 334 unsigned int read_words = 0; 335 unsigned len; 336 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; 337 338 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); 339 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status); 340 if (tspi->is_packed) { 341 len = tspi->curr_dma_words * tspi->bytes_per_word; 342 for (count = 0; count < rx_full_count; count++) { 343 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); 344 for (i = 0; len && (i < 4); i++, len--) 345 *rx_buf++ = (x >> i*8) & 0xFF; 346 } 347 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 348 read_words += tspi->curr_dma_words; 349 } else { 350 for (count = 0; count < rx_full_count; count++) { 351 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); 352 for (i = 0; (i < tspi->bytes_per_word); i++) 353 *rx_buf++ = (x >> (i*8)) & 0xFF; 354 } 355 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; 356 read_words += rx_full_count; 357 } 358 return read_words; 359 } 360 361 static void tegra_slink_copy_client_txbuf_to_spi_txbuf( 362 struct tegra_slink_data *tspi, struct spi_transfer *t) 363 { 364 /* Make the dma buffer to read by cpu */ 365 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, 366 tspi->dma_buf_size, DMA_TO_DEVICE); 367 368 if (tspi->is_packed) { 369 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; 370 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); 371 } else { 372 unsigned int i; 373 unsigned int count; 374 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 375 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; 376 377 for (count = 0; count < tspi->curr_dma_words; count++) { 378 u32 x = 0; 379 for (i = 0; consume && (i < tspi->bytes_per_word); 380 i++, consume--) 381 x |= (u32)(*tx_buf++) << (i * 8); 382 tspi->tx_dma_buf[count] = x; 383 } 384 } 385 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 386 387 /* Make the dma buffer to read by dma */ 388 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, 389 tspi->dma_buf_size, DMA_TO_DEVICE); 390 } 391 392 static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf( 393 struct tegra_slink_data *tspi, struct spi_transfer *t) 394 { 395 unsigned len; 396 397 /* Make the dma buffer to read by cpu */ 398 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, 399 tspi->dma_buf_size, DMA_FROM_DEVICE); 400 401 if (tspi->is_packed) { 402 len = tspi->curr_dma_words * tspi->bytes_per_word; 403 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); 404 } else { 405 unsigned int i; 406 unsigned int count; 407 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; 408 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; 409 410 for (count = 0; count < tspi->curr_dma_words; count++) { 411 u32 x = tspi->rx_dma_buf[count] & rx_mask; 412 for (i = 0; (i < tspi->bytes_per_word); i++) 413 *rx_buf++ = (x >> (i*8)) & 0xFF; 414 } 415 } 416 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 417 418 /* Make the dma buffer to read by dma */ 419 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, 420 tspi->dma_buf_size, DMA_FROM_DEVICE); 421 } 422 423 static void tegra_slink_dma_complete(void *args) 424 { 425 struct completion *dma_complete = args; 426 427 complete(dma_complete); 428 } 429 430 static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len) 431 { 432 reinit_completion(&tspi->tx_dma_complete); 433 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, 434 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, 435 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 436 if (!tspi->tx_dma_desc) { 437 dev_err(tspi->dev, "Not able to get desc for Tx\n"); 438 return -EIO; 439 } 440 441 tspi->tx_dma_desc->callback = tegra_slink_dma_complete; 442 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; 443 444 dmaengine_submit(tspi->tx_dma_desc); 445 dma_async_issue_pending(tspi->tx_dma_chan); 446 return 0; 447 } 448 449 static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len) 450 { 451 reinit_completion(&tspi->rx_dma_complete); 452 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, 453 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, 454 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 455 if (!tspi->rx_dma_desc) { 456 dev_err(tspi->dev, "Not able to get desc for Rx\n"); 457 return -EIO; 458 } 459 460 tspi->rx_dma_desc->callback = tegra_slink_dma_complete; 461 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; 462 463 dmaengine_submit(tspi->rx_dma_desc); 464 dma_async_issue_pending(tspi->rx_dma_chan); 465 return 0; 466 } 467 468 static int tegra_slink_start_dma_based_transfer( 469 struct tegra_slink_data *tspi, struct spi_transfer *t) 470 { 471 u32 val; 472 unsigned int len; 473 int ret = 0; 474 u32 status; 475 476 /* Make sure that Rx and Tx fifo are empty */ 477 status = tegra_slink_readl(tspi, SLINK_STATUS); 478 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) { 479 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n", 480 (unsigned)status); 481 return -EIO; 482 } 483 484 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1); 485 val |= tspi->packed_size; 486 if (tspi->is_packed) 487 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, 488 4) * 4; 489 else 490 len = tspi->curr_dma_words * 4; 491 492 /* Set attention level based on length of transfer */ 493 if (len & 0xF) 494 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1; 495 else if (((len) >> 4) & 0x1) 496 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4; 497 else 498 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8; 499 500 if (tspi->cur_direction & DATA_DIR_TX) 501 val |= SLINK_IE_TXC; 502 503 if (tspi->cur_direction & DATA_DIR_RX) 504 val |= SLINK_IE_RXC; 505 506 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 507 tspi->dma_control_reg = val; 508 509 if (tspi->cur_direction & DATA_DIR_TX) { 510 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t); 511 wmb(); 512 ret = tegra_slink_start_tx_dma(tspi, len); 513 if (ret < 0) { 514 dev_err(tspi->dev, 515 "Starting tx dma failed, err %d\n", ret); 516 return ret; 517 } 518 519 /* Wait for tx fifo to be fill before starting slink */ 520 status = tegra_slink_readl(tspi, SLINK_STATUS); 521 while (!(status & SLINK_TX_FULL)) 522 status = tegra_slink_readl(tspi, SLINK_STATUS); 523 } 524 525 if (tspi->cur_direction & DATA_DIR_RX) { 526 /* Make the dma buffer to read by dma */ 527 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, 528 tspi->dma_buf_size, DMA_FROM_DEVICE); 529 530 ret = tegra_slink_start_rx_dma(tspi, len); 531 if (ret < 0) { 532 dev_err(tspi->dev, 533 "Starting rx dma failed, err %d\n", ret); 534 if (tspi->cur_direction & DATA_DIR_TX) 535 dmaengine_terminate_all(tspi->tx_dma_chan); 536 return ret; 537 } 538 } 539 tspi->is_curr_dma_xfer = true; 540 if (tspi->is_packed) { 541 val |= SLINK_PACKED; 542 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 543 /* HW need small delay after settign Packed mode */ 544 udelay(1); 545 } 546 tspi->dma_control_reg = val; 547 548 val |= SLINK_DMA_EN; 549 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 550 return ret; 551 } 552 553 static int tegra_slink_start_cpu_based_transfer( 554 struct tegra_slink_data *tspi, struct spi_transfer *t) 555 { 556 u32 val; 557 unsigned cur_words; 558 559 val = tspi->packed_size; 560 if (tspi->cur_direction & DATA_DIR_TX) 561 val |= SLINK_IE_TXC; 562 563 if (tspi->cur_direction & DATA_DIR_RX) 564 val |= SLINK_IE_RXC; 565 566 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 567 tspi->dma_control_reg = val; 568 569 if (tspi->cur_direction & DATA_DIR_TX) 570 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t); 571 else 572 cur_words = tspi->curr_dma_words; 573 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1); 574 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 575 tspi->dma_control_reg = val; 576 577 tspi->is_curr_dma_xfer = false; 578 if (tspi->is_packed) { 579 val |= SLINK_PACKED; 580 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 581 udelay(1); 582 wmb(); 583 } 584 tspi->dma_control_reg = val; 585 val |= SLINK_DMA_EN; 586 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 587 return 0; 588 } 589 590 static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi, 591 bool dma_to_memory) 592 { 593 struct dma_chan *dma_chan; 594 u32 *dma_buf; 595 dma_addr_t dma_phys; 596 int ret; 597 struct dma_slave_config dma_sconfig; 598 599 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); 600 if (IS_ERR(dma_chan)) 601 return dev_err_probe(tspi->dev, PTR_ERR(dma_chan), 602 "Dma channel is not available\n"); 603 604 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, 605 &dma_phys, GFP_KERNEL); 606 if (!dma_buf) { 607 dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); 608 dma_release_channel(dma_chan); 609 return -ENOMEM; 610 } 611 612 if (dma_to_memory) { 613 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; 614 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 615 dma_sconfig.src_maxburst = 0; 616 } else { 617 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO; 618 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 619 dma_sconfig.dst_maxburst = 0; 620 } 621 622 ret = dmaengine_slave_config(dma_chan, &dma_sconfig); 623 if (ret) 624 goto scrub; 625 if (dma_to_memory) { 626 tspi->rx_dma_chan = dma_chan; 627 tspi->rx_dma_buf = dma_buf; 628 tspi->rx_dma_phys = dma_phys; 629 } else { 630 tspi->tx_dma_chan = dma_chan; 631 tspi->tx_dma_buf = dma_buf; 632 tspi->tx_dma_phys = dma_phys; 633 } 634 return 0; 635 636 scrub: 637 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); 638 dma_release_channel(dma_chan); 639 return ret; 640 } 641 642 static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi, 643 bool dma_to_memory) 644 { 645 u32 *dma_buf; 646 dma_addr_t dma_phys; 647 struct dma_chan *dma_chan; 648 649 if (dma_to_memory) { 650 dma_buf = tspi->rx_dma_buf; 651 dma_chan = tspi->rx_dma_chan; 652 dma_phys = tspi->rx_dma_phys; 653 tspi->rx_dma_chan = NULL; 654 tspi->rx_dma_buf = NULL; 655 } else { 656 dma_buf = tspi->tx_dma_buf; 657 dma_chan = tspi->tx_dma_chan; 658 dma_phys = tspi->tx_dma_phys; 659 tspi->tx_dma_buf = NULL; 660 tspi->tx_dma_chan = NULL; 661 } 662 if (!dma_chan) 663 return; 664 665 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); 666 dma_release_channel(dma_chan); 667 } 668 669 static int tegra_slink_start_transfer_one(struct spi_device *spi, 670 struct spi_transfer *t) 671 { 672 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); 673 u32 speed; 674 u8 bits_per_word; 675 unsigned total_fifo_words; 676 int ret; 677 u32 command; 678 u32 command2; 679 680 bits_per_word = t->bits_per_word; 681 speed = t->speed_hz; 682 if (speed != tspi->cur_speed) { 683 clk_set_rate(tspi->clk, speed * 4); 684 tspi->cur_speed = speed; 685 } 686 687 tspi->cur_spi = spi; 688 tspi->cur_pos = 0; 689 tspi->cur_rx_pos = 0; 690 tspi->cur_tx_pos = 0; 691 tspi->curr_xfer = t; 692 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t); 693 694 command = tspi->command_reg; 695 command &= ~SLINK_BIT_LENGTH(~0); 696 command |= SLINK_BIT_LENGTH(bits_per_word - 1); 697 698 command2 = tspi->command2_reg; 699 command2 &= ~(SLINK_RXEN | SLINK_TXEN); 700 701 tspi->cur_direction = 0; 702 if (t->rx_buf) { 703 command2 |= SLINK_RXEN; 704 tspi->cur_direction |= DATA_DIR_RX; 705 } 706 if (t->tx_buf) { 707 command2 |= SLINK_TXEN; 708 tspi->cur_direction |= DATA_DIR_TX; 709 } 710 711 /* 712 * Writing to the command2 register bevore the command register prevents 713 * a spike in chip_select line 0. This selects the chip_select line 714 * before changing the chip_select value. 715 */ 716 tegra_slink_writel(tspi, command2, SLINK_COMMAND2); 717 tspi->command2_reg = command2; 718 719 tegra_slink_writel(tspi, command, SLINK_COMMAND); 720 tspi->command_reg = command; 721 722 if (total_fifo_words > SLINK_FIFO_DEPTH) 723 ret = tegra_slink_start_dma_based_transfer(tspi, t); 724 else 725 ret = tegra_slink_start_cpu_based_transfer(tspi, t); 726 return ret; 727 } 728 729 static int tegra_slink_setup(struct spi_device *spi) 730 { 731 static const u32 cs_pol_bit[MAX_CHIP_SELECT] = { 732 SLINK_CS_POLARITY, 733 SLINK_CS_POLARITY1, 734 SLINK_CS_POLARITY2, 735 SLINK_CS_POLARITY3, 736 }; 737 738 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); 739 u32 val; 740 unsigned long flags; 741 int ret; 742 743 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", 744 spi->bits_per_word, 745 spi->mode & SPI_CPOL ? "" : "~", 746 spi->mode & SPI_CPHA ? "" : "~", 747 spi->max_speed_hz); 748 749 ret = pm_runtime_get_sync(tspi->dev); 750 if (ret < 0) { 751 pm_runtime_put_noidle(tspi->dev); 752 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); 753 return ret; 754 } 755 756 spin_lock_irqsave(&tspi->lock, flags); 757 val = tspi->def_command_reg; 758 if (spi->mode & SPI_CS_HIGH) 759 val |= cs_pol_bit[spi->chip_select]; 760 else 761 val &= ~cs_pol_bit[spi->chip_select]; 762 tspi->def_command_reg = val; 763 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 764 spin_unlock_irqrestore(&tspi->lock, flags); 765 766 pm_runtime_put(tspi->dev); 767 return 0; 768 } 769 770 static int tegra_slink_prepare_message(struct spi_master *master, 771 struct spi_message *msg) 772 { 773 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 774 struct spi_device *spi = msg->spi; 775 776 tegra_slink_clear_status(tspi); 777 778 tspi->command_reg = tspi->def_command_reg; 779 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE; 780 781 tspi->command2_reg = tspi->def_command2_reg; 782 tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select); 783 784 tspi->command_reg &= ~SLINK_MODES; 785 if (spi->mode & SPI_CPHA) 786 tspi->command_reg |= SLINK_CK_SDA; 787 788 if (spi->mode & SPI_CPOL) 789 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH; 790 else 791 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW; 792 793 return 0; 794 } 795 796 static int tegra_slink_transfer_one(struct spi_master *master, 797 struct spi_device *spi, 798 struct spi_transfer *xfer) 799 { 800 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 801 int ret; 802 803 reinit_completion(&tspi->xfer_completion); 804 ret = tegra_slink_start_transfer_one(spi, xfer); 805 if (ret < 0) { 806 dev_err(tspi->dev, 807 "spi can not start transfer, err %d\n", ret); 808 return ret; 809 } 810 811 ret = wait_for_completion_timeout(&tspi->xfer_completion, 812 SLINK_DMA_TIMEOUT); 813 if (WARN_ON(ret == 0)) { 814 dev_err(tspi->dev, 815 "spi transfer timeout, err %d\n", ret); 816 return -EIO; 817 } 818 819 if (tspi->tx_status) 820 return tspi->tx_status; 821 if (tspi->rx_status) 822 return tspi->rx_status; 823 824 return 0; 825 } 826 827 static int tegra_slink_unprepare_message(struct spi_master *master, 828 struct spi_message *msg) 829 { 830 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 831 832 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 833 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); 834 835 return 0; 836 } 837 838 static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi) 839 { 840 struct spi_transfer *t = tspi->curr_xfer; 841 unsigned long flags; 842 843 spin_lock_irqsave(&tspi->lock, flags); 844 if (tspi->tx_status || tspi->rx_status || 845 (tspi->status_reg & SLINK_BSY)) { 846 dev_err(tspi->dev, 847 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg); 848 dev_err(tspi->dev, 849 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 850 tspi->command2_reg, tspi->dma_control_reg); 851 reset_control_assert(tspi->rst); 852 udelay(2); 853 reset_control_deassert(tspi->rst); 854 complete(&tspi->xfer_completion); 855 goto exit; 856 } 857 858 if (tspi->cur_direction & DATA_DIR_RX) 859 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t); 860 861 if (tspi->cur_direction & DATA_DIR_TX) 862 tspi->cur_pos = tspi->cur_tx_pos; 863 else 864 tspi->cur_pos = tspi->cur_rx_pos; 865 866 if (tspi->cur_pos == t->len) { 867 complete(&tspi->xfer_completion); 868 goto exit; 869 } 870 871 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); 872 tegra_slink_start_cpu_based_transfer(tspi, t); 873 exit: 874 spin_unlock_irqrestore(&tspi->lock, flags); 875 return IRQ_HANDLED; 876 } 877 878 static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi) 879 { 880 struct spi_transfer *t = tspi->curr_xfer; 881 long wait_status; 882 int err = 0; 883 unsigned total_fifo_words; 884 unsigned long flags; 885 886 /* Abort dmas if any error */ 887 if (tspi->cur_direction & DATA_DIR_TX) { 888 if (tspi->tx_status) { 889 dmaengine_terminate_all(tspi->tx_dma_chan); 890 err += 1; 891 } else { 892 wait_status = wait_for_completion_interruptible_timeout( 893 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT); 894 if (wait_status <= 0) { 895 dmaengine_terminate_all(tspi->tx_dma_chan); 896 dev_err(tspi->dev, "TxDma Xfer failed\n"); 897 err += 1; 898 } 899 } 900 } 901 902 if (tspi->cur_direction & DATA_DIR_RX) { 903 if (tspi->rx_status) { 904 dmaengine_terminate_all(tspi->rx_dma_chan); 905 err += 2; 906 } else { 907 wait_status = wait_for_completion_interruptible_timeout( 908 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT); 909 if (wait_status <= 0) { 910 dmaengine_terminate_all(tspi->rx_dma_chan); 911 dev_err(tspi->dev, "RxDma Xfer failed\n"); 912 err += 2; 913 } 914 } 915 } 916 917 spin_lock_irqsave(&tspi->lock, flags); 918 if (err) { 919 dev_err(tspi->dev, 920 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg); 921 dev_err(tspi->dev, 922 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 923 tspi->command2_reg, tspi->dma_control_reg); 924 reset_control_assert(tspi->rst); 925 udelay(2); 926 reset_control_assert(tspi->rst); 927 complete(&tspi->xfer_completion); 928 spin_unlock_irqrestore(&tspi->lock, flags); 929 return IRQ_HANDLED; 930 } 931 932 if (tspi->cur_direction & DATA_DIR_RX) 933 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t); 934 935 if (tspi->cur_direction & DATA_DIR_TX) 936 tspi->cur_pos = tspi->cur_tx_pos; 937 else 938 tspi->cur_pos = tspi->cur_rx_pos; 939 940 if (tspi->cur_pos == t->len) { 941 complete(&tspi->xfer_completion); 942 goto exit; 943 } 944 945 /* Continue transfer in current message */ 946 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, 947 tspi, t); 948 if (total_fifo_words > SLINK_FIFO_DEPTH) 949 err = tegra_slink_start_dma_based_transfer(tspi, t); 950 else 951 err = tegra_slink_start_cpu_based_transfer(tspi, t); 952 953 exit: 954 spin_unlock_irqrestore(&tspi->lock, flags); 955 return IRQ_HANDLED; 956 } 957 958 static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data) 959 { 960 struct tegra_slink_data *tspi = context_data; 961 962 if (!tspi->is_curr_dma_xfer) 963 return handle_cpu_based_xfer(tspi); 964 return handle_dma_based_xfer(tspi); 965 } 966 967 static irqreturn_t tegra_slink_isr(int irq, void *context_data) 968 { 969 struct tegra_slink_data *tspi = context_data; 970 971 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS); 972 if (tspi->cur_direction & DATA_DIR_TX) 973 tspi->tx_status = tspi->status_reg & 974 (SLINK_TX_OVF | SLINK_TX_UNF); 975 976 if (tspi->cur_direction & DATA_DIR_RX) 977 tspi->rx_status = tspi->status_reg & 978 (SLINK_RX_OVF | SLINK_RX_UNF); 979 tegra_slink_clear_status(tspi); 980 981 return IRQ_WAKE_THREAD; 982 } 983 984 static const struct tegra_slink_chip_data tegra30_spi_cdata = { 985 .cs_hold_time = true, 986 }; 987 988 static const struct tegra_slink_chip_data tegra20_spi_cdata = { 989 .cs_hold_time = false, 990 }; 991 992 static const struct of_device_id tegra_slink_of_match[] = { 993 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, }, 994 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, }, 995 {} 996 }; 997 MODULE_DEVICE_TABLE(of, tegra_slink_of_match); 998 999 static int tegra_slink_probe(struct platform_device *pdev) 1000 { 1001 struct spi_master *master; 1002 struct tegra_slink_data *tspi; 1003 struct resource *r; 1004 int ret, spi_irq; 1005 const struct tegra_slink_chip_data *cdata = NULL; 1006 const struct of_device_id *match; 1007 1008 match = of_match_device(tegra_slink_of_match, &pdev->dev); 1009 if (!match) { 1010 dev_err(&pdev->dev, "Error: No device match found\n"); 1011 return -ENODEV; 1012 } 1013 cdata = match->data; 1014 1015 master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); 1016 if (!master) { 1017 dev_err(&pdev->dev, "master allocation failed\n"); 1018 return -ENOMEM; 1019 } 1020 1021 /* the spi->mode bits understood by this driver: */ 1022 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1023 master->setup = tegra_slink_setup; 1024 master->prepare_message = tegra_slink_prepare_message; 1025 master->transfer_one = tegra_slink_transfer_one; 1026 master->unprepare_message = tegra_slink_unprepare_message; 1027 master->auto_runtime_pm = true; 1028 master->num_chipselect = MAX_CHIP_SELECT; 1029 1030 platform_set_drvdata(pdev, master); 1031 tspi = spi_master_get_devdata(master); 1032 tspi->master = master; 1033 tspi->dev = &pdev->dev; 1034 tspi->chip_data = cdata; 1035 spin_lock_init(&tspi->lock); 1036 1037 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency", 1038 &master->max_speed_hz)) 1039 master->max_speed_hz = 25000000; /* 25MHz */ 1040 1041 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1042 if (!r) { 1043 dev_err(&pdev->dev, "No IO memory resource\n"); 1044 ret = -ENODEV; 1045 goto exit_free_master; 1046 } 1047 tspi->phys = r->start; 1048 tspi->base = devm_ioremap_resource(&pdev->dev, r); 1049 if (IS_ERR(tspi->base)) { 1050 ret = PTR_ERR(tspi->base); 1051 goto exit_free_master; 1052 } 1053 1054 /* disabled clock may cause interrupt storm upon request */ 1055 tspi->clk = devm_clk_get(&pdev->dev, NULL); 1056 if (IS_ERR(tspi->clk)) { 1057 ret = PTR_ERR(tspi->clk); 1058 dev_err(&pdev->dev, "Can not get clock %d\n", ret); 1059 goto exit_free_master; 1060 } 1061 1062 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); 1063 if (IS_ERR(tspi->rst)) { 1064 dev_err(&pdev->dev, "can not get reset\n"); 1065 ret = PTR_ERR(tspi->rst); 1066 goto exit_free_master; 1067 } 1068 1069 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; 1070 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; 1071 1072 ret = tegra_slink_init_dma_param(tspi, true); 1073 if (ret < 0) 1074 goto exit_free_master; 1075 ret = tegra_slink_init_dma_param(tspi, false); 1076 if (ret < 0) 1077 goto exit_rx_dma_free; 1078 tspi->max_buf_size = tspi->dma_buf_size; 1079 init_completion(&tspi->tx_dma_complete); 1080 init_completion(&tspi->rx_dma_complete); 1081 1082 init_completion(&tspi->xfer_completion); 1083 1084 pm_runtime_enable(&pdev->dev); 1085 ret = pm_runtime_resume_and_get(&pdev->dev); 1086 if (ret) { 1087 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); 1088 goto exit_pm_disable; 1089 } 1090 1091 reset_control_assert(tspi->rst); 1092 udelay(2); 1093 reset_control_deassert(tspi->rst); 1094 1095 spi_irq = platform_get_irq(pdev, 0); 1096 tspi->irq = spi_irq; 1097 ret = request_threaded_irq(tspi->irq, tegra_slink_isr, 1098 tegra_slink_isr_thread, IRQF_ONESHOT, 1099 dev_name(&pdev->dev), tspi); 1100 if (ret < 0) { 1101 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", 1102 tspi->irq); 1103 goto exit_pm_put; 1104 } 1105 1106 tspi->def_command_reg = SLINK_M_S; 1107 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN; 1108 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 1109 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); 1110 1111 master->dev.of_node = pdev->dev.of_node; 1112 ret = spi_register_master(master); 1113 if (ret < 0) { 1114 dev_err(&pdev->dev, "can not register to master err %d\n", ret); 1115 goto exit_free_irq; 1116 } 1117 1118 pm_runtime_put(&pdev->dev); 1119 1120 return ret; 1121 1122 exit_free_irq: 1123 free_irq(spi_irq, tspi); 1124 exit_pm_put: 1125 pm_runtime_put(&pdev->dev); 1126 exit_pm_disable: 1127 pm_runtime_disable(&pdev->dev); 1128 1129 tegra_slink_deinit_dma_param(tspi, false); 1130 exit_rx_dma_free: 1131 tegra_slink_deinit_dma_param(tspi, true); 1132 exit_free_master: 1133 spi_master_put(master); 1134 return ret; 1135 } 1136 1137 static int tegra_slink_remove(struct platform_device *pdev) 1138 { 1139 struct spi_master *master = platform_get_drvdata(pdev); 1140 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1141 1142 spi_unregister_master(master); 1143 1144 free_irq(tspi->irq, tspi); 1145 1146 pm_runtime_disable(&pdev->dev); 1147 1148 if (tspi->tx_dma_chan) 1149 tegra_slink_deinit_dma_param(tspi, false); 1150 1151 if (tspi->rx_dma_chan) 1152 tegra_slink_deinit_dma_param(tspi, true); 1153 1154 return 0; 1155 } 1156 1157 #ifdef CONFIG_PM_SLEEP 1158 static int tegra_slink_suspend(struct device *dev) 1159 { 1160 struct spi_master *master = dev_get_drvdata(dev); 1161 1162 return spi_master_suspend(master); 1163 } 1164 1165 static int tegra_slink_resume(struct device *dev) 1166 { 1167 struct spi_master *master = dev_get_drvdata(dev); 1168 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1169 int ret; 1170 1171 ret = pm_runtime_get_sync(dev); 1172 if (ret < 0) { 1173 pm_runtime_put_noidle(dev); 1174 dev_err(dev, "pm runtime failed, e = %d\n", ret); 1175 return ret; 1176 } 1177 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND); 1178 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2); 1179 pm_runtime_put(dev); 1180 1181 return spi_master_resume(master); 1182 } 1183 #endif 1184 1185 #ifdef CONFIG_PM 1186 static int tegra_slink_runtime_suspend(struct device *dev) 1187 { 1188 struct spi_master *master = dev_get_drvdata(dev); 1189 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1190 1191 /* Flush all write which are in PPSB queue by reading back */ 1192 tegra_slink_readl(tspi, SLINK_MAS_DATA); 1193 1194 clk_disable_unprepare(tspi->clk); 1195 return 0; 1196 } 1197 1198 static int tegra_slink_runtime_resume(struct device *dev) 1199 { 1200 struct spi_master *master = dev_get_drvdata(dev); 1201 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1202 int ret; 1203 1204 ret = clk_prepare_enable(tspi->clk); 1205 if (ret < 0) { 1206 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); 1207 return ret; 1208 } 1209 return 0; 1210 } 1211 #endif /* CONFIG_PM */ 1212 1213 static const struct dev_pm_ops slink_pm_ops = { 1214 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend, 1215 tegra_slink_runtime_resume, NULL) 1216 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume) 1217 }; 1218 static struct platform_driver tegra_slink_driver = { 1219 .driver = { 1220 .name = "spi-tegra-slink", 1221 .pm = &slink_pm_ops, 1222 .of_match_table = tegra_slink_of_match, 1223 }, 1224 .probe = tegra_slink_probe, 1225 .remove = tegra_slink_remove, 1226 }; 1227 module_platform_driver(tegra_slink_driver); 1228 1229 MODULE_ALIAS("platform:spi-tegra-slink"); 1230 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver"); 1231 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1232 MODULE_LICENSE("GPL v2"); 1233