1 /* 2 * SPI driver for Nvidia's Tegra20 Serial Flash Controller. 3 * 4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 5 * 6 * Author: Laxman Dewangan <ldewangan@nvidia.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/completion.h> 23 #include <linux/delay.h> 24 #include <linux/err.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/kthread.h> 29 #include <linux/module.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/reset.h> 35 #include <linux/spi/spi.h> 36 37 #define SPI_COMMAND 0x000 38 #define SPI_GO BIT(30) 39 #define SPI_M_S BIT(28) 40 #define SPI_ACTIVE_SCLK_MASK (0x3 << 26) 41 #define SPI_ACTIVE_SCLK_DRIVE_LOW (0 << 26) 42 #define SPI_ACTIVE_SCLK_DRIVE_HIGH (1 << 26) 43 #define SPI_ACTIVE_SCLK_PULL_LOW (2 << 26) 44 #define SPI_ACTIVE_SCLK_PULL_HIGH (3 << 26) 45 46 #define SPI_CK_SDA_FALLING (1 << 21) 47 #define SPI_CK_SDA_RISING (0 << 21) 48 #define SPI_CK_SDA_MASK (1 << 21) 49 #define SPI_ACTIVE_SDA (0x3 << 18) 50 #define SPI_ACTIVE_SDA_DRIVE_LOW (0 << 18) 51 #define SPI_ACTIVE_SDA_DRIVE_HIGH (1 << 18) 52 #define SPI_ACTIVE_SDA_PULL_LOW (2 << 18) 53 #define SPI_ACTIVE_SDA_PULL_HIGH (3 << 18) 54 55 #define SPI_CS_POL_INVERT BIT(16) 56 #define SPI_TX_EN BIT(15) 57 #define SPI_RX_EN BIT(14) 58 #define SPI_CS_VAL_HIGH BIT(13) 59 #define SPI_CS_VAL_LOW 0x0 60 #define SPI_CS_SW BIT(12) 61 #define SPI_CS_HW 0x0 62 #define SPI_CS_DELAY_MASK (7 << 9) 63 #define SPI_CS3_EN BIT(8) 64 #define SPI_CS2_EN BIT(7) 65 #define SPI_CS1_EN BIT(6) 66 #define SPI_CS0_EN BIT(5) 67 68 #define SPI_CS_MASK (SPI_CS3_EN | SPI_CS2_EN | \ 69 SPI_CS1_EN | SPI_CS0_EN) 70 #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0) 71 72 #define SPI_MODES (SPI_ACTIVE_SCLK_MASK | SPI_CK_SDA_MASK) 73 74 #define SPI_STATUS 0x004 75 #define SPI_BSY BIT(31) 76 #define SPI_RDY BIT(30) 77 #define SPI_TXF_FLUSH BIT(29) 78 #define SPI_RXF_FLUSH BIT(28) 79 #define SPI_RX_UNF BIT(27) 80 #define SPI_TX_OVF BIT(26) 81 #define SPI_RXF_EMPTY BIT(25) 82 #define SPI_RXF_FULL BIT(24) 83 #define SPI_TXF_EMPTY BIT(23) 84 #define SPI_TXF_FULL BIT(22) 85 #define SPI_BLK_CNT(count) (((count) & 0xffff) + 1) 86 87 #define SPI_FIFO_ERROR (SPI_RX_UNF | SPI_TX_OVF) 88 #define SPI_FIFO_EMPTY (SPI_TX_EMPTY | SPI_RX_EMPTY) 89 90 #define SPI_RX_CMP 0x8 91 #define SPI_DMA_CTL 0x0C 92 #define SPI_DMA_EN BIT(31) 93 #define SPI_IE_RXC BIT(27) 94 #define SPI_IE_TXC BIT(26) 95 #define SPI_PACKED BIT(20) 96 #define SPI_RX_TRIG_MASK (0x3 << 18) 97 #define SPI_RX_TRIG_1W (0x0 << 18) 98 #define SPI_RX_TRIG_4W (0x1 << 18) 99 #define SPI_TX_TRIG_MASK (0x3 << 16) 100 #define SPI_TX_TRIG_1W (0x0 << 16) 101 #define SPI_TX_TRIG_4W (0x1 << 16) 102 #define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF); 103 104 #define SPI_TX_FIFO 0x10 105 #define SPI_RX_FIFO 0x20 106 107 #define DATA_DIR_TX (1 << 0) 108 #define DATA_DIR_RX (1 << 1) 109 110 #define MAX_CHIP_SELECT 4 111 #define SPI_FIFO_DEPTH 4 112 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) 113 114 struct tegra_sflash_data { 115 struct device *dev; 116 struct spi_master *master; 117 spinlock_t lock; 118 119 struct clk *clk; 120 struct reset_control *rst; 121 void __iomem *base; 122 unsigned irq; 123 u32 cur_speed; 124 125 struct spi_device *cur_spi; 126 unsigned cur_pos; 127 unsigned cur_len; 128 unsigned bytes_per_word; 129 unsigned cur_direction; 130 unsigned curr_xfer_words; 131 132 unsigned cur_rx_pos; 133 unsigned cur_tx_pos; 134 135 u32 tx_status; 136 u32 rx_status; 137 u32 status_reg; 138 139 u32 def_command_reg; 140 u32 command_reg; 141 u32 dma_control_reg; 142 143 struct completion xfer_completion; 144 struct spi_transfer *curr_xfer; 145 }; 146 147 static int tegra_sflash_runtime_suspend(struct device *dev); 148 static int tegra_sflash_runtime_resume(struct device *dev); 149 150 static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd, 151 unsigned long reg) 152 { 153 return readl(tsd->base + reg); 154 } 155 156 static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd, 157 u32 val, unsigned long reg) 158 { 159 writel(val, tsd->base + reg); 160 } 161 162 static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd) 163 { 164 /* Write 1 to clear status register */ 165 tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS); 166 } 167 168 static unsigned tegra_sflash_calculate_curr_xfer_param( 169 struct spi_device *spi, struct tegra_sflash_data *tsd, 170 struct spi_transfer *t) 171 { 172 unsigned remain_len = t->len - tsd->cur_pos; 173 unsigned max_word; 174 175 tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8); 176 max_word = remain_len / tsd->bytes_per_word; 177 if (max_word > SPI_FIFO_DEPTH) 178 max_word = SPI_FIFO_DEPTH; 179 tsd->curr_xfer_words = max_word; 180 return max_word; 181 } 182 183 static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf( 184 struct tegra_sflash_data *tsd, struct spi_transfer *t) 185 { 186 unsigned nbytes; 187 u32 status; 188 unsigned max_n_32bit = tsd->curr_xfer_words; 189 u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos; 190 191 if (max_n_32bit > SPI_FIFO_DEPTH) 192 max_n_32bit = SPI_FIFO_DEPTH; 193 nbytes = max_n_32bit * tsd->bytes_per_word; 194 195 status = tegra_sflash_readl(tsd, SPI_STATUS); 196 while (!(status & SPI_TXF_FULL)) { 197 int i; 198 u32 x = 0; 199 200 for (i = 0; nbytes && (i < tsd->bytes_per_word); 201 i++, nbytes--) 202 x |= (u32)(*tx_buf++) << (i * 8); 203 tegra_sflash_writel(tsd, x, SPI_TX_FIFO); 204 if (!nbytes) 205 break; 206 207 status = tegra_sflash_readl(tsd, SPI_STATUS); 208 } 209 tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word; 210 return max_n_32bit; 211 } 212 213 static int tegra_sflash_read_rx_fifo_to_client_rxbuf( 214 struct tegra_sflash_data *tsd, struct spi_transfer *t) 215 { 216 u32 status; 217 unsigned int read_words = 0; 218 u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos; 219 220 status = tegra_sflash_readl(tsd, SPI_STATUS); 221 while (!(status & SPI_RXF_EMPTY)) { 222 int i; 223 u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO); 224 for (i = 0; (i < tsd->bytes_per_word); i++) 225 *rx_buf++ = (x >> (i*8)) & 0xFF; 226 read_words++; 227 status = tegra_sflash_readl(tsd, SPI_STATUS); 228 } 229 tsd->cur_rx_pos += read_words * tsd->bytes_per_word; 230 return 0; 231 } 232 233 static int tegra_sflash_start_cpu_based_transfer( 234 struct tegra_sflash_data *tsd, struct spi_transfer *t) 235 { 236 u32 val = 0; 237 unsigned cur_words; 238 239 if (tsd->cur_direction & DATA_DIR_TX) 240 val |= SPI_IE_TXC; 241 242 if (tsd->cur_direction & DATA_DIR_RX) 243 val |= SPI_IE_RXC; 244 245 tegra_sflash_writel(tsd, val, SPI_DMA_CTL); 246 tsd->dma_control_reg = val; 247 248 if (tsd->cur_direction & DATA_DIR_TX) 249 cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t); 250 else 251 cur_words = tsd->curr_xfer_words; 252 val |= SPI_DMA_BLK_COUNT(cur_words); 253 tegra_sflash_writel(tsd, val, SPI_DMA_CTL); 254 tsd->dma_control_reg = val; 255 val |= SPI_DMA_EN; 256 tegra_sflash_writel(tsd, val, SPI_DMA_CTL); 257 return 0; 258 } 259 260 static int tegra_sflash_start_transfer_one(struct spi_device *spi, 261 struct spi_transfer *t, bool is_first_of_msg, 262 bool is_single_xfer) 263 { 264 struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master); 265 u32 speed; 266 u32 command; 267 268 speed = t->speed_hz; 269 if (speed != tsd->cur_speed) { 270 clk_set_rate(tsd->clk, speed); 271 tsd->cur_speed = speed; 272 } 273 274 tsd->cur_spi = spi; 275 tsd->cur_pos = 0; 276 tsd->cur_rx_pos = 0; 277 tsd->cur_tx_pos = 0; 278 tsd->curr_xfer = t; 279 tegra_sflash_calculate_curr_xfer_param(spi, tsd, t); 280 if (is_first_of_msg) { 281 command = tsd->def_command_reg; 282 command |= SPI_BIT_LENGTH(t->bits_per_word - 1); 283 command |= SPI_CS_VAL_HIGH; 284 285 command &= ~SPI_MODES; 286 if (spi->mode & SPI_CPHA) 287 command |= SPI_CK_SDA_FALLING; 288 289 if (spi->mode & SPI_CPOL) 290 command |= SPI_ACTIVE_SCLK_DRIVE_HIGH; 291 else 292 command |= SPI_ACTIVE_SCLK_DRIVE_LOW; 293 command |= SPI_CS0_EN << spi->chip_select; 294 } else { 295 command = tsd->command_reg; 296 command &= ~SPI_BIT_LENGTH(~0); 297 command |= SPI_BIT_LENGTH(t->bits_per_word - 1); 298 command &= ~(SPI_RX_EN | SPI_TX_EN); 299 } 300 301 tsd->cur_direction = 0; 302 if (t->rx_buf) { 303 command |= SPI_RX_EN; 304 tsd->cur_direction |= DATA_DIR_RX; 305 } 306 if (t->tx_buf) { 307 command |= SPI_TX_EN; 308 tsd->cur_direction |= DATA_DIR_TX; 309 } 310 tegra_sflash_writel(tsd, command, SPI_COMMAND); 311 tsd->command_reg = command; 312 313 return tegra_sflash_start_cpu_based_transfer(tsd, t); 314 } 315 316 static int tegra_sflash_transfer_one_message(struct spi_master *master, 317 struct spi_message *msg) 318 { 319 bool is_first_msg = true; 320 int single_xfer; 321 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); 322 struct spi_transfer *xfer; 323 struct spi_device *spi = msg->spi; 324 int ret; 325 326 msg->status = 0; 327 msg->actual_length = 0; 328 single_xfer = list_is_singular(&msg->transfers); 329 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 330 reinit_completion(&tsd->xfer_completion); 331 ret = tegra_sflash_start_transfer_one(spi, xfer, 332 is_first_msg, single_xfer); 333 if (ret < 0) { 334 dev_err(tsd->dev, 335 "spi can not start transfer, err %d\n", ret); 336 goto exit; 337 } 338 is_first_msg = false; 339 ret = wait_for_completion_timeout(&tsd->xfer_completion, 340 SPI_DMA_TIMEOUT); 341 if (WARN_ON(ret == 0)) { 342 dev_err(tsd->dev, 343 "spi trasfer timeout, err %d\n", ret); 344 ret = -EIO; 345 goto exit; 346 } 347 348 if (tsd->tx_status || tsd->rx_status) { 349 dev_err(tsd->dev, "Error in Transfer\n"); 350 ret = -EIO; 351 goto exit; 352 } 353 msg->actual_length += xfer->len; 354 if (xfer->cs_change && xfer->delay_usecs) { 355 tegra_sflash_writel(tsd, tsd->def_command_reg, 356 SPI_COMMAND); 357 udelay(xfer->delay_usecs); 358 } 359 } 360 ret = 0; 361 exit: 362 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); 363 msg->status = ret; 364 spi_finalize_current_message(master); 365 return ret; 366 } 367 368 static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd) 369 { 370 struct spi_transfer *t = tsd->curr_xfer; 371 unsigned long flags; 372 373 spin_lock_irqsave(&tsd->lock, flags); 374 if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) { 375 dev_err(tsd->dev, 376 "CpuXfer ERROR bit set 0x%x\n", tsd->status_reg); 377 dev_err(tsd->dev, 378 "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg, 379 tsd->dma_control_reg); 380 reset_control_assert(tsd->rst); 381 udelay(2); 382 reset_control_deassert(tsd->rst); 383 complete(&tsd->xfer_completion); 384 goto exit; 385 } 386 387 if (tsd->cur_direction & DATA_DIR_RX) 388 tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t); 389 390 if (tsd->cur_direction & DATA_DIR_TX) 391 tsd->cur_pos = tsd->cur_tx_pos; 392 else 393 tsd->cur_pos = tsd->cur_rx_pos; 394 395 if (tsd->cur_pos == t->len) { 396 complete(&tsd->xfer_completion); 397 goto exit; 398 } 399 400 tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t); 401 tegra_sflash_start_cpu_based_transfer(tsd, t); 402 exit: 403 spin_unlock_irqrestore(&tsd->lock, flags); 404 return IRQ_HANDLED; 405 } 406 407 static irqreturn_t tegra_sflash_isr(int irq, void *context_data) 408 { 409 struct tegra_sflash_data *tsd = context_data; 410 411 tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS); 412 if (tsd->cur_direction & DATA_DIR_TX) 413 tsd->tx_status = tsd->status_reg & SPI_TX_OVF; 414 415 if (tsd->cur_direction & DATA_DIR_RX) 416 tsd->rx_status = tsd->status_reg & SPI_RX_UNF; 417 tegra_sflash_clear_status(tsd); 418 419 return handle_cpu_based_xfer(tsd); 420 } 421 422 static struct of_device_id tegra_sflash_of_match[] = { 423 { .compatible = "nvidia,tegra20-sflash", }, 424 {} 425 }; 426 MODULE_DEVICE_TABLE(of, tegra_sflash_of_match); 427 428 static int tegra_sflash_probe(struct platform_device *pdev) 429 { 430 struct spi_master *master; 431 struct tegra_sflash_data *tsd; 432 struct resource *r; 433 int ret; 434 const struct of_device_id *match; 435 436 match = of_match_device(tegra_sflash_of_match, &pdev->dev); 437 if (!match) { 438 dev_err(&pdev->dev, "Error: No device match found\n"); 439 return -ENODEV; 440 } 441 442 master = spi_alloc_master(&pdev->dev, sizeof(*tsd)); 443 if (!master) { 444 dev_err(&pdev->dev, "master allocation failed\n"); 445 return -ENOMEM; 446 } 447 448 /* the spi->mode bits understood by this driver: */ 449 master->mode_bits = SPI_CPOL | SPI_CPHA; 450 master->transfer_one_message = tegra_sflash_transfer_one_message; 451 master->auto_runtime_pm = true; 452 master->num_chipselect = MAX_CHIP_SELECT; 453 454 platform_set_drvdata(pdev, master); 455 tsd = spi_master_get_devdata(master); 456 tsd->master = master; 457 tsd->dev = &pdev->dev; 458 spin_lock_init(&tsd->lock); 459 460 if (of_property_read_u32(tsd->dev->of_node, "spi-max-frequency", 461 &master->max_speed_hz)) 462 master->max_speed_hz = 25000000; /* 25MHz */ 463 464 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 465 tsd->base = devm_ioremap_resource(&pdev->dev, r); 466 if (IS_ERR(tsd->base)) { 467 ret = PTR_ERR(tsd->base); 468 goto exit_free_master; 469 } 470 471 tsd->irq = platform_get_irq(pdev, 0); 472 ret = request_irq(tsd->irq, tegra_sflash_isr, 0, 473 dev_name(&pdev->dev), tsd); 474 if (ret < 0) { 475 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", 476 tsd->irq); 477 goto exit_free_master; 478 } 479 480 tsd->clk = devm_clk_get(&pdev->dev, NULL); 481 if (IS_ERR(tsd->clk)) { 482 dev_err(&pdev->dev, "can not get clock\n"); 483 ret = PTR_ERR(tsd->clk); 484 goto exit_free_irq; 485 } 486 487 tsd->rst = devm_reset_control_get(&pdev->dev, "spi"); 488 if (IS_ERR(tsd->rst)) { 489 dev_err(&pdev->dev, "can not get reset\n"); 490 ret = PTR_ERR(tsd->rst); 491 goto exit_free_irq; 492 } 493 494 init_completion(&tsd->xfer_completion); 495 pm_runtime_enable(&pdev->dev); 496 if (!pm_runtime_enabled(&pdev->dev)) { 497 ret = tegra_sflash_runtime_resume(&pdev->dev); 498 if (ret) 499 goto exit_pm_disable; 500 } 501 502 ret = pm_runtime_get_sync(&pdev->dev); 503 if (ret < 0) { 504 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); 505 goto exit_pm_disable; 506 } 507 508 /* Reset controller */ 509 reset_control_assert(tsd->rst); 510 udelay(2); 511 reset_control_deassert(tsd->rst); 512 513 tsd->def_command_reg = SPI_M_S | SPI_CS_SW; 514 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); 515 pm_runtime_put(&pdev->dev); 516 517 master->dev.of_node = pdev->dev.of_node; 518 ret = devm_spi_register_master(&pdev->dev, master); 519 if (ret < 0) { 520 dev_err(&pdev->dev, "can not register to master err %d\n", ret); 521 goto exit_pm_disable; 522 } 523 return ret; 524 525 exit_pm_disable: 526 pm_runtime_disable(&pdev->dev); 527 if (!pm_runtime_status_suspended(&pdev->dev)) 528 tegra_sflash_runtime_suspend(&pdev->dev); 529 exit_free_irq: 530 free_irq(tsd->irq, tsd); 531 exit_free_master: 532 spi_master_put(master); 533 return ret; 534 } 535 536 static int tegra_sflash_remove(struct platform_device *pdev) 537 { 538 struct spi_master *master = platform_get_drvdata(pdev); 539 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); 540 541 free_irq(tsd->irq, tsd); 542 543 pm_runtime_disable(&pdev->dev); 544 if (!pm_runtime_status_suspended(&pdev->dev)) 545 tegra_sflash_runtime_suspend(&pdev->dev); 546 547 return 0; 548 } 549 550 #ifdef CONFIG_PM_SLEEP 551 static int tegra_sflash_suspend(struct device *dev) 552 { 553 struct spi_master *master = dev_get_drvdata(dev); 554 555 return spi_master_suspend(master); 556 } 557 558 static int tegra_sflash_resume(struct device *dev) 559 { 560 struct spi_master *master = dev_get_drvdata(dev); 561 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); 562 int ret; 563 564 ret = pm_runtime_get_sync(dev); 565 if (ret < 0) { 566 dev_err(dev, "pm runtime failed, e = %d\n", ret); 567 return ret; 568 } 569 tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND); 570 pm_runtime_put(dev); 571 572 return spi_master_resume(master); 573 } 574 #endif 575 576 static int tegra_sflash_runtime_suspend(struct device *dev) 577 { 578 struct spi_master *master = dev_get_drvdata(dev); 579 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); 580 581 /* Flush all write which are in PPSB queue by reading back */ 582 tegra_sflash_readl(tsd, SPI_COMMAND); 583 584 clk_disable_unprepare(tsd->clk); 585 return 0; 586 } 587 588 static int tegra_sflash_runtime_resume(struct device *dev) 589 { 590 struct spi_master *master = dev_get_drvdata(dev); 591 struct tegra_sflash_data *tsd = spi_master_get_devdata(master); 592 int ret; 593 594 ret = clk_prepare_enable(tsd->clk); 595 if (ret < 0) { 596 dev_err(tsd->dev, "clk_prepare failed: %d\n", ret); 597 return ret; 598 } 599 return 0; 600 } 601 602 static const struct dev_pm_ops slink_pm_ops = { 603 SET_RUNTIME_PM_OPS(tegra_sflash_runtime_suspend, 604 tegra_sflash_runtime_resume, NULL) 605 SET_SYSTEM_SLEEP_PM_OPS(tegra_sflash_suspend, tegra_sflash_resume) 606 }; 607 static struct platform_driver tegra_sflash_driver = { 608 .driver = { 609 .name = "spi-tegra-sflash", 610 .owner = THIS_MODULE, 611 .pm = &slink_pm_ops, 612 .of_match_table = tegra_sflash_of_match, 613 }, 614 .probe = tegra_sflash_probe, 615 .remove = tegra_sflash_remove, 616 }; 617 module_platform_driver(tegra_sflash_driver); 618 619 MODULE_ALIAS("platform:spi-tegra-sflash"); 620 MODULE_DESCRIPTION("NVIDIA Tegra20 Serial Flash Controller Driver"); 621 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 622 MODULE_LICENSE("GPL v2"); 623