1 /* 2 * Copyright (C) 2012 - 2014 Allwinner Tech 3 * Pan Nan <pannan@allwinnertech.com> 4 * 5 * Copyright (C) 2014 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 23 #include <linux/spi/spi.h> 24 25 #define SUN4I_FIFO_DEPTH 64 26 27 #define SUN4I_RXDATA_REG 0x00 28 29 #define SUN4I_TXDATA_REG 0x04 30 31 #define SUN4I_CTL_REG 0x08 32 #define SUN4I_CTL_ENABLE BIT(0) 33 #define SUN4I_CTL_MASTER BIT(1) 34 #define SUN4I_CTL_CPHA BIT(2) 35 #define SUN4I_CTL_CPOL BIT(3) 36 #define SUN4I_CTL_CS_ACTIVE_LOW BIT(4) 37 #define SUN4I_CTL_LMTF BIT(6) 38 #define SUN4I_CTL_TF_RST BIT(8) 39 #define SUN4I_CTL_RF_RST BIT(9) 40 #define SUN4I_CTL_XCH BIT(10) 41 #define SUN4I_CTL_CS_MASK 0x3000 42 #define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK) 43 #define SUN4I_CTL_DHB BIT(15) 44 #define SUN4I_CTL_CS_MANUAL BIT(16) 45 #define SUN4I_CTL_CS_LEVEL BIT(17) 46 #define SUN4I_CTL_TP BIT(18) 47 48 #define SUN4I_INT_CTL_REG 0x0c 49 #define SUN4I_INT_CTL_TC BIT(16) 50 51 #define SUN4I_INT_STA_REG 0x10 52 53 #define SUN4I_DMA_CTL_REG 0x14 54 55 #define SUN4I_WAIT_REG 0x18 56 57 #define SUN4I_CLK_CTL_REG 0x1c 58 #define SUN4I_CLK_CTL_CDR2_MASK 0xff 59 #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK) 60 #define SUN4I_CLK_CTL_CDR1_MASK 0xf 61 #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8) 62 #define SUN4I_CLK_CTL_DRS BIT(12) 63 64 #define SUN4I_BURST_CNT_REG 0x20 65 #define SUN4I_BURST_CNT(cnt) ((cnt) & 0xffffff) 66 67 #define SUN4I_XMIT_CNT_REG 0x24 68 #define SUN4I_XMIT_CNT(cnt) ((cnt) & 0xffffff) 69 70 #define SUN4I_FIFO_STA_REG 0x28 71 #define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f 72 #define SUN4I_FIFO_STA_RF_CNT_BITS 0 73 #define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f 74 #define SUN4I_FIFO_STA_TF_CNT_BITS 16 75 76 struct sun4i_spi { 77 struct spi_master *master; 78 void __iomem *base_addr; 79 struct clk *hclk; 80 struct clk *mclk; 81 82 struct completion done; 83 84 const u8 *tx_buf; 85 u8 *rx_buf; 86 int len; 87 }; 88 89 static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg) 90 { 91 return readl(sspi->base_addr + reg); 92 } 93 94 static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value) 95 { 96 writel(value, sspi->base_addr + reg); 97 } 98 99 static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len) 100 { 101 u32 reg, cnt; 102 u8 byte; 103 104 /* See how much data is available */ 105 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG); 106 reg &= SUN4I_FIFO_STA_RF_CNT_MASK; 107 cnt = reg >> SUN4I_FIFO_STA_RF_CNT_BITS; 108 109 if (len > cnt) 110 len = cnt; 111 112 while (len--) { 113 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG); 114 if (sspi->rx_buf) 115 *sspi->rx_buf++ = byte; 116 } 117 } 118 119 static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len) 120 { 121 u8 byte; 122 123 if (len > sspi->len) 124 len = sspi->len; 125 126 while (len--) { 127 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; 128 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG); 129 sspi->len--; 130 } 131 } 132 133 static void sun4i_spi_set_cs(struct spi_device *spi, bool enable) 134 { 135 struct sun4i_spi *sspi = spi_master_get_devdata(spi->master); 136 u32 reg; 137 138 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); 139 140 reg &= ~SUN4I_CTL_CS_MASK; 141 reg |= SUN4I_CTL_CS(spi->chip_select); 142 143 /* We want to control the chip select manually */ 144 reg |= SUN4I_CTL_CS_MANUAL; 145 146 if (enable) 147 reg |= SUN4I_CTL_CS_LEVEL; 148 else 149 reg &= ~SUN4I_CTL_CS_LEVEL; 150 151 /* 152 * Even though this looks irrelevant since we are supposed to 153 * be controlling the chip select manually, this bit also 154 * controls the levels of the chip select for inactive 155 * devices. 156 * 157 * If we don't set it, the chip select level will go low by 158 * default when the device is idle, which is not really 159 * expected in the common case where the chip select is active 160 * low. 161 */ 162 if (spi->mode & SPI_CS_HIGH) 163 reg &= ~SUN4I_CTL_CS_ACTIVE_LOW; 164 else 165 reg |= SUN4I_CTL_CS_ACTIVE_LOW; 166 167 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); 168 } 169 170 static int sun4i_spi_transfer_one(struct spi_master *master, 171 struct spi_device *spi, 172 struct spi_transfer *tfr) 173 { 174 struct sun4i_spi *sspi = spi_master_get_devdata(master); 175 unsigned int mclk_rate, div, timeout; 176 unsigned int start, end, tx_time; 177 unsigned int tx_len = 0; 178 int ret = 0; 179 u32 reg; 180 181 /* We don't support transfer larger than the FIFO */ 182 if (tfr->len > SUN4I_FIFO_DEPTH) 183 return -EMSGSIZE; 184 185 if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH) 186 return -EMSGSIZE; 187 188 reinit_completion(&sspi->done); 189 sspi->tx_buf = tfr->tx_buf; 190 sspi->rx_buf = tfr->rx_buf; 191 sspi->len = tfr->len; 192 193 /* Clear pending interrupts */ 194 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0); 195 196 197 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); 198 199 /* Reset FIFOs */ 200 sun4i_spi_write(sspi, SUN4I_CTL_REG, 201 reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST); 202 203 /* 204 * Setup the transfer control register: Chip Select, 205 * polarities, etc. 206 */ 207 if (spi->mode & SPI_CPOL) 208 reg |= SUN4I_CTL_CPOL; 209 else 210 reg &= ~SUN4I_CTL_CPOL; 211 212 if (spi->mode & SPI_CPHA) 213 reg |= SUN4I_CTL_CPHA; 214 else 215 reg &= ~SUN4I_CTL_CPHA; 216 217 if (spi->mode & SPI_LSB_FIRST) 218 reg |= SUN4I_CTL_LMTF; 219 else 220 reg &= ~SUN4I_CTL_LMTF; 221 222 223 /* 224 * If it's a TX only transfer, we don't want to fill the RX 225 * FIFO with bogus data 226 */ 227 if (sspi->rx_buf) 228 reg &= ~SUN4I_CTL_DHB; 229 else 230 reg |= SUN4I_CTL_DHB; 231 232 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg); 233 234 /* Ensure that we have a parent clock fast enough */ 235 mclk_rate = clk_get_rate(sspi->mclk); 236 if (mclk_rate < (2 * tfr->speed_hz)) { 237 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); 238 mclk_rate = clk_get_rate(sspi->mclk); 239 } 240 241 /* 242 * Setup clock divider. 243 * 244 * We have two choices there. Either we can use the clock 245 * divide rate 1, which is calculated thanks to this formula: 246 * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) 247 * Or we can use CDR2, which is calculated with the formula: 248 * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) 249 * Wether we use the former or the latter is set through the 250 * DRS bit. 251 * 252 * First try CDR2, and if we can't reach the expected 253 * frequency, fall back to CDR1. 254 */ 255 div = mclk_rate / (2 * tfr->speed_hz); 256 if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { 257 if (div > 0) 258 div--; 259 260 reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; 261 } else { 262 div = ilog2(mclk_rate) - ilog2(tfr->speed_hz); 263 reg = SUN4I_CLK_CTL_CDR1(div); 264 } 265 266 sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg); 267 268 /* Setup the transfer now... */ 269 if (sspi->tx_buf) 270 tx_len = tfr->len; 271 272 /* Setup the counters */ 273 sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len)); 274 sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len)); 275 276 /* 277 * Fill the TX FIFO 278 * Filling the FIFO fully causes timeout for some reason 279 * at least on spi2 on A10s 280 */ 281 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1); 282 283 /* Enable the interrupts */ 284 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC); 285 286 /* Start the transfer */ 287 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG); 288 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH); 289 290 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); 291 start = jiffies; 292 timeout = wait_for_completion_timeout(&sspi->done, 293 msecs_to_jiffies(tx_time)); 294 end = jiffies; 295 if (!timeout) { 296 dev_warn(&master->dev, 297 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", 298 dev_name(&spi->dev), tfr->len, tfr->speed_hz, 299 jiffies_to_msecs(end - start), tx_time); 300 ret = -ETIMEDOUT; 301 goto out; 302 } 303 304 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH); 305 306 out: 307 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0); 308 309 return ret; 310 } 311 312 static irqreturn_t sun4i_spi_handler(int irq, void *dev_id) 313 { 314 struct sun4i_spi *sspi = dev_id; 315 u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG); 316 317 /* Transfer complete */ 318 if (status & SUN4I_INT_CTL_TC) { 319 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC); 320 complete(&sspi->done); 321 return IRQ_HANDLED; 322 } 323 324 return IRQ_NONE; 325 } 326 327 static int sun4i_spi_runtime_resume(struct device *dev) 328 { 329 struct spi_master *master = dev_get_drvdata(dev); 330 struct sun4i_spi *sspi = spi_master_get_devdata(master); 331 int ret; 332 333 ret = clk_prepare_enable(sspi->hclk); 334 if (ret) { 335 dev_err(dev, "Couldn't enable AHB clock\n"); 336 goto out; 337 } 338 339 ret = clk_prepare_enable(sspi->mclk); 340 if (ret) { 341 dev_err(dev, "Couldn't enable module clock\n"); 342 goto err; 343 } 344 345 sun4i_spi_write(sspi, SUN4I_CTL_REG, 346 SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP); 347 348 return 0; 349 350 err: 351 clk_disable_unprepare(sspi->hclk); 352 out: 353 return ret; 354 } 355 356 static int sun4i_spi_runtime_suspend(struct device *dev) 357 { 358 struct spi_master *master = dev_get_drvdata(dev); 359 struct sun4i_spi *sspi = spi_master_get_devdata(master); 360 361 clk_disable_unprepare(sspi->mclk); 362 clk_disable_unprepare(sspi->hclk); 363 364 return 0; 365 } 366 367 static int sun4i_spi_probe(struct platform_device *pdev) 368 { 369 struct spi_master *master; 370 struct sun4i_spi *sspi; 371 struct resource *res; 372 int ret = 0, irq; 373 374 master = spi_alloc_master(&pdev->dev, sizeof(struct sun4i_spi)); 375 if (!master) { 376 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 377 return -ENOMEM; 378 } 379 380 platform_set_drvdata(pdev, master); 381 sspi = spi_master_get_devdata(master); 382 383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 384 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res); 385 if (IS_ERR(sspi->base_addr)) { 386 ret = PTR_ERR(sspi->base_addr); 387 goto err_free_master; 388 } 389 390 irq = platform_get_irq(pdev, 0); 391 if (irq < 0) { 392 dev_err(&pdev->dev, "No spi IRQ specified\n"); 393 ret = -ENXIO; 394 goto err_free_master; 395 } 396 397 ret = devm_request_irq(&pdev->dev, irq, sun4i_spi_handler, 398 0, "sun4i-spi", sspi); 399 if (ret) { 400 dev_err(&pdev->dev, "Cannot request IRQ\n"); 401 goto err_free_master; 402 } 403 404 sspi->master = master; 405 master->set_cs = sun4i_spi_set_cs; 406 master->transfer_one = sun4i_spi_transfer_one; 407 master->num_chipselect = 4; 408 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 409 master->bits_per_word_mask = SPI_BPW_MASK(8); 410 master->dev.of_node = pdev->dev.of_node; 411 master->auto_runtime_pm = true; 412 413 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); 414 if (IS_ERR(sspi->hclk)) { 415 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); 416 ret = PTR_ERR(sspi->hclk); 417 goto err_free_master; 418 } 419 420 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); 421 if (IS_ERR(sspi->mclk)) { 422 dev_err(&pdev->dev, "Unable to acquire module clock\n"); 423 ret = PTR_ERR(sspi->mclk); 424 goto err_free_master; 425 } 426 427 init_completion(&sspi->done); 428 429 /* 430 * This wake-up/shutdown pattern is to be able to have the 431 * device woken up, even if runtime_pm is disabled 432 */ 433 ret = sun4i_spi_runtime_resume(&pdev->dev); 434 if (ret) { 435 dev_err(&pdev->dev, "Couldn't resume the device\n"); 436 goto err_free_master; 437 } 438 439 pm_runtime_set_active(&pdev->dev); 440 pm_runtime_enable(&pdev->dev); 441 pm_runtime_idle(&pdev->dev); 442 443 ret = devm_spi_register_master(&pdev->dev, master); 444 if (ret) { 445 dev_err(&pdev->dev, "cannot register SPI master\n"); 446 goto err_pm_disable; 447 } 448 449 return 0; 450 451 err_pm_disable: 452 pm_runtime_disable(&pdev->dev); 453 sun4i_spi_runtime_suspend(&pdev->dev); 454 err_free_master: 455 spi_master_put(master); 456 return ret; 457 } 458 459 static int sun4i_spi_remove(struct platform_device *pdev) 460 { 461 pm_runtime_disable(&pdev->dev); 462 463 return 0; 464 } 465 466 static const struct of_device_id sun4i_spi_match[] = { 467 { .compatible = "allwinner,sun4i-a10-spi", }, 468 {} 469 }; 470 MODULE_DEVICE_TABLE(of, sun4i_spi_match); 471 472 static const struct dev_pm_ops sun4i_spi_pm_ops = { 473 .runtime_resume = sun4i_spi_runtime_resume, 474 .runtime_suspend = sun4i_spi_runtime_suspend, 475 }; 476 477 static struct platform_driver sun4i_spi_driver = { 478 .probe = sun4i_spi_probe, 479 .remove = sun4i_spi_remove, 480 .driver = { 481 .name = "sun4i-spi", 482 .of_match_table = sun4i_spi_match, 483 .pm = &sun4i_spi_pm_ops, 484 }, 485 }; 486 module_platform_driver(sun4i_spi_driver); 487 488 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); 489 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 490 MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver"); 491 MODULE_LICENSE("GPL"); 492