1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // STMicroelectronics STM32 SPI Controller driver (master mode only) 4 // 5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved 6 // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics. 7 8 #include <linux/debugfs.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/of_platform.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 #include <linux/spi/spi.h> 19 20 #define DRIVER_NAME "spi_stm32" 21 22 /* STM32F4 SPI registers */ 23 #define STM32F4_SPI_CR1 0x00 24 #define STM32F4_SPI_CR2 0x04 25 #define STM32F4_SPI_SR 0x08 26 #define STM32F4_SPI_DR 0x0C 27 #define STM32F4_SPI_I2SCFGR 0x1C 28 29 /* STM32F4_SPI_CR1 bit fields */ 30 #define STM32F4_SPI_CR1_CPHA BIT(0) 31 #define STM32F4_SPI_CR1_CPOL BIT(1) 32 #define STM32F4_SPI_CR1_MSTR BIT(2) 33 #define STM32F4_SPI_CR1_BR_SHIFT 3 34 #define STM32F4_SPI_CR1_BR GENMASK(5, 3) 35 #define STM32F4_SPI_CR1_SPE BIT(6) 36 #define STM32F4_SPI_CR1_LSBFRST BIT(7) 37 #define STM32F4_SPI_CR1_SSI BIT(8) 38 #define STM32F4_SPI_CR1_SSM BIT(9) 39 #define STM32F4_SPI_CR1_RXONLY BIT(10) 40 #define STM32F4_SPI_CR1_DFF BIT(11) 41 #define STM32F4_SPI_CR1_CRCNEXT BIT(12) 42 #define STM32F4_SPI_CR1_CRCEN BIT(13) 43 #define STM32F4_SPI_CR1_BIDIOE BIT(14) 44 #define STM32F4_SPI_CR1_BIDIMODE BIT(15) 45 #define STM32F4_SPI_CR1_BR_MIN 0 46 #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3) 47 48 /* STM32F4_SPI_CR2 bit fields */ 49 #define STM32F4_SPI_CR2_RXDMAEN BIT(0) 50 #define STM32F4_SPI_CR2_TXDMAEN BIT(1) 51 #define STM32F4_SPI_CR2_SSOE BIT(2) 52 #define STM32F4_SPI_CR2_FRF BIT(4) 53 #define STM32F4_SPI_CR2_ERRIE BIT(5) 54 #define STM32F4_SPI_CR2_RXNEIE BIT(6) 55 #define STM32F4_SPI_CR2_TXEIE BIT(7) 56 57 /* STM32F4_SPI_SR bit fields */ 58 #define STM32F4_SPI_SR_RXNE BIT(0) 59 #define STM32F4_SPI_SR_TXE BIT(1) 60 #define STM32F4_SPI_SR_CHSIDE BIT(2) 61 #define STM32F4_SPI_SR_UDR BIT(3) 62 #define STM32F4_SPI_SR_CRCERR BIT(4) 63 #define STM32F4_SPI_SR_MODF BIT(5) 64 #define STM32F4_SPI_SR_OVR BIT(6) 65 #define STM32F4_SPI_SR_BSY BIT(7) 66 #define STM32F4_SPI_SR_FRE BIT(8) 67 68 /* STM32F4_SPI_I2SCFGR bit fields */ 69 #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11) 70 71 /* STM32F4 SPI Baud Rate min/max divisor */ 72 #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN) 73 #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX) 74 75 /* STM32H7 SPI registers */ 76 #define STM32H7_SPI_CR1 0x00 77 #define STM32H7_SPI_CR2 0x04 78 #define STM32H7_SPI_CFG1 0x08 79 #define STM32H7_SPI_CFG2 0x0C 80 #define STM32H7_SPI_IER 0x10 81 #define STM32H7_SPI_SR 0x14 82 #define STM32H7_SPI_IFCR 0x18 83 #define STM32H7_SPI_TXDR 0x20 84 #define STM32H7_SPI_RXDR 0x30 85 #define STM32H7_SPI_I2SCFGR 0x50 86 87 /* STM32H7_SPI_CR1 bit fields */ 88 #define STM32H7_SPI_CR1_SPE BIT(0) 89 #define STM32H7_SPI_CR1_MASRX BIT(8) 90 #define STM32H7_SPI_CR1_CSTART BIT(9) 91 #define STM32H7_SPI_CR1_CSUSP BIT(10) 92 #define STM32H7_SPI_CR1_HDDIR BIT(11) 93 #define STM32H7_SPI_CR1_SSI BIT(12) 94 95 /* STM32H7_SPI_CR2 bit fields */ 96 #define STM32H7_SPI_CR2_TSIZE_SHIFT 0 97 #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0) 98 99 /* STM32H7_SPI_CFG1 bit fields */ 100 #define STM32H7_SPI_CFG1_DSIZE_SHIFT 0 101 #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0) 102 #define STM32H7_SPI_CFG1_FTHLV_SHIFT 5 103 #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5) 104 #define STM32H7_SPI_CFG1_RXDMAEN BIT(14) 105 #define STM32H7_SPI_CFG1_TXDMAEN BIT(15) 106 #define STM32H7_SPI_CFG1_MBR_SHIFT 28 107 #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28) 108 #define STM32H7_SPI_CFG1_MBR_MIN 0 109 #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28) 110 111 /* STM32H7_SPI_CFG2 bit fields */ 112 #define STM32H7_SPI_CFG2_MIDI_SHIFT 4 113 #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4) 114 #define STM32H7_SPI_CFG2_COMM_SHIFT 17 115 #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17) 116 #define STM32H7_SPI_CFG2_SP_SHIFT 19 117 #define STM32H7_SPI_CFG2_SP GENMASK(21, 19) 118 #define STM32H7_SPI_CFG2_MASTER BIT(22) 119 #define STM32H7_SPI_CFG2_LSBFRST BIT(23) 120 #define STM32H7_SPI_CFG2_CPHA BIT(24) 121 #define STM32H7_SPI_CFG2_CPOL BIT(25) 122 #define STM32H7_SPI_CFG2_SSM BIT(26) 123 #define STM32H7_SPI_CFG2_AFCNTR BIT(31) 124 125 /* STM32H7_SPI_IER bit fields */ 126 #define STM32H7_SPI_IER_RXPIE BIT(0) 127 #define STM32H7_SPI_IER_TXPIE BIT(1) 128 #define STM32H7_SPI_IER_DXPIE BIT(2) 129 #define STM32H7_SPI_IER_EOTIE BIT(3) 130 #define STM32H7_SPI_IER_TXTFIE BIT(4) 131 #define STM32H7_SPI_IER_OVRIE BIT(6) 132 #define STM32H7_SPI_IER_MODFIE BIT(9) 133 #define STM32H7_SPI_IER_ALL GENMASK(10, 0) 134 135 /* STM32H7_SPI_SR bit fields */ 136 #define STM32H7_SPI_SR_RXP BIT(0) 137 #define STM32H7_SPI_SR_TXP BIT(1) 138 #define STM32H7_SPI_SR_EOT BIT(3) 139 #define STM32H7_SPI_SR_OVR BIT(6) 140 #define STM32H7_SPI_SR_MODF BIT(9) 141 #define STM32H7_SPI_SR_SUSP BIT(11) 142 #define STM32H7_SPI_SR_RXPLVL_SHIFT 13 143 #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13) 144 #define STM32H7_SPI_SR_RXWNE BIT(15) 145 146 /* STM32H7_SPI_IFCR bit fields */ 147 #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3) 148 149 /* STM32H7_SPI_I2SCFGR bit fields */ 150 #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0) 151 152 /* STM32H7 SPI Master Baud Rate min/max divisor */ 153 #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN) 154 #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX) 155 156 /* STM32H7 SPI Communication mode */ 157 #define STM32H7_SPI_FULL_DUPLEX 0 158 #define STM32H7_SPI_SIMPLEX_TX 1 159 #define STM32H7_SPI_SIMPLEX_RX 2 160 #define STM32H7_SPI_HALF_DUPLEX 3 161 162 /* SPI Communication type */ 163 #define SPI_FULL_DUPLEX 0 164 #define SPI_SIMPLEX_TX 1 165 #define SPI_SIMPLEX_RX 2 166 #define SPI_3WIRE_TX 3 167 #define SPI_3WIRE_RX 4 168 169 #define SPI_1HZ_NS 1000000000 170 171 /* 172 * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers 173 * without fifo buffers. 174 */ 175 #define SPI_DMA_MIN_BYTES 16 176 177 /** 178 * stm32_spi_reg - stm32 SPI register & bitfield desc 179 * @reg: register offset 180 * @mask: bitfield mask 181 * @shift: left shift 182 */ 183 struct stm32_spi_reg { 184 int reg; 185 int mask; 186 int shift; 187 }; 188 189 /** 190 * stm32_spi_regspec - stm32 registers definition, compatible dependent data 191 * en: enable register and SPI enable bit 192 * dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit 193 * dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit 194 * cpol: clock polarity register and polarity bit 195 * cpha: clock phase register and phase bit 196 * lsb_first: LSB transmitted first register and bit 197 * br: baud rate register and bitfields 198 * rx: SPI RX data register 199 * tx: SPI TX data register 200 */ 201 struct stm32_spi_regspec { 202 const struct stm32_spi_reg en; 203 const struct stm32_spi_reg dma_rx_en; 204 const struct stm32_spi_reg dma_tx_en; 205 const struct stm32_spi_reg cpol; 206 const struct stm32_spi_reg cpha; 207 const struct stm32_spi_reg lsb_first; 208 const struct stm32_spi_reg br; 209 const struct stm32_spi_reg rx; 210 const struct stm32_spi_reg tx; 211 }; 212 213 struct stm32_spi; 214 215 /** 216 * stm32_spi_cfg - stm32 compatible configuration data 217 * @regs: registers descriptions 218 * @get_fifo_size: routine to get fifo size 219 * @get_bpw_mask: routine to get bits per word mask 220 * @disable: routine to disable controller 221 * @config: routine to configure controller as SPI Master 222 * @set_bpw: routine to configure registers to for bits per word 223 * @set_mode: routine to configure registers to desired mode 224 * @set_data_idleness: optional routine to configure registers to desired idle 225 * time between frames (if driver has this functionality) 226 * set_number_of_data: optional routine to configure registers to desired 227 * number of data (if driver has this functionality) 228 * @can_dma: routine to determine if the transfer is eligible for DMA use 229 * @transfer_one_dma_start: routine to start transfer a single spi_transfer 230 * using DMA 231 * @dma_rx cb: routine to call after DMA RX channel operation is complete 232 * @dma_tx cb: routine to call after DMA TX channel operation is complete 233 * @transfer_one_irq: routine to configure interrupts for driver 234 * @irq_handler_event: Interrupt handler for SPI controller events 235 * @irq_handler_thread: thread of interrupt handler for SPI controller 236 * @baud_rate_div_min: minimum baud rate divisor 237 * @baud_rate_div_max: maximum baud rate divisor 238 * @has_fifo: boolean to know if fifo is used for driver 239 * @has_startbit: boolean to know if start bit is used to start transfer 240 */ 241 struct stm32_spi_cfg { 242 const struct stm32_spi_regspec *regs; 243 int (*get_fifo_size)(struct stm32_spi *spi); 244 int (*get_bpw_mask)(struct stm32_spi *spi); 245 void (*disable)(struct stm32_spi *spi); 246 int (*config)(struct stm32_spi *spi); 247 void (*set_bpw)(struct stm32_spi *spi); 248 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type); 249 void (*set_data_idleness)(struct stm32_spi *spi, u32 length); 250 int (*set_number_of_data)(struct stm32_spi *spi, u32 length); 251 void (*transfer_one_dma_start)(struct stm32_spi *spi); 252 void (*dma_rx_cb)(void *data); 253 void (*dma_tx_cb)(void *data); 254 int (*transfer_one_irq)(struct stm32_spi *spi); 255 irqreturn_t (*irq_handler_event)(int irq, void *dev_id); 256 irqreturn_t (*irq_handler_thread)(int irq, void *dev_id); 257 unsigned int baud_rate_div_min; 258 unsigned int baud_rate_div_max; 259 bool has_fifo; 260 }; 261 262 /** 263 * struct stm32_spi - private data of the SPI controller 264 * @dev: driver model representation of the controller 265 * @master: controller master interface 266 * @cfg: compatible configuration data 267 * @base: virtual memory area 268 * @clk: hw kernel clock feeding the SPI clock generator 269 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator 270 * @rst: SPI controller reset line 271 * @lock: prevent I/O concurrent access 272 * @irq: SPI controller interrupt line 273 * @fifo_size: size of the embedded fifo in bytes 274 * @cur_midi: master inter-data idleness in ns 275 * @cur_speed: speed configured in Hz 276 * @cur_bpw: number of bits in a single SPI data frame 277 * @cur_fthlv: fifo threshold level (data frames in a single data packet) 278 * @cur_comm: SPI communication mode 279 * @cur_xferlen: current transfer length in bytes 280 * @cur_usedma: boolean to know if dma is used in current transfer 281 * @tx_buf: data to be written, or NULL 282 * @rx_buf: data to be read, or NULL 283 * @tx_len: number of data to be written in bytes 284 * @rx_len: number of data to be read in bytes 285 * @dma_tx: dma channel for TX transfer 286 * @dma_rx: dma channel for RX transfer 287 * @phys_addr: SPI registers physical base address 288 */ 289 struct stm32_spi { 290 struct device *dev; 291 struct spi_master *master; 292 const struct stm32_spi_cfg *cfg; 293 void __iomem *base; 294 struct clk *clk; 295 u32 clk_rate; 296 struct reset_control *rst; 297 spinlock_t lock; /* prevent I/O concurrent access */ 298 int irq; 299 unsigned int fifo_size; 300 301 unsigned int cur_midi; 302 unsigned int cur_speed; 303 unsigned int cur_bpw; 304 unsigned int cur_fthlv; 305 unsigned int cur_comm; 306 unsigned int cur_xferlen; 307 bool cur_usedma; 308 309 const void *tx_buf; 310 void *rx_buf; 311 int tx_len; 312 int rx_len; 313 struct dma_chan *dma_tx; 314 struct dma_chan *dma_rx; 315 dma_addr_t phys_addr; 316 }; 317 318 static const struct stm32_spi_regspec stm32f4_spi_regspec = { 319 .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE }, 320 321 .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN }, 322 .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN }, 323 324 .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL }, 325 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA }, 326 .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST }, 327 .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT }, 328 329 .rx = { STM32F4_SPI_DR }, 330 .tx = { STM32F4_SPI_DR }, 331 }; 332 333 static const struct stm32_spi_regspec stm32h7_spi_regspec = { 334 /* SPI data transfer is enabled but spi_ker_ck is idle. 335 * CFG1 and CFG2 registers are write protected when SPE is enabled. 336 */ 337 .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE }, 338 339 .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN }, 340 .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN }, 341 342 .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL }, 343 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA }, 344 .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST }, 345 .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR, 346 STM32H7_SPI_CFG1_MBR_SHIFT }, 347 348 .rx = { STM32H7_SPI_RXDR }, 349 .tx = { STM32H7_SPI_TXDR }, 350 }; 351 352 static inline void stm32_spi_set_bits(struct stm32_spi *spi, 353 u32 offset, u32 bits) 354 { 355 writel_relaxed(readl_relaxed(spi->base + offset) | bits, 356 spi->base + offset); 357 } 358 359 static inline void stm32_spi_clr_bits(struct stm32_spi *spi, 360 u32 offset, u32 bits) 361 { 362 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, 363 spi->base + offset); 364 } 365 366 /** 367 * stm32h7_spi_get_fifo_size - Return fifo size 368 * @spi: pointer to the spi controller data structure 369 */ 370 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) 371 { 372 unsigned long flags; 373 u32 count = 0; 374 375 spin_lock_irqsave(&spi->lock, flags); 376 377 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); 378 379 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) 380 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); 381 382 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); 383 384 spin_unlock_irqrestore(&spi->lock, flags); 385 386 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); 387 388 return count; 389 } 390 391 /** 392 * stm32f4_spi_get_bpw_mask - Return bits per word mask 393 * @spi: pointer to the spi controller data structure 394 */ 395 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi) 396 { 397 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); 398 return SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 399 } 400 401 /** 402 * stm32h7_spi_get_bpw_mask - Return bits per word mask 403 * @spi: pointer to the spi controller data structure 404 */ 405 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi) 406 { 407 unsigned long flags; 408 u32 cfg1, max_bpw; 409 410 spin_lock_irqsave(&spi->lock, flags); 411 412 /* 413 * The most significant bit at DSIZE bit field is reserved when the 414 * maximum data size of periperal instances is limited to 16-bit 415 */ 416 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); 417 418 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); 419 max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >> 420 STM32H7_SPI_CFG1_DSIZE_SHIFT; 421 max_bpw += 1; 422 423 spin_unlock_irqrestore(&spi->lock, flags); 424 425 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); 426 427 return SPI_BPW_RANGE_MASK(4, max_bpw); 428 } 429 430 /** 431 * stm32_spi_prepare_mbr - Determine baud rate divisor value 432 * @spi: pointer to the spi controller data structure 433 * @speed_hz: requested speed 434 * @min_div: minimum baud rate divisor 435 * @max_div: maximum baud rate divisor 436 * 437 * Return baud rate divisor value in case of success or -EINVAL 438 */ 439 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, 440 u32 min_div, u32 max_div) 441 { 442 u32 div, mbrdiv; 443 444 div = DIV_ROUND_UP(spi->clk_rate, speed_hz); 445 446 /* 447 * SPI framework set xfer->speed_hz to master->max_speed_hz if 448 * xfer->speed_hz is greater than master->max_speed_hz, and it returns 449 * an error when xfer->speed_hz is lower than master->min_speed_hz, so 450 * no need to check it there. 451 * However, we need to ensure the following calculations. 452 */ 453 if ((div < min_div) || (div > max_div)) 454 return -EINVAL; 455 456 /* Determine the first power of 2 greater than or equal to div */ 457 if (div & (div - 1)) 458 mbrdiv = fls(div); 459 else 460 mbrdiv = fls(div) - 1; 461 462 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); 463 464 return mbrdiv - 1; 465 } 466 467 /** 468 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level 469 * @spi: pointer to the spi controller data structure 470 */ 471 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi) 472 { 473 u32 fthlv, half_fifo; 474 475 /* data packet should not exceed 1/2 of fifo space */ 476 half_fifo = (spi->fifo_size / 2); 477 478 if (spi->cur_bpw <= 8) 479 fthlv = half_fifo; 480 else if (spi->cur_bpw <= 16) 481 fthlv = half_fifo / 2; 482 else 483 fthlv = half_fifo / 4; 484 485 /* align packet size with data registers access */ 486 if (spi->cur_bpw > 8) 487 fthlv -= (fthlv % 2); /* multiple of 2 */ 488 else 489 fthlv -= (fthlv % 4); /* multiple of 4 */ 490 491 return fthlv; 492 } 493 494 /** 495 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register 496 * @spi: pointer to the spi controller data structure 497 * 498 * Read from tx_buf depends on remaining bytes to avoid to read beyond 499 * tx_buf end. 500 */ 501 static void stm32f4_spi_write_tx(struct stm32_spi *spi) 502 { 503 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & 504 STM32F4_SPI_SR_TXE)) { 505 u32 offs = spi->cur_xferlen - spi->tx_len; 506 507 if (spi->cur_bpw == 16) { 508 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); 509 510 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); 511 spi->tx_len -= sizeof(u16); 512 } else { 513 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); 514 515 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); 516 spi->tx_len -= sizeof(u8); 517 } 518 } 519 520 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); 521 } 522 523 /** 524 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register 525 * @spi: pointer to the spi controller data structure 526 * 527 * Read from tx_buf depends on remaining bytes to avoid to read beyond 528 * tx_buf end. 529 */ 530 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi) 531 { 532 while ((spi->tx_len > 0) && 533 (readl_relaxed(spi->base + STM32H7_SPI_SR) & 534 STM32H7_SPI_SR_TXP)) { 535 u32 offs = spi->cur_xferlen - spi->tx_len; 536 537 if (spi->tx_len >= sizeof(u32)) { 538 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); 539 540 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); 541 spi->tx_len -= sizeof(u32); 542 } else if (spi->tx_len >= sizeof(u16)) { 543 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); 544 545 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); 546 spi->tx_len -= sizeof(u16); 547 } else { 548 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); 549 550 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); 551 spi->tx_len -= sizeof(u8); 552 } 553 } 554 555 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); 556 } 557 558 /** 559 * stm32f4_spi_read_rx - Read bytes from Receive Data Register 560 * @spi: pointer to the spi controller data structure 561 * 562 * Write in rx_buf depends on remaining bytes to avoid to write beyond 563 * rx_buf end. 564 */ 565 static void stm32f4_spi_read_rx(struct stm32_spi *spi) 566 { 567 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & 568 STM32F4_SPI_SR_RXNE)) { 569 u32 offs = spi->cur_xferlen - spi->rx_len; 570 571 if (spi->cur_bpw == 16) { 572 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); 573 574 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); 575 spi->rx_len -= sizeof(u16); 576 } else { 577 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); 578 579 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); 580 spi->rx_len -= sizeof(u8); 581 } 582 } 583 584 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); 585 } 586 587 /** 588 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register 589 * @spi: pointer to the spi controller data structure 590 * 591 * Write in rx_buf depends on remaining bytes to avoid to write beyond 592 * rx_buf end. 593 */ 594 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush) 595 { 596 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); 597 u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> 598 STM32H7_SPI_SR_RXPLVL_SHIFT; 599 600 while ((spi->rx_len > 0) && 601 ((sr & STM32H7_SPI_SR_RXP) || 602 (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) { 603 u32 offs = spi->cur_xferlen - spi->rx_len; 604 605 if ((spi->rx_len >= sizeof(u32)) || 606 (flush && (sr & STM32H7_SPI_SR_RXWNE))) { 607 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); 608 609 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); 610 spi->rx_len -= sizeof(u32); 611 } else if ((spi->rx_len >= sizeof(u16)) || 612 (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) { 613 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); 614 615 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); 616 spi->rx_len -= sizeof(u16); 617 } else { 618 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); 619 620 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); 621 spi->rx_len -= sizeof(u8); 622 } 623 624 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); 625 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> 626 STM32H7_SPI_SR_RXPLVL_SHIFT; 627 } 628 629 dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__, 630 flush ? "(flush)" : "", spi->rx_len); 631 } 632 633 /** 634 * stm32_spi_enable - Enable SPI controller 635 * @spi: pointer to the spi controller data structure 636 */ 637 static void stm32_spi_enable(struct stm32_spi *spi) 638 { 639 dev_dbg(spi->dev, "enable controller\n"); 640 641 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, 642 spi->cfg->regs->en.mask); 643 } 644 645 /** 646 * stm32f4_spi_disable - Disable SPI controller 647 * @spi: pointer to the spi controller data structure 648 */ 649 static void stm32f4_spi_disable(struct stm32_spi *spi) 650 { 651 unsigned long flags; 652 u32 sr; 653 654 dev_dbg(spi->dev, "disable controller\n"); 655 656 spin_lock_irqsave(&spi->lock, flags); 657 658 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & 659 STM32F4_SPI_CR1_SPE)) { 660 spin_unlock_irqrestore(&spi->lock, flags); 661 return; 662 } 663 664 /* Disable interrupts */ 665 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE | 666 STM32F4_SPI_CR2_RXNEIE | 667 STM32F4_SPI_CR2_ERRIE); 668 669 /* Wait until BSY = 0 */ 670 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, 671 sr, !(sr & STM32F4_SPI_SR_BSY), 672 10, 100000) < 0) { 673 dev_warn(spi->dev, "disabling condition timeout\n"); 674 } 675 676 if (spi->cur_usedma && spi->dma_tx) 677 dmaengine_terminate_all(spi->dma_tx); 678 if (spi->cur_usedma && spi->dma_rx) 679 dmaengine_terminate_all(spi->dma_rx); 680 681 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE); 682 683 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN | 684 STM32F4_SPI_CR2_RXDMAEN); 685 686 /* Sequence to clear OVR flag */ 687 readl_relaxed(spi->base + STM32F4_SPI_DR); 688 readl_relaxed(spi->base + STM32F4_SPI_SR); 689 690 spin_unlock_irqrestore(&spi->lock, flags); 691 } 692 693 /** 694 * stm32h7_spi_disable - Disable SPI controller 695 * @spi: pointer to the spi controller data structure 696 * 697 * RX-Fifo is flushed when SPI controller is disabled. To prevent any data 698 * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in 699 * RX-Fifo. 700 * Normally, if TSIZE has been configured, we should relax the hardware at the 701 * reception of the EOT interrupt. But in case of error, EOT will not be 702 * raised. So the subsystem unprepare_message call allows us to properly 703 * complete the transfer from an hardware point of view. 704 */ 705 static void stm32h7_spi_disable(struct stm32_spi *spi) 706 { 707 unsigned long flags; 708 u32 cr1, sr; 709 710 dev_dbg(spi->dev, "disable controller\n"); 711 712 spin_lock_irqsave(&spi->lock, flags); 713 714 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); 715 716 if (!(cr1 & STM32H7_SPI_CR1_SPE)) { 717 spin_unlock_irqrestore(&spi->lock, flags); 718 return; 719 } 720 721 /* Wait on EOT or suspend the flow */ 722 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR, 723 sr, !(sr & STM32H7_SPI_SR_EOT), 724 10, 100000) < 0) { 725 if (cr1 & STM32H7_SPI_CR1_CSTART) { 726 writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP, 727 spi->base + STM32H7_SPI_CR1); 728 if (readl_relaxed_poll_timeout_atomic( 729 spi->base + STM32H7_SPI_SR, 730 sr, !(sr & STM32H7_SPI_SR_SUSP), 731 10, 100000) < 0) 732 dev_warn(spi->dev, 733 "Suspend request timeout\n"); 734 } 735 } 736 737 if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0)) 738 stm32h7_spi_read_rxfifo(spi, true); 739 740 if (spi->cur_usedma && spi->dma_tx) 741 dmaengine_terminate_all(spi->dma_tx); 742 if (spi->cur_usedma && spi->dma_rx) 743 dmaengine_terminate_all(spi->dma_rx); 744 745 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); 746 747 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN | 748 STM32H7_SPI_CFG1_RXDMAEN); 749 750 /* Disable interrupts and clear status flags */ 751 writel_relaxed(0, spi->base + STM32H7_SPI_IER); 752 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); 753 754 spin_unlock_irqrestore(&spi->lock, flags); 755 } 756 757 /** 758 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use 759 * 760 * If driver has fifo and the current transfer size is greater than fifo size, 761 * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes. 762 */ 763 static bool stm32_spi_can_dma(struct spi_master *master, 764 struct spi_device *spi_dev, 765 struct spi_transfer *transfer) 766 { 767 unsigned int dma_size; 768 struct stm32_spi *spi = spi_master_get_devdata(master); 769 770 if (spi->cfg->has_fifo) 771 dma_size = spi->fifo_size; 772 else 773 dma_size = SPI_DMA_MIN_BYTES; 774 775 dev_dbg(spi->dev, "%s: %s\n", __func__, 776 (transfer->len > dma_size) ? "true" : "false"); 777 778 return (transfer->len > dma_size); 779 } 780 781 /** 782 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events 783 * @irq: interrupt line 784 * @dev_id: SPI controller master interface 785 */ 786 static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id) 787 { 788 struct spi_master *master = dev_id; 789 struct stm32_spi *spi = spi_master_get_devdata(master); 790 u32 sr, mask = 0; 791 unsigned long flags; 792 bool end = false; 793 794 spin_lock_irqsave(&spi->lock, flags); 795 796 sr = readl_relaxed(spi->base + STM32F4_SPI_SR); 797 /* 798 * BSY flag is not handled in interrupt but it is normal behavior when 799 * this flag is set. 800 */ 801 sr &= ~STM32F4_SPI_SR_BSY; 802 803 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || 804 spi->cur_comm == SPI_3WIRE_TX)) { 805 /* OVR flag shouldn't be handled for TX only mode */ 806 sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE; 807 mask |= STM32F4_SPI_SR_TXE; 808 } 809 810 if (!spi->cur_usedma && spi->cur_comm == SPI_FULL_DUPLEX) { 811 /* TXE flag is set and is handled when RXNE flag occurs */ 812 sr &= ~STM32F4_SPI_SR_TXE; 813 mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR; 814 } 815 816 if (!(sr & mask)) { 817 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); 818 spin_unlock_irqrestore(&spi->lock, flags); 819 return IRQ_NONE; 820 } 821 822 if (sr & STM32F4_SPI_SR_OVR) { 823 dev_warn(spi->dev, "Overrun: received value discarded\n"); 824 825 /* Sequence to clear OVR flag */ 826 readl_relaxed(spi->base + STM32F4_SPI_DR); 827 readl_relaxed(spi->base + STM32F4_SPI_SR); 828 829 /* 830 * If overrun is detected, it means that something went wrong, 831 * so stop the current transfer. Transfer can wait for next 832 * RXNE but DR is already read and end never happens. 833 */ 834 end = true; 835 goto end_irq; 836 } 837 838 if (sr & STM32F4_SPI_SR_TXE) { 839 if (spi->tx_buf) 840 stm32f4_spi_write_tx(spi); 841 if (spi->tx_len == 0) 842 end = true; 843 } 844 845 if (sr & STM32F4_SPI_SR_RXNE) { 846 stm32f4_spi_read_rx(spi); 847 if (spi->rx_len == 0) 848 end = true; 849 else /* Load data for discontinuous mode */ 850 stm32f4_spi_write_tx(spi); 851 } 852 853 end_irq: 854 if (end) { 855 /* Immediately disable interrupts to do not generate new one */ 856 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, 857 STM32F4_SPI_CR2_TXEIE | 858 STM32F4_SPI_CR2_RXNEIE | 859 STM32F4_SPI_CR2_ERRIE); 860 spin_unlock_irqrestore(&spi->lock, flags); 861 return IRQ_WAKE_THREAD; 862 } 863 864 spin_unlock_irqrestore(&spi->lock, flags); 865 return IRQ_HANDLED; 866 } 867 868 /** 869 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller 870 * @irq: interrupt line 871 * @dev_id: SPI controller master interface 872 */ 873 static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id) 874 { 875 struct spi_master *master = dev_id; 876 struct stm32_spi *spi = spi_master_get_devdata(master); 877 878 spi_finalize_current_transfer(master); 879 stm32f4_spi_disable(spi); 880 881 return IRQ_HANDLED; 882 } 883 884 /** 885 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller 886 * @irq: interrupt line 887 * @dev_id: SPI controller master interface 888 */ 889 static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id) 890 { 891 struct spi_master *master = dev_id; 892 struct stm32_spi *spi = spi_master_get_devdata(master); 893 u32 sr, ier, mask; 894 unsigned long flags; 895 bool end = false; 896 897 spin_lock_irqsave(&spi->lock, flags); 898 899 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); 900 ier = readl_relaxed(spi->base + STM32H7_SPI_IER); 901 902 mask = ier; 903 /* EOTIE is triggered on EOT, SUSP and TXC events. */ 904 mask |= STM32H7_SPI_SR_SUSP; 905 /* 906 * When TXTF is set, DXPIE and TXPIE are cleared. So in case of 907 * Full-Duplex, need to poll RXP event to know if there are remaining 908 * data, before disabling SPI. 909 */ 910 if (spi->rx_buf && !spi->cur_usedma) 911 mask |= STM32H7_SPI_SR_RXP; 912 913 if (!(sr & mask)) { 914 dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", 915 sr, ier); 916 spin_unlock_irqrestore(&spi->lock, flags); 917 return IRQ_NONE; 918 } 919 920 if (sr & STM32H7_SPI_SR_SUSP) { 921 dev_warn(spi->dev, "Communication suspended\n"); 922 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) 923 stm32h7_spi_read_rxfifo(spi, false); 924 /* 925 * If communication is suspended while using DMA, it means 926 * that something went wrong, so stop the current transfer 927 */ 928 if (spi->cur_usedma) 929 end = true; 930 } 931 932 if (sr & STM32H7_SPI_SR_MODF) { 933 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); 934 end = true; 935 } 936 937 if (sr & STM32H7_SPI_SR_OVR) { 938 dev_warn(spi->dev, "Overrun: received value discarded\n"); 939 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) 940 stm32h7_spi_read_rxfifo(spi, false); 941 /* 942 * If overrun is detected while using DMA, it means that 943 * something went wrong, so stop the current transfer 944 */ 945 if (spi->cur_usedma) 946 end = true; 947 } 948 949 if (sr & STM32H7_SPI_SR_EOT) { 950 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) 951 stm32h7_spi_read_rxfifo(spi, true); 952 end = true; 953 } 954 955 if (sr & STM32H7_SPI_SR_TXP) 956 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) 957 stm32h7_spi_write_txfifo(spi); 958 959 if (sr & STM32H7_SPI_SR_RXP) 960 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) 961 stm32h7_spi_read_rxfifo(spi, false); 962 963 writel_relaxed(mask, spi->base + STM32H7_SPI_IFCR); 964 965 spin_unlock_irqrestore(&spi->lock, flags); 966 967 if (end) { 968 spi_finalize_current_transfer(master); 969 stm32h7_spi_disable(spi); 970 } 971 972 return IRQ_HANDLED; 973 } 974 975 /** 976 * stm32_spi_prepare_msg - set up the controller to transfer a single message 977 */ 978 static int stm32_spi_prepare_msg(struct spi_master *master, 979 struct spi_message *msg) 980 { 981 struct stm32_spi *spi = spi_master_get_devdata(master); 982 struct spi_device *spi_dev = msg->spi; 983 struct device_node *np = spi_dev->dev.of_node; 984 unsigned long flags; 985 u32 clrb = 0, setb = 0; 986 987 /* SPI slave device may need time between data frames */ 988 spi->cur_midi = 0; 989 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) 990 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); 991 992 if (spi_dev->mode & SPI_CPOL) 993 setb |= spi->cfg->regs->cpol.mask; 994 else 995 clrb |= spi->cfg->regs->cpol.mask; 996 997 if (spi_dev->mode & SPI_CPHA) 998 setb |= spi->cfg->regs->cpha.mask; 999 else 1000 clrb |= spi->cfg->regs->cpha.mask; 1001 1002 if (spi_dev->mode & SPI_LSB_FIRST) 1003 setb |= spi->cfg->regs->lsb_first.mask; 1004 else 1005 clrb |= spi->cfg->regs->lsb_first.mask; 1006 1007 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", 1008 spi_dev->mode & SPI_CPOL, 1009 spi_dev->mode & SPI_CPHA, 1010 spi_dev->mode & SPI_LSB_FIRST, 1011 spi_dev->mode & SPI_CS_HIGH); 1012 1013 spin_lock_irqsave(&spi->lock, flags); 1014 1015 /* CPOL, CPHA and LSB FIRST bits have common register */ 1016 if (clrb || setb) 1017 writel_relaxed( 1018 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & 1019 ~clrb) | setb, 1020 spi->base + spi->cfg->regs->cpol.reg); 1021 1022 spin_unlock_irqrestore(&spi->lock, flags); 1023 1024 return 0; 1025 } 1026 1027 /** 1028 * stm32f4_spi_dma_tx_cb - dma callback 1029 * 1030 * DMA callback is called when the transfer is complete for DMA TX channel. 1031 */ 1032 static void stm32f4_spi_dma_tx_cb(void *data) 1033 { 1034 struct stm32_spi *spi = data; 1035 1036 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { 1037 spi_finalize_current_transfer(spi->master); 1038 stm32f4_spi_disable(spi); 1039 } 1040 } 1041 1042 /** 1043 * stm32f4_spi_dma_rx_cb - dma callback 1044 * 1045 * DMA callback is called when the transfer is complete for DMA RX channel. 1046 */ 1047 static void stm32f4_spi_dma_rx_cb(void *data) 1048 { 1049 struct stm32_spi *spi = data; 1050 1051 spi_finalize_current_transfer(spi->master); 1052 stm32f4_spi_disable(spi); 1053 } 1054 1055 /** 1056 * stm32h7_spi_dma_cb - dma callback 1057 * 1058 * DMA callback is called when the transfer is complete or when an error 1059 * occurs. If the transfer is complete, EOT flag is raised. 1060 */ 1061 static void stm32h7_spi_dma_cb(void *data) 1062 { 1063 struct stm32_spi *spi = data; 1064 unsigned long flags; 1065 u32 sr; 1066 1067 spin_lock_irqsave(&spi->lock, flags); 1068 1069 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); 1070 1071 spin_unlock_irqrestore(&spi->lock, flags); 1072 1073 if (!(sr & STM32H7_SPI_SR_EOT)) 1074 dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); 1075 1076 /* Now wait for EOT, or SUSP or OVR in case of error */ 1077 } 1078 1079 /** 1080 * stm32_spi_dma_config - configure dma slave channel depending on current 1081 * transfer bits_per_word. 1082 */ 1083 static void stm32_spi_dma_config(struct stm32_spi *spi, 1084 struct dma_slave_config *dma_conf, 1085 enum dma_transfer_direction dir) 1086 { 1087 enum dma_slave_buswidth buswidth; 1088 u32 maxburst; 1089 1090 if (spi->cur_bpw <= 8) 1091 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 1092 else if (spi->cur_bpw <= 16) 1093 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 1094 else 1095 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; 1096 1097 if (spi->cfg->has_fifo) { 1098 /* Valid for DMA Half or Full Fifo threshold */ 1099 if (spi->cur_fthlv == 2) 1100 maxburst = 1; 1101 else 1102 maxburst = spi->cur_fthlv; 1103 } else { 1104 maxburst = 1; 1105 } 1106 1107 memset(dma_conf, 0, sizeof(struct dma_slave_config)); 1108 dma_conf->direction = dir; 1109 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ 1110 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; 1111 dma_conf->src_addr_width = buswidth; 1112 dma_conf->src_maxburst = maxburst; 1113 1114 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", 1115 buswidth, maxburst); 1116 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ 1117 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; 1118 dma_conf->dst_addr_width = buswidth; 1119 dma_conf->dst_maxburst = maxburst; 1120 1121 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", 1122 buswidth, maxburst); 1123 } 1124 } 1125 1126 /** 1127 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using 1128 * interrupts 1129 * 1130 * It must returns 0 if the transfer is finished or 1 if the transfer is still 1131 * in progress. 1132 */ 1133 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) 1134 { 1135 unsigned long flags; 1136 u32 cr2 = 0; 1137 1138 /* Enable the interrupts relative to the current communication mode */ 1139 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { 1140 cr2 |= STM32F4_SPI_CR2_TXEIE; 1141 } else if (spi->cur_comm == SPI_FULL_DUPLEX) { 1142 /* In transmit-only mode, the OVR flag is set in the SR register 1143 * since the received data are never read. Therefore set OVR 1144 * interrupt only when rx buffer is available. 1145 */ 1146 cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE; 1147 } else { 1148 return -EINVAL; 1149 } 1150 1151 spin_lock_irqsave(&spi->lock, flags); 1152 1153 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2); 1154 1155 stm32_spi_enable(spi); 1156 1157 /* starting data transfer when buffer is loaded */ 1158 if (spi->tx_buf) 1159 stm32f4_spi_write_tx(spi); 1160 1161 spin_unlock_irqrestore(&spi->lock, flags); 1162 1163 return 1; 1164 } 1165 1166 /** 1167 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using 1168 * interrupts 1169 * 1170 * It must returns 0 if the transfer is finished or 1 if the transfer is still 1171 * in progress. 1172 */ 1173 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi) 1174 { 1175 unsigned long flags; 1176 u32 ier = 0; 1177 1178 /* Enable the interrupts relative to the current communication mode */ 1179 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ 1180 ier |= STM32H7_SPI_IER_DXPIE; 1181 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ 1182 ier |= STM32H7_SPI_IER_TXPIE; 1183 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ 1184 ier |= STM32H7_SPI_IER_RXPIE; 1185 1186 /* Enable the interrupts relative to the end of transfer */ 1187 ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE | 1188 STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE; 1189 1190 spin_lock_irqsave(&spi->lock, flags); 1191 1192 stm32_spi_enable(spi); 1193 1194 /* Be sure to have data in fifo before starting data transfer */ 1195 if (spi->tx_buf) 1196 stm32h7_spi_write_txfifo(spi); 1197 1198 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); 1199 1200 writel_relaxed(ier, spi->base + STM32H7_SPI_IER); 1201 1202 spin_unlock_irqrestore(&spi->lock, flags); 1203 1204 return 1; 1205 } 1206 1207 /** 1208 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start 1209 * transfer using DMA 1210 */ 1211 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi) 1212 { 1213 /* In DMA mode end of transfer is handled by DMA TX or RX callback. */ 1214 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || 1215 spi->cur_comm == SPI_FULL_DUPLEX) { 1216 /* 1217 * In transmit-only mode, the OVR flag is set in the SR register 1218 * since the received data are never read. Therefore set OVR 1219 * interrupt only when rx buffer is available. 1220 */ 1221 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE); 1222 } 1223 1224 stm32_spi_enable(spi); 1225 } 1226 1227 /** 1228 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start 1229 * transfer using DMA 1230 */ 1231 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) 1232 { 1233 /* Enable the interrupts relative to the end of transfer */ 1234 stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE | 1235 STM32H7_SPI_IER_TXTFIE | 1236 STM32H7_SPI_IER_OVRIE | 1237 STM32H7_SPI_IER_MODFIE); 1238 1239 stm32_spi_enable(spi); 1240 1241 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); 1242 } 1243 1244 /** 1245 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA 1246 * 1247 * It must returns 0 if the transfer is finished or 1 if the transfer is still 1248 * in progress. 1249 */ 1250 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, 1251 struct spi_transfer *xfer) 1252 { 1253 struct dma_slave_config tx_dma_conf, rx_dma_conf; 1254 struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc; 1255 unsigned long flags; 1256 1257 spin_lock_irqsave(&spi->lock, flags); 1258 1259 rx_dma_desc = NULL; 1260 if (spi->rx_buf && spi->dma_rx) { 1261 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); 1262 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); 1263 1264 /* Enable Rx DMA request */ 1265 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, 1266 spi->cfg->regs->dma_rx_en.mask); 1267 1268 rx_dma_desc = dmaengine_prep_slave_sg( 1269 spi->dma_rx, xfer->rx_sg.sgl, 1270 xfer->rx_sg.nents, 1271 rx_dma_conf.direction, 1272 DMA_PREP_INTERRUPT); 1273 } 1274 1275 tx_dma_desc = NULL; 1276 if (spi->tx_buf && spi->dma_tx) { 1277 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); 1278 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); 1279 1280 tx_dma_desc = dmaengine_prep_slave_sg( 1281 spi->dma_tx, xfer->tx_sg.sgl, 1282 xfer->tx_sg.nents, 1283 tx_dma_conf.direction, 1284 DMA_PREP_INTERRUPT); 1285 } 1286 1287 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || 1288 (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) 1289 goto dma_desc_error; 1290 1291 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) 1292 goto dma_desc_error; 1293 1294 if (rx_dma_desc) { 1295 rx_dma_desc->callback = spi->cfg->dma_rx_cb; 1296 rx_dma_desc->callback_param = spi; 1297 1298 if (dma_submit_error(dmaengine_submit(rx_dma_desc))) { 1299 dev_err(spi->dev, "Rx DMA submit failed\n"); 1300 goto dma_desc_error; 1301 } 1302 /* Enable Rx DMA channel */ 1303 dma_async_issue_pending(spi->dma_rx); 1304 } 1305 1306 if (tx_dma_desc) { 1307 if (spi->cur_comm == SPI_SIMPLEX_TX || 1308 spi->cur_comm == SPI_3WIRE_TX) { 1309 tx_dma_desc->callback = spi->cfg->dma_tx_cb; 1310 tx_dma_desc->callback_param = spi; 1311 } 1312 1313 if (dma_submit_error(dmaengine_submit(tx_dma_desc))) { 1314 dev_err(spi->dev, "Tx DMA submit failed\n"); 1315 goto dma_submit_error; 1316 } 1317 /* Enable Tx DMA channel */ 1318 dma_async_issue_pending(spi->dma_tx); 1319 1320 /* Enable Tx DMA request */ 1321 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, 1322 spi->cfg->regs->dma_tx_en.mask); 1323 } 1324 1325 spi->cfg->transfer_one_dma_start(spi); 1326 1327 spin_unlock_irqrestore(&spi->lock, flags); 1328 1329 return 1; 1330 1331 dma_submit_error: 1332 if (spi->dma_rx) 1333 dmaengine_terminate_all(spi->dma_rx); 1334 1335 dma_desc_error: 1336 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, 1337 spi->cfg->regs->dma_rx_en.mask); 1338 1339 spin_unlock_irqrestore(&spi->lock, flags); 1340 1341 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); 1342 1343 spi->cur_usedma = false; 1344 return spi->cfg->transfer_one_irq(spi); 1345 } 1346 1347 /** 1348 * stm32f4_spi_set_bpw - Configure bits per word 1349 * @spi: pointer to the spi controller data structure 1350 */ 1351 static void stm32f4_spi_set_bpw(struct stm32_spi *spi) 1352 { 1353 if (spi->cur_bpw == 16) 1354 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); 1355 else 1356 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); 1357 } 1358 1359 /** 1360 * stm32h7_spi_set_bpw - configure bits per word 1361 * @spi: pointer to the spi controller data structure 1362 */ 1363 static void stm32h7_spi_set_bpw(struct stm32_spi *spi) 1364 { 1365 u32 bpw, fthlv; 1366 u32 cfg1_clrb = 0, cfg1_setb = 0; 1367 1368 bpw = spi->cur_bpw - 1; 1369 1370 cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE; 1371 cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) & 1372 STM32H7_SPI_CFG1_DSIZE; 1373 1374 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi); 1375 fthlv = spi->cur_fthlv - 1; 1376 1377 cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV; 1378 cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) & 1379 STM32H7_SPI_CFG1_FTHLV; 1380 1381 writel_relaxed( 1382 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & 1383 ~cfg1_clrb) | cfg1_setb, 1384 spi->base + STM32H7_SPI_CFG1); 1385 } 1386 1387 /** 1388 * stm32_spi_set_mbr - Configure baud rate divisor in master mode 1389 * @spi: pointer to the spi controller data structure 1390 * @mbrdiv: baud rate divisor value 1391 */ 1392 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) 1393 { 1394 u32 clrb = 0, setb = 0; 1395 1396 clrb |= spi->cfg->regs->br.mask; 1397 setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) & 1398 spi->cfg->regs->br.mask; 1399 1400 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & 1401 ~clrb) | setb, 1402 spi->base + spi->cfg->regs->br.reg); 1403 } 1404 1405 /** 1406 * stm32_spi_communication_type - return transfer communication type 1407 * @spi_dev: pointer to the spi device 1408 * transfer: pointer to spi transfer 1409 */ 1410 static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev, 1411 struct spi_transfer *transfer) 1412 { 1413 unsigned int type = SPI_FULL_DUPLEX; 1414 1415 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ 1416 /* 1417 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL 1418 * is forbidden and unvalidated by SPI subsystem so depending 1419 * on the valid buffer, we can determine the direction of the 1420 * transfer. 1421 */ 1422 if (!transfer->tx_buf) 1423 type = SPI_3WIRE_RX; 1424 else 1425 type = SPI_3WIRE_TX; 1426 } else { 1427 if (!transfer->tx_buf) 1428 type = SPI_SIMPLEX_RX; 1429 else if (!transfer->rx_buf) 1430 type = SPI_SIMPLEX_TX; 1431 } 1432 1433 return type; 1434 } 1435 1436 /** 1437 * stm32f4_spi_set_mode - configure communication mode 1438 * @spi: pointer to the spi controller data structure 1439 * @comm_type: type of communication to configure 1440 */ 1441 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) 1442 { 1443 if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) { 1444 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, 1445 STM32F4_SPI_CR1_BIDIMODE | 1446 STM32F4_SPI_CR1_BIDIOE); 1447 } else if (comm_type == SPI_FULL_DUPLEX) { 1448 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, 1449 STM32F4_SPI_CR1_BIDIMODE | 1450 STM32F4_SPI_CR1_BIDIOE); 1451 } else { 1452 return -EINVAL; 1453 } 1454 1455 return 0; 1456 } 1457 1458 /** 1459 * stm32h7_spi_set_mode - configure communication mode 1460 * @spi: pointer to the spi controller data structure 1461 * @comm_type: type of communication to configure 1462 */ 1463 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) 1464 { 1465 u32 mode; 1466 u32 cfg2_clrb = 0, cfg2_setb = 0; 1467 1468 if (comm_type == SPI_3WIRE_RX) { 1469 mode = STM32H7_SPI_HALF_DUPLEX; 1470 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); 1471 } else if (comm_type == SPI_3WIRE_TX) { 1472 mode = STM32H7_SPI_HALF_DUPLEX; 1473 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); 1474 } else if (comm_type == SPI_SIMPLEX_RX) { 1475 mode = STM32H7_SPI_SIMPLEX_RX; 1476 } else if (comm_type == SPI_SIMPLEX_TX) { 1477 mode = STM32H7_SPI_SIMPLEX_TX; 1478 } else { 1479 mode = STM32H7_SPI_FULL_DUPLEX; 1480 } 1481 1482 cfg2_clrb |= STM32H7_SPI_CFG2_COMM; 1483 cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) & 1484 STM32H7_SPI_CFG2_COMM; 1485 1486 writel_relaxed( 1487 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & 1488 ~cfg2_clrb) | cfg2_setb, 1489 spi->base + STM32H7_SPI_CFG2); 1490 1491 return 0; 1492 } 1493 1494 /** 1495 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two 1496 * consecutive data frames in master mode 1497 * @spi: pointer to the spi controller data structure 1498 * @len: transfer len 1499 */ 1500 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) 1501 { 1502 u32 cfg2_clrb = 0, cfg2_setb = 0; 1503 1504 cfg2_clrb |= STM32H7_SPI_CFG2_MIDI; 1505 if ((len > 1) && (spi->cur_midi > 0)) { 1506 u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed); 1507 u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns), 1508 (u32)STM32H7_SPI_CFG2_MIDI >> 1509 STM32H7_SPI_CFG2_MIDI_SHIFT); 1510 1511 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", 1512 sck_period_ns, midi, midi * sck_period_ns); 1513 cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) & 1514 STM32H7_SPI_CFG2_MIDI; 1515 } 1516 1517 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & 1518 ~cfg2_clrb) | cfg2_setb, 1519 spi->base + STM32H7_SPI_CFG2); 1520 } 1521 1522 /** 1523 * stm32h7_spi_number_of_data - configure number of data at current transfer 1524 * @spi: pointer to the spi controller data structure 1525 * @len: transfer length 1526 */ 1527 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) 1528 { 1529 u32 cr2_clrb = 0, cr2_setb = 0; 1530 1531 if (nb_words <= (STM32H7_SPI_CR2_TSIZE >> 1532 STM32H7_SPI_CR2_TSIZE_SHIFT)) { 1533 cr2_clrb |= STM32H7_SPI_CR2_TSIZE; 1534 cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT; 1535 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) & 1536 ~cr2_clrb) | cr2_setb, 1537 spi->base + STM32H7_SPI_CR2); 1538 } else { 1539 return -EMSGSIZE; 1540 } 1541 1542 return 0; 1543 } 1544 1545 /** 1546 * stm32_spi_transfer_one_setup - common setup to transfer a single 1547 * spi_transfer either using DMA or 1548 * interrupts. 1549 */ 1550 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, 1551 struct spi_device *spi_dev, 1552 struct spi_transfer *transfer) 1553 { 1554 unsigned long flags; 1555 unsigned int comm_type; 1556 int nb_words, ret = 0; 1557 1558 spin_lock_irqsave(&spi->lock, flags); 1559 1560 if (spi->cur_bpw != transfer->bits_per_word) { 1561 spi->cur_bpw = transfer->bits_per_word; 1562 spi->cfg->set_bpw(spi); 1563 } 1564 1565 if (spi->cur_speed != transfer->speed_hz) { 1566 int mbr; 1567 1568 /* Update spi->cur_speed with real clock speed */ 1569 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, 1570 spi->cfg->baud_rate_div_min, 1571 spi->cfg->baud_rate_div_max); 1572 if (mbr < 0) { 1573 ret = mbr; 1574 goto out; 1575 } 1576 1577 transfer->speed_hz = spi->cur_speed; 1578 stm32_spi_set_mbr(spi, mbr); 1579 } 1580 1581 comm_type = stm32_spi_communication_type(spi_dev, transfer); 1582 if (spi->cur_comm != comm_type) { 1583 ret = spi->cfg->set_mode(spi, comm_type); 1584 1585 if (ret < 0) 1586 goto out; 1587 1588 spi->cur_comm = comm_type; 1589 } 1590 1591 if (spi->cfg->set_data_idleness) 1592 spi->cfg->set_data_idleness(spi, transfer->len); 1593 1594 if (spi->cur_bpw <= 8) 1595 nb_words = transfer->len; 1596 else if (spi->cur_bpw <= 16) 1597 nb_words = DIV_ROUND_UP(transfer->len * 8, 16); 1598 else 1599 nb_words = DIV_ROUND_UP(transfer->len * 8, 32); 1600 1601 if (spi->cfg->set_number_of_data) { 1602 ret = spi->cfg->set_number_of_data(spi, nb_words); 1603 if (ret < 0) 1604 goto out; 1605 } 1606 1607 spi->cur_xferlen = transfer->len; 1608 1609 dev_dbg(spi->dev, "transfer communication mode set to %d\n", 1610 spi->cur_comm); 1611 dev_dbg(spi->dev, 1612 "data frame of %d-bit, data packet of %d data frames\n", 1613 spi->cur_bpw, spi->cur_fthlv); 1614 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); 1615 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", 1616 spi->cur_xferlen, nb_words); 1617 dev_dbg(spi->dev, "dma %s\n", 1618 (spi->cur_usedma) ? "enabled" : "disabled"); 1619 1620 out: 1621 spin_unlock_irqrestore(&spi->lock, flags); 1622 1623 return ret; 1624 } 1625 1626 /** 1627 * stm32_spi_transfer_one - transfer a single spi_transfer 1628 * 1629 * It must return 0 if the transfer is finished or 1 if the transfer is still 1630 * in progress. 1631 */ 1632 static int stm32_spi_transfer_one(struct spi_master *master, 1633 struct spi_device *spi_dev, 1634 struct spi_transfer *transfer) 1635 { 1636 struct stm32_spi *spi = spi_master_get_devdata(master); 1637 int ret; 1638 1639 spi->tx_buf = transfer->tx_buf; 1640 spi->rx_buf = transfer->rx_buf; 1641 spi->tx_len = spi->tx_buf ? transfer->len : 0; 1642 spi->rx_len = spi->rx_buf ? transfer->len : 0; 1643 1644 spi->cur_usedma = (master->can_dma && 1645 master->can_dma(master, spi_dev, transfer)); 1646 1647 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); 1648 if (ret) { 1649 dev_err(spi->dev, "SPI transfer setup failed\n"); 1650 return ret; 1651 } 1652 1653 if (spi->cur_usedma) 1654 return stm32_spi_transfer_one_dma(spi, transfer); 1655 else 1656 return spi->cfg->transfer_one_irq(spi); 1657 } 1658 1659 /** 1660 * stm32_spi_unprepare_msg - relax the hardware 1661 */ 1662 static int stm32_spi_unprepare_msg(struct spi_master *master, 1663 struct spi_message *msg) 1664 { 1665 struct stm32_spi *spi = spi_master_get_devdata(master); 1666 1667 spi->cfg->disable(spi); 1668 1669 return 0; 1670 } 1671 1672 /** 1673 * stm32f4_spi_config - Configure SPI controller as SPI master 1674 */ 1675 static int stm32f4_spi_config(struct stm32_spi *spi) 1676 { 1677 unsigned long flags; 1678 1679 spin_lock_irqsave(&spi->lock, flags); 1680 1681 /* Ensure I2SMOD bit is kept cleared */ 1682 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR, 1683 STM32F4_SPI_I2SCFGR_I2SMOD); 1684 1685 /* 1686 * - SS input value high 1687 * - transmitter half duplex direction 1688 * - Set the master mode (default Motorola mode) 1689 * - Consider 1 master/n slaves configuration and 1690 * SS input value is determined by the SSI bit 1691 */ 1692 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI | 1693 STM32F4_SPI_CR1_BIDIOE | 1694 STM32F4_SPI_CR1_MSTR | 1695 STM32F4_SPI_CR1_SSM); 1696 1697 spin_unlock_irqrestore(&spi->lock, flags); 1698 1699 return 0; 1700 } 1701 1702 /** 1703 * stm32h7_spi_config - Configure SPI controller as SPI master 1704 */ 1705 static int stm32h7_spi_config(struct stm32_spi *spi) 1706 { 1707 unsigned long flags; 1708 1709 spin_lock_irqsave(&spi->lock, flags); 1710 1711 /* Ensure I2SMOD bit is kept cleared */ 1712 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR, 1713 STM32H7_SPI_I2SCFGR_I2SMOD); 1714 1715 /* 1716 * - SS input value high 1717 * - transmitter half duplex direction 1718 * - automatic communication suspend when RX-Fifo is full 1719 */ 1720 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI | 1721 STM32H7_SPI_CR1_HDDIR | 1722 STM32H7_SPI_CR1_MASRX); 1723 1724 /* 1725 * - Set the master mode (default Motorola mode) 1726 * - Consider 1 master/n slaves configuration and 1727 * SS input value is determined by the SSI bit 1728 * - keep control of all associated GPIOs 1729 */ 1730 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER | 1731 STM32H7_SPI_CFG2_SSM | 1732 STM32H7_SPI_CFG2_AFCNTR); 1733 1734 spin_unlock_irqrestore(&spi->lock, flags); 1735 1736 return 0; 1737 } 1738 1739 static const struct stm32_spi_cfg stm32f4_spi_cfg = { 1740 .regs = &stm32f4_spi_regspec, 1741 .get_bpw_mask = stm32f4_spi_get_bpw_mask, 1742 .disable = stm32f4_spi_disable, 1743 .config = stm32f4_spi_config, 1744 .set_bpw = stm32f4_spi_set_bpw, 1745 .set_mode = stm32f4_spi_set_mode, 1746 .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start, 1747 .dma_tx_cb = stm32f4_spi_dma_tx_cb, 1748 .dma_rx_cb = stm32f4_spi_dma_rx_cb, 1749 .transfer_one_irq = stm32f4_spi_transfer_one_irq, 1750 .irq_handler_event = stm32f4_spi_irq_event, 1751 .irq_handler_thread = stm32f4_spi_irq_thread, 1752 .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN, 1753 .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX, 1754 .has_fifo = false, 1755 }; 1756 1757 static const struct stm32_spi_cfg stm32h7_spi_cfg = { 1758 .regs = &stm32h7_spi_regspec, 1759 .get_fifo_size = stm32h7_spi_get_fifo_size, 1760 .get_bpw_mask = stm32h7_spi_get_bpw_mask, 1761 .disable = stm32h7_spi_disable, 1762 .config = stm32h7_spi_config, 1763 .set_bpw = stm32h7_spi_set_bpw, 1764 .set_mode = stm32h7_spi_set_mode, 1765 .set_data_idleness = stm32h7_spi_data_idleness, 1766 .set_number_of_data = stm32h7_spi_number_of_data, 1767 .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start, 1768 .dma_rx_cb = stm32h7_spi_dma_cb, 1769 .dma_tx_cb = stm32h7_spi_dma_cb, 1770 .transfer_one_irq = stm32h7_spi_transfer_one_irq, 1771 .irq_handler_thread = stm32h7_spi_irq_thread, 1772 .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN, 1773 .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX, 1774 .has_fifo = true, 1775 }; 1776 1777 static const struct of_device_id stm32_spi_of_match[] = { 1778 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg }, 1779 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg }, 1780 {}, 1781 }; 1782 MODULE_DEVICE_TABLE(of, stm32_spi_of_match); 1783 1784 static int stm32_spi_probe(struct platform_device *pdev) 1785 { 1786 struct spi_master *master; 1787 struct stm32_spi *spi; 1788 struct resource *res; 1789 int ret; 1790 1791 master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi)); 1792 if (!master) { 1793 dev_err(&pdev->dev, "spi master allocation failed\n"); 1794 return -ENOMEM; 1795 } 1796 platform_set_drvdata(pdev, master); 1797 1798 spi = spi_master_get_devdata(master); 1799 spi->dev = &pdev->dev; 1800 spi->master = master; 1801 spin_lock_init(&spi->lock); 1802 1803 spi->cfg = (const struct stm32_spi_cfg *) 1804 of_match_device(pdev->dev.driver->of_match_table, 1805 &pdev->dev)->data; 1806 1807 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1808 spi->base = devm_ioremap_resource(&pdev->dev, res); 1809 if (IS_ERR(spi->base)) { 1810 ret = PTR_ERR(spi->base); 1811 goto err_master_put; 1812 } 1813 1814 spi->phys_addr = (dma_addr_t)res->start; 1815 1816 spi->irq = platform_get_irq(pdev, 0); 1817 if (spi->irq <= 0) { 1818 ret = spi->irq; 1819 if (ret != -EPROBE_DEFER) 1820 dev_err(&pdev->dev, "failed to get irq: %d\n", ret); 1821 goto err_master_put; 1822 } 1823 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, 1824 spi->cfg->irq_handler_event, 1825 spi->cfg->irq_handler_thread, 1826 IRQF_ONESHOT, pdev->name, master); 1827 if (ret) { 1828 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, 1829 ret); 1830 goto err_master_put; 1831 } 1832 1833 spi->clk = devm_clk_get(&pdev->dev, NULL); 1834 if (IS_ERR(spi->clk)) { 1835 ret = PTR_ERR(spi->clk); 1836 dev_err(&pdev->dev, "clk get failed: %d\n", ret); 1837 goto err_master_put; 1838 } 1839 1840 ret = clk_prepare_enable(spi->clk); 1841 if (ret) { 1842 dev_err(&pdev->dev, "clk enable failed: %d\n", ret); 1843 goto err_master_put; 1844 } 1845 spi->clk_rate = clk_get_rate(spi->clk); 1846 if (!spi->clk_rate) { 1847 dev_err(&pdev->dev, "clk rate = 0\n"); 1848 ret = -EINVAL; 1849 goto err_clk_disable; 1850 } 1851 1852 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1853 if (!IS_ERR(spi->rst)) { 1854 reset_control_assert(spi->rst); 1855 udelay(2); 1856 reset_control_deassert(spi->rst); 1857 } 1858 1859 if (spi->cfg->has_fifo) 1860 spi->fifo_size = spi->cfg->get_fifo_size(spi); 1861 1862 ret = spi->cfg->config(spi); 1863 if (ret) { 1864 dev_err(&pdev->dev, "controller configuration failed: %d\n", 1865 ret); 1866 goto err_clk_disable; 1867 } 1868 1869 master->dev.of_node = pdev->dev.of_node; 1870 master->auto_runtime_pm = true; 1871 master->bus_num = pdev->id; 1872 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | 1873 SPI_3WIRE; 1874 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); 1875 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; 1876 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; 1877 master->use_gpio_descriptors = true; 1878 master->prepare_message = stm32_spi_prepare_msg; 1879 master->transfer_one = stm32_spi_transfer_one; 1880 master->unprepare_message = stm32_spi_unprepare_msg; 1881 1882 spi->dma_tx = dma_request_chan(spi->dev, "tx"); 1883 if (IS_ERR(spi->dma_tx)) { 1884 ret = PTR_ERR(spi->dma_tx); 1885 spi->dma_tx = NULL; 1886 if (ret == -EPROBE_DEFER) 1887 goto err_clk_disable; 1888 1889 dev_warn(&pdev->dev, "failed to request tx dma channel\n"); 1890 } else { 1891 master->dma_tx = spi->dma_tx; 1892 } 1893 1894 spi->dma_rx = dma_request_chan(spi->dev, "rx"); 1895 if (IS_ERR(spi->dma_rx)) { 1896 ret = PTR_ERR(spi->dma_rx); 1897 spi->dma_rx = NULL; 1898 if (ret == -EPROBE_DEFER) 1899 goto err_dma_release; 1900 1901 dev_warn(&pdev->dev, "failed to request rx dma channel\n"); 1902 } else { 1903 master->dma_rx = spi->dma_rx; 1904 } 1905 1906 if (spi->dma_tx || spi->dma_rx) 1907 master->can_dma = stm32_spi_can_dma; 1908 1909 pm_runtime_set_active(&pdev->dev); 1910 pm_runtime_enable(&pdev->dev); 1911 1912 ret = devm_spi_register_master(&pdev->dev, master); 1913 if (ret) { 1914 dev_err(&pdev->dev, "spi master registration failed: %d\n", 1915 ret); 1916 goto err_pm_disable; 1917 } 1918 1919 if (!master->cs_gpiods) { 1920 dev_err(&pdev->dev, "no CS gpios available\n"); 1921 ret = -EINVAL; 1922 goto err_pm_disable; 1923 } 1924 1925 dev_info(&pdev->dev, "driver initialized\n"); 1926 1927 return 0; 1928 1929 err_pm_disable: 1930 pm_runtime_disable(&pdev->dev); 1931 err_dma_release: 1932 if (spi->dma_tx) 1933 dma_release_channel(spi->dma_tx); 1934 if (spi->dma_rx) 1935 dma_release_channel(spi->dma_rx); 1936 err_clk_disable: 1937 clk_disable_unprepare(spi->clk); 1938 err_master_put: 1939 spi_master_put(master); 1940 1941 return ret; 1942 } 1943 1944 static int stm32_spi_remove(struct platform_device *pdev) 1945 { 1946 struct spi_master *master = platform_get_drvdata(pdev); 1947 struct stm32_spi *spi = spi_master_get_devdata(master); 1948 1949 spi->cfg->disable(spi); 1950 1951 if (master->dma_tx) 1952 dma_release_channel(master->dma_tx); 1953 if (master->dma_rx) 1954 dma_release_channel(master->dma_rx); 1955 1956 clk_disable_unprepare(spi->clk); 1957 1958 pm_runtime_disable(&pdev->dev); 1959 1960 return 0; 1961 } 1962 1963 #ifdef CONFIG_PM 1964 static int stm32_spi_runtime_suspend(struct device *dev) 1965 { 1966 struct spi_master *master = dev_get_drvdata(dev); 1967 struct stm32_spi *spi = spi_master_get_devdata(master); 1968 1969 clk_disable_unprepare(spi->clk); 1970 1971 return 0; 1972 } 1973 1974 static int stm32_spi_runtime_resume(struct device *dev) 1975 { 1976 struct spi_master *master = dev_get_drvdata(dev); 1977 struct stm32_spi *spi = spi_master_get_devdata(master); 1978 1979 return clk_prepare_enable(spi->clk); 1980 } 1981 #endif 1982 1983 #ifdef CONFIG_PM_SLEEP 1984 static int stm32_spi_suspend(struct device *dev) 1985 { 1986 struct spi_master *master = dev_get_drvdata(dev); 1987 int ret; 1988 1989 ret = spi_master_suspend(master); 1990 if (ret) 1991 return ret; 1992 1993 return pm_runtime_force_suspend(dev); 1994 } 1995 1996 static int stm32_spi_resume(struct device *dev) 1997 { 1998 struct spi_master *master = dev_get_drvdata(dev); 1999 struct stm32_spi *spi = spi_master_get_devdata(master); 2000 int ret; 2001 2002 ret = pm_runtime_force_resume(dev); 2003 if (ret) 2004 return ret; 2005 2006 ret = spi_master_resume(master); 2007 if (ret) 2008 clk_disable_unprepare(spi->clk); 2009 2010 return ret; 2011 } 2012 #endif 2013 2014 static const struct dev_pm_ops stm32_spi_pm_ops = { 2015 SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume) 2016 SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend, 2017 stm32_spi_runtime_resume, NULL) 2018 }; 2019 2020 static struct platform_driver stm32_spi_driver = { 2021 .probe = stm32_spi_probe, 2022 .remove = stm32_spi_remove, 2023 .driver = { 2024 .name = DRIVER_NAME, 2025 .pm = &stm32_spi_pm_ops, 2026 .of_match_table = stm32_spi_of_match, 2027 }, 2028 }; 2029 2030 module_platform_driver(stm32_spi_driver); 2031 2032 MODULE_ALIAS("platform:" DRIVER_NAME); 2033 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver"); 2034 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); 2035 MODULE_LICENSE("GPL v2"); 2036