1 /* 2 * Copyright (c) 2008-2014 STMicroelectronics Limited 3 * 4 * Author: Angus Clark <Angus.Clark@st.com> 5 * Patrice Chotard <patrice.chotard@st.com> 6 * Lee Jones <lee.jones@linaro.org> 7 * 8 * SPI master mode controller driver, used in STMicroelectronics devices. 9 * 10 * May be copied or modified under the terms of the GNU General Public 11 * License Version 2.0 only. See linux/COPYING for more information. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/of.h> 22 #include <linux/of_gpio.h> 23 #include <linux/of_irq.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/spi/spi.h> 26 #include <linux/spi/spi_bitbang.h> 27 28 /* SSC registers */ 29 #define SSC_BRG 0x000 30 #define SSC_TBUF 0x004 31 #define SSC_RBUF 0x008 32 #define SSC_CTL 0x00C 33 #define SSC_IEN 0x010 34 #define SSC_I2C 0x018 35 36 /* SSC Control */ 37 #define SSC_CTL_DATA_WIDTH_9 0x8 38 #define SSC_CTL_DATA_WIDTH_MSK 0xf 39 #define SSC_CTL_BM 0xf 40 #define SSC_CTL_HB BIT(4) 41 #define SSC_CTL_PH BIT(5) 42 #define SSC_CTL_PO BIT(6) 43 #define SSC_CTL_SR BIT(7) 44 #define SSC_CTL_MS BIT(8) 45 #define SSC_CTL_EN BIT(9) 46 #define SSC_CTL_LPB BIT(10) 47 #define SSC_CTL_EN_TX_FIFO BIT(11) 48 #define SSC_CTL_EN_RX_FIFO BIT(12) 49 #define SSC_CTL_EN_CLST_RX BIT(13) 50 51 /* SSC Interrupt Enable */ 52 #define SSC_IEN_TEEN BIT(2) 53 54 #define FIFO_SIZE 8 55 56 struct spi_st { 57 /* SSC SPI Controller */ 58 void __iomem *base; 59 struct clk *clk; 60 struct device *dev; 61 62 /* SSC SPI current transaction */ 63 const u8 *tx_ptr; 64 u8 *rx_ptr; 65 u16 bytes_per_word; 66 unsigned int words_remaining; 67 unsigned int baud; 68 struct completion done; 69 }; 70 71 /* Load the TX FIFO */ 72 static void ssc_write_tx_fifo(struct spi_st *spi_st) 73 { 74 unsigned int count, i; 75 uint32_t word = 0; 76 77 if (spi_st->words_remaining > FIFO_SIZE) 78 count = FIFO_SIZE; 79 else 80 count = spi_st->words_remaining; 81 82 for (i = 0; i < count; i++) { 83 if (spi_st->tx_ptr) { 84 if (spi_st->bytes_per_word == 1) { 85 word = *spi_st->tx_ptr++; 86 } else { 87 word = *spi_st->tx_ptr++; 88 word = *spi_st->tx_ptr++ | (word << 8); 89 } 90 } 91 writel_relaxed(word, spi_st->base + SSC_TBUF); 92 } 93 } 94 95 /* Read the RX FIFO */ 96 static void ssc_read_rx_fifo(struct spi_st *spi_st) 97 { 98 unsigned int count, i; 99 uint32_t word = 0; 100 101 if (spi_st->words_remaining > FIFO_SIZE) 102 count = FIFO_SIZE; 103 else 104 count = spi_st->words_remaining; 105 106 for (i = 0; i < count; i++) { 107 word = readl_relaxed(spi_st->base + SSC_RBUF); 108 109 if (spi_st->rx_ptr) { 110 if (spi_st->bytes_per_word == 1) { 111 *spi_st->rx_ptr++ = (uint8_t)word; 112 } else { 113 *spi_st->rx_ptr++ = (word >> 8); 114 *spi_st->rx_ptr++ = word & 0xff; 115 } 116 } 117 } 118 spi_st->words_remaining -= count; 119 } 120 121 static int spi_st_transfer_one(struct spi_master *master, 122 struct spi_device *spi, struct spi_transfer *t) 123 { 124 struct spi_st *spi_st = spi_master_get_devdata(master); 125 uint32_t ctl = 0; 126 127 /* Setup transfer */ 128 spi_st->tx_ptr = t->tx_buf; 129 spi_st->rx_ptr = t->rx_buf; 130 131 if (spi->bits_per_word > 8) { 132 /* 133 * Anything greater than 8 bits-per-word requires 2 134 * bytes-per-word in the RX/TX buffers 135 */ 136 spi_st->bytes_per_word = 2; 137 spi_st->words_remaining = t->len / 2; 138 139 } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) { 140 /* 141 * If transfer is even-length, and 8 bits-per-word, then 142 * implement as half-length 16 bits-per-word transfer 143 */ 144 spi_st->bytes_per_word = 2; 145 spi_st->words_remaining = t->len / 2; 146 147 /* Set SSC_CTL to 16 bits-per-word */ 148 ctl = readl_relaxed(spi_st->base + SSC_CTL); 149 writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL); 150 151 readl_relaxed(spi_st->base + SSC_RBUF); 152 153 } else { 154 spi_st->bytes_per_word = 1; 155 spi_st->words_remaining = t->len; 156 } 157 158 reinit_completion(&spi_st->done); 159 160 /* Start transfer by writing to the TX FIFO */ 161 ssc_write_tx_fifo(spi_st); 162 writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN); 163 164 /* Wait for transfer to complete */ 165 wait_for_completion(&spi_st->done); 166 167 /* Restore SSC_CTL if necessary */ 168 if (ctl) 169 writel_relaxed(ctl, spi_st->base + SSC_CTL); 170 171 spi_finalize_current_transfer(spi->master); 172 173 return t->len; 174 } 175 176 static void spi_st_cleanup(struct spi_device *spi) 177 { 178 int cs = spi->cs_gpio; 179 180 if (gpio_is_valid(cs)) 181 devm_gpio_free(&spi->dev, cs); 182 } 183 184 /* the spi->mode bits understood by this driver: */ 185 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH) 186 static int spi_st_setup(struct spi_device *spi) 187 { 188 struct spi_st *spi_st = spi_master_get_devdata(spi->master); 189 u32 spi_st_clk, sscbrg, var; 190 u32 hz = spi->max_speed_hz; 191 int cs = spi->cs_gpio; 192 int ret; 193 194 if (!hz) { 195 dev_err(&spi->dev, "max_speed_hz unspecified\n"); 196 return -EINVAL; 197 } 198 199 if (!gpio_is_valid(cs)) { 200 dev_err(&spi->dev, "%d is not a valid gpio\n", cs); 201 return -EINVAL; 202 } 203 204 if (devm_gpio_request(&spi->dev, cs, dev_name(&spi->dev))) { 205 dev_err(&spi->dev, "could not request gpio:%d\n", cs); 206 return -EINVAL; 207 } 208 209 ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH); 210 if (ret) 211 return ret; 212 213 spi_st_clk = clk_get_rate(spi_st->clk); 214 215 /* Set SSC_BRF */ 216 sscbrg = spi_st_clk / (2 * hz); 217 if (sscbrg < 0x07 || sscbrg > BIT(16)) { 218 dev_err(&spi->dev, 219 "baudrate %d outside valid range %d\n", sscbrg, hz); 220 return -EINVAL; 221 } 222 223 spi_st->baud = spi_st_clk / (2 * sscbrg); 224 if (sscbrg == BIT(16)) /* 16-bit counter wraps */ 225 sscbrg = 0x0; 226 227 writel_relaxed(sscbrg, spi_st->base + SSC_BRG); 228 229 dev_dbg(&spi->dev, 230 "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n", 231 hz, spi_st->baud, sscbrg); 232 233 /* Set SSC_CTL and enable SSC */ 234 var = readl_relaxed(spi_st->base + SSC_CTL); 235 var |= SSC_CTL_MS; 236 237 if (spi->mode & SPI_CPOL) 238 var |= SSC_CTL_PO; 239 else 240 var &= ~SSC_CTL_PO; 241 242 if (spi->mode & SPI_CPHA) 243 var |= SSC_CTL_PH; 244 else 245 var &= ~SSC_CTL_PH; 246 247 if ((spi->mode & SPI_LSB_FIRST) == 0) 248 var |= SSC_CTL_HB; 249 else 250 var &= ~SSC_CTL_HB; 251 252 if (spi->mode & SPI_LOOP) 253 var |= SSC_CTL_LPB; 254 else 255 var &= ~SSC_CTL_LPB; 256 257 var &= ~SSC_CTL_DATA_WIDTH_MSK; 258 var |= (spi->bits_per_word - 1); 259 260 var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO; 261 var |= SSC_CTL_EN; 262 263 writel_relaxed(var, spi_st->base + SSC_CTL); 264 265 /* Clear the status register */ 266 readl_relaxed(spi_st->base + SSC_RBUF); 267 268 return 0; 269 } 270 271 /* Interrupt fired when TX shift register becomes empty */ 272 static irqreturn_t spi_st_irq(int irq, void *dev_id) 273 { 274 struct spi_st *spi_st = (struct spi_st *)dev_id; 275 276 /* Read RX FIFO */ 277 ssc_read_rx_fifo(spi_st); 278 279 /* Fill TX FIFO */ 280 if (spi_st->words_remaining) { 281 ssc_write_tx_fifo(spi_st); 282 } else { 283 /* TX/RX complete */ 284 writel_relaxed(0x0, spi_st->base + SSC_IEN); 285 /* 286 * read SSC_IEN to ensure that this bit is set 287 * before re-enabling interrupt 288 */ 289 readl(spi_st->base + SSC_IEN); 290 complete(&spi_st->done); 291 } 292 293 return IRQ_HANDLED; 294 } 295 296 static int spi_st_probe(struct platform_device *pdev) 297 { 298 struct device_node *np = pdev->dev.of_node; 299 struct spi_master *master; 300 struct resource *res; 301 struct spi_st *spi_st; 302 int irq, ret = 0; 303 u32 var; 304 305 master = spi_alloc_master(&pdev->dev, sizeof(*spi_st)); 306 if (!master) 307 return -ENOMEM; 308 309 master->dev.of_node = np; 310 master->mode_bits = MODEBITS; 311 master->setup = spi_st_setup; 312 master->cleanup = spi_st_cleanup; 313 master->transfer_one = spi_st_transfer_one; 314 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); 315 master->auto_runtime_pm = true; 316 master->bus_num = pdev->id; 317 spi_st = spi_master_get_devdata(master); 318 319 spi_st->clk = devm_clk_get(&pdev->dev, "ssc"); 320 if (IS_ERR(spi_st->clk)) { 321 dev_err(&pdev->dev, "Unable to request clock\n"); 322 ret = PTR_ERR(spi_st->clk); 323 goto put_master; 324 } 325 326 ret = clk_prepare_enable(spi_st->clk); 327 if (ret) 328 goto put_master; 329 330 init_completion(&spi_st->done); 331 332 /* Get resources */ 333 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 334 spi_st->base = devm_ioremap_resource(&pdev->dev, res); 335 if (IS_ERR(spi_st->base)) { 336 ret = PTR_ERR(spi_st->base); 337 goto clk_disable; 338 } 339 340 /* Disable I2C and Reset SSC */ 341 writel_relaxed(0x0, spi_st->base + SSC_I2C); 342 var = readw_relaxed(spi_st->base + SSC_CTL); 343 var |= SSC_CTL_SR; 344 writel_relaxed(var, spi_st->base + SSC_CTL); 345 346 udelay(1); 347 var = readl_relaxed(spi_st->base + SSC_CTL); 348 var &= ~SSC_CTL_SR; 349 writel_relaxed(var, spi_st->base + SSC_CTL); 350 351 /* Set SSC into slave mode before reconfiguring PIO pins */ 352 var = readl_relaxed(spi_st->base + SSC_CTL); 353 var &= ~SSC_CTL_MS; 354 writel_relaxed(var, spi_st->base + SSC_CTL); 355 356 irq = irq_of_parse_and_map(np, 0); 357 if (!irq) { 358 dev_err(&pdev->dev, "IRQ missing or invalid\n"); 359 ret = -EINVAL; 360 goto clk_disable; 361 } 362 363 ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0, 364 pdev->name, spi_st); 365 if (ret) { 366 dev_err(&pdev->dev, "Failed to request irq %d\n", irq); 367 goto clk_disable; 368 } 369 370 /* by default the device is on */ 371 pm_runtime_set_active(&pdev->dev); 372 pm_runtime_enable(&pdev->dev); 373 374 platform_set_drvdata(pdev, master); 375 376 ret = devm_spi_register_master(&pdev->dev, master); 377 if (ret) { 378 dev_err(&pdev->dev, "Failed to register master\n"); 379 goto clk_disable; 380 } 381 382 return 0; 383 384 clk_disable: 385 clk_disable_unprepare(spi_st->clk); 386 put_master: 387 spi_master_put(master); 388 return ret; 389 } 390 391 static int spi_st_remove(struct platform_device *pdev) 392 { 393 struct spi_master *master = platform_get_drvdata(pdev); 394 struct spi_st *spi_st = spi_master_get_devdata(master); 395 396 clk_disable_unprepare(spi_st->clk); 397 398 pinctrl_pm_select_sleep_state(&pdev->dev); 399 400 return 0; 401 } 402 403 #ifdef CONFIG_PM 404 static int spi_st_runtime_suspend(struct device *dev) 405 { 406 struct spi_master *master = dev_get_drvdata(dev); 407 struct spi_st *spi_st = spi_master_get_devdata(master); 408 409 writel_relaxed(0, spi_st->base + SSC_IEN); 410 pinctrl_pm_select_sleep_state(dev); 411 412 clk_disable_unprepare(spi_st->clk); 413 414 return 0; 415 } 416 417 static int spi_st_runtime_resume(struct device *dev) 418 { 419 struct spi_master *master = dev_get_drvdata(dev); 420 struct spi_st *spi_st = spi_master_get_devdata(master); 421 int ret; 422 423 ret = clk_prepare_enable(spi_st->clk); 424 pinctrl_pm_select_default_state(dev); 425 426 return ret; 427 } 428 #endif 429 430 #ifdef CONFIG_PM_SLEEP 431 static int spi_st_suspend(struct device *dev) 432 { 433 struct spi_master *master = dev_get_drvdata(dev); 434 int ret; 435 436 ret = spi_master_suspend(master); 437 if (ret) 438 return ret; 439 440 return pm_runtime_force_suspend(dev); 441 } 442 443 static int spi_st_resume(struct device *dev) 444 { 445 struct spi_master *master = dev_get_drvdata(dev); 446 int ret; 447 448 ret = spi_master_resume(master); 449 if (ret) 450 return ret; 451 452 return pm_runtime_force_resume(dev); 453 } 454 #endif 455 456 static const struct dev_pm_ops spi_st_pm = { 457 SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume) 458 SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL) 459 }; 460 461 static const struct of_device_id stm_spi_match[] = { 462 { .compatible = "st,comms-ssc4-spi", }, 463 {}, 464 }; 465 MODULE_DEVICE_TABLE(of, stm_spi_match); 466 467 static struct platform_driver spi_st_driver = { 468 .driver = { 469 .name = "spi-st", 470 .pm = &spi_st_pm, 471 .of_match_table = of_match_ptr(stm_spi_match), 472 }, 473 .probe = spi_st_probe, 474 .remove = spi_st_remove, 475 }; 476 module_platform_driver(spi_st_driver); 477 478 MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>"); 479 MODULE_DESCRIPTION("STM SSC SPI driver"); 480 MODULE_LICENSE("GPL v2"); 481